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+;/*
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+; * File : start_rvds.S
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+; * This file is part of RT-Thread RTOS
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+; * COPYRIGHT (C) 2006, RT-Thread Development Team
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+; *
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+; * The license and distribution terms for this file may be
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+; * found in the file LICENSE in this distribution or at
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+; * http://www.rt-thread.org/license/LICENSE
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+; *
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+; * Change Logs:
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+; * Date Author Notes
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+; * 2011-08-14 weety first version
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+; */
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+
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+
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+; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
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+
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+Mode_USR EQU 0x10
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+Mode_FIQ EQU 0x11
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+Mode_IRQ EQU 0x12
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+Mode_SVC EQU 0x13
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+Mode_ABT EQU 0x17
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+Mode_UND EQU 0x1B
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+Mode_SYS EQU 0x1F
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+
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+SVCMODE EQU 0x13
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+MODEMASK EQU 0x1f
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+
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+I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
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+F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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+
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+
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+;----------------------- Stack and Heap Definitions ----------------------------
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+
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+;// <h> Stack Configuration (Stack Sizes in Bytes)
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+;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
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+;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
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+;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
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+;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
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+;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
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+;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
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+;// </h>
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+
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+UND_Stack_Size EQU 512
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+SVC_Stack_Size EQU 4096
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+ABT_Stack_Size EQU 512
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+FIQ_Stack_Size EQU 1024
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+IRQ_Stack_Size EQU 1024
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+USR_Stack_Size EQU 512
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+
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+ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
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+ FIQ_Stack_Size + IRQ_Stack_Size)
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+
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+ AREA STACK, NOINIT, READWRITE, ALIGN=3
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+
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+Stack_Mem SPACE USR_Stack_Size
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+__initial_sp SPACE ISR_Stack_Size
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+Stack_Top
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+
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+
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+;// <h> Heap Configuration
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+;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
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+;// </h>
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+
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+Heap_Size EQU 0x00000000
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+
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+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
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+__heap_base
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+Heap_Mem SPACE Heap_Size
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+__heap_limit
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+
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+
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+;----------------------- Memory Definitions ------------------------------------
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+
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+AT91_MATRIX_BASE EQU 0xffffee00
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+AT91_MATRIX_MRCR EQU (AT91_MATRIX_BASE + 0x100)
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+AT91_MATRIX_RCB0 EQU 0x00000001
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+AT91_MATRIX_RCB1 EQU 0x00000002
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+AT91_AIC_BASE EQU 0xfffff000
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+AT91_AIC_IDCR EQU 0x124
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+AT91_AIC_ICCR EQU 0x128
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+
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+;----------------------- CODE --------------------------------------------------
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+
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+ PRESERVE8
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+
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+
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+; Area Definition and Entry Point
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+; Startup Code must be linked first at Address at which it expects to run.
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+
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+ AREA RESET, CODE, READONLY
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+ ARM
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+
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+; Exception Vectors
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+; Mapped to Address 0.
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+; Absolute addressing mode must be used.
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+; Dummy Handlers are implemented as infinite loops which can be modified.
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+
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+ EXPORT Entry_Point
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+Entry_Point
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+Vectors LDR PC, Reset_Addr
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+ LDR PC, Undef_Addr
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+ LDR PC, SWI_Addr
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+ LDR PC, PAbt_Addr
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+ LDR PC, DAbt_Addr
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+ NOP
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+ LDR PC, IRQ_Addr
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+ LDR PC, FIQ_Addr
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+
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+Reset_Addr DCD Reset_Handler
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+Undef_Addr DCD Undef_Handler
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+SWI_Addr DCD SWI_Handler
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+PAbt_Addr DCD PAbt_Handler
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+DAbt_Addr DCD DAbt_Handler
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+ DCD 0 ; Reserved Address
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+IRQ_Addr DCD IRQ_Handler
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+FIQ_Addr DCD FIQ_Handler
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+
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+Undef_Handler B Undef_Handler
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+SWI_Handler B SWI_Handler
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+PAbt_Handler B PAbt_Handler
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+;DAbt_Handler B DAbt_Handler
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+FIQ_Handler B FIQ_Handler
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+
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+;*
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+;*************************************************************************
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+;*
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+;* Interrupt handling
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+;*
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+;*************************************************************************
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+;*
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+; DAbt Handler
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+DAbt_Handler
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+ IMPORT rt_hw_trap_dabt
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+
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+ sub sp, sp, #72
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+ stmia sp, {r0 - r12} ;/* Calling r0-r12 */
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+ add r8, sp, #60
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+ stmdb r8, {sp, lr} ;/* Calling SP, LR */
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+ str lr, [r8, #0] ;/* Save calling PC */
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+ mrs r6, spsr
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+ str r6, [r8, #4] ;/* Save CPSR */
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+ str r0, [r8, #8] ;/* Save OLD_R0 */
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+ mov r0, sp
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+
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+ bl rt_hw_trap_dabt
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+
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+
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+;##########################################
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+; Reset Handler
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+
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+ EXPORT Reset_Handler
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+Reset_Handler
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+
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+
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+; set the cpu to SVC32 mode-----------------------------------------------------
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+
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+ MRS R0,CPSR
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+ BIC R0,R0,#MODEMASK
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+ ORR R0,R0,#SVCMODE
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+ MSR CPSR_cxsf,R0
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+ LDR R1, =AT91_AIC_BASE
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+ LDR R0, =0xffffffff
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+ STR R0, [R1, #AT91_AIC_IDCR]
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+ STR R0, [R1, #AT91_AIC_ICCR]
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+
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+; remap internal ram to 0x00000000 address
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+ LDR R0, =AT91_MATRIX_MRCR
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+ LDR R1, =(AT91_MATRIX_RCB0|AT91_MATRIX_RCB1)
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+ STR R1, [R0]
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+
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+
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+; Copy Exception Vectors to Internal RAM ---------------------------------------
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+
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+ ADR R8, Vectors ; Source
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+ LDR R9, =0x00 ; Destination
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+ LDMIA R8!, {R0-R7} ; Load Vectors
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+ STMIA R9!, {R0-R7} ; Store Vectors
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+ LDMIA R8!, {R0-R7} ; Load Handler Addresses
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+ STMIA R9!, {R0-R7} ; Store Handler Addresses
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+
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+
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+; Setup Stack for each mode ----------------------------------------------------
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+
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+ LDR R0, =Stack_Top
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+
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+; Enter Undefined Instruction Mode and set its Stack Pointer
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+ MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
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+ MOV SP, R0
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+ SUB R0, R0, #UND_Stack_Size
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+
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+; Enter Abort Mode and set its Stack Pointer
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+ MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
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+ MOV SP, R0
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+ SUB R0, R0, #ABT_Stack_Size
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+
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+; Enter FIQ Mode and set its Stack Pointer
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+ MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
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+ MOV SP, R0
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+ SUB R0, R0, #FIQ_Stack_Size
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+
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+; Enter IRQ Mode and set its Stack Pointer
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+ MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
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+ MOV SP, R0
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+ SUB R0, R0, #IRQ_Stack_Size
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+
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+; Enter Supervisor Mode and set its Stack Pointer
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+ MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
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+ MOV SP, R0
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+ SUB R0, R0, #SVC_Stack_Size
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+
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+; Enter User Mode and set its Stack Pointer
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+ ; MSR CPSR_c, #Mode_USR
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+ MOV SP, R0
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+ SUB SL, SP, #USR_Stack_Size
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+
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+; Enter the C code -------------------------------------------------------------
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+
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+ IMPORT __main
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+ LDR R0, =__main
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+ BX R0
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+
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+ IMPORT rt_interrupt_enter
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+ IMPORT rt_interrupt_leave
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+ IMPORT rt_thread_switch_interrput_flag
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+ IMPORT rt_interrupt_from_thread
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+ IMPORT rt_interrupt_to_thread
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+ IMPORT rt_hw_trap_irq
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+
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+IRQ_Handler PROC
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+ EXPORT IRQ_Handler
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+ STMFD sp!, {r0-r12,lr}
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+ BL rt_interrupt_enter
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+ BL rt_hw_trap_irq
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+ BL rt_interrupt_leave
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+
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+ ; if rt_thread_switch_interrput_flag set, jump to
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+ ; rt_hw_context_switch_interrupt_do and don't return
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+ LDR r0, =rt_thread_switch_interrput_flag
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+ LDR r1, [r0]
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+ CMP r1, #1
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+ BEQ rt_hw_context_switch_interrupt_do
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+
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+ LDMFD sp!, {r0-r12,lr}
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+ SUBS pc, lr, #4
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+ ENDP
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+
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+; /*
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+; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
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+; */
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+rt_hw_context_switch_interrupt_do PROC
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+ EXPORT rt_hw_context_switch_interrupt_do
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+ MOV r1, #0 ; clear flag
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+ STR r1, [r0]
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+
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+ LDMFD sp!, {r0-r12,lr}; reload saved registers
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+ STMFD sp!, {r0-r3} ; save r0-r3
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+ MOV r1, sp
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+ ADD sp, sp, #16 ; restore sp
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+ SUB r2, lr, #4 ; save old task's pc to r2
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+
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+ MRS r3, spsr ; get cpsr of interrupt thread
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+
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+ ; switch to SVC mode and no interrupt
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+ MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC
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+
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+ STMFD sp!, {r2} ; push old task's pc
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+ STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
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+ MOV r4, r1 ; Special optimised code below
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+ MOV r5, r3
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+ LDMFD r4!, {r0-r3}
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+ STMFD sp!, {r0-r3} ; push old task's r3-r0
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+ STMFD sp!, {r5} ; push old task's cpsr
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+ MRS r4, spsr
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+ STMFD sp!, {r4} ; push old task's spsr
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+
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+ LDR r4, =rt_interrupt_from_thread
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+ LDR r5, [r4]
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+ STR sp, [r5] ; store sp in preempted tasks's TCB
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+
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+ LDR r6, =rt_interrupt_to_thread
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+ LDR r6, [r6]
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+ LDR sp, [r6] ; get new task's stack pointer
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+
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+ LDMFD sp!, {r4} ; pop new task's spsr
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+ MSR spsr_cxsf, r4
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+ LDMFD sp!, {r4} ; pop new task's psr
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+ MSR cpsr_cxsf, r4
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+
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+ LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
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+ ENDP
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+
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+ IF :DEF:__MICROLIB
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+
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+ EXPORT __heap_base
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+ EXPORT __heap_limit
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+
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+ ELSE
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+; User Initial Stack & Heap
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+ AREA |.text|, CODE, READONLY
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+
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+ IMPORT __use_two_region_memory
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+ EXPORT __user_initial_stackheap
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+__user_initial_stackheap
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+
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+ LDR R0, = Heap_Mem
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+ LDR R1, =(Stack_Mem + USR_Stack_Size)
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+ LDR R2, = (Heap_Mem + Heap_Size)
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+ LDR R3, = Stack_Mem
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+ BX LR
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+ ENDIF
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+
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+
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+ END
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+
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luohui2320@gmail.com