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@@ -525,17 +525,17 @@ void *rt_hw_mmu_v2p(struct rt_aspace *aspace, void *vaddr)
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return (void *)paddr;
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return (void *)paddr;
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}
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}
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-static int _noncache(rt_base_t *pte)
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+static int _noncache(rt_ubase_t *pte)
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{
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{
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return 0;
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return 0;
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}
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}
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-static int _cache(rt_base_t *pte)
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+static int _cache(rt_ubase_t *pte)
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{
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{
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return 0;
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return 0;
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}
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}
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-static int (*control_handler[MMU_CNTL_DUMMY_END])(rt_base_t *pte)=
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+static int (*control_handler[MMU_CNTL_DUMMY_END])(rt_ubase_t *pte)=
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{
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{
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[MMU_CNTL_CACHE] = _cache,
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[MMU_CNTL_CACHE] = _cache,
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[MMU_CNTL_NONCACHE] = _noncache,
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[MMU_CNTL_NONCACHE] = _noncache,
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@@ -565,14 +565,14 @@ int rt_hw_mmu_control(struct rt_aspace *aspace, void *vaddr, size_t size,
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int err = -RT_EINVAL;
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int err = -RT_EINVAL;
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void *vend = vaddr + size;
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void *vend = vaddr + size;
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- int (*handler)(rt_base_t *pte);
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+ int (*handler)(rt_ubase_t *pte);
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if (cmd >= 0 && cmd < MMU_CNTL_DUMMY_END)
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if (cmd >= 0 && cmd < MMU_CNTL_DUMMY_END)
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{
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{
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handler = control_handler[cmd];
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handler = control_handler[cmd];
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while (vaddr < vend)
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while (vaddr < vend)
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{
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{
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- rt_base_t *pte = _query(aspace, vaddr, &level);
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+ rt_ubase_t *pte = _query(aspace, vaddr, &level);
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void *range_end = vaddr + _get_level_size(level);
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void *range_end = vaddr + _get_level_size(level);
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RT_ASSERT(range_end <= vend);
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RT_ASSERT(range_end <= vend);
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@@ -755,4 +755,4 @@ void *rt_hw_mmu_pgtbl_create(void)
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void rt_hw_mmu_pgtbl_delete(void *pgtbl)
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void rt_hw_mmu_pgtbl_delete(void *pgtbl)
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{
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{
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rt_pages_free(pgtbl, 0);
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rt_pages_free(pgtbl, 0);
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-}
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+}
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