|
@@ -73,44 +73,53 @@
|
|
|
#define Heap_Size 0x0400
|
|
|
#endif
|
|
|
|
|
|
-LR_m_rom_config m_flash_config_start m_flash_config_size { ; load region size_region
|
|
|
- RW_m_config_text m_flash_config_start m_flash_config_size { ; load address = execution address
|
|
|
- * (.boot_hdr.conf, +FIRST)
|
|
|
- }
|
|
|
+#if (defined(BOARD_RT1050_EVK)) || (defined(BOARD_RT1050_SeeedStudio))
|
|
|
+LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region
|
|
|
+{
|
|
|
+ RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address
|
|
|
+ {
|
|
|
+ * (.boot_hdr.conf, +FIRST)
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
-LR_m_rom_ivt m_ivt_start m_ivt_size { ; load region size_region
|
|
|
- RW_m_ivt_text m_ivt_start m_ivt_size { ; load address = execution address
|
|
|
- * (.boot_hdr.ivt, +FIRST)
|
|
|
- * (.boot_hdr.boot_data)
|
|
|
- * (.boot_hdr.dcd_data)
|
|
|
- }
|
|
|
+LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region
|
|
|
+{
|
|
|
+ RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address
|
|
|
+ {
|
|
|
+ * (.boot_hdr.ivt, +FIRST)
|
|
|
+ * (.boot_hdr.boot_data)
|
|
|
+ * (.boot_hdr.dcd_data)
|
|
|
+ }
|
|
|
}
|
|
|
+#endif
|
|
|
|
|
|
-#define RTT_HEAP_SIZE \
|
|
|
- (m_data_size - ImageLength(RW_m_data) - ImageLength(ARM_LIB_HEAP) - ImageLength(ARM_LIB_STACK))
|
|
|
-
|
|
|
-LR_m_text m_text_start m_text_size { ; load region size_region
|
|
|
- ER_m_text m_text_start m_text_size { ; load address = execution address
|
|
|
- * (RESET,+FIRST)
|
|
|
- * (InRoot$$Sections)
|
|
|
- .ANY (+RO)
|
|
|
- }
|
|
|
- RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
|
|
- .ANY (+RW +ZI)
|
|
|
+#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
|
|
|
|
|
|
- }
|
|
|
- ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
|
|
- }
|
|
|
- ARM_LIB_STACK +0 EMPTY Stack_Size { ; Stack region growing down
|
|
|
- }
|
|
|
- RTT_HEAP +0 EMPTY RTT_HEAP_SIZE {
|
|
|
- }
|
|
|
+; load region size_region
|
|
|
+LR_IROM1 m_text_start m_text_size
|
|
|
+{
|
|
|
+ ER_IROM1 m_text_start m_text_size ; load address = execution address
|
|
|
+ {
|
|
|
+ * (RESET,+FIRST)
|
|
|
+ * (InRoot$$Sections)
|
|
|
+ .ANY (+RO)
|
|
|
+ }
|
|
|
+
|
|
|
+ RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
|
|
|
+ {
|
|
|
+ .ANY (+RW +ZI)
|
|
|
+ }
|
|
|
+
|
|
|
+ ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up
|
|
|
+ ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
|
|
|
+ RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
|
|
|
|
|
|
- RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
|
|
|
- * (NonCacheable.init)
|
|
|
- * (NonCacheable)
|
|
|
- }
|
|
|
+ ; ncache RW data
|
|
|
+ RW_m_ncache m_ncache_start m_ncache_size
|
|
|
+ {
|
|
|
+ * (NonCacheable.init)
|
|
|
+ * (NonCacheable)
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
|