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+/**
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+ ******************************************************************************
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+ * @file system_stm32f10x.c
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+ * @author MCD Application Team
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+ * @version V3.5.0
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+ * @date 11-March-2011
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+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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+ *
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+ * 1. This file provides two functions and one global variable to be called from
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+ * user application:
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+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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+ * factors, AHB/APBx prescalers and Flash settings).
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+ * This function is called at startup just after reset and
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+ * before branch to main program. This call is made inside
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+ * the "startup_stm32f10x_xx.s" file.
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+ *
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+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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+ * by the user application to setup the SysTick
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+ * timer or configure other parameters.
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+ *
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+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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+ * be called whenever the core clock is changed
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+ * during program execution.
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+ *
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+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
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+ * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
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+ * configure the system clock before to branch to main program.
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+ *
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+ * 3. If the system clock source selected by user fails to startup, the SystemInit()
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+ * function will do nothing and HSI still used as system clock source. User can
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+ * add some code to deal with this issue inside the SetSysClock() function.
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+ *
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+ * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
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+ * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
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+ * When HSE is used as system clock source, directly or through PLL, and you
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+ * are using different crystal you have to adapt the HSE value to your own
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+ * configuration.
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+ *
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+ ******************************************************************************
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+ * @attention
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+ *
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+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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+ *
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+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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+ ******************************************************************************
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+ */
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+
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+/** @addtogroup CMSIS
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+ * @{
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+ */
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+
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+/** @addtogroup stm32f10x_system
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+ * @{
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+ */
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+
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+/** @addtogroup STM32F10x_System_Private_Includes
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+ * @{
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+ */
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+
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+#include "stm32f10x.h"
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+
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+/**
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+ * @}
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+ */
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+
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+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
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+ * @{
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+ */
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+
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+/**
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+ * @}
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+ */
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+
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+/** @addtogroup STM32F10x_System_Private_Defines
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+ * @{
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+ */
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+
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+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
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+ frequency (after reset the HSI is used as SYSCLK source)
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+
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+ IMPORTANT NOTE:
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+ ==============
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+ 1. After each device reset the HSI is used as System clock source.
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+
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+ 2. Please make sure that the selected System clock doesn't exceed your device's
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+ maximum frequency.
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+
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+ 3. If none of the define below is enabled, the HSI is used as System clock
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+ source.
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+
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+ 4. The System clock configuration functions provided within this file assume that:
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+ - For Low, Medium and High density Value line devices an external 8MHz
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+ crystal is used to drive the System clock.
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+ - For Low, Medium and High density devices an external 8MHz crystal is
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+ used to drive the System clock.
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+ - For Connectivity line devices an external 25MHz crystal is used to drive
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+ the System clock.
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+ If you are using different crystal you have to adapt those functions accordingly.
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+ */
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+
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+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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+/* #define SYSCLK_FREQ_HSE HSE_VALUE */
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+ #define SYSCLK_FREQ_24MHz 24000000
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+#else
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+/* #define SYSCLK_FREQ_HSE HSE_VALUE */
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+/* #define SYSCLK_FREQ_24MHz 24000000 */
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+/* #define SYSCLK_FREQ_36MHz 36000000 */
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+/* #define SYSCLK_FREQ_48MHz 48000000 */
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+/* #define SYSCLK_FREQ_56MHz 56000000 */
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+#define SYSCLK_FREQ_72MHz 72000000
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+#endif
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+
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+/*!< Uncomment the following line if you need to use external SRAM mounted
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+ on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
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+ STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
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+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
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+/* #define DATA_IN_ExtSRAM */
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+#endif
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+
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+/*!< Uncomment the following line if you need to relocate your vector Table in
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+ Internal SRAM. */
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+/* #define VECT_TAB_SRAM */
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+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
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+ This value must be a multiple of 0x200. */
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+
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+
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+/**
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+ * @}
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+ */
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+
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+/** @addtogroup STM32F10x_System_Private_Macros
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+ * @{
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+ */
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+
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+/**
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+ * @}
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+ */
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+
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+/** @addtogroup STM32F10x_System_Private_Variables
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+ * @{
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+ */
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+
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+/*******************************************************************************
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+* Clock Definitions
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+*******************************************************************************/
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+#ifdef SYSCLK_FREQ_HSE
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+ uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
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+#elif defined SYSCLK_FREQ_24MHz
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+ uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
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+#elif defined SYSCLK_FREQ_36MHz
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+ uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
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+#elif defined SYSCLK_FREQ_48MHz
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+ uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
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+#elif defined SYSCLK_FREQ_56MHz
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+ uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
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+#elif defined SYSCLK_FREQ_72MHz
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+ uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
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+#else /*!< HSI Selected as System Clock source */
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+ uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
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+#endif
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+
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+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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+/**
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+ * @}
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+ */
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+
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+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
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+ * @{
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+ */
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+
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+static void SetSysClock(void);
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+
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+#ifdef SYSCLK_FREQ_HSE
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+ static void SetSysClockToHSE(void);
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+#elif defined SYSCLK_FREQ_24MHz
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+ static void SetSysClockTo24(void);
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+#elif defined SYSCLK_FREQ_36MHz
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+ static void SetSysClockTo36(void);
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+#elif defined SYSCLK_FREQ_48MHz
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+ static void SetSysClockTo48(void);
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+#elif defined SYSCLK_FREQ_56MHz
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+ static void SetSysClockTo56(void);
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+#elif defined SYSCLK_FREQ_72MHz
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+ static void SetSysClockTo72(void);
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+#endif
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+
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+#ifdef DATA_IN_ExtSRAM
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+ static void SystemInit_ExtMemCtl(void);
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+#endif /* DATA_IN_ExtSRAM */
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+
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+/**
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+ * @}
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+ */
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+
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+/** @addtogroup STM32F10x_System_Private_Functions
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+ * @{
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+ */
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+
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+/**
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+ * @brief Setup the microcontroller system
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+ * Initialize the Embedded Flash Interface, the PLL and update the
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+ * SystemCoreClock variable.
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+ * @note This function should be used only after reset.
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+ * @param None
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+ * @retval None
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+ */
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+void SystemInit (void)
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+{
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+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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+ /* Set HSION bit */
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+ RCC->CR |= (uint32_t)0x00000001;
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+
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+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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+#ifndef STM32F10X_CL
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+ RCC->CFGR &= (uint32_t)0xF8FF0000;
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+#else
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+ RCC->CFGR &= (uint32_t)0xF0FF0000;
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+#endif /* STM32F10X_CL */
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+
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+ /* Reset HSEON, CSSON and PLLON bits */
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+ RCC->CR &= (uint32_t)0xFEF6FFFF;
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+
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+ /* Reset HSEBYP bit */
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+ RCC->CR &= (uint32_t)0xFFFBFFFF;
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+
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+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
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+
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+#ifdef STM32F10X_CL
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+ /* Reset PLL2ON and PLL3ON bits */
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+ RCC->CR &= (uint32_t)0xEBFFFFFF;
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+
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+ /* Disable all interrupts and clear pending bits */
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+ RCC->CIR = 0x00FF0000;
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+
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+ /* Reset CFGR2 register */
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+ RCC->CFGR2 = 0x00000000;
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+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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+ /* Disable all interrupts and clear pending bits */
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+ RCC->CIR = 0x009F0000;
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+
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+ /* Reset CFGR2 register */
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+ RCC->CFGR2 = 0x00000000;
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+#else
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+ /* Disable all interrupts and clear pending bits */
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+ RCC->CIR = 0x009F0000;
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+#endif /* STM32F10X_CL */
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+
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+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
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+ #ifdef DATA_IN_ExtSRAM
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+ SystemInit_ExtMemCtl();
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+ #endif /* DATA_IN_ExtSRAM */
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+#endif
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+
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+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
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+ /* Configure the Flash Latency cycles and enable prefetch buffer */
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+ SetSysClock();
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+
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+#ifdef VECT_TAB_SRAM
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+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
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+#else
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+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
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+#endif
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+}
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+
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+/**
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+ * @brief Update SystemCoreClock variable according to Clock Register Values.
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+ * The SystemCoreClock variable contains the core clock (HCLK), it can
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+ * be used by the user application to setup the SysTick timer or configure
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+ * other parameters.
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+ *
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+ * @note Each time the core clock (HCLK) changes, this function must be called
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+ * to update SystemCoreClock variable value. Otherwise, any configuration
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+ * based on this variable will be incorrect.
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+ *
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+ * @note - The system frequency computed by this function is not the real
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+ * frequency in the chip. It is calculated based on the predefined
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+ * constant and the selected clock source:
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+ *
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+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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+ *
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+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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+ *
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+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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+ * or HSI_VALUE(*) multiplied by the PLL factors.
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+ *
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+ * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
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+ * 8 MHz) but the real value may vary depending on the variations
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+ * in voltage and temperature.
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+ *
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+ * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
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+ * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
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+ * that HSE_VALUE is same as the real frequency of the crystal used.
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+ * Otherwise, this function may have wrong result.
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+ *
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+ * - The result of this function could be not correct when using fractional
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+ * value for HSE crystal.
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+ * @param None
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+ * @retval None
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+ */
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+void SystemCoreClockUpdate (void)
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+{
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+ uint32_t tmp = 0, pllmull = 0, pllsource = 0;
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+
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+#ifdef STM32F10X_CL
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+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
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+#endif /* STM32F10X_CL */
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+
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+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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+ uint32_t prediv1factor = 0;
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+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
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+
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+ /* Get SYSCLK source -------------------------------------------------------*/
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+ tmp = RCC->CFGR & RCC_CFGR_SWS;
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+
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+ switch (tmp)
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+ {
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+ case 0x00: /* HSI used as system clock */
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+ SystemCoreClock = HSI_VALUE;
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+ break;
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+ case 0x04: /* HSE used as system clock */
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+ SystemCoreClock = HSE_VALUE;
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+ break;
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+ case 0x08: /* PLL used as system clock */
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+
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+ /* Get PLL clock source and multiplication factor ----------------------*/
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+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
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+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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+
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+#ifndef STM32F10X_CL
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+ pllmull = ( pllmull >> 18) + 2;
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+
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+ if (pllsource == 0x00)
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+ {
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+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
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+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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+ }
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+ else
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+ {
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+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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+ /* HSE oscillator clock selected as PREDIV1 clock entry */
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+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
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+ #else
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+ /* HSE selected as PLL clock entry */
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+ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
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+ {/* HSE oscillator clock divided by 2 */
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+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
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+ }
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+ else
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+ {
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+ SystemCoreClock = HSE_VALUE * pllmull;
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+ }
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+ #endif
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+ }
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+#else
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+ pllmull = pllmull >> 18;
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+
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+ if (pllmull != 0x0D)
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+ {
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+ pllmull += 2;
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+ }
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+ else
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+ { /* PLL multiplication factor = PLL input clock * 6.5 */
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+ pllmull = 13 / 2;
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+ }
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+
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+ if (pllsource == 0x00)
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+ {
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+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
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+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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+ }
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+ else
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+ {/* PREDIV1 selected as PLL clock entry */
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+
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+ /* Get PREDIV1 clock source and division factor */
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+ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
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+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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+
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|
+ if (prediv1source == 0)
|
|
|
+ {
|
|
|
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
|
|
|
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {/* PLL2 clock selected as PREDIV1 clock entry */
|
|
|
+
|
|
|
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */
|
|
|
+ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
|
|
|
+ pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
|
|
|
+ SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
|
|
|
+ }
|
|
|
+ }
|
|
|
+#endif /* STM32F10X_CL */
|
|
|
+ break;
|
|
|
+
|
|
|
+ default:
|
|
|
+ SystemCoreClock = HSI_VALUE;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Compute HCLK clock frequency ----------------*/
|
|
|
+ /* Get HCLK prescaler */
|
|
|
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
|
|
+ /* HCLK clock frequency */
|
|
|
+ SystemCoreClock >>= tmp;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
|
|
|
+ * @param None
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+static void SetSysClock(void)
|
|
|
+{
|
|
|
+#ifdef SYSCLK_FREQ_HSE
|
|
|
+ SetSysClockToHSE();
|
|
|
+#elif defined SYSCLK_FREQ_24MHz
|
|
|
+ SetSysClockTo24();
|
|
|
+#elif defined SYSCLK_FREQ_36MHz
|
|
|
+ SetSysClockTo36();
|
|
|
+#elif defined SYSCLK_FREQ_48MHz
|
|
|
+ SetSysClockTo48();
|
|
|
+#elif defined SYSCLK_FREQ_56MHz
|
|
|
+ SetSysClockTo56();
|
|
|
+#elif defined SYSCLK_FREQ_72MHz
|
|
|
+ SetSysClockTo72();
|
|
|
+#endif
|
|
|
+
|
|
|
+ /* If none of the define above is enabled, the HSI is used as System clock
|
|
|
+ source (default after reset) */
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Setup the external memory controller. Called in startup_stm32f10x.s
|
|
|
+ * before jump to __main
|
|
|
+ * @param None
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+#ifdef DATA_IN_ExtSRAM
|
|
|
+/**
|
|
|
+ * @brief Setup the external memory controller.
|
|
|
+ * Called in startup_stm32f10x_xx.s/.c before jump to main.
|
|
|
+ * This function configures the external SRAM mounted on STM3210E-EVAL
|
|
|
+ * board (STM32 High density devices). This SRAM will be used as program
|
|
|
+ * data memory (including heap and stack).
|
|
|
+ * @param None
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+void SystemInit_ExtMemCtl(void)
|
|
|
+{
|
|
|
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
|
|
|
+ required, then adjust the Register Addresses */
|
|
|
+
|
|
|
+ /* Enable FSMC clock */
|
|
|
+ RCC->AHBENR = 0x00000114;
|
|
|
+
|
|
|
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
|
|
|
+ RCC->APB2ENR = 0x000001E0;
|
|
|
+
|
|
|
+/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
|
|
|
+/*---------------- SRAM Address lines configuration -------------------------*/
|
|
|
+/*---------------- NOE and NWE configuration --------------------------------*/
|
|
|
+/*---------------- NE3 configuration ----------------------------------------*/
|
|
|
+/*---------------- NBL0, NBL1 configuration ---------------------------------*/
|
|
|
+
|
|
|
+ GPIOD->CRL = 0x44BB44BB;
|
|
|
+ GPIOD->CRH = 0xBBBBBBBB;
|
|
|
+
|
|
|
+ GPIOE->CRL = 0xB44444BB;
|
|
|
+ GPIOE->CRH = 0xBBBBBBBB;
|
|
|
+
|
|
|
+ GPIOF->CRL = 0x44BBBBBB;
|
|
|
+ GPIOF->CRH = 0xBBBB4444;
|
|
|
+
|
|
|
+ GPIOG->CRL = 0x44BBBBBB;
|
|
|
+ GPIOG->CRH = 0x44444B44;
|
|
|
+
|
|
|
+/*---------------- FSMC Configuration ---------------------------------------*/
|
|
|
+/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
|
|
|
+
|
|
|
+ FSMC_Bank1->BTCR[4] = 0x00001011;
|
|
|
+ FSMC_Bank1->BTCR[5] = 0x00000200;
|
|
|
+}
|
|
|
+#endif /* DATA_IN_ExtSRAM */
|
|
|
+
|
|
|
+#ifdef SYSCLK_FREQ_HSE
|
|
|
+/**
|
|
|
+ * @brief Selects HSE as System clock source and configure HCLK, PCLK2
|
|
|
+ * and PCLK1 prescalers.
|
|
|
+ * @note This function should be used only after reset.
|
|
|
+ * @param None
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+static void SetSysClockToHSE(void)
|
|
|
+{
|
|
|
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
+
|
|
|
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
|
|
+ /* Enable HSE */
|
|
|
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
|
|
+
|
|
|
+ /* Wait till HSE is ready and if Time out is reached exit */
|
|
|
+ do
|
|
|
+ {
|
|
|
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
|
|
+ StartUpCounter++;
|
|
|
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
+
|
|
|
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
|
|
+ {
|
|
|
+ HSEStatus = (uint32_t)0x01;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ HSEStatus = (uint32_t)0x00;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (HSEStatus == (uint32_t)0x01)
|
|
|
+ {
|
|
|
+
|
|
|
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
|
|
|
+ /* Enable Prefetch Buffer */
|
|
|
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
|
|
|
+
|
|
|
+ /* Flash 0 wait state */
|
|
|
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
|
|
+
|
|
|
+#ifndef STM32F10X_CL
|
|
|
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
|
|
|
+#else
|
|
|
+ if (HSE_VALUE <= 24000000)
|
|
|
+ {
|
|
|
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
|
|
|
+ }
|
|
|
+#endif /* STM32F10X_CL */
|
|
|
+#endif
|
|
|
+
|
|
|
+ /* HCLK = SYSCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
|
|
+
|
|
|
+ /* PCLK2 = HCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
|
|
+
|
|
|
+ /* PCLK1 = HCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
|
|
+
|
|
|
+ /* Select HSE as system clock source */
|
|
|
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
|
|
|
+
|
|
|
+ /* Wait till HSE is used as system clock source */
|
|
|
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
|
|
|
+ {
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else
|
|
|
+ { /* If HSE fails to start-up, the application will have wrong clock
|
|
|
+ configuration. User can add here some code to deal with this error */
|
|
|
+ }
|
|
|
+}
|
|
|
+#elif defined SYSCLK_FREQ_24MHz
|
|
|
+/**
|
|
|
+ * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
|
|
|
+ * and PCLK1 prescalers.
|
|
|
+ * @note This function should be used only after reset.
|
|
|
+ * @param None
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+static void SetSysClockTo24(void)
|
|
|
+{
|
|
|
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
+
|
|
|
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
|
|
+ /* Enable HSE */
|
|
|
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
|
|
+
|
|
|
+ /* Wait till HSE is ready and if Time out is reached exit */
|
|
|
+ do
|
|
|
+ {
|
|
|
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
|
|
+ StartUpCounter++;
|
|
|
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
+
|
|
|
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
|
|
+ {
|
|
|
+ HSEStatus = (uint32_t)0x01;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ HSEStatus = (uint32_t)0x00;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (HSEStatus == (uint32_t)0x01)
|
|
|
+ {
|
|
|
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
|
|
|
+ /* Enable Prefetch Buffer */
|
|
|
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
|
|
|
+
|
|
|
+ /* Flash 0 wait state */
|
|
|
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
|
|
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
|
|
|
+#endif
|
|
|
+
|
|
|
+ /* HCLK = SYSCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
|
|
+
|
|
|
+ /* PCLK2 = HCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
|
|
+
|
|
|
+ /* PCLK1 = HCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
|
|
+
|
|
|
+#ifdef STM32F10X_CL
|
|
|
+ /* Configure PLLs ------------------------------------------------------*/
|
|
|
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
|
|
|
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
|
|
|
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
|
|
|
+ RCC_CFGR_PLLMULL6);
|
|
|
+
|
|
|
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
|
|
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
|
|
|
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
|
|
|
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
|
|
|
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
|
|
|
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
|
|
|
+
|
|
|
+ /* Enable PLL2 */
|
|
|
+ RCC->CR |= RCC_CR_PLL2ON;
|
|
|
+ /* Wait till PLL2 is ready */
|
|
|
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
|
|
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
|
|
|
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
|
|
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
|
|
|
+#else
|
|
|
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
|
|
|
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
|
|
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
|
|
|
+#endif /* STM32F10X_CL */
|
|
|
+
|
|
|
+ /* Enable PLL */
|
|
|
+ RCC->CR |= RCC_CR_PLLON;
|
|
|
+
|
|
|
+ /* Wait till PLL is ready */
|
|
|
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Select PLL as system clock source */
|
|
|
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
|
|
+
|
|
|
+ /* Wait till PLL is used as system clock source */
|
|
|
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
|
|
+ {
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else
|
|
|
+ { /* If HSE fails to start-up, the application will have wrong clock
|
|
|
+ configuration. User can add here some code to deal with this error */
|
|
|
+ }
|
|
|
+}
|
|
|
+#elif defined SYSCLK_FREQ_36MHz
|
|
|
+/**
|
|
|
+ * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
|
|
|
+ * and PCLK1 prescalers.
|
|
|
+ * @note This function should be used only after reset.
|
|
|
+ * @param None
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+static void SetSysClockTo36(void)
|
|
|
+{
|
|
|
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
+
|
|
|
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
|
|
+ /* Enable HSE */
|
|
|
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
|
|
+
|
|
|
+ /* Wait till HSE is ready and if Time out is reached exit */
|
|
|
+ do
|
|
|
+ {
|
|
|
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
|
|
+ StartUpCounter++;
|
|
|
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
+
|
|
|
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
|
|
+ {
|
|
|
+ HSEStatus = (uint32_t)0x01;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ HSEStatus = (uint32_t)0x00;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (HSEStatus == (uint32_t)0x01)
|
|
|
+ {
|
|
|
+ /* Enable Prefetch Buffer */
|
|
|
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
|
|
|
+
|
|
|
+ /* Flash 1 wait state */
|
|
|
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
|
|
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
|
|
|
+
|
|
|
+ /* HCLK = SYSCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
|
|
+
|
|
|
+ /* PCLK2 = HCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
|
|
+
|
|
|
+ /* PCLK1 = HCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
|
|
+
|
|
|
+#ifdef STM32F10X_CL
|
|
|
+ /* Configure PLLs ------------------------------------------------------*/
|
|
|
+
|
|
|
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
|
|
|
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
|
|
|
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
|
|
|
+ RCC_CFGR_PLLMULL9);
|
|
|
+
|
|
|
+ /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
|
|
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
|
|
|
+
|
|
|
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
|
|
|
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
|
|
|
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
|
|
|
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
|
|
|
+
|
|
|
+ /* Enable PLL2 */
|
|
|
+ RCC->CR |= RCC_CR_PLL2ON;
|
|
|
+ /* Wait till PLL2 is ready */
|
|
|
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+
|
|
|
+#else
|
|
|
+ /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
|
|
|
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
|
|
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
|
|
|
+#endif /* STM32F10X_CL */
|
|
|
+
|
|
|
+ /* Enable PLL */
|
|
|
+ RCC->CR |= RCC_CR_PLLON;
|
|
|
+
|
|
|
+ /* Wait till PLL is ready */
|
|
|
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Select PLL as system clock source */
|
|
|
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
|
|
+
|
|
|
+ /* Wait till PLL is used as system clock source */
|
|
|
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
|
|
+ {
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else
|
|
|
+ { /* If HSE fails to start-up, the application will have wrong clock
|
|
|
+ configuration. User can add here some code to deal with this error */
|
|
|
+ }
|
|
|
+}
|
|
|
+#elif defined SYSCLK_FREQ_48MHz
|
|
|
+/**
|
|
|
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
|
|
|
+ * and PCLK1 prescalers.
|
|
|
+ * @note This function should be used only after reset.
|
|
|
+ * @param None
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+static void SetSysClockTo48(void)
|
|
|
+{
|
|
|
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
+
|
|
|
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
|
|
+ /* Enable HSE */
|
|
|
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
|
|
+
|
|
|
+ /* Wait till HSE is ready and if Time out is reached exit */
|
|
|
+ do
|
|
|
+ {
|
|
|
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
|
|
+ StartUpCounter++;
|
|
|
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
+
|
|
|
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
|
|
+ {
|
|
|
+ HSEStatus = (uint32_t)0x01;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ HSEStatus = (uint32_t)0x00;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (HSEStatus == (uint32_t)0x01)
|
|
|
+ {
|
|
|
+ /* Enable Prefetch Buffer */
|
|
|
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
|
|
|
+
|
|
|
+ /* Flash 1 wait state */
|
|
|
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
|
|
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
|
|
|
+
|
|
|
+ /* HCLK = SYSCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
|
|
+
|
|
|
+ /* PCLK2 = HCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
|
|
+
|
|
|
+ /* PCLK1 = HCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
|
|
+
|
|
|
+#ifdef STM32F10X_CL
|
|
|
+ /* Configure PLLs ------------------------------------------------------*/
|
|
|
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
|
|
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
|
|
+
|
|
|
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
|
|
|
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
|
|
|
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
|
|
|
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
|
|
|
+
|
|
|
+ /* Enable PLL2 */
|
|
|
+ RCC->CR |= RCC_CR_PLL2ON;
|
|
|
+ /* Wait till PLL2 is ready */
|
|
|
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+
|
|
|
+
|
|
|
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
|
|
|
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
|
|
|
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
|
|
|
+ RCC_CFGR_PLLMULL6);
|
|
|
+#else
|
|
|
+ /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
|
|
|
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
|
|
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
|
|
|
+#endif /* STM32F10X_CL */
|
|
|
+
|
|
|
+ /* Enable PLL */
|
|
|
+ RCC->CR |= RCC_CR_PLLON;
|
|
|
+
|
|
|
+ /* Wait till PLL is ready */
|
|
|
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Select PLL as system clock source */
|
|
|
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
|
|
+
|
|
|
+ /* Wait till PLL is used as system clock source */
|
|
|
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
|
|
+ {
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else
|
|
|
+ { /* If HSE fails to start-up, the application will have wrong clock
|
|
|
+ configuration. User can add here some code to deal with this error */
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+#elif defined SYSCLK_FREQ_56MHz
|
|
|
+/**
|
|
|
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
|
|
|
+ * and PCLK1 prescalers.
|
|
|
+ * @note This function should be used only after reset.
|
|
|
+ * @param None
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+static void SetSysClockTo56(void)
|
|
|
+{
|
|
|
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
+
|
|
|
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
|
|
+ /* Enable HSE */
|
|
|
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
|
|
+
|
|
|
+ /* Wait till HSE is ready and if Time out is reached exit */
|
|
|
+ do
|
|
|
+ {
|
|
|
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
|
|
+ StartUpCounter++;
|
|
|
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
+
|
|
|
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
|
|
+ {
|
|
|
+ HSEStatus = (uint32_t)0x01;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ HSEStatus = (uint32_t)0x00;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (HSEStatus == (uint32_t)0x01)
|
|
|
+ {
|
|
|
+ /* Enable Prefetch Buffer */
|
|
|
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
|
|
|
+
|
|
|
+ /* Flash 2 wait state */
|
|
|
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
|
|
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
|
|
|
+
|
|
|
+ /* HCLK = SYSCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
|
|
+
|
|
|
+ /* PCLK2 = HCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
|
|
+
|
|
|
+ /* PCLK1 = HCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
|
|
+
|
|
|
+#ifdef STM32F10X_CL
|
|
|
+ /* Configure PLLs ------------------------------------------------------*/
|
|
|
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
|
|
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
|
|
+
|
|
|
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
|
|
|
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
|
|
|
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
|
|
|
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
|
|
|
+
|
|
|
+ /* Enable PLL2 */
|
|
|
+ RCC->CR |= RCC_CR_PLL2ON;
|
|
|
+ /* Wait till PLL2 is ready */
|
|
|
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+
|
|
|
+
|
|
|
+ /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
|
|
|
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
|
|
|
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
|
|
|
+ RCC_CFGR_PLLMULL7);
|
|
|
+#else
|
|
|
+ /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
|
|
|
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
|
|
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
|
|
|
+
|
|
|
+#endif /* STM32F10X_CL */
|
|
|
+
|
|
|
+ /* Enable PLL */
|
|
|
+ RCC->CR |= RCC_CR_PLLON;
|
|
|
+
|
|
|
+ /* Wait till PLL is ready */
|
|
|
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Select PLL as system clock source */
|
|
|
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
|
|
+
|
|
|
+ /* Wait till PLL is used as system clock source */
|
|
|
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
|
|
+ {
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else
|
|
|
+ { /* If HSE fails to start-up, the application will have wrong clock
|
|
|
+ configuration. User can add here some code to deal with this error */
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+#elif defined SYSCLK_FREQ_72MHz
|
|
|
+/**
|
|
|
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
|
|
|
+ * and PCLK1 prescalers.
|
|
|
+ * @note This function should be used only after reset.
|
|
|
+ * @param None
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+static void SetSysClockTo72(void)
|
|
|
+{
|
|
|
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
+
|
|
|
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
|
|
+ /* Enable HSE */
|
|
|
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
|
|
+
|
|
|
+ /* Wait till HSE is ready and if Time out is reached exit */
|
|
|
+ do
|
|
|
+ {
|
|
|
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
|
|
+ StartUpCounter++;
|
|
|
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
+
|
|
|
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
|
|
+ {
|
|
|
+ HSEStatus = (uint32_t)0x01;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ HSEStatus = (uint32_t)0x00;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (HSEStatus == (uint32_t)0x01)
|
|
|
+ {
|
|
|
+ /* Enable Prefetch Buffer */
|
|
|
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
|
|
|
+
|
|
|
+ /* Flash 2 wait state */
|
|
|
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
|
|
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
|
|
|
+
|
|
|
+
|
|
|
+ /* HCLK = SYSCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
|
|
+
|
|
|
+ /* PCLK2 = HCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
|
|
+
|
|
|
+ /* PCLK1 = HCLK */
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
|
|
+
|
|
|
+#ifdef STM32F10X_CL
|
|
|
+ /* Configure PLLs ------------------------------------------------------*/
|
|
|
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
|
|
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
|
|
+
|
|
|
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
|
|
|
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
|
|
|
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
|
|
|
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
|
|
|
+
|
|
|
+ /* Enable PLL2 */
|
|
|
+ RCC->CR |= RCC_CR_PLL2ON;
|
|
|
+ /* Wait till PLL2 is ready */
|
|
|
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+
|
|
|
+
|
|
|
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
|
|
|
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
|
|
|
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
|
|
|
+ RCC_CFGR_PLLMULL9);
|
|
|
+#else
|
|
|
+ /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
|
|
|
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
|
|
|
+ RCC_CFGR_PLLMULL));
|
|
|
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
|
|
|
+#endif /* STM32F10X_CL */
|
|
|
+
|
|
|
+ /* Enable PLL */
|
|
|
+ RCC->CR |= RCC_CR_PLLON;
|
|
|
+
|
|
|
+ /* Wait till PLL is ready */
|
|
|
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
|
|
+ {
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Select PLL as system clock source */
|
|
|
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
|
|
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
|
|
+
|
|
|
+ /* Wait till PLL is used as system clock source */
|
|
|
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
|
|
+ {
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else
|
|
|
+ { /* If HSE fails to start-up, the application will have wrong clock
|
|
|
+ configuration. User can add here some code to deal with this error */
|
|
|
+ }
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|