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@@ -4,7 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*
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* Date Author Notes
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- * 2020-01-15 bigmagic the first version
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+ * 2020-01-15 bigmagic the first version
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+ * 2020-08-10 SummerGift support clang compiler
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*/
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#include "rtconfig.h"
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@@ -14,87 +15,87 @@
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.global __start
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-// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware
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-// loads 'kernel8.img' file in.
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+/* This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware
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+ loads 'kernel8.img' file in. */
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__start:
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- // read cpu id, stop slave cores
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- mrs x1, mpidr_el1 // MPIDR_EL1: Multi-Processor Affinity Register
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+ /* read cpu id, stop slave cores */
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+ mrs x1, mpidr_el1 /* MPIDR_EL1: Multi-Processor Affinity Register */
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and x1, x1, #3
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- cbz x1, .L__cpu_0 // .L prefix is the local label in ELF
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+ cbz x1, .L__cpu_0 /* .L prefix is the local label in ELF */
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- // cpu id > 0, stop
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- // cpu id == 0 will also goto here after returned from entry() if possible
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+ /* cpu id > 0, stop */
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+ /* cpu id == 0 will also goto here after returned from entry() if possible */
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.L__current_cpu_idle:
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wfe
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b .L__current_cpu_idle
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-.L__cpu_0: // cpu id == 0
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+.L__cpu_0: /* cpu id == 0 */
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- // set stack before our code
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+ /* set stack before our code */
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- /* Define stack pointer for current exception level */
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- // ldr x2, =EL1_stack
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- // mov sp, x2
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+ /* Define stack pointer for current exception level */
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+ /* ldr x2, =EL1_stack */
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+ /* mov sp, x2 */
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adr x1, __start
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- // set up EL1
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- mrs x0, CurrentEL // CurrentEL Register. bit 2, 3. Others reserved
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- and x0, x0, #12 // clear reserved bits
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+ /* set up EL1 */
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+ mrs x0, CurrentEL /* CurrentEL Register. bit 2, 3. Others reserved */
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+ and x0, x0, #12 /* clear reserved bits */
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- // running at EL3?
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- cmp x0, #12 // 1100b. So, EL3
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- bne .L__not_in_el3 // 11? !EL3 -> 5:
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+ /* running at EL3? */
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+ cmp x0, #12 /* 1100b. So, EL3 */
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+ bne .L__not_in_el3 /* 11? !EL3 -> 5: */
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- // should never be executed, just for completeness. (EL3)
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+ /* should never be executed, just for completeness. (EL3) */
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mov x2, #0x5b1
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- msr scr_el3, x2 // SCR_ELn Secure Configuration Register
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+ msr scr_el3, x2 /* SCR_ELn Secure Configuration Register */
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mov x2, #0x3c9
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- msr spsr_el3, x2 // SPSR_ELn. Saved Program Status Register. 1111001001
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+ msr spsr_el3, x2 /* SPSR_ELn. Saved Program Status Register. 1111001001 */
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adr x2, .L__not_in_el3
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msr elr_el3, x2
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- eret // Exception Return: from EL3, continue from .L__not_in_el3
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+ eret /* Exception Return: from EL3, continue from .L__not_in_el3 */
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- // running at EL2 or EL1
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+/* running at EL2 or EL1 */
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.L__not_in_el3:
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- cmp x0, #4 // 0x04 0100 EL1
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- beq .L__in_el1 // EL1 -> 5:
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-
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+ cmp x0, #4 /* 0x04 0100 EL1 */
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+ beq .L__in_el1 /* EL1 -> 5: */
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+
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mrs x0, hcr_el2
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bic x0, x0, #0xff
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msr hcr_el2, x0
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- // in EL2
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- msr sp_el1, x1 // Set sp of EL1 to _start
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+ /* in EL2 */
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+ msr sp_el1, x1 /* Set sp of EL1 to _start */
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- // enable CNTP for EL1
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- mrs x0, cnthctl_el2 // Counter-timer Hypervisor Control register
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+ /* enable CNTP for EL1 */
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+ mrs x0, cnthctl_el2 /* Counter-timer Hypervisor Control register */
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orr x0, x0, #3
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msr cnthctl_el2, x0
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msr cntvoff_el2, xzr
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- // enable AArch64 in EL1
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- mov x0, #(1 << 31) // AArch64
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- orr x0, x0, #(1 << 1) // SWIO hardwired on Pi3
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+ /* enable AArch64 in EL1 */
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+ mov x0, #(1 << 31) /* AArch64 */
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+ orr x0, x0, #(1 << 1) /* SWIO hardwired on Pi3 */
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msr hcr_el2, x0
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mrs x0, hcr_el2
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- // change execution level to EL1
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+ /* change execution level to EL1 */
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mov x2, #0x3c4
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- msr spsr_el2, x2 // 1111000100
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+ msr spsr_el2, x2 /* 1111000100 */
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adr x2, .L__in_el1
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msr elr_el2, x2
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- eret // exception return. from EL2. continue from .L__in_el1
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+ eret /* exception return. from EL2. continue from .L__in_el1 */
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.L__in_el1:
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ldr x9, =PV_OFFSET
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- mov sp, x1 // in EL1. Set sp to _start
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+ mov sp, x1 /* in EL1. Set sp to _start */
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- // Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction
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- mov x1, #0x00300000 // Don't trap any SIMD/FP instructions in both EL0 and EL1
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+ /* Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction */
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+ mov x1, #0x00300000 /* Don't trap any SIMD/FP instructions in both EL0 and EL1 */
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msr cpacr_el1, x1
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- // clear bss
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+ /* clear bss */
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ldr x1, =__bss_start
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add x1, x1, x9
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ldr w2, =__bss_size
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@@ -105,8 +106,8 @@ __start:
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sub w2, w2, #1
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cbnz w2, .L__clean_bss_loop
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- // jump to C code, should not return
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-.L__jump_to_entry:
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+/* jump to C code, should not return */
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+.L__jump_to_entry:
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bl get_free_page
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mov x21, x0
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@@ -123,32 +124,32 @@ __start:
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msr ttbr1_el1, x1
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dsb sy
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- ldr x2, =0x40000000 //1G
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+ ldr x2, =0x40000000 /* map 1G memory for kernel space */
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ldr x3, =PV_OFFSET
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bl rt_hw_mmu_setup_early
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ldr x30, =after_mmu_enable
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mrs x1, sctlr_el1
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- bic x1, x1, #(3 << 3) /* dis SA, SA0 */
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- bic x1, x1, #(1 << 1) /* dis A */
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- orr x1, x1, #(1 << 12) /* I */
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- orr x1, x1, #(1 << 2) /* C */
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- orr x1, x1, #(1 << 0) /* M */
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- msr sctlr_el1, x1
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+ bic x1, x1, #(3 << 3) /* dis SA, SA0 */
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+ bic x1, x1, #(1 << 1) /* dis A */
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+ orr x1, x1, #(1 << 12) /* I */
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+ orr x1, x1, #(1 << 2) /* C */
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+ orr x1, x1, #(1 << 0) /* M */
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+ msr sctlr_el1, x1 /* enable MMU */
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+
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dsb sy
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isb sy
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- ic ialluis
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+ ic ialluis /* Invalidate all instruction caches in Inner Shareable domain to Point of Unification */
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dsb sy
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isb sy
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- tlbi vmalle1
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+ tlbi vmalle1 /* Invalidate all stage 1 translations used at EL1 with the current VMID */
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dsb sy
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isb sy
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ret
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after_mmu_enable:
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- // disable ttbr0
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- mrs x0, tcr_el1
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+ mrs x0, tcr_el1 /* disable ttbr0, only using kernel space */
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orr x0, x0, #(1 << 7)
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msr tcr_el1, x0
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msr ttbr0_el1, xzr
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@@ -157,6 +158,6 @@ after_mmu_enable:
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mov x0, #1
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msr spsel, x0
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adr x1, __start
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- mov sp, x1 // sp_el1 set to _start
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+ mov sp, x1 /* sp_el1 set to _start */
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b rtthread_startup
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SummerGift