[imxrt1060] Update 1060 sdk 2.12.1 (#6892)

更新的SDK2.12.1更新imxrt1060的驱动

bsp/imxrt/imxrt1060-nxp-evk/.config

@@ -73,6 +73,7 @@ CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
 CONFIG_RT_VER_NUM=0x50000
+
 CONFIG_RT_USING_CACHE=y
 # CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@@ -105,7 +106,39 @@ CONFIG_FINSH_USING_DESCRIPTION=y
 # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
 # CONFIG_FINSH_USING_AUTH is not set
 CONFIG_FINSH_ARG_MAX=10
-# CONFIG_RT_USING_DFS is not set
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
 # CONFIG_RT_USING_FAL is not set
 # CONFIG_RT_USING_LWP is not set
 
@@ -127,7 +160,7 @@ CONFIG_RT_USING_I2C=y
 # CONFIG_RT_I2C_DEBUG is not set
 CONFIG_RT_USING_I2C_BITOPS=y
 # CONFIG_RT_I2C_BITOPS_DEBUG is not set
-# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PHY=y
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
@@ -157,9 +190,13 @@ CONFIG_RT_USING_PIN=y
 #
 # Using USB
 #
-# CONFIG_RT_USING_USB is not set
-# CONFIG_RT_USING_USB_HOST is not set
+CONFIG_RT_USING_USB=y
+CONFIG_RT_USING_USB_HOST=y
+CONFIG_RT_USBH_MSTORAGE=y
+CONFIG_UDISK_MOUNTPOINT="/"
+# CONFIG_RT_USBH_HID is not set
 # CONFIG_RT_USING_USB_DEVICE is not set
+CONFIG_RT_USBD_THREAD_STACK_SZ=4096
 
 #
 # C/C++ and POSIX layer
@@ -192,7 +229,15 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # Network
 #
 # CONFIG_RT_USING_SAL is not set
-# CONFIG_RT_USING_NETDEV is not set
+CONFIG_RT_USING_NETDEV=y
+CONFIG_NETDEV_USING_IFCONFIG=y
+CONFIG_NETDEV_USING_PING=y
+CONFIG_NETDEV_USING_NETSTAT=y
+CONFIG_NETDEV_USING_AUTO_DEFAULT=y
+# CONFIG_NETDEV_USING_IPV6 is not set
+CONFIG_NETDEV_IPV4=1
+CONFIG_NETDEV_IPV6=0
+# CONFIG_NETDEV_IPV6_SCOPES is not set
 # CONFIG_RT_USING_LWIP is not set
 # CONFIG_RT_USING_AT is not set
 
@@ -297,6 +342,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_AGILE_FTP is not set
 # CONFIG_PKG_USING_EMBEDDEDPROTO is not set
 # CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
 # CONFIG_PKG_USING_LORA_PKT_FWD is not set
 # CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
 # CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@@ -1013,19 +1059,23 @@ CONFIG_SOC_MIMXRT1062DVL6A=y
 #
 # Onboard Peripheral Drivers
 #
-# CONFIG_BSP_USING_SDRAM is not set
+CONFIG_BSP_USING_SDRAM=y
+# CONFIG_BSP_USING_ETH is not set
 # CONFIG_BSP_USING_LCD is not set
 # CONFIG_BSP_USING_TOUCHPAD is not set
 # CONFIG_BSP_USING_LVGL is not set
+# CONFIG_BSP_USING_FS is not set
 
 #
 # On-chip Peripheral Drivers
 #
 CONFIG_BSP_USING_GPIO=y
-CONFIG_BSP_USING_I2C=y
-CONFIG_BSP_USING_I2C1=y
-CONFIG_HW_I2C1_BADURATE_100kHZ=y
-# CONFIG_HW_I2C1_BADURATE_400kHZ is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_SDIO is not set
+CONFIG_BSP_USING_USB=y
+CONFIG_BSP_USB0_HOST=y
+# CONFIG_BSP_USB1_HOST is not set
+# CONFIG_BSP_USING_I2C is not set
 CONFIG_BSP_USING_LPUART=y
 CONFIG_BSP_USING_LPUART1=y
 # CONFIG_BSP_USING_LPUART2 is not set
@@ -1035,7 +1085,7 @@ CONFIG_BSP_USING_LPUART1=y
 # CONFIG_BSP_USING_LPUART6 is not set
 # CONFIG_BSP_USING_LPUART7 is not set
 # CONFIG_BSP_USING_LPUART8 is not set
-CONFIG_BSP_USING_PXP=y
+# CONFIG_BSP_USING_PXP is not set
 CONFIG_BSP_USING_CACHE=y
 
 #

bsp/imxrt/imxrt1060-nxp-evk/applications/main.c

@@ -14,7 +14,7 @@
 #include "core_cm7.h"
 
 /* defined the LED pin: GPIO1_IO9 */
-#define LED0_PIN               GET_PIN(1, 8)
+#define LED0_PIN               GET_PIN(1, 9)
 
 int main(void)
 {

bsp/imxrt/imxrt1060-nxp-evk/applications/mnt.c

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-09-19     Gavin        first version
+ *
+ */
+
+#include <rtthread.h>
+#ifdef RT_USING_DFS_RAMFS
+#include <dfs_fs.h>
+
+extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size);
+
+int mnt_init(void)
+{
+    rt_uint8_t *pool = RT_NULL;
+    rt_size_t size = 8*1024*1024;
+
+    pool = rt_malloc(size);
+    if (pool == RT_NULL)
+        return 0;
+
+    if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0)
+        rt_kprintf("RAM file system initializated!\n");
+    else
+        rt_kprintf("RAM file system initializate failed!\n");
+
+    return 0;
+}
+INIT_ENV_EXPORT(mnt_init);
+#endif
+
+#ifdef BSP_USING_SDCARD_FATFS
+#include <dfs_fs.h>
+#include <dfs_file.h>
+#define DBG_TAG "app.filesystem"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
+static int filesystem_mount(void)
+{
+    while(rt_device_find("sd0") == RT_NULL)
+    {
+        rt_thread_mdelay(1);
+    }
+
+    int ret = dfs_mount("sd0", "/", "elm", 0, 0);
+    if (ret != 0)
+    {
+        rt_kprintf("ret: %d\n",ret);
+        LOG_E("sd0 mount to '/' failed!");
+        return ret;
+    }
+
+    return RT_EOK;
+}
+INIT_ENV_EXPORT(filesystem_mount);
+#endif

bsp/imxrt/imxrt1060-nxp-evk/board/Kconfig

@@ -23,6 +23,44 @@ menu "Onboard Peripheral Drivers"
         bool "Enable SDRAM"
         default n
 
+    menuconfig BSP_USING_ETH
+        bool "Enable Ethernet"
+        select RT_USING_NETDEV
+        select RT_USING_LWIP
+        default n
+
+    if BSP_USING_ETH
+        config BSP_USING_PHY
+            select RT_USING_PHY
+            bool "Enable ethernet phy"
+            default y
+
+        if BSP_USING_PHY
+            config PHY_USING_KSZ8081
+                bool "i.MX RT1060EVK uses ksz8081 phy"
+                default y
+
+            if PHY_USING_KSZ8081
+                config PHY_KSZ8081_ADDRESS
+                int "Specify address of phy device"
+                default 2
+
+                config PHY_RESET_KSZ8081_PORT
+                    int "indicate port of reset"
+                    default 1
+
+                config PHY_RESET_KSZ8081_PIN
+                    int "indicate pin of reset"
+                    default 9
+
+                config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
+                    bool "Enable the PHY ksz8081 RMII50M mode"
+                    depends on PHY_USING_KSZ8081
+                    default y
+            endif
+        endif
+    endif
+
     menuconfig BSP_USING_LCD
         bool "Enable LCD"
         default n
@@ -108,6 +146,20 @@ menu "Onboard Peripheral Drivers"
             select PKG_USING_GUI_GUIDER_DEMO
             default n
     endif
+
+    menuconfig BSP_USING_FS
+        bool "Enable File System"
+        select RT_USING_DFS_DEVFS
+        select RT_USING_DFS
+        default n
+
+        if BSP_USING_FS
+            config BSP_USING_SDCARD_FATFS
+                bool "Enable SDCARD (FATFS)"
+                select BSP_USING_SDIO
+                select RT_USING_DFS_ELMFAT
+                default n
+        endif
 endmenu
 
 menu "On-chip Peripheral Drivers"
@@ -117,6 +169,40 @@ menu "On-chip Peripheral Drivers"
         select RT_USING_PIN
         default y
 
+    config BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+
+    config BSP_USING_SDIO
+        bool "Enable SDIO"
+        select RT_USING_SDIO
+        select RT_USING_DFS
+        default n
+
+        if BSP_USING_SDIO
+            config CODE_STORED_ON_SDCARD
+                bool "Enable Code STORED On SDCARD"
+                default n
+                help 
+                    "SD CARD work as boot devive"				
+        endif
+
+    config BSP_USING_USB
+        bool "Enable USB"
+        select RT_USING_USB_HOST
+        default n
+		
+        if BSP_USING_USB
+        config BSP_USB0_HOST
+            bool "Enable USB0"
+            default n
+
+        config BSP_USB1_HOST
+            bool "Enable USB1"
+            default n	
+        endif
+
     menuconfig BSP_USING_I2C
         bool "Enable I2C"
         select RT_USING_I2C

bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/MCUX_Config.mex

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding= "UTF-8" ?>
-<configuration name="MIMXRT1062xxxxA" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_1.8 http://mcuxpresso.nxp.com/XSD/mex_configuration_1.8.xsd" uuid="22c3ac06-9f09-4f14-9c74-93bdfd15fb8a" version="1.8" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_1.8" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+<configuration name="MIMXRT1062xxxxA" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_12 http://mcuxpresso.nxp.com/XSD/mex_configuration_12.xsd" uuid="22c3ac06-9f09-4f14-9c74-93bdfd15fb8a" version="12" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_12" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
    <common>
       <processor>MIMXRT1062xxxxA</processor>
       <package>MIMXRT1062DVL6A</package>
@@ -14,11 +14,16 @@
       <validate_boot_init_only>true</validate_boot_init_only>
       <generate_extended_information>false</generate_extended_information>
       <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
    </preferences>
    <tools>
-      <pins name="Pins" version="8.0" enabled="true" update_project_code="true">
+      <pins name="Pins" version="12.0" enabled="true" update_project_code="true">
          <pins_profile>
-            <processor_version>0.8.11</processor_version>
+            <processor_version>12.0.1</processor_version>
+            <pin_labels>
+               <pin_label pin_num="F13" pin_signal="GPIO_AD_B0_08" label="GPIO1_08" identifier="gpio1_08"/>
+            </pin_labels>
             <power_domains/>
          </pins_profile>
          <functions_list>
@@ -35,17 +40,17 @@
                         <data>true</data>
                      </feature>
                   </dependency>
-                  <dependency resourceType="Peripheral" resourceId="ARM" description="Peripheral ARM is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
-                     <feature name="initialized" evaluation="equal">
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
                         <data>true</data>
                      </feature>
                   </dependency>
-                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
                      <feature name="enabled" evaluation="equal" configuration="core0">
                         <data>true</data>
                      </feature>
                   </dependency>
-                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
                      <feature name="enabled" evaluation="equal" configuration="core0">
                         <data>true</data>
                      </feature>
@@ -78,21 +83,23 @@
                         <pin_feature name="slew_rate" value="Slow"/>
                      </pin_features>
                   </pin>
-                  <pin peripheral="ARM" signal="arm_trace_swo" pin_num="G13" pin_signal="GPIO_AD_B0_10">
+                  <pin peripheral="GPIO1" signal="gpio_io, 08" pin_num="F13" pin_signal="GPIO_AD_B0_08">
                      <pin_features>
-                        <pin_feature name="slew_rate" value="Fast"/>
+                        <pin_feature name="direction" value="OUTPUT"/>
                      </pin_features>
                   </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 09" pin_num="F14" pin_signal="GPIO_AD_B0_09"/>
+                  <pin peripheral="GPIO1" signal="gpio_io, 10" pin_num="G13" pin_signal="GPIO_AD_B0_10"/>
                </pins>
             </function>
          </functions_list>
       </pins>
-      <clocks name="Clocks" version="7.0" enabled="true" update_project_code="true">
+      <clocks name="Clocks" version="10.0" enabled="true" update_project_code="true">
          <clocks_profile>
-            <processor_version>0.8.11</processor_version>
+            <processor_version>12.0.1</processor_version>
          </clocks_profile>
          <clock_configurations>
-            <clock_configuration name="BOARD_BootClockRUN">
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
                <description></description>
                <options/>
                <dependencies>
@@ -157,9 +164,7 @@
                   <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
                   <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
                   <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
-                  <clock_output id="ENET1_TX_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
                   <clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
-                  <clock_output id="ENET2_TX_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
                   <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
                   <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
                   <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
@@ -240,7 +245,7 @@
       </clocks>
       <dcdx name="DCDx" version="3.0" enabled="true" update_project_code="true">
          <dcdx_profile>
-            <processor_version>0.8.11</processor_version>
+            <processor_version>12.0.1</processor_version>
             <output_format>c_array</output_format>
          </dcdx_profile>
          <dcdx_configurations>
@@ -392,8 +397,6 @@
          <tee_profile>
             <processor_version>N/A</processor_version>
          </tee_profile>
-         <global_options/>
-         <user_memory_regions/>
       </tee>
    </tools>
 </configuration>

bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/clock_config.c

@@ -1,3 +1,10 @@
+/*
+ * Copyright 2018-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
 /*
  * How to setup clock using clock driver functions:
  *
@@ -15,11 +22,11 @@
 
 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 !!GlobalInfo
-product: Clocks v7.0
+product: Clocks v8.0
 processor: MIMXRT1062xxxxA
 package_id: MIMXRT1062DVL6A
 mcu_data: ksdk2_0
-processor_version: 8.0.3
+processor_version: 10.0.0
 board: MIMXRT1060-EVK
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
 
@@ -58,9 +65,7 @@ outputs:
 - {id: CLK_1M.outFreq, value: 1 MHz}
 - {id: CLK_24M.outFreq, value: 24 MHz}
 - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
-- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
 - {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
-- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz}
 - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
 - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
@@ -100,6 +105,8 @@ settings:
 - {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
 - {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
 - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
+- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
 - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
 - {id: CCM.SEMC_PODF.scale, value: '8'}
@@ -128,8 +135,8 @@ settings:
 - {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
 - {id: CCM_ANALOG.PLL5.num, value: '0'}
 - {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
-- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
-- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
 - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
 - {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
@@ -491,14 +498,10 @@ void BOARD_BootClockRUN(void)
     IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
     /* Set MQS configuration. */
     IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
-    /* Set ENET1 Tx clock source. */
-    IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
-    /* Set ENET2 Tx clock source. */
-#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0)))
-    IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false);
-#else
-    IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false);
-#endif
+    /* Set ENET Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+    /* Set ENET2 Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
     /* Set GPT1 High frequency reference clock source. */
     IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
     /* Set GPT2 High frequency reference clock source. */

bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/clock_config.h

@@ -1,3 +1,10 @@
+/*
+ * Copyright 2018-2020 ,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
 #ifndef _CLOCK_CONFIG_H_
 #define _CLOCK_CONFIG_H_
 
@@ -44,11 +51,13 @@ void BOARD_InitBootClocks(void);
 #define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
 #define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
 #define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               12000000UL
-#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK               2400000UL
 #define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK             1200000UL
-#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK               1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK              0UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK               0UL
 #define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL
 #define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
 #define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
 #define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           30000000UL
 #define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT          130909090UL

bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.c

@@ -32,281 +32,281 @@ processor: MIMXRT1062xxxxA
 package_id: MIMXRT1062DVL6A
 mcu_data: ksdk2_0
 processor_version: 0.0.0
-board: MIMXRT1060-EVKB
+board: MIMXRT1060-EVK
 output_format: c_array
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
 /* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
 const uint8_t dcd_data[] = {
-    /* HEADER */
-    /* Tag */
-    0xD2,
-    /* Image Length */
-    0x04, 0x10,
-    /* Version */
-    0x41,
+	/* HEADER */
+	/* Tag */
+	0xD2,
+	/* Image Length */
+	0x04, 0x10,
+	/* Version */
+	0x41,
 
-    /* COMMANDS */
+	/* COMMANDS */
 
-    /* group: 'Imported Commands' */
-    /* #1.1-113, command header bytes for merged 'Write - value' command */
-    0xCC, 0x03, 0x8C, 0x04,
-    /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
-    0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
-    /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
-    0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
-    /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
-    0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
-    /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
-    0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
-    /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
-    0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
-    /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
-    0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
-    /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
-    0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
-    /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
-    0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
-    /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */
-    0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B,
-    /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */
-    0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40,
-    /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
-    /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
-    /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
-    /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
-    /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
-    /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
-    /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
-    /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
-    /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
-    /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
-    /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
-    /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
-    /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
-    /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
-    /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
-    /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
-    /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
-    /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
-    /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
-    /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
-    /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
-    /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
-    /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
-    /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
-    /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
-    /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
-    /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
-    /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
-    /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
-    /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
-    /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
-    /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
-    /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
-    /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
-    /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
-    /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
-    /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
-    /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
-    /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
-    0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
-    /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */
-    0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10,
-    /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */
-    0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9,
-    /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
-    0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
-    /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
-    0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
-    /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
-    0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
-    /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
-    0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
-    /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
-    0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
-    /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
-    0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
-    /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */
-    0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
-    /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */
-    0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
-    /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */
-    0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19,
-    /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */
-    0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17,
-    /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */
-    0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B,
-    /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */
-    0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21,
-    /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */
-    0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8,
-    /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */
-    0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31,
-    /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
-    0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
-    /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
-    0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
-    /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
-    0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
-    /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
-    0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
-    /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
-    0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
-    /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
-    0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
-    /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
-    0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
-    /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
-    0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
-    /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
-    0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
-    /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
-    0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
-    /* #3.1-2, command header bytes for merged 'Write - value' command */
-    0xCC, 0x00, 0x14, 0x04,
-    /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
-    0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
-    /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
-    0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
-    /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
-    0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
-    /* #5.1-2, command header bytes for merged 'Write - value' command */
-    0xCC, 0x00, 0x14, 0x04,
-    /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
-    0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
-    /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
-    0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
-    /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
-    0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
-    /* #7.1-3, command header bytes for merged 'Write - value' command */
-    0xCC, 0x00, 0x1C, 0x04,
-    /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
-    0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33,
-    /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
-    0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
-    /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
-    0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
-    /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
-    0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
-    /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
-    0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
-    };
+	/* group: 'Imported Commands' */
+	/* #1.1-113, command header bytes for merged 'Write - value' command */
+	0xCC, 0x03, 0x8C, 0x04,
+	/* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
+	0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
+	/* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
+	0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
+	/* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
+	0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
+	/* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
+	0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
+	/* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
+	0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
+	/* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
+	0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
+	/* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
+	0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
+	/* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
+	0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
+	/* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */
+	0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B,
+	/* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */
+	0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40,
+	/* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
+	/* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
+	/* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
+	/* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
+	/* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
+	/* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
+	/* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
+	/* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
+	/* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
+	/* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
+	/* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
+	/* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
+	/* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
+	/* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
+	/* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
+	/* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
+	/* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
+	/* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
+	/* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
+	/* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
+	/* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
+	/* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
+	/* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
+	/* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
+	/* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
+	/* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
+	/* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
+	/* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
+	/* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
+	/* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
+	/* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
+	/* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
+	/* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
+	/* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
+	/* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
+	/* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
+	/* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
+	/* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
+	/* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
+	0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
+	/* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */
+	0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10,
+	/* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */
+	0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9,
+	/* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
+	0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
+	/* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
+	0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
+	/* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
+	0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
+	/* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
+	0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
+	/* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
+	0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
+	/* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
+	0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
+	/* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */
+	0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
+	/* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */
+	0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
+	/* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */
+	0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19,
+	/* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */
+	0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17,
+	/* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */
+	0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B,
+	/* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */
+	0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21,
+	/* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */
+	0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8,
+	/* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */
+	0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31,
+	/* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
+	0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
+	/* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
+	0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
+	/* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
+	0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
+	/* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
+	0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
+	/* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
+	0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
+	/* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
+	0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
+	/* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
+	0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
+	/* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+	0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+	/* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
+	0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
+	/* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+	0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+	/* #3.1-2, command header bytes for merged 'Write - value' command */
+	0xCC, 0x00, 0x14, 0x04,
+	/* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+	0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+	/* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
+	0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
+	/* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+	0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+	/* #5.1-2, command header bytes for merged 'Write - value' command */
+	0xCC, 0x00, 0x14, 0x04,
+	/* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+	0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+	/* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
+	0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
+	/* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+	0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+	/* #7.1-3, command header bytes for merged 'Write - value' command */
+	0xCC, 0x00, 0x1C, 0x04,
+	/* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
+	0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33,
+	/* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+	0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+	/* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
+	0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
+	/* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+	0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+	/* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
+	0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
+	};
 /* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
 
 #else

bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2021 NXP
+ * Copyright 2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause

bsp/imxrt/imxrt1060-nxp-evk/board/SConscript

@@ -17,7 +17,12 @@ if GetDepend(['BSP_USING_TOUCHPAD']):
 
 CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']
 
-CPPDEFINES = ['CPU_MIMXRT1062DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1', 'FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1', 'DATA_SECTION_IS_CACHEABLE=1']
+# CPPDEFINES = ['CPU_MIMXRT1062DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1', 
+#                 'FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1','DATA_SECTION_IS_CACHEABLE=1']
+
+
+CPPDEFINES = ['CPU_MIMXRT1062DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1', 
+                'FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1','DATA_SECTION_IS_CACHEABLE=0', 'XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1']
 
 if rtconfig.PLATFORM in ['armcc', 'armclang']:
     CPPDEFINES.append('__FPU_PRESENT=1')

bsp/imxrt/imxrt1060-nxp-evk/board/board.c

@@ -31,6 +31,7 @@
 #define NVIC_PRIORITYGROUP_4         0x00000003U /*!< 4 bits for pre-emption priority
                                                       0 bits for subpriority */
 
+/* MPU configuration. */
 void BOARD_ConfigMPU(void)
 {
 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
@@ -48,10 +49,10 @@ void BOARD_ConfigMPU(void)
     uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
     uint32_t size          = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
 #elif defined(__ICCARM__) || defined(__GNUC__)
-    extern uint32_t __noncachedata_start__[];
-    extern uint32_t __noncachedata_end__[];
-    uint32_t nonCacheStart = (uint32_t)__noncachedata_start__;
-    uint32_t size          = (uint32_t)((uint32_t)__noncachedata_end__ - (uint32_t)__noncachedata_start__);
+    extern uint32_t __NCACHE_REGION_START[];
+    extern uint32_t __NCACHE_REGION_SIZE[];
+    uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
+    uint32_t size          = (uint32_t)__NCACHE_REGION_SIZE;
 #endif
     volatile uint32_t i = 0;
 
@@ -79,7 +80,7 @@ void BOARD_ConfigMPU(void)
      *      Use MACROS defined in mpu_armv7.h:
      * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
      * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
-     *  TypeExtField  IsShareable  IsCacheable  IsBufferable   Memory Attribtue    Shareability        Cache
+     *  TypeExtField  IsShareable  IsCacheable  IsBufferable   Memory Attribute    Shareability        Cache
      *     0             x           0           0             Strongly Ordered    shareable
      *     0             x           0           1              Device             shareable
      *     0             0           1           0              Normal             not shareable   Outer and inner write
@@ -772,47 +773,51 @@ static void imxrt_lcd_pins_init(void)
 #ifdef BSP_USING_ETH
 void imxrt_enet_pins_init(void)
 {
-    CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
-
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
-        0U);                             /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
-        0U);
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
-        0U);                              /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
-        0U);                              /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */
-        0U);                          /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
-        0U);                              /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
-        0U);                              /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */
-        0U);                          /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */
-        1U);                            /* Software Input On Field: Force input path of pad GPIO_B1_10 */
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */
-        0U);                          /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */
-        0U);                         /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */
-        0U);                          /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
-        0xB0A9u);                        /* Slew Rate Field: Fast Slew Rate
+  CLOCK_EnableClock(kCLOCK_Iomuxc);           /* iomuxc clock (iomuxc_clk_enable): 0x03U */
+
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,        /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_10_GPIO1_IO10,        /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_B1_04_ENET_RX_DATA00,       /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_B1_05_ENET_RX_DATA01,       /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_B1_06_ENET_RX_EN,           /* GPIO_B1_06 is configured as ENET_RX_EN */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_B1_07_ENET_TX_DATA00,       /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_B1_08_ENET_TX_DATA01,       /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_B1_09_ENET_TX_EN,           /* GPIO_B1_09 is configured as ENET_TX_EN */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_B1_10_ENET_REF_CLK,         /* GPIO_B1_10 is configured as ENET_REF_CLK */
+      1U);                                    /* Software Input On Field: Force input path of pad GPIO_B1_10 */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_B1_11_ENET_RX_ER,           /* GPIO_B1_11 is configured as ENET_RX_ER */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_40_ENET_MDC,            /* GPIO_EMC_40 is configured as ENET_MDC */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_EMC_41_ENET_MDIO,           /* GPIO_EMC_41 is configured as ENET_MDIO */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
+    (~(IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK))) /* Mask bits to zero which are setting */
+      | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U) /* GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: 0x00U */
+    );
+  IOMUXC_SetPinConfig(
+      IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,        /* GPIO_AD_B0_09 PAD functional properties : */
+      0xB0A9U);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: medium(100MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -820,9 +825,9 @@ void imxrt_enet_pins_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */
-        0xB0A9u);                        /* Slew Rate Field: Fast Slew Rate
+  IOMUXC_SetPinConfig(
+      IOMUXC_GPIO_AD_B0_10_GPIO1_IO10,        /* GPIO_AD_B0_10 PAD functional properties : */
+      0xB0A9U);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: medium(100MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -830,9 +835,9 @@ void imxrt_enet_pins_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */
-        0xB0E9u);                         /* Slew Rate Field: Fast Slew Rate
+  IOMUXC_SetPinConfig(
+      IOMUXC_GPIO_B1_04_ENET_RX_DATA00,       /* GPIO_B1_04 PAD functional properties : */
+      0xB0E9U);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -840,9 +845,9 @@ void imxrt_enet_pins_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */
-        0xB0E9u);                         /* Slew Rate Field: Fast Slew Rate
+  IOMUXC_SetPinConfig(
+      IOMUXC_GPIO_B1_05_ENET_RX_DATA01,       /* GPIO_B1_05 PAD functional properties : */
+      0xB0E9U);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -850,9 +855,9 @@ void imxrt_enet_pins_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */
-        0xB0E9u);                     /* Slew Rate Field: Fast Slew Rate
+  IOMUXC_SetPinConfig(
+      IOMUXC_GPIO_B1_06_ENET_RX_EN,           /* GPIO_B1_06 PAD functional properties : */
+      0xB0E9U);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -860,9 +865,9 @@ void imxrt_enet_pins_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */
-        0xB0E9u);                         /* Slew Rate Field: Fast Slew Rate
+  IOMUXC_SetPinConfig(
+      IOMUXC_GPIO_B1_07_ENET_TX_DATA00,       /* GPIO_B1_07 PAD functional properties : */
+      0xB0E9U);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -870,9 +875,9 @@ void imxrt_enet_pins_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */
-        0xB0E9u);                         /* Slew Rate Field: Fast Slew Rate
+  IOMUXC_SetPinConfig(
+      IOMUXC_GPIO_B1_08_ENET_TX_DATA01,       /* GPIO_B1_08 PAD functional properties : */
+      0xB0E9U);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -880,9 +885,9 @@ void imxrt_enet_pins_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */
-        0xB0E9u);                     /* Slew Rate Field: Fast Slew Rate
+  IOMUXC_SetPinConfig(
+      IOMUXC_GPIO_B1_09_ENET_TX_EN,           /* GPIO_B1_09 PAD functional properties : */
+      0xB0E9U);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -890,9 +895,9 @@ void imxrt_enet_pins_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */
-        0x31u);                         /* Slew Rate Field: Fast Slew Rate
+  IOMUXC_SetPinConfig(
+      IOMUXC_GPIO_B1_10_ENET_REF_CLK,         /* GPIO_B1_10 PAD functional properties : */
+      0x31U);                                 /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/6
                                                  Speed Field: low(50MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -900,9 +905,9 @@ void imxrt_enet_pins_init(void)
                                                  Pull / Keep Select Field: Keeper
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Down
                                                  Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */
-        0xB0E9u);                     /* Slew Rate Field: Fast Slew Rate
+  IOMUXC_SetPinConfig(
+      IOMUXC_GPIO_B1_11_ENET_RX_ER,           /* GPIO_B1_11 PAD functional properties : */
+      0xB0E9U);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -910,9 +915,9 @@ void imxrt_enet_pins_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */
-        0xB0E9u);                    /* Slew Rate Field: Fast Slew Rate
+  IOMUXC_SetPinConfig(
+      IOMUXC_GPIO_EMC_40_ENET_MDC,            /* GPIO_EMC_40 PAD functional properties : */
+      0xB0E9U);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: max(200MHz)
                                                  Open Drain Enable Field: Open Drain Disabled
@@ -920,9 +925,9 @@ void imxrt_enet_pins_init(void)
                                                  Pull / Keep Select Field: Pull
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */
-        0xB829u);                     /* Slew Rate Field: Fast Slew Rate
+  IOMUXC_SetPinConfig(
+      IOMUXC_GPIO_EMC_41_ENET_MDIO,           /* GPIO_EMC_41 PAD functional properties : */
+      0xB829U);                               /* Slew Rate Field: Fast Slew Rate
                                                  Drive Strength Field: R0/5
                                                  Speed Field: low(50MHz)
                                                  Open Drain Enable Field: Open Drain Enabled
@@ -968,6 +973,140 @@ void imxrt_phy_pins_init( void )
 }
 #endif /* BSP_USING_PHY */
 
+#ifdef BSP_USING_SDIO
+void imrt_sdio_pins_init(void)
+{
+    CLOCK_EnableClock(kCLOCK_Iomuxc);           /* iomuxc clock (iomuxc_clk_enable): 0x03U */
+
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_AD_B0_05_GPIO1_IO05,        /* GPIO_AD_B0_05 is configured as GPIO1_IO05 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_12_GPIO2_IO28,           /* GPIO_B1_12 is configured as GPIO2_IO28 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_14_USDHC1_VSELECT,       /* GPIO_B1_14 is configured as USDHC1_VSELECT */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,        /* GPIO_SD_B0_00 is configured as USDHC1_CMD */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,        /* GPIO_SD_B0_01 is configured as USDHC1_CLK */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,      /* GPIO_SD_B0_02 is configured as USDHC1_DATA0 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,      /* GPIO_SD_B0_03 is configured as USDHC1_DATA1 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,      /* GPIO_SD_B0_04 is configured as USDHC1_DATA2 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,      /* GPIO_SD_B0_05 is configured as USDHC1_DATA3 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
+        (~(IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK))) /* Mask bits to zero which are setting */
+        | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U) /* GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: 0x00U */
+        );
+    IOMUXC_GPR->GPR27 = ((IOMUXC_GPR->GPR27 &
+        (~(IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK))) /* Mask bits to zero which are setting */
+        | IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(0x00U) /* GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function: 0x00U */
+        );
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_AD_B0_05_GPIO1_IO05,        /* GPIO_AD_B0_05 PAD functional properties : */
+        0x10B0U);                               /* Slew Rate Field: Slow Slew Rate
+                                                    Drive Strength Field: R0/6
+                                                    Speed Field: medium(100MHz)
+                                                    Open Drain Enable Field: Open Drain Disabled
+                                                    Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                    Pull / Keep Select Field: Keeper
+                                                    Pull Up / Down Config. Field: 100K Ohm Pull Down
+                                                    Hyst. Enable Field: Hysteresis Disabled */
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_12_GPIO2_IO28,           /* GPIO_B1_12 PAD functional properties : */
+        0x017089U);                             /* Slew Rate Field: Fast Slew Rate
+                                                    Drive Strength Field: R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
+                                                    Speed Field: medium(100MHz)
+                                                    Open Drain Enable Field: Open Drain Disabled
+                                                    Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                    Pull / Keep Select Field: Pull
+                                                    Pull Up / Down Config. Field: 47K Ohm Pull Up
+                                                    Hyst. Enable Field: Hysteresis Enabled */
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_14_USDHC1_VSELECT,       /* GPIO_B1_14 PAD functional properties : */
+        0x0170A1U);                             /* Slew Rate Field: Fast Slew Rate
+                                                    Drive Strength Field: R0/4
+                                                    Speed Field: medium(100MHz)
+                                                    Open Drain Enable Field: Open Drain Disabled
+                                                    Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                    Pull / Keep Select Field: Pull
+                                                    Pull Up / Down Config. Field: 47K Ohm Pull Up
+                                                    Hyst. Enable Field: Hysteresis Enabled */
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,        /* GPIO_SD_B0_00 PAD functional properties : */
+        0x017089U);                             /* Slew Rate Field: Fast Slew Rate
+                                                    Drive Strength Field: R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
+                                                    Speed Field: medium(100MHz)
+                                                    Open Drain Enable Field: Open Drain Disabled
+                                                    Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                    Pull / Keep Select Field: Pull
+                                                    Pull Up / Down Config. Field: 47K Ohm Pull Up
+                                                    Hyst. Enable Field: Hysteresis Enabled */
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,        /* GPIO_SD_B0_01 PAD functional properties : */
+        0x014089U);                             /* Slew Rate Field: Fast Slew Rate
+                                                    Drive Strength Field: R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
+                                                    Speed Field: medium(100MHz)
+                                                    Open Drain Enable Field: Open Drain Disabled
+                                                    Pull / Keep Enable Field: Pull/Keeper Disabled
+                                                    Pull / Keep Select Field: Keeper
+                                                    Pull Up / Down Config. Field: 47K Ohm Pull Up
+                                                    Hyst. Enable Field: Hysteresis Enabled */
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,      /* GPIO_SD_B0_02 PAD functional properties : */
+        0x017089U);                             /* Slew Rate Field: Fast Slew Rate
+                                                    Drive Strength Field: R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
+                                                    Speed Field: medium(100MHz)
+                                                    Open Drain Enable Field: Open Drain Disabled
+                                                    Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                    Pull / Keep Select Field: Pull
+                                                    Pull Up / Down Config. Field: 47K Ohm Pull Up
+                                                    Hyst. Enable Field: Hysteresis Enabled */
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,      /* GPIO_SD_B0_03 PAD functional properties : */
+        0x017089U);                             /* Slew Rate Field: Fast Slew Rate
+                                                    Drive Strength Field: R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
+                                                    Speed Field: medium(100MHz)
+                                                    Open Drain Enable Field: Open Drain Disabled
+                                                    Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                    Pull / Keep Select Field: Pull
+                                                    Pull Up / Down Config. Field: 47K Ohm Pull Up
+                                                    Hyst. Enable Field: Hysteresis Enabled */
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,      /* GPIO_SD_B0_04 PAD functional properties : */
+        0x017089U);                             /* Slew Rate Field: Fast Slew Rate
+                                                    Drive Strength Field: R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
+                                                    Speed Field: medium(100MHz)
+                                                    Open Drain Enable Field: Open Drain Disabled
+                                                    Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                    Pull / Keep Select Field: Pull
+                                                    Pull Up / Down Config. Field: 47K Ohm Pull Up
+                                                    Hyst. Enable Field: Hysteresis Enabled */
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,      /* GPIO_SD_B0_05 PAD functional properties : */
+        0x017089U);                             /* Slew Rate Field: Fast Slew Rate
+                                                    Drive Strength Field: R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
+                                                    Speed Field: medium(100MHz)
+                                                    Open Drain Enable Field: Open Drain Disabled
+                                                    Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                    Pull / Keep Select Field: Pull
+                                                    Pull Up / Down Config. Field: 47K Ohm Pull Up
+                                                    Hyst. Enable Field: Hysteresis Enabled */
+}
+#endif
+
 /*
  * When PXP fetch images from FlexSPI flash, the default FlexSPI RX buffer
  * configuration does not meet the PXP bandwidth requirement. Reconfigure
@@ -1060,6 +1199,10 @@ void rt_hw_board_init()
     imxrt_lcd_pins_init();
 #endif
 
+#ifdef BSP_USING_SDIO
+    imrt_sdio_pins_init();
+#endif
+
 #ifdef BSP_USING_DMA
     imxrt_dma_init();
 #endif

bsp/imxrt/imxrt1060-nxp-evk/board/board.h

@@ -41,7 +41,7 @@ extern int heap_end;
 
 
 /*! @brief The board flash size */
-#define BOARD_FLASH_SIZE (0x400000U)
+#define BOARD_FLASH_SIZE (0x800000U)
 
 void rt_hw_board_init(void);
 

bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.icf

@@ -1,20 +1,22 @@
 /*
 ** ###################################################################
-**     Processors:          MIMXRT1052CVJ5B
-**                          MIMXRT1052CVL5B
-**                          MIMXRT1052DVJ6B
-**                          MIMXRT1052DVL6B
+**     Processors:          MIMXRT1062CVJ5A
+**                          MIMXRT1062CVL5A
+**                          MIMXRT1062DVJ6A
+**                          MIMXRT1062DVL6A
+**                          MIMXRT1062DVN6B
+**                          MIMXRT1062XVN5B
 **
 **     Compiler:            IAR ANSI C/C++ Compiler for ARM
-**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
-**     Version:             rev. 1.0, 2018-09-21
-**     Build:               b180921
+**     Reference manual:    IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+**     Version:             rev. 0.2, 2022-03-25
+**     Build:               b220401
 **
 **     Abstract:
 **         Linker file for the IAR ANSI C/C++ Compiler for ARM
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2022 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -25,45 +27,57 @@
 ** ###################################################################
 */
 
-define symbol m_interrupts_start       = 0x70002000;
-define symbol m_interrupts_end         = 0x700023FF;
+define symbol __ram_vector_table_size__        =  isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
+define symbol __ram_vector_table_offset__      =  isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
 
-define symbol m_text_start             = 0x70002400;
-define symbol m_text_end               = 0x73FFFFFF;
+define symbol m_interrupts_start       = 0x60002000;
+define symbol m_interrupts_end         = 0x600023FF;
 
-define symbol m_data_start             = 0x20000000;
+define symbol m_text_start             = 0x60002400;
+define symbol m_text_end               = 0x607FFFFF;
+
+define symbol m_interrupts_ram_start   = 0x20000000;
+define symbol m_interrupts_ram_end     = 0x20000000 + __ram_vector_table_offset__;
+
+define symbol m_data_start             = m_interrupts_ram_start + __ram_vector_table_size__;
 define symbol m_data_end               = 0x2001FFFF;
 
 define symbol m_data2_start            = 0x20200000;
-define symbol m_data2_end              = 0x2023FFFF;
+define symbol m_data2_end              = 0x202BFFFF;
 
-define exported symbol m_boot_hdr_conf_start = 0x70000000;
-define symbol m_boot_hdr_ivt_start           = 0x70001000;
-define symbol m_boot_hdr_boot_data_start     = 0x70001020;
-define symbol m_boot_hdr_dcd_data_start      = 0x70001030;
+define symbol m_qacode_start           = 0x00000000;
+define symbol m_qacode_end             = 0x0001FFFF;
+
+define exported symbol m_boot_hdr_conf_start = 0x60000000;
+define symbol m_boot_hdr_ivt_start           = 0x60001000;
+define symbol m_boot_hdr_boot_data_start     = 0x60001020;
+define symbol m_boot_hdr_dcd_data_start      = 0x60001030;
 
 /* Sizes */
 if (isdefinedsymbol(__stack_size__)) {
   define symbol __size_cstack__        = __stack_size__;
 } else {
-  define symbol __size_cstack__        = 0x0400;
+  define symbol __size_cstack__        = 0x2000;
 }
 
 if (isdefinedsymbol(__heap_size__)) {
   define symbol __size_heap__          = __heap_size__;
 } else {
-  define symbol __size_heap__          = 0x0400;
+  define symbol __size_heap__          = 0x2000;
 }
 
-define exported symbol __VECTOR_TABLE  = m_interrupts_start;
-define exported symbol __VECTOR_RAM    = m_interrupts_start;
-define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
+define exported symbol __NCACHE_REGION_START   = m_data2_start;
+define exported symbol __NCACHE_REGION_SIZE    = 0x0;
+
+define exported symbol __VECTOR_TABLE          = m_interrupts_start;
+define exported symbol __VECTOR_RAM            = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
 define exported symbol __RTT_HEAP_END = m_data2_end;
 
 define memory mem with size = 4G;
 define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
                           | mem:[from m_text_start to m_text_end];
-
+define region QACODE_region = mem:[from m_qacode_start to m_qacode_end];
 define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
 define region DATA2_region = mem:[from m_data2_start to m_data2_end];
 define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
@@ -73,16 +87,17 @@ define block HEAP      with alignment = 8, size = __size_heap__     { };
 define block RW        { readwrite };
 define block ZI        { zi };
 define block NCACHE_VAR    { section NonCacheable , section NonCacheable.init };
+define block QACCESS_CODE  { section CodeQuickAccess };
+define block QACCESS_DATA  { section DataQuickAccess };
 
-initialize by copy { readwrite, section .textrw };
+initialize by copy { readwrite, section .textrw, section CodeQuickAccess, section DataQuickAccess};
 do not initialize  { section .noinit };
 
 place at address mem: m_interrupts_start    { readonly section .intvec };
-
-place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
-place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
-place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
-place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
+place at address mem: m_boot_hdr_conf_start { section .boot_hdr.conf };
+place at address mem: m_boot_hdr_ivt_start { section .boot_hdr.ivt };
+place at address mem: m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
+place at address mem: m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
 
 keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
 
@@ -92,4 +107,5 @@ place in DATA_region                        { block ZI };
 place in DATA_region                        { last block HEAP };
 place in DATA_region                        { block NCACHE_VAR };
 place in CSTACK_region                      { block CSTACK };
-
+place in QACODE_region                      { block QACCESS_CODE };
+place in DATA_region                        { block QACCESS_DATA };

bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds

@@ -1,42 +1,25 @@
 /*
 ** ###################################################################
-**     Processors:          MIMXRT1052CVL5A
-**                          MIMXRT1052DVL6A
+**     Processors:          MIMXRT1062CVJ5A
+**                          MIMXRT1062CVL5A
+**                          MIMXRT1062DVJ6A
+**                          MIMXRT1062DVL6A
+**                          MIMXRT1062DVN6B
+**                          MIMXRT1062XVN5B
 **
 **     Compiler:            GNU C Compiler
-**     Reference manual:    IMXRT1050RM Rev.C, 08/2017
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b170927
+**     Reference manual:    IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+**     Version:             rev. 0.2, 2022-03-25
+**     Build:               b220401
 **
 **     Abstract:
 **         Linker file for the GNU C Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2017 NXP
-**     Redistribution and use in source and binary forms, with or without modification,
-**     are permitted provided that the following conditions are met:
+**     Copyright 2016-2022 NXP
+**     All rights reserved.
 **
-**     1. Redistributions of source code must retain the above copyright notice, this list
-**       of conditions and the following disclaimer.
-**
-**     2. Redistributions in binary form must reproduce the above copyright notice, this
-**       list of conditions and the following disclaimer in the documentation and/or
-**       other materials provided with the distribution.
-**
-**     3. Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from this
-**       software without specific prior written permission.
-**
-**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
 **     mail:                 support@nxp.com
@@ -47,60 +30,57 @@
 /* Entry Point */
 ENTRY(Reset_Handler)
 
-HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
-STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x2000;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0;
 
 /* Specify the memory areas */
 MEMORY
 {
-  m_boot_data           (RX)  : ORIGIN = 0x60000000, LENGTH = 0x00001000
-  m_image_vertor_table  (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000
-
+  m_flash_config        (RX)  : ORIGIN = 0x60000000, LENGTH = 0x00001000
+  m_ivt                 (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000
   m_interrupts          (RX)  : ORIGIN = 0x60002000, LENGTH = 0x00000400
-  m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x003FDC00
-
-  m_itcm                (RW)  : ORIGIN = 0x00000000, LENGTH = 0x00020000
-  m_dtcm                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000
-  m_ocram               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00040000
-
-  m_sdram               (RW)  : ORIGIN = 0x80000000, LENGTH = 0x01E00000
-  m_nocache             (RW)  : ORIGIN = 0x81E00000, LENGTH = 0x00200000
+  m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x007FDC00
+  m_qacode              (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00020000
+  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000
+  m_data2               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x000C0000
 }
 
 /* Define output sections */
 SECTIONS
 {
-  .boot_data :
+  __NCACHE_REGION_START = ORIGIN(m_data2);
+  __NCACHE_REGION_SIZE  = 0;
+
+  .flash_config :
   {
     . = ALIGN(4);
     __FLASH_BASE = .;
     KEEP(* (.boot_hdr.conf))     /* flash config section */
     . = ALIGN(4);
-  } > m_boot_data
+  } > m_flash_config
 
-  ivt_begin = ORIGIN(m_boot_data) + LENGTH(m_boot_data);
+  ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config);
 
-  .image_vertor_table : AT(ivt_begin)
+  .ivt : AT(ivt_begin)
   {
     . = ALIGN(4);
-    KEEP(*(.boot_hdr.ivt))
-    KEEP(*(.boot_hdr.boot_data))
-    KEEP(*(.boot_hdr.dcd_data))
+    KEEP(* (.boot_hdr.ivt))           /* ivt section */
+    KEEP(* (.boot_hdr.boot_data))     /* boot section */
+    KEEP(* (.boot_hdr.dcd_data))      /* dcd section */
     . = ALIGN(4);
-  } > m_image_vertor_table
+  } > m_ivt
 
   /* The startup code goes first into internal RAM */
   .interrupts :
   {
     __VECTOR_TABLE = .;
+    __Vectors = .;
     . = ALIGN(4);
     KEEP(*(.isr_vector))     /* Startup code */
     . = ALIGN(4);
   } > m_interrupts
 
-  __VECTOR_RAM = __VECTOR_TABLE;
-  __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
-
   /* The program code and other data goes into internal RAM */
   .text :
   {
@@ -211,6 +191,20 @@ SECTIONS
   __etext = .;    /* define a global symbol at end of code */
   __DATA_ROM = .; /* Symbol is used by startup for data initialization */
 
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
   .data : AT(__DATA_ROM)
   {
     . = ALIGN(4);
@@ -219,26 +213,38 @@ SECTIONS
     *(m_usb_dma_init_data)
     *(.data)                 /* .data sections */
     *(.data*)                /* .data* sections */
+    *(DataQuickAccess)       /* quick access data section */
     KEEP(*(.jcr*))
-    *(NonCacheable.init)
-    *(NonCacheable)
     . = ALIGN(4);
     __data_end__ = .;        /* define a global symbol at data end */
-  } > m_sdram
+  } > m_data
 
-  __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
+  __ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */
+
+  .ram_function : AT(__ram_function_flash_start)
+  {
+    . = ALIGN(32);
+    __ram_function_start__ = .;
+    *(CodeQuickAccess)
+    . = ALIGN(128);
+    __ram_function_end__ = .;
+  } > m_qacode
+
+  __NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__);
   .ncache.init : AT(__NDATA_ROM)
   {
     __noncachedata_start__ = .;   /* create a global symbol at ncache data start */
+    *(NonCacheable.init)
     . = ALIGN(4);
     __noncachedata_init_end__ = .;   /* create a global symbol at initialized ncache data end */
-  } > m_ocram
+  } > m_data
   . = __noncachedata_init_end__;
   .ncache :
   {
+    *(NonCacheable)
     . = ALIGN(4);
     __noncachedata_end__ = .;     /* define a global symbol at ncache data end */
-  } > m_ocram
+  } > m_data
 
   __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
   text_end = ORIGIN(m_text) + LENGTH(m_text);
@@ -258,26 +264,25 @@ SECTIONS
     . = ALIGN(4);
     __bss_end__ = .;
     __END_BSS = .;
-  } > m_sdram
+  } > m_data
 
-  .stack :
+    .stack :
   {
     . = ALIGN(8);
     stack_start = .;
     . += STACK_SIZE;
     stack_end = .;
     __StackTop = .;
-  } > m_sdram
+  } > m_data
 
   .RTT_HEAP :
   {
     heap_start = .;
     . = ALIGN(8);
-  } > m_sdram
+  } > m_data
 
-  PROVIDE(heap_end = ORIGIN(m_sdram) + LENGTH(m_sdram));
+  PROVIDE(heap_end = ORIGIN(m_data2) + LENGTH(m_data2));
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 
 }
-

bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.sct

@@ -60,13 +60,13 @@
 #if (defined(__stack_size__))
   #define Stack_Size                   __stack_size__
 #else
-  #define Stack_Size                   0x0400
+  #define Stack_Size                   0x2000
 #endif
 
 #if (defined(__heap_size__))
   #define Heap_Size                    __heap_size__
 #else
-  #define Heap_Size                    0x0400
+  #define Heap_Size                    0x2000
 #endif
 
 #define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))

bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_ram.icf

@@ -0,0 +1,91 @@
+/*
+** ###################################################################
+**     Processors:          MIMXRT1062CVJ5A
+**                          MIMXRT1062CVL5A
+**                          MIMXRT1062DVJ6A
+**                          MIMXRT1062DVL6A
+**                          MIMXRT1062DVN6B
+**                          MIMXRT1062XVN5B
+**
+**     Compiler:            IAR ANSI C/C++ Compiler for ARM
+**     Reference manual:    IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+**     Version:             rev. 0.2, 2022-03-25
+**     Build:               b220401
+**
+**     Abstract:
+**         Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2022 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start       = 0x00000000;
+define symbol m_interrupts_end         = 0x000003FF;
+
+define symbol m_text_start             = 0x00000400;
+define symbol m_text_end               = 0x0001FFFF;
+
+define symbol m_data_start             = 0x20000000;
+define symbol m_data_end               = 0x2001FFFF;
+
+define symbol m_data2_start            = 0x20200000;
+define symbol m_data2_end              = 0x202BFFFF;
+
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+  define symbol __size_cstack__        = __stack_size__;
+} else {
+  define symbol __size_cstack__        = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+  define symbol __size_heap__          = __heap_size__;
+} else {
+  define symbol __size_heap__          = 0x2000;
+}
+
+define exported symbol __NCACHE_REGION_START   = m_data2_start;
+define exported symbol __NCACHE_REGION_SIZE    = 0x0;
+
+define exported symbol __VECTOR_TABLE          = m_interrupts_start;
+define exported symbol __VECTOR_RAM            = m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
+define exported symbol __RTT_HEAP_END = m_data2_end;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+                          | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region DATA2_region = mem:[from m_data2_start to m_data2_end];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block RW        { readwrite };
+define block ZI        { zi };
+define block NCACHE_VAR    { section NonCacheable , section NonCacheable.init };
+define block QACCESS_CODE  { section CodeQuickAccess };
+define block QACCESS_DATA  { section DataQuickAccess };
+
+initialize by copy { readwrite, section .textrw, section CodeQuickAccess, section DataQuickAccess };
+do not initialize  { section .noinit };
+
+place at address mem: m_interrupts_start    { readonly section .intvec };
+
+place in TEXT_region                        { readonly };
+place in DATA_region                        { block RW };
+place in DATA_region                        { block ZI };
+place in DATA_region                        { last block HEAP };
+place in DATA_region                        { block NCACHE_VAR };
+place in TEXT_region                        { block QACCESS_CODE };
+place in DATA_region                        { block QACCESS_DATA };
+place in CSTACK_region                      { block CSTACK };

bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_sdram_txt.icf

@@ -0,0 +1,106 @@
+/*
+** ###################################################################
+**     Processors:          MIMXRT1062CVJ5A
+**                          MIMXRT1062CVL5A
+**                          MIMXRT1062DVJ6A
+**                          MIMXRT1062DVL6A
+**                          MIMXRT1062DVN6B
+**                          MIMXRT1062XVN5B
+**
+**     Compiler:            IAR ANSI C/C++ Compiler for ARM
+**     Reference manual:    IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+**     Version:             rev. 0.2, 2022-03-25
+**     Build:               b220401
+**
+**     Abstract:
+**         Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2022 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start       = 0x80000000;
+define symbol m_interrupts_end         = 0x800003FF;
+
+define symbol m_text_start             = 0x80000400;
+define symbol m_text_end               = 0x801FFFFF;
+
+define symbol m_data_start             = 0x20000000;
+define symbol m_data_end               = 0x2001FFFF;
+
+define symbol m_data2_start            = 0x20200000;
+define symbol m_data2_end              = 0x202BFFFF;
+
+define symbol m_data3_start            = 0x80200000;
+define symbol m_data3_end              = 0x81DFFFFF;
+
+define symbol m_ncache_start           = 0x81E00000;
+define symbol m_ncache_end             = 0x81FFFFFF;
+
+define symbol m_qacode_start           = 0x00000000;
+define symbol m_qacode_end             = 0x0001FFFF;
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+  define symbol __size_cstack__        = __stack_size__;
+} else {
+  define symbol __size_cstack__        = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+  define symbol __size_heap__          = __heap_size__;
+} else {
+  define symbol __size_heap__          = 0x0400;
+}
+
+define exported symbol __NCACHE_REGION_START   = m_ncache_start;
+define exported symbol __NCACHE_REGION_SIZE    = m_ncache_end - m_ncache_start + 1;
+
+define exported symbol __VECTOR_TABLE          = m_interrupts_start;
+define exported symbol __VECTOR_RAM            = m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
+define exported symbol __RTT_HEAP_END = m_data2_end-__size_cstack__;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+                          | mem:[from m_text_start to m_text_end];
+define region QACODE_region = mem:[from m_qacode_start to m_qacode_end];
+define region DATA_region = mem:[from m_data_start to m_data_end];
+define region DATA2_region = mem:[from m_data2_start to m_data2_end-__size_cstack__];
+define region DATA3_region  = mem:[from m_data3_start to m_data3_end];
+define region CSTACK_region = mem:[from m_data2_end-__size_cstack__+1 to m_data2_end];
+define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block RW        { first readwrite, section m_usb_dma_init_data };
+define block ZI        with alignment = 32  { first zi, section m_usb_dma_noninit_data };
+define block NCACHE_VAR    { section NonCacheable , section NonCacheable.init };
+define block QACCESS_CODE  { section CodeQuickAccess };
+define block QACCESS_DATA  { section DataQuickAccess };
+
+initialize by copy { readwrite, section .textrw, section CodeQuickAccess, section DataQuickAccess };
+do not initialize  { section .noinit };
+
+place at address mem: m_interrupts_start    { readonly section .intvec };
+
+place in TEXT_region                        { readonly };
+place in DATA2_region                       { block RW };
+place in DATA2_region                       { block ZI };
+if (isdefinedsymbol(__heap_noncacheable__)) {
+  place in NCACHE_region                    { last block HEAP };
+} else {
+  place in DATA2_region                     { last block HEAP };
+}
+place in NCACHE_region                      { block NCACHE_VAR };
+place in QACODE_region                      { block QACCESS_CODE };
+place in DATA_region                        { block QACCESS_DATA };
+place in CSTACK_region                      { block CSTACK };

bsp/imxrt/imxrt1060-nxp-evk/evkmimxrt1060_sdram_init.mac

@@ -0,0 +1,258 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+_load_dcdc_trim()
+{
+  __var dcdc_trim_loaded;
+  __var ocotp_base;
+  __var ocotp_fuse_bank0_base;
+  __var dcdc_base;
+  __var reg;
+  __var trim_value;
+  __var index;
+
+  ocotp_base = 0x401F4000;
+  ocotp_fuse_bank0_base = 0x401F4000 + 0x400;
+  dcdc_base = 0x40080000;
+
+  dcdc_trim_loaded = 0;
+
+  reg = __readMemory32(ocotp_fuse_bank0_base + 0x90, "Memory");
+  if (reg & (1<<10))
+  {
+      // DCDC: REG0->VBG_TRM
+      trim_value = (reg & (0x1F << 11)) >> 11;
+      reg = (__readMemory32(dcdc_base + 0x4, "Memory") & ~(0x1F << 24)) | (trim_value << 24);
+      __writeMemory32(reg, dcdc_base + 0x4, "Memory");
+      dcdc_trim_loaded = 1;
+  }
+
+  reg = __readMemory32(ocotp_fuse_bank0_base + 0x80, "Memory");
+  if (reg & (1<<30))
+  {
+    index = (reg & (3 << 28)) >> 28;
+    if (index < 4)
+    {
+      // DCDC: REG3->TRG 
+      reg = (__readMemory32(dcdc_base + 0xC, "Memory") & ~(0x1F)) | (0xF + index);
+      __writeMemory32(reg, dcdc_base + 0xC, "Memory");
+      dcdc_trim_loaded = 1;
+    }
+  }
+
+  if (dcdc_trim_loaded)
+  {
+      // delay 1ms for dcdc to get stable
+      __delay(1);
+      __message "DCDC trim value loaded.\n";
+  }
+
+}
+
+SDRAM_WaitIpCmdDone()
+{
+  __var reg;
+  do
+  {
+    reg = __readMemory32(0x402F003C, "Memory");
+  }while((reg & 0x3) == 0);
+  
+  __writeMemory32(0x00000003, 0x402F003C, "Memory");    // clear IPCMDERR and IPCMDDONE bits  
+}
+
+_clock_init()
+{
+  __var reg;
+  // Enable all clocks
+  __writeMemory32(0xffffffff, 0x400FC068, "Memory");
+  __writeMemory32(0xffffffff, 0x400FC06C, "Memory");
+  __writeMemory32(0xffffffff, 0x400FC070, "Memory");
+  __writeMemory32(0xffffffff, 0x400FC074, "Memory");
+  __writeMemory32(0xffffffff, 0x400FC078, "Memory");
+  __writeMemory32(0xffffffff, 0x400FC07C, "Memory");
+  __writeMemory32(0xffffffff, 0x400FC080, "Memory");
+
+  // PERCLK_PODF: 1 divide by 2
+  __writeMemory32(0x04900001, 0x400FC01C, "Memory");
+  // Enable SYS PLL but keep it bypassed.
+  __writeMemory32(0x00012001, 0x400D8030, "Memory");
+  do
+  {
+    reg = __readMemory32(0x400D8030, "Memory");
+  }while((reg & 0x80000000) == 0);
+  // Disable bypass of SYS PLL
+  __writeMemory32(0x00002001, 0x400D8030, "Memory");
+  
+  // PFD2_FRAC: 29, PLL2 PFD2=528*18/PFD2_FRAC=327
+  // Ungate SYS PLL PFD2
+  reg = __readMemory32(0x400D8100, "Memory");
+  reg &= ~0xBF0000;
+  reg |= 0x1D0000;
+  __writeMemory32(reg, 0x400D8100, "Memory");
+  
+  // SEMC_PODF: 001, AHB_PODF: 011, IPG_PODF: 01
+  // SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2
+  // SEMC_CLK_SEL: 1 SEMC_ALT_CLK
+  __writeMemory32(0x00010D40, 0x400FC014, "Memory");
+  
+  __message "clock init done\n";
+}
+
+_sdr_Init()
+{
+  // Config IOMUX
+  __writeMemory32(0x00000000, 0x401F8014, "Memory"); 
+  __writeMemory32(0x00000000, 0x401F8018, "Memory");
+  __writeMemory32(0x00000000, 0x401F801C, "Memory");
+  __writeMemory32(0x00000000, 0x401F8020, "Memory");
+  __writeMemory32(0x00000000, 0x401F8024, "Memory");
+  __writeMemory32(0x00000000, 0x401F8028, "Memory");
+  __writeMemory32(0x00000000, 0x401F802C, "Memory");
+  __writeMemory32(0x00000000, 0x401F8030, "Memory");
+  __writeMemory32(0x00000000, 0x401F8034, "Memory");
+  __writeMemory32(0x00000000, 0x401F8038, "Memory");
+  __writeMemory32(0x00000000, 0x401F803C, "Memory");
+  __writeMemory32(0x00000000, 0x401F8040, "Memory");
+  __writeMemory32(0x00000000, 0x401F8044, "Memory");
+  __writeMemory32(0x00000000, 0x401F8048, "Memory");
+  __writeMemory32(0x00000000, 0x401F804C, "Memory");
+  __writeMemory32(0x00000000, 0x401F8050, "Memory");
+  __writeMemory32(0x00000000, 0x401F8054, "Memory");
+  __writeMemory32(0x00000000, 0x401F8058, "Memory");
+  __writeMemory32(0x00000000, 0x401F805C, "Memory");
+  __writeMemory32(0x00000000, 0x401F8060, "Memory");
+  __writeMemory32(0x00000000, 0x401F8064, "Memory");
+  __writeMemory32(0x00000000, 0x401F8068, "Memory");
+  __writeMemory32(0x00000000, 0x401F806C, "Memory");
+  __writeMemory32(0x00000000, 0x401F8070, "Memory");
+  __writeMemory32(0x00000000, 0x401F8074, "Memory");
+  __writeMemory32(0x00000000, 0x401F8078, "Memory");
+  __writeMemory32(0x00000000, 0x401F807C, "Memory");
+  __writeMemory32(0x00000000, 0x401F8080, "Memory");
+  __writeMemory32(0x00000000, 0x401F8084, "Memory");
+  __writeMemory32(0x00000000, 0x401F8088, "Memory");
+  __writeMemory32(0x00000000, 0x401F808C, "Memory");
+  __writeMemory32(0x00000000, 0x401F8090, "Memory");
+  __writeMemory32(0x00000000, 0x401F8094, "Memory");
+  __writeMemory32(0x00000000, 0x401F8098, "Memory");
+  __writeMemory32(0x00000000, 0x401F809C, "Memory");
+  __writeMemory32(0x00000000, 0x401F80A0, "Memory");
+  __writeMemory32(0x00000000, 0x401F80A4, "Memory");
+  __writeMemory32(0x00000000, 0x401F80A8, "Memory");
+  __writeMemory32(0x00000000, 0x401F80AC, "Memory");
+  __writeMemory32(0x00000010, 0x401F80B0, "Memory"); // EMC_39, DQS PIN, enable SION
+
+  // PAD ctrl
+  // drive strength = 0x7 to increase drive strength
+  // otherwise the data7 bit may fail.
+  __writeMemory32(0x000110F9, 0x401F8204, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8208, "Memory");
+  __writeMemory32(0x000110F9, 0x401F820C, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8210, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8214, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8218, "Memory");
+  __writeMemory32(0x000110F9, 0x401F821C, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8220, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8224, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8228, "Memory");
+  __writeMemory32(0x000110F9, 0x401F822C, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8230, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8234, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8238, "Memory");
+  __writeMemory32(0x000110F9, 0x401F823C, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8240, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8244, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8248, "Memory");
+  __writeMemory32(0x000110F9, 0x401F824C, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8250, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8254, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8258, "Memory");
+  __writeMemory32(0x000110F9, 0x401F825C, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8260, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8264, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8268, "Memory");
+  __writeMemory32(0x000110F9, 0x401F826C, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8270, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8274, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8278, "Memory");
+  __writeMemory32(0x000110F9, 0x401F827C, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8280, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8284, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8288, "Memory");
+  __writeMemory32(0x000110F9, 0x401F828C, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8290, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8294, "Memory");
+  __writeMemory32(0x000110F9, 0x401F8298, "Memory");
+  __writeMemory32(0x000110F9, 0x401F829C, "Memory");
+  __writeMemory32(0x000110F9, 0x401F82A0, "Memory");
+  
+  // Config SDR Controller Registers/
+  __writeMemory32(0x10000004, 0x402F0000, "Memory"); // MCR
+  __writeMemory32(0x00000081, 0x402F0008, "Memory"); // BMCR0
+  __writeMemory32(0x00000081, 0x402F000C, "Memory"); // BMCR1
+  __writeMemory32(0x8000001B, 0x402F0010, "Memory"); // BR0, 32MB
+ 
+  __writeMemory32(0x00000F31, 0x402F0040, "Memory"); // SDRAMCR0
+  __writeMemory32(0x00662A22, 0x402F0044, "Memory"); // SDRAMCR1
+  __writeMemory32(0x000A0A0A, 0x402F0048, "Memory"); // SDRAMCR2
+  __writeMemory32(0x08080A00, 0x402F004C, "Memory"); // SDRAMCR3
+
+  __writeMemory32(0x80000000, 0x402F0090, "Memory"); // IPCR0
+  __writeMemory32(0x00000002, 0x402F0094, "Memory"); // IPCR1
+  __writeMemory32(0x00000000, 0x402F0098, "Memory"); // IPCR2
+
+  __writeMemory32(0xA55A000F, 0x402F009C, "Memory"); // IPCMD, SD_CC_IPREA
+  SDRAM_WaitIpCmdDone();
+  __writeMemory32(0xA55A000C, 0x402F009C, "Memory"); // SD_CC_IAF
+  SDRAM_WaitIpCmdDone();
+  __writeMemory32(0xA55A000C, 0x402F009C, "Memory"); // SD_CC_IAF
+  SDRAM_WaitIpCmdDone();
+  __writeMemory32(0x00000033, 0x402F00A0, "Memory"); // IPTXDAT
+  __writeMemory32(0xA55A000A, 0x402F009C, "Memory"); // SD_CC_IMS
+  SDRAM_WaitIpCmdDone();
+
+  __writeMemory32(0x08080A01, 0x402F004C, "Memory"); // enable sdram self refresh after initialization done.
+
+  __message "SDRAM init done\n";
+}
+
+restoreFlexRAM()
+{
+    __var base;
+    __var value;
+
+    base = 0x400AC000;
+
+    value = __readMemory32(base + 0x44, "Memory");
+    value &= ~(0xFFFFFFFF);
+    value |= 0x55AFFA55;
+    __writeMemory32(value, base + 0x44, "Memory");
+
+    value = __readMemory32(base + 0x40, "Memory");
+    value |= (1 << 2);
+    __writeMemory32(value, base + 0x40, "Memory");
+    __message "FlexRAM configuration is restored";
+}
+
+execUserPreload()
+{
+  restoreFlexRAM();
+  _load_dcdc_trim();
+  _clock_init();
+  _sdr_Init();
+  __message "execUserPreload() done.\n";
+}
+
+execUserReset()
+{
+  restoreFlexRAM();
+  _load_dcdc_trim();
+  _clock_init();
+  _sdr_Init();
+  __message "execUserReset() done.\n";
+}
+

bsp/imxrt/imxrt1060-nxp-evk/project.ewd

@@ -0,0 +1,1546 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>rtthread</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>C-SPY</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>32</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCVariant</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacFile</name>
+                    <state>$PROJ_DIR$/evkmimxrt1060_sdram_init.mac</state>
+                </option>
+                <option>
+                    <name>MemOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MemFile</name>
+                    <state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\MIMXRT1062xxx6A.ddf</state>
+                </option>
+                <option>
+                    <name>RunToEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RunToName</name>
+                    <state>main</state>
+                </option>
+                <option>
+                    <name>CExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDDFArgumentProducer</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadSuppressDownload</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDownloadVerifyAll</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProductVersion</name>
+                    <state>8.32.1.18618</state>
+                </option>
+                <option>
+                    <name>OCDynDriverList</name>
+                    <state>CMSISDAP_ID</state>
+                </option>
+                <option>
+                    <name>OCLastSavedByProductVersion</name>
+                    <state>9.30.1.50052</state>
+                </option>
+                <option>
+                    <name>UseFlashLoader</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CLowLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CDevice</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>FlashLoadersV3</name>
+                    <state>$TOOLKIT_DIR$/config/flashloader/NXP/FlashIMXRT1060_EVK_FlexSPI.board</state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OverrideDefFlashBoard</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesOffset1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesUse1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDeviceConfigMacroFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDebuggerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAllMTBOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCores</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreWorkspace</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveProject</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveConfiguration</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadExtraImage</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAttachSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MassEraseBeforeFlashing</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCoresSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreAMPConfigType</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreSessionFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCTpiuBaseOption</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ARMSIM_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCSimDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSimEnablePSP</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspOverrideConfig</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspConfigFile</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CADI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCadiMemory</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Fast Model</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCADILogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCADILogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CMSISDAP_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>4</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPResetList</name>
+                    <version>1</version>
+                    <state>4</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>CMSISDAPDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CMSISDAPProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPSelectedCPUBehaviour</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>GDBSERVER_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJTagBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IJET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>9</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>IjetPowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPowerRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetProtocolRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSwoPin</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetSwoPrescalerList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPreferETB</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetTraceSettingsList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetTraceSizeList</name>
+                    <version>0</version>
+                    <state>4</state>
+                </option>
+                <option>
+                    <name>FlashBoardPathSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL3S</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>JLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>16</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>JLinkSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJLinkHWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>JLinkInitialSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCDoJlinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkCommRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>CCJLinkSpeedRadioV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCUSBDevice</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkResetList</name>
+                    <version>6</version>
+                    <state>5</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCTcpIpAlt</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTcpIpSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSourceDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkDeviceName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>LMIFTDI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>LmiftdiSpeed</name>
+                    <state>500</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>NULINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>PEMICRO_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJPEMicroShowSettings</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>STLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>7</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkResetList</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkJtagSpeedList</name>
+                    <version>2</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDAPNumber</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkDebugAccessPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUseServerSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkProbeList</name>
+                    <version>1</version>
+                    <state>2</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>THIRDPARTY_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CThirdPartyDriverDll</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>TIFET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVccTypeDefault</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CCMSPFetVCCDefault</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetSettlingtime</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioJtagSpeedType</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetConnection</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetUsbComPort</name>
+                    <state>Automatic</state>
+                </option>
+                <option>
+                    <name>CCMSPFetAllowAccessToBSL</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioEraseFlash</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>XDS100_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>9</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TIPackageOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TIPackage</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>BoardFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCXds100BreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100DoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockEdit</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCXds100HWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100JtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceRadio</name>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ProbeList</name>
+                    <version>0</version>
+                    <state>3</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPort</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVccEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>OCXDSDigitalStatesConfigFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSelectedCoreName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <debuggerPlugins>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+        </debuggerPlugins>
+    </configuration>
+</project>

bsp/imxrt/imxrt1060-nxp-evk/project.ewp

@@ -0,0 +1,1613 @@
+<project>
+  <fileVersion>3</fileVersion>
+  <configuration>
+    <name>rtthread</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>35</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>BrowseInfoPath</name>
+          <state>rtthread\BrowseInfo</state>
+        </option>
+        <option>
+          <name>ExePath</name>
+          <state>build\iar\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>build\iar\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>build\iar\List</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Automatic choice of formatter, without multibyte support.</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Automatic choice of formatter, without multibyte support.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>6.30.6.53380</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>9.30.1.50052</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>MIMXRT1062xxx6A	NXP MIMXRT1062xxx6A</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>32</version>
+          <state>41</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GRuntimeLibThreads</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CoreVariant</name>
+          <version>32</version>
+          <state>41</state>
+        </option>
+        <option>
+          <name>GFPUDeviceSlave</name>
+          <state>MIMXRT1062xxx6A	NXP MIMXRT1062xxx6A</state>
+        </option>
+        <option>
+          <name>FPU2</name>
+          <version>0</version>
+          <state>6</state>
+        </option>
+        <option>
+          <name>NrRegs</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>NEON</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave2</name>
+          <version>32</version>
+          <state>41</state>
+        </option>
+        <option>
+          <name>OGCMSISPackSelectDevice</name>
+        </option>
+        <option>
+          <name>OgLibHeap</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGLibAdditionalLocale</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGPrintfVariant</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGPrintfMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGScanfVariant</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGScanfMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenLocaleTags</name>
+          <state />
+        </option>
+        <option>
+          <name>GenLocaleDisplayOnly</name>
+          <state />
+        </option>
+        <option>
+          <name>DSPExtension</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TrustZone</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TrustZoneModes</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGAarch64Abi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OG_32_64Device</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BuildFilesPath</name>
+          <state>rtthread</state>
+        </option>
+        <option>
+          <name>PointerAuthentication</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU64</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>37</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          <state />
+          <state>CLOCKS_PER_SEC=RT_TICK_PER_SECOND</state>
+          <state>RT_USING_DLIBC</state>
+          <state>RT_USING_LIBC</state>
+          <state>_DLIB_ADD_EXTRA_SYMBOLS=0</state>
+          <state>_DLIB_FILE_DESCRIPTOR</state>
+          <state>CPU_MIMXRT1062DVL6A</state>
+          <state>SKIP_SYSCLK_INIT</state>
+          <state>EVK_MCIMXRM</state>
+          <state>FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1</state>
+          <state>FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1</state>
+          <state>DATA_SECTION_IS_CACHEABLE=0</state>
+          <state>XIP_EXTERNAL_FLASH=1</state>
+          <state>XIP_BOOT_HEADER_ENABLE=1</state>
+          <state>ENDIANNESS</state>
+          <state>USE_RTOS</state>
+          <state>__RTTHREAD__</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state>Pa082,Pa050,Pe167</state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state />
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state />
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state />
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>00000000</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state />
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state />
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+          <state />
+          <state>$PROJ_DIR$\..\..\..\components\dfs\filesystems\devfs</state>
+          <state>$PROJ_DIR$\..\..\..\components\finsh</state>
+          <state>$PROJ_DIR$\board\MCUX_Config</state>
+          <state>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\include\posix</state>
+          <state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
+          <state>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers</state>
+          <state>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\include\netif</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension</state>
+          <state>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\core</state>
+          <state>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\include</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
+          <state>$PROJ_DIR$\..\..\..\components\dfs\include</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\stdio</state>
+          <state>$PROJ_DIR$\..\libraries\drivers</state>
+          <state>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\include</state>
+          <state>$PROJ_DIR$\..\libraries\MIMXRT1060\CMSIS\Include</state>
+          <state>$PROJ_DIR$\.</state>
+          <state>$PROJ_DIR$\xip</state>
+          <state>$PROJ_DIR$\..\..\..\components\utilities\libadt</state>
+          <state>$PROJ_DIR$\board</state>
+          <state>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
+          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
+          <state>$PROJ_DIR$\board\ports</state>
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+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c</name>
+    </file>
+  </group>
+  <group>
+    <name>CPU</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\context_iar.S</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\cpu_cache.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\cpuport.c</name>
+    </file>
+  </group>
+  <group>
+    <name>DeviceDrivers</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\i2c\i2c-bit-ops.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_dev.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\misc\pin.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\phy\phy.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\block_dev.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\gpt.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\mmc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\mmcsd_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\sd.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\sdio\sdio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\serial\serial.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Drivers</name>
+    <file>
+      <name>$PROJ_DIR$\board\MCUX_Config\clock_config.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\board\MCUX_Config\dcd.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\board\MCUX_Config\pin_mux.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\board\board.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\drivers\drv_common.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\drivers\drv_eth.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\drivers\drv_gpio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\drivers\drv_ksz8081.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\drivers\drv_mdio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\drivers\drv_sdio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\drivers\drv_sdram.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\drivers\drv_uart.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\drivers\drv_usbh.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\drivers\usb\host\usb_host_devices.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\drivers\usb\host\usb_host_ehci.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\drivers\usb\host\usb_host_framework.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\drivers\usb\host\usb_host_hci.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\drivers\usb\phy\usb_phy.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Filesystem</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\devfs\devfs.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\dfs_elm.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\ff.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\ffunicode.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_file.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_fs.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\dfs\src\dfs_posix.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Finsh</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\finsh\shell.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\finsh\msh.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\finsh\msh_parse.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\finsh\cmd.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\finsh\msh_file.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Kernel</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\clock.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\components.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\device.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\idle.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\ipc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\irq.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\kservice.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\memheap.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\mempool.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\object.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\scheduler.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\thread.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\timer.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Libraries</name>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_lpuart.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\system_MIMXRT1062.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_xbara.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_clock.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_usdhc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_gpio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_xbarb.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_enet.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_common.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_semc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_os_abstraction_rtthread.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_cache.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\fsl_common_arm.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\iar\startup_MIMXRT1062.s</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\MIMXRT1060\MIMXRT1060\drivers\generic_list.c</name>
+    </file>
+  </group>
+  <group>
+    <name>lwIP</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\api_lib.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\api_msg.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\err.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\netbuf.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\netdb.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\netifapi.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\sockets.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\api\tcpip.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\apps\ping\ping.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\def.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\dns.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\inet_chksum.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\init.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ip.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\autoip.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\dhcp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\etharp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\icmp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\igmp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\ip4.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\ip4_addr.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\ip4_frag.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\memp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\netif.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\pbuf.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\raw.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\stats.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\sys.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\tcp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\tcp_in.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\tcp_out.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\timeouts.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\core\udp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\netif\ethernet.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\lwip-2.0.3\src\netif\lowpan6.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\port\ethernetif.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\lwip\port\sys_arch.c</name>
+    </file>
+  </group>
+  <group>
+    <name>POSIX</name>
+  </group>
+  <group>
+    <name>rt_usbh</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\core\hub.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\core\usbhost.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\core\usbhost_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\class\udisk.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\class\mass.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\usb\usbhost\core\driver.c</name>
+    </file>
+  </group>
+  <group>
+    <name>SAL</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\netdev\src\netdev.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\net\netdev\src\netdev_ipaddr.c</name>
+    </file>
+  </group>
+  <group>
+    <name>xip</name>
+    <file>
+      <name>$PROJ_DIR$\xip\evkmimxrt1060_flexspi_nor_config.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\xip\fsl_flexspi_nor_boot.c</name>
+    </file>
+  </group>
+</project>

bsp/imxrt/imxrt1060-nxp-evk/project.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/imxrt/imxrt1060-nxp-evk/rtconfig.h

@@ -45,6 +45,7 @@
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
 #define RT_VER_NUM 0x50000
+
 #define RT_USING_CACHE
 #define RT_USING_CPU_FFS
 #define ARCH_ARM
@@ -52,6 +53,7 @@
 #define ARCH_ARM_CORTEX_FPU
 #define ARCH_ARM_CORTEX_M7
 
+
 /* RT-Thread Components */
 
 #define RT_USING_COMPONENTS_INIT
@@ -71,6 +73,28 @@
 #define MSH_USING_BUILT_IN_COMMANDS
 #define FINSH_USING_DESCRIPTION
 #define FINSH_ARG_MAX 10
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_ELMFAT
+
+/* elm-chan's FatFs, Generic FAT Filesystem Module */
+
+#define RT_DFS_ELM_CODE_PAGE 437
+#define RT_DFS_ELM_WORD_ACCESS
+#define RT_DFS_ELM_USE_LFN_3
+#define RT_DFS_ELM_USE_LFN 3
+#define RT_DFS_ELM_LFN_UNICODE_0
+#define RT_DFS_ELM_LFN_UNICODE 0
+#define RT_DFS_ELM_MAX_LFN 255
+#define RT_DFS_ELM_DRIVES 2
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+#define RT_DFS_ELM_REENTRANT
+#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
+#define RT_USING_DFS_DEVFS
 
 /* Device Drivers */
 
@@ -81,10 +105,16 @@
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_I2C
 #define RT_USING_I2C_BITOPS
+#define RT_USING_PHY
 #define RT_USING_PIN
 
 /* Using USB */
 
+#define RT_USING_USB
+#define RT_USING_USB_HOST
+#define RT_USBH_MSTORAGE
+#define UDISK_MOUNTPOINT "/"
+#define RT_USBD_THREAD_STACK_SZ 4096
 
 /* C/C++ and POSIX layer */
 
@@ -101,6 +131,13 @@
 
 /* Network */
 
+#define RT_USING_NETDEV
+#define NETDEV_USING_IFCONFIG
+#define NETDEV_USING_PING
+#define NETDEV_USING_NETSTAT
+#define NETDEV_USING_AUTO_DEFAULT
+#define NETDEV_IPV4 1
+#define NETDEV_IPV6 0
 
 /* Utilities */
 
@@ -215,7 +252,6 @@
 
 /* Device Control */
 
-
 /* Other */
 
 /* Signal IO */
@@ -226,13 +262,14 @@
 /* Privated Packages of RealThread */
 
 
-/* Network Utilities */
 
+/* Other */
 
-/* RT-Thread Smart */
+/* Signal IO */
 
 #define SOC_IMXRT1060_SERIES
 
+
 /* Hardware Drivers Config */
 
 #define BSP_USING_4MFLASH
@@ -240,16 +277,15 @@
 
 /* Onboard Peripheral Drivers */
 
+#define BSP_USING_SDRAM
 
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_GPIO
-#define BSP_USING_I2C
-#define BSP_USING_I2C1
-#define HW_I2C1_BADURATE_100kHZ
+#define BSP_USING_USB
+#define BSP_USB0_HOST
 #define BSP_USING_LPUART
 #define BSP_USING_LPUART1
-#define BSP_USING_PXP
 #define BSP_USING_CACHE
 
 /* Board extended module Drivers */

bsp/imxrt/imxrt1060-nxp-evk/template.ewd

@@ -0,0 +1,1546 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>rtthread</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>C-SPY</name>
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+                    <name>CEndian</name>
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+                    <state>1</state>
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+                <option>
+                    <name>OCVariant</name>
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+                    <name>MacOverride</name>
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+                <option>
+                    <name>MacFile</name>
+                    <state></state>
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+                    <name>MemOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MemFile</name>
+                    <state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\MIMXRT1062xxx6A.ddf</state>
+                </option>
+                <option>
+                    <name>RunToEnable</name>
+                    <state>1</state>
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+                <option>
+                    <name>RunToName</name>
+                    <state>main</state>
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+                    <name>CExtraOptionsCheck</name>
+                    <state>0</state>
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+                    <name>CExtraOptions</name>
+                    <state></state>
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+                    <name>CFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDDFArgumentProducer</name>
+                    <state></state>
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+                    <name>OCDownloadSuppressDownload</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDownloadVerifyAll</name>
+                    <state>1</state>
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+                <option>
+                    <name>OCProductVersion</name>
+                    <state>8.20.1.14181</state>
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+                    <name>OCDynDriverList</name>
+                    <state>CMSISDAP_ID</state>
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+                    <name>CLowLevel</name>
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+                <option>
+                    <name>OCBE8Slave</name>
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+                <option>
+                    <name>MacFile2</name>
+                    <state></state>
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+                <option>
+                    <name>CDevice</name>
+                    <state>1</state>
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+                <option>
+                    <name>FlashLoadersV3</name>
+                    <state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashIMXRT1050_EVK_FlexSPI.board</state>
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+                    <name>OCImagesSuppressCheck1</name>
+                    <state>0</state>
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+                <option>
+                    <name>OCImagesPath1</name>
+                    <state></state>
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+                    <name>OCImagesSuppressCheck2</name>
+                    <state>0</state>
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+                <option>
+                    <name>OCImagesPath2</name>
+                    <state></state>
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+                    <name>OCImagesSuppressCheck3</name>
+                    <state>0</state>
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+                <option>
+                    <name>OCImagesPath3</name>
+                    <state></state>
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+                    <name>OverrideDefFlashBoard</name>
+                    <state>1</state>
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+                <option>
+                    <name>OCImagesOffset1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset2</name>
+                    <state></state>
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+                <option>
+                    <name>OCImagesOffset3</name>
+                    <state></state>
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+                    <name>OCImagesUse1</name>
+                    <state>0</state>
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+                    <name>OCImagesUse2</name>
+                    <state>0</state>
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+                    <name>OCImagesUse3</name>
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+                    <name>OCDeviceConfigMacroFile</name>
+                    <state>1</state>
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+                    <name>OCDebuggerExtraOption</name>
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+                    <name>OCAllMTBOptions</name>
+                    <state>1</state>
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+                    <name>OCMulticoreNrOfCores</name>
+                    <state>1</state>
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+                    <name>OCMulticoreWorkspace</name>
+                    <state></state>
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+                    <name>OCMulticoreSlaveProject</name>
+                    <state></state>
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+                    <name>OCMulticoreSlaveConfiguration</name>
+                    <state></state>
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+                    <name>OCDownloadExtraImage</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAttachSlave</name>
+                    <state>0</state>
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+                <option>
+                    <name>MassEraseBeforeFlashing</name>
+                    <state>0</state>
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+                    <name>OCMulticoreNrOfCoresSlave</name>
+                    <state>1</state>
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+                    <name>OCMulticoreAMPConfigType</name>
+                    <state>0</state>
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+                <option>
+                    <name>OCMulticoreSessionFile</name>
+                    <state></state>
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+                <option>
+                    <name>OCTpiuBaseOption</name>
+                    <state>1</state>
+                </option>
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+            <name>ARMSIM_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCSimDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSimEnablePSP</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspOverrideConfig</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspConfigFile</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CADI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCadiMemory</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Fast Model</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCADILogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCADILogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CMSISDAP_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>4</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPResetList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>CMSISDAPDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
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+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
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+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
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+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
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+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
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+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
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+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
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+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
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+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
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+                    <name>CatchSTATERR</name>
+                    <state>1</state>
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+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
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+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
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+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
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+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CMSISDAPProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPSelectedCPUBehaviour</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
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+            <name>GDBSERVER_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
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+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJTagBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
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+            <name>IJET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>9</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
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+                    <name>OCDriverInfo</name>
+                    <state>1</state>
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+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
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+                    <name>IjetResetList</name>
+                    <version>1</version>
+                    <state>10</state>
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+                <option>
+                    <name>IjetHWResetDuration</name>
+                    <state>300</state>
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+                <option>
+                    <name>IjetHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>IjetPowerFromProbe</name>
+                    <state>1</state>
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+                <option>
+                    <name>IjetPowerRadio</name>
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+                    <name>IjetDoLogfile</name>
+                    <state>0</state>
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+                    <name>IjetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceCmdLine</name>
+                    <state>0</state>
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+                <option>
+                    <name>IjetMultiTargetEnable</name>
+                    <state>0</state>
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+                <option>
+                    <name>IjetMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetProtocolRadio</name>
+                    <state>0</state>
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+                <option>
+                    <name>IjetSwoPin</name>
+                    <state>0</state>
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+                <option>
+                    <name>IjetCpuClockEdit</name>
+                    <state></state>
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+                <option>
+                    <name>IjetSwoPrescalerList</name>
+                    <version>1</version>
+                    <state>0</state>
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+                <option>
+                    <name>IjetBreakpointRadio</name>
+                    <state>0</state>
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+                <option>
+                    <name>IjetRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
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+                    <name>RDICatchUndef</name>
+                    <state>1</state>
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+                    <name>RDICatchSWI</name>
+                    <state>0</state>
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+                    <name>RDICatchData</name>
+                    <state>1</state>
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+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
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+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
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+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
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+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
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+                    <name>CatchMMERR</name>
+                    <state>1</state>
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+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
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+                    <state>1</state>
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+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
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+                    <name>OCProbeConfig</name>
+                    <state></state>
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+                    <name>IjetMultiCPUEnable</name>
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+                    <state>0</state>
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+                    <name>ICpuName</name>
+                    <state></state>
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+                    <state>1</state>
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+                    <name>IjetPreferETB</name>
+                    <state>1</state>
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+                    <state>0</state>
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+                    <version>0</version>
+                    <state>4</state>
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+                    <name>FlashBoardPathSlave</name>
+                    <state>0</state>
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+                    <state></state>
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+                    <state>0</state>
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+                <option>
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+                    <state>0</state>
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+                    <state>0</state>
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+                    <state>0</state>
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+                    <state>0</state>
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+                <option>
+                    <name>CatchV8ARREL3S</name>
+                    <state>0</state>
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+            <archiveVersion>2</archiveVersion>
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+                <version>16</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>JLinkSpeed</name>
+                    <state>1000</state>
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+                <option>
+                    <name>CCJLinkDoLogfile</name>
+                    <state>0</state>
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+                <option>
+                    <name>CCJLinkLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
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+                    <name>CCJLinkHWResetDelay</name>
+                    <state>0</state>
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+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
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+                <option>
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+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCDoJlinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkCommRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>CCJLinkSpeedRadioV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCUSBDevice</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkResetList</name>
+                    <version>6</version>
+                    <state>5</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCTcpIpAlt</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTcpIpSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSourceDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkDeviceName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>LMIFTDI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>LmiftdiSpeed</name>
+                    <state>500</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>NULINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>PEMICRO_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJPEMicroShowSettings</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>STLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>7</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkResetList</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkJtagSpeedList</name>
+                    <version>2</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDAPNumber</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkDebugAccessPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUseServerSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkProbeList</name>
+                    <version>1</version>
+                    <state>2</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>THIRDPARTY_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CThirdPartyDriverDll</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>TIFET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVccTypeDefault</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CCMSPFetVCCDefault</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetSettlingtime</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioJtagSpeedType</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetConnection</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetUsbComPort</name>
+                    <state>Automatic</state>
+                </option>
+                <option>
+                    <name>CCMSPFetAllowAccessToBSL</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioEraseFlash</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>XDS100_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>9</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TIPackageOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TIPackage</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>BoardFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCXds100BreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100DoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockEdit</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCXds100HWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100JtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceRadio</name>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ProbeList</name>
+                    <version>0</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPort</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVccEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>OCXDSDigitalStatesConfigFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSelectedCoreName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <debuggerPlugins>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+        </debuggerPlugins>
+    </configuration>
+</project>

bsp/imxrt/imxrt1060-nxp-evk/template.ewp

@@ -0,0 +1,1074 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>rtthread</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>General</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
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+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>BrowseInfoPath</name>
+                    <state>rtthread\BrowseInfo</state>
+                </option>
+                <option>
+                    <name>ExePath</name>
+                    <state>build\iar\Exe</state>
+                </option>
+                <option>
+                    <name>ObjPath</name>
+                    <state>build\iar\Obj</state>
+                </option>
+                <option>
+                    <name>ListPath</name>
+                    <state>build\iar\List</state>
+                </option>
+                <option>
+                    <name>GEndianMode</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>Input description</name>
+                    <state>Automatic choice of formatter, without multibyte support.</state>
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+                <option>
+                    <name>Output description</name>
+                    <state>Automatic choice of formatter, without multibyte support.</state>
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+                <option>
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+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGCoreOrChip</name>
+                    <state>1</state>
+                </option>
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+                    <name>GRuntimeLibSelect</name>
+                    <version>0</version>
+                    <state>1</state>
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+                <option>
+                    <name>GRuntimeLibSelectSlave</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
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+                    <state>A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
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+                    <name>OGChipSelectEditMenu</name>
+                    <state>MIMXRT1062xxx6A	NXP MIMXRT1062xxx6A</state>
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+                <option>
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+                    <state>1</state>
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+                <option>
+                    <name>GEndianModeBE</name>
+                    <state>1</state>
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+                <option>
+                    <name>OGBufferedTerminalOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenStdoutInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RTConfigPath2</name>
+                    <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
+                </option>
+                <option>
+                    <name>GBECoreSlave</name>
+                    <version>32</version>
+                    <state>41</state>
+                </option>
+                <option>
+                    <name>OGUseCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGUseCmsisDspLib</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibThreads</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CoreVariant</name>
+                    <version>32</version>
+                    <state>41</state>
+                </option>
+                <option>
+                    <name>GFPUDeviceSlave</name>
+                    <state>MIMXRT1062xxx6A	NXP MIMXRT1062xxx6A</state>
+                </option>
+                <option>
+                    <name>FPU2</name>
+                    <version>0</version>
+                    <state>6</state>
+                </option>
+                <option>
+                    <name>NrRegs</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>NEON</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GFPUCoreSlave2</name>
+                    <version>32</version>
+                    <state>41</state>
+                </option>
+                <option>
+                    <name>OGCMSISPackSelectDevice</name>
+                </option>
+                <option>
+                    <name>OgLibHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGLibAdditionalLocale</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenLocaleTags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GenLocaleDisplayOnly</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DSPExtension</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TrustZone</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZoneModes</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGAarch64Abi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OG_32_64Device</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>BuildFilesPath</name>
+                    <state>rtthread</state>
+                </option>
+                <option>
+                    <name>PointerAuthentication</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FPU64</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ICCARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>37</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCOptimizationNoSizeConstraints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCPreprocFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocComments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMnemonics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMessages</name>
+                    <state>0</state>
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+                <option>
+                    <name>CCListAssFile</name>
+                    <state>0</state>
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+                <option>
+                    <name>CCListAssSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagSuppress</name>
+                    <state>Pa082,Pa050,Pe167</state>
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+                <option>
+                    <name>CCDiagRemark</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagWarning</name>
+                    <state></state>
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+                <option>
+                    <name>CCDiagError</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCObjPrefix</name>
+                    <state>1</state>
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+                <option>
+                    <name>CCAllowList</name>
+                    <version>1</version>
+                    <state>00000000</state>
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+                <option>
+                    <name>CCDebugInfo</name>
+                    <state>1</state>
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+                <option>
+                    <name>IEndianMode</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLangConformance</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSignedPlainChar</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRequirePrototypes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagWarnAreErr</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCompilerRuntimeInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
+                    <name>CCLibConfigHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIncludePath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCStdIncCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCodeSection</name>
+                    <state>.text</state>
+                </option>
+                <option>
+                    <name>IProcessorMode2</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptStrategy</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptLevelSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCPosIndRopi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndRwpi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndNoDynInit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccLang</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCDialect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccAllowVLA</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccStaticDestr</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccCppInlineSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccFloatSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptStrategySlave</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCGuardCalls</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccExceptions2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccRTTI2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OICompilerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCStackProtection</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>AARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>11</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>AObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>ACaseSensitivity</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacroChars</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnWhat</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnOne</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ADebug</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AltRegisterNames</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ADefines</name>
+                    <state></state>
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+                <option>
+                    <name>AList</name>
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+                <option>
+                    <name>AListHeader</name>
+                    <state>1</state>
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+                <option>
+                    <name>AListing</name>
+                    <state>1</state>
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+                <option>
+                    <name>Includes</name>
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+                <option>
+                    <name>MacDefs</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacExps</name>
+                    <state>1</state>
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+                <option>
+                    <name>MacExec</name>
+                    <state>0</state>
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+                <option>
+                    <name>OnlyAssed</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MultiLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLengthCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLength</name>
+                    <state>80</state>
+                </option>
+                <option>
+                    <name>TabSpacing</name>
+                    <state>8</state>
+                </option>
+                <option>
+                    <name>AXRef</name>
+                    <state>0</state>
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+                <option>
+                    <name>AXRefDefines</name>
+                    <state>0</state>
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+                    <name>AXRefInternal</name>
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+                    <name>AXRefDual</name>
+                    <state>0</state>
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+                    <name>AProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AOutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsCheck</name>
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+                <option>
+                    <name>ALimitErrorsEdit</name>
+                    <state>100</state>
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+                <option>
+                    <name>AUserIncludes</name>
+                    <state></state>
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+                    <name>AExtraOptionsV2</name>
+                    <state></state>
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+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
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+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
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+                    <name>OOCOutputFormat</name>
+                    <version>3</version>
+                    <state>0</state>
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+                <option>
+                    <name>OCOutputOverride</name>
+                    <state>0</state>
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+                <option>
+                    <name>OOCOutputFile</name>
+                    <state>template.srec</state>
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+                    <name>OOCCommandLineProducer</name>
+                    <state>1</state>
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+                <option>
+                    <name>OOCObjCopyEnable</name>
+                    <state>0</state>
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+            <data>
+                <extensions></extensions>
+                <cmdline></cmdline>
+                <hasPrio>0</hasPrio>
+                <buildSequence>inputOutputBased</buildSequence>
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+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>1</archiveVersion>
+            <data>
+                <prebuild></prebuild>
+                <postbuild></postbuild>
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+            <archiveVersion>0</archiveVersion>
+            <data>
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+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
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+                    <state>1</state>
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+                <option>
+                    <name>IlinkInputFileSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOutputFile</name>
+                    <state>rtthread.out</state>
+                </option>
+                <option>
+                    <name>IlinkDebugInfoEnable</name>
+                    <state>1</state>
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+                <option>
+                    <name>IlinkKeepSymbols</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkRawBinarySymbol</name>
+                    <state></state>
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+                    <name>IlinkRawBinarySegment</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkRawBinaryAlign</name>
+                    <state></state>
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+                    <state></state>
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+                    <state></state>
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+                    <name>IlinkMapFile</name>
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+                    <name>IlinkLogFile</name>
+                    <state>1</state>
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+                    <state>1</state>
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+                    <state>1</state>
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+                    <name>IlinkLogVeneer</name>
+                    <state>1</state>
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+                    <name>IlinkIcfOverride</name>
+                    <state>1</state>
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+                    <name>IlinkIcfFile</name>
+                    <state>$PROJ_DIR$\board\linker_scripts\link.icf</state>
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+                    <name>IlinkIcfFileSlave</name>
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+                    <name>IlinkEnableRemarks</name>
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+                    <state></state>
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+                    <state></state>
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+                    <name>IlinkTreatAsWarn</name>
+                    <state></state>
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+                    <name>IlinkTreatAsErr</name>
+                    <state></state>
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+                    <name>IlinkAutoLibEnable</name>
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+                    <name>IlinkAdditionalLibs</name>
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+                    <name>IlinkOverrideProgramEntryLabel</name>
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+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state>__iar_program_start</state>
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+                <option>
+                    <name>FillerByte</name>
+                    <state>0xFF</state>
+                </option>
+                <option>
+                    <name>FillerStart</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>FillerEnd</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>CrcSize</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcAlign</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcPoly</name>
+                    <state>0x11021</state>
+                </option>
+                <option>
+                    <name>CrcCompl</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcBitOrder</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkBufferedTerminalOutput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkStdoutInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIElfToolPostProcess</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptInline</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsAllow</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsForce</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptUseVfe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptForceVfe</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackAnalysisEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackControlFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkStackCallGraphFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkThreadsSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLocaleSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkTrustzoneImportLibraryOut</name>
+                    <state>template_import_lib.o</state>
+                </option>
+                <option>
+                    <name>OILinkExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkLogCrtRoutineSelection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogFragmentInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInlining</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogMerging</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkDemangle</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkWrapperFileEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkWrapperFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkFpuProcessor</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IARCHIVE</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+    </configuration>
+</project>

bsp/imxrt/imxrt1060-nxp-evk/template.ewt

@@ -0,0 +1,1426 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>rtthread</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>C-STAT</name>
+            <archiveVersion>516</archiveVersion>
+            <data>
+                <version>516</version>
+                <cstatargs>
+                    <useExtraArgs>0</useExtraArgs>
+                    <extraArgs></extraArgs>
+                    <analyzeTimeoutEnabled>1</analyzeTimeoutEnabled>
+                    <analyzeTimeout>600</analyzeTimeout>
+                    <enableParallel>0</enableParallel>
+                    <parallelThreads>2</parallelThreads>
+                    <enableFalsePositives>0</enableFalsePositives>
+                    <messagesLimitEnabled>1</messagesLimitEnabled>
+                    <messagesLimit>100</messagesLimit>
+                    <outputDir>rtthread/C-STAT</outputDir>
+                </cstatargs>
+                <cstat_settings>
+                    <cstat_version>2.4.1</cstat_version>
+                    <checks_tree>
+                        <package enabled="true" name="STDCHECKS">
+                            <group enabled="true" name="ARR">
+                                <check enabled="true" name="ARR-inv-index-pos" />
+                                <check enabled="true" name="ARR-inv-index-ptr-pos" />
+                                <check enabled="true" name="ARR-inv-index-ptr" />
+                                <check enabled="true" name="ARR-inv-index" />
+                                <check enabled="true" name="ARR-neg-index" />
+                                <check enabled="true" name="ARR-uninit-index" />
+                            </group>
+                            <group enabled="true" name="ATH">
+                                <check enabled="true" name="ATH-cmp-float" />
+                                <check enabled="true" name="ATH-cmp-unsign-neg" />
+                                <check enabled="true" name="ATH-cmp-unsign-pos" />
+                                <check enabled="true" name="ATH-div-0-assign" />
+                                <check enabled="false" name="ATH-div-0-cmp-aft" />
+                                <check enabled="true" name="ATH-div-0-cmp-bef" />
+                                <check enabled="true" name="ATH-div-0-interval" />
+                                <check enabled="true" name="ATH-div-0-pos" />
+                                <check enabled="true" name="ATH-div-0-unchk-global" />
+                                <check enabled="true" name="ATH-div-0-unchk-local" />
+                                <check enabled="true" name="ATH-div-0-unchk-param" />
+                                <check enabled="true" name="ATH-div-0" />
+                                <check enabled="true" name="ATH-inc-bool" />
+                                <check enabled="true" name="ATH-malloc-overrun" />
+                                <check enabled="true" name="ATH-neg-check-nonneg" />
+                                <check enabled="true" name="ATH-neg-check-pos" />
+                                <check enabled="true" name="ATH-new-overrun" />
+                                <check enabled="false" name="ATH-overflow-cast" />
+                                <check enabled="true" name="ATH-overflow" />
+                                <check enabled="true" name="ATH-shift-bounds" />
+                                <check enabled="true" name="ATH-shift-neg" />
+                                <check enabled="true" name="ATH-sizeof-by-sizeof" />
+                            </group>
+                            <group enabled="true" name="CAST">
+                                <check enabled="false" name="CAST-old-style" />
+                            </group>
+                            <group enabled="true" name="CATCH">
+                                <check enabled="true" name="CATCH-object-slicing" />
+                                <check enabled="false" name="CATCH-xtor-bad-member" />
+                            </group>
+                            <group enabled="true" name="COMMA">
+                                <check enabled="false" name="COMMA-overload" />
+                            </group>
+                            <group enabled="true" name="COMMENT">
+                                <check enabled="true" name="COMMENT-nested" />
+                            </group>
+                            <group enabled="true" name="CONST">
+                                <check enabled="true" name="CONST-member-ret" />
+                            </group>
+                            <group enabled="true" name="COP">
+                                <check enabled="false" name="COP-alloc-ctor" />
+                                <check enabled="true" name="COP-assign-op-ret" />
+                                <check enabled="true" name="COP-assign-op-self" />
+                                <check enabled="true" name="COP-assign-op" />
+                                <check enabled="true" name="COP-copy-ctor" />
+                                <check enabled="false" name="COP-dealloc-dtor" />
+                                <check enabled="true" name="COP-dtor-throw" />
+                                <check enabled="true" name="COP-dtor" />
+                                <check enabled="true" name="COP-init-order" />
+                                <check enabled="true" name="COP-init-uninit" />
+                                <check enabled="true" name="COP-member-uninit" />
+                            </group>
+                            <group enabled="true" name="CPU">
+                                <check enabled="true" name="CPU-ctor-call-virt" />
+                                <check enabled="false" name="CPU-ctor-implicit" />
+                                <check enabled="true" name="CPU-delete-throw" />
+                                <check enabled="true" name="CPU-delete-void" />
+                                <check enabled="true" name="CPU-dtor-call-virt" />
+                                <check enabled="true" name="CPU-malloc-class" />
+                                <check enabled="true" name="CPU-nonvirt-dtor" />
+                                <check enabled="true" name="CPU-return-ref-to-class-data" />
+                            </group>
+                            <group enabled="true" name="DECL">
+                                <check enabled="false" name="DECL-implicit-int" />
+                            </group>
+                            <group enabled="true" name="DEFINE">
+                                <check enabled="true" name="DEFINE-hash-multiple" />
+                            </group>
+                            <group enabled="true" name="ENUM">
+                                <check enabled="false" name="ENUM-bounds" />
+                            </group>
+                            <group enabled="true" name="EXP">
+                                <check enabled="true" name="EXP-cond-assign" />
+                                <check enabled="true" name="EXP-dangling-else" />
+                                <check enabled="true" name="EXP-loop-exit" />
+                                <check enabled="false" name="EXP-main-ret-int" />
+                                <check enabled="false" name="EXP-null-stmt" />
+                                <check enabled="false" name="EXP-stray-semicolon" />
+                            </group>
+                            <group enabled="true" name="EXPR">
+                                <check enabled="true" name="EXPR-const-overflow" />
+                            </group>
+                            <group enabled="true" name="FPT">
+                                <check enabled="true" name="FPT-cmp-null" />
+                                <check enabled="false" name="FPT-literal" />
+                                <check enabled="true" name="FPT-misuse" />
+                            </group>
+                            <group enabled="true" name="FUNC">
+                                <check enabled="false" name="FUNC-implicit-decl" />
+                                <check enabled="false" name="FUNC-unprototyped-all" />
+                                <check enabled="true" name="FUNC-unprototyped-used" />
+                            </group>
+                            <group enabled="true" name="INCLUDE">
+                                <check enabled="false" name="INCLUDE-c-file" />
+                            </group>
+                            <group enabled="true" name="INT">
+                                <check enabled="false" name="INT-use-signed-as-unsigned-pos" />
+                                <check enabled="true" name="INT-use-signed-as-unsigned" />
+                            </group>
+                            <group enabled="true" name="ITR">
+                                <check enabled="true" name="ITR-end-cmp-aft" />
+                                <check enabled="true" name="ITR-end-cmp-bef" />
+                                <check enabled="true" name="ITR-invalidated" />
+                                <check enabled="false" name="ITR-mismatch-alg" />
+                                <check enabled="false" name="ITR-store" />
+                                <check enabled="true" name="ITR-uninit" />
+                            </group>
+                            <group enabled="true" name="LIB">
+                                <check enabled="false" name="LIB-bsearch-overrun-pos" />
+                                <check enabled="false" name="LIB-bsearch-overrun" />
+                                <check enabled="false" name="LIB-fn-unsafe" />
+                                <check enabled="false" name="LIB-fread-overrun-pos" />
+                                <check enabled="true" name="LIB-fread-overrun" />
+                                <check enabled="false" name="LIB-memchr-overrun-pos" />
+                                <check enabled="true" name="LIB-memchr-overrun" />
+                                <check enabled="false" name="LIB-memcpy-overrun-pos" />
+                                <check enabled="true" name="LIB-memcpy-overrun" />
+                                <check enabled="false" name="LIB-memset-overrun-pos" />
+                                <check enabled="true" name="LIB-memset-overrun" />
+                                <check enabled="false" name="LIB-putenv" />
+                                <check enabled="false" name="LIB-qsort-overrun-pos" />
+                                <check enabled="false" name="LIB-qsort-overrun" />
+                                <check enabled="true" name="LIB-return-const" />
+                                <check enabled="true" name="LIB-return-error" />
+                                <check enabled="true" name="LIB-return-leak" />
+                                <check enabled="true" name="LIB-return-neg" />
+                                <check enabled="true" name="LIB-return-null" />
+                                <check enabled="false" name="LIB-sprintf-overrun" />
+                                <check enabled="false" name="LIB-std-sort-overrun-pos" />
+                                <check enabled="true" name="LIB-std-sort-overrun" />
+                                <check enabled="false" name="LIB-strcat-overrun-pos" />
+                                <check enabled="true" name="LIB-strcat-overrun" />
+                                <check enabled="false" name="LIB-strcpy-overrun-pos" />
+                                <check enabled="true" name="LIB-strcpy-overrun" />
+                                <check enabled="false" name="LIB-strncat-overrun-pos" />
+                                <check enabled="true" name="LIB-strncat-overrun" />
+                                <check enabled="false" name="LIB-strncmp-overrun-pos" />
+                                <check enabled="true" name="LIB-strncmp-overrun" />
+                                <check enabled="false" name="LIB-strncpy-overrun-pos" />
+                                <check enabled="true" name="LIB-strncpy-overrun" />
+                            </group>
+                            <group enabled="true" name="LOGIC">
+                                <check enabled="false" name="LOGIC-overload" />
+                            </group>
+                            <group enabled="true" name="MEM">
+                                <check enabled="true" name="MEM-delete-array-op" />
+                                <check enabled="true" name="MEM-delete-op" />
+                                <check enabled="true" name="MEM-double-free-alias" />
+                                <check enabled="true" name="MEM-double-free-some" />
+                                <check enabled="true" name="MEM-double-free" />
+                                <check enabled="true" name="MEM-free-field" />
+                                <check enabled="true" name="MEM-free-fptr" />
+                                <check enabled="false" name="MEM-free-no-alloc-struct" />
+                                <check enabled="false" name="MEM-free-no-alloc" />
+                                <check enabled="true" name="MEM-free-no-use" />
+                                <check enabled="true" name="MEM-free-op" />
+                                <check enabled="true" name="MEM-free-struct-field" />
+                                <check enabled="true" name="MEM-free-variable-alias" />
+                                <check enabled="true" name="MEM-free-variable" />
+                                <check enabled="true" name="MEM-leak-alias" />
+                                <check enabled="false" name="MEM-leak" />
+                                <check enabled="false" name="MEM-malloc-arith" />
+                                <check enabled="true" name="MEM-malloc-diff-type" />
+                                <check enabled="true" name="MEM-malloc-sizeof-ptr" />
+                                <check enabled="true" name="MEM-malloc-sizeof" />
+                                <check enabled="false" name="MEM-malloc-strlen" />
+                                <check enabled="true" name="MEM-realloc-diff-type" />
+                                <check enabled="true" name="MEM-return-free" />
+                                <check enabled="true" name="MEM-return-no-assign" />
+                                <check enabled="true" name="MEM-stack-global-field" />
+                                <check enabled="true" name="MEM-stack-global" />
+                                <check enabled="true" name="MEM-stack-param-ref" />
+                                <check enabled="true" name="MEM-stack-param" />
+                                <check enabled="true" name="MEM-stack-pos" />
+                                <check enabled="true" name="MEM-stack-ref" />
+                                <check enabled="true" name="MEM-stack" />
+                                <check enabled="true" name="MEM-use-free-all" />
+                                <check enabled="true" name="MEM-use-free-some" />
+                            </group>
+                            <group enabled="true" name="PTR">
+                                <check enabled="true" name="PTR-arith-field" />
+                                <check enabled="true" name="PTR-arith-stack" />
+                                <check enabled="true" name="PTR-arith-var" />
+                                <check enabled="true" name="PTR-cmp-str-lit" />
+                                <check enabled="false" name="PTR-null-assign-fun-pos" />
+                                <check enabled="false" name="PTR-null-assign-pos" />
+                                <check enabled="true" name="PTR-null-assign" />
+                                <check enabled="true" name="PTR-null-cmp-aft" />
+                                <check enabled="true" name="PTR-null-cmp-bef-fun" />
+                                <check enabled="true" name="PTR-null-cmp-bef" />
+                                <check enabled="true" name="PTR-null-fun-pos" />
+                                <check enabled="false" name="PTR-null-literal-pos" />
+                                <check enabled="false" name="PTR-overload" />
+                                <check enabled="false" name="PTR-singleton-arith-pos" />
+                                <check enabled="true" name="PTR-singleton-arith" />
+                                <check enabled="true" name="PTR-unchk-param-some" />
+                                <check enabled="false" name="PTR-unchk-param" />
+                                <check enabled="false" name="PTR-uninit-pos" />
+                                <check enabled="true" name="PTR-uninit" />
+                            </group>
+                            <group enabled="true" name="RED">
+                                <check enabled="false" name="RED-alloc-zero-bytes" />
+                                <check enabled="false" name="RED-case-reach" />
+                                <check enabled="false" name="RED-cmp-always" />
+                                <check enabled="false" name="RED-cmp-never" />
+                                <check enabled="false" name="RED-cond-always" />
+                                <check enabled="true" name="RED-cond-const-assign" />
+                                <check enabled="false" name="RED-cond-const-expr" />
+                                <check enabled="false" name="RED-cond-const" />
+                                <check enabled="false" name="RED-cond-never" />
+                                <check enabled="true" name="RED-dead" />
+                                <check enabled="false" name="RED-expr" />
+                                <check enabled="false" name="RED-func-no-effect" />
+                                <check enabled="true" name="RED-local-hides-global" />
+                                <check enabled="false" name="RED-local-hides-local" />
+                                <check enabled="false" name="RED-local-hides-member" />
+                                <check enabled="true" name="RED-local-hides-param" />
+                                <check enabled="false" name="RED-no-effect" />
+                                <check enabled="true" name="RED-self-assign" />
+                                <check enabled="true" name="RED-unused-assign" />
+                                <check enabled="false" name="RED-unused-param" />
+                                <check enabled="false" name="RED-unused-return-val" />
+                                <check enabled="false" name="RED-unused-val" />
+                                <check enabled="true" name="RED-unused-var-all" />
+                            </group>
+                            <group enabled="true" name="RESOURCE">
+                                <check enabled="false" name="RESOURCE-deref-file" />
+                                <check enabled="true" name="RESOURCE-double-close" />
+                                <check enabled="true" name="RESOURCE-file-no-close-all" />
+                                <check enabled="false" name="RESOURCE-file-pos-neg" />
+                                <check enabled="true" name="RESOURCE-file-use-after-close" />
+                                <check enabled="false" name="RESOURCE-implicit-deref-file" />
+                                <check enabled="true" name="RESOURCE-write-ronly-file" />
+                            </group>
+                            <group enabled="true" name="SIZEOF">
+                                <check enabled="true" name="SIZEOF-side-effect" />
+                            </group>
+                            <group enabled="true" name="SPC">
+                                <check enabled="true" name="SPC-order" />
+                                <check enabled="false" name="SPC-uninit-arr-all" />
+                                <check enabled="true" name="SPC-uninit-struct-field-heap" />
+                                <check enabled="false" name="SPC-uninit-struct-field" />
+                                <check enabled="true" name="SPC-uninit-struct" />
+                                <check enabled="true" name="SPC-uninit-var-all" />
+                                <check enabled="true" name="SPC-uninit-var-some" />
+                                <check enabled="false" name="SPC-volatile-reads" />
+                                <check enabled="false" name="SPC-volatile-writes" />
+                            </group>
+                            <group enabled="true" name="STRUCT">
+                                <check enabled="false" name="STRUCT-signed-bit" />
+                            </group>
+                            <group enabled="true" name="SWITCH">
+                                <check enabled="true" name="SWITCH-fall-through" />
+                            </group>
+                            <group enabled="true" name="THROW">
+                                <check enabled="false" name="THROW-empty" />
+                                <check enabled="false" name="THROW-main" />
+                                <check enabled="true" name="THROW-null" />
+                                <check enabled="true" name="THROW-ptr" />
+                                <check enabled="true" name="THROW-static" />
+                                <check enabled="true" name="THROW-unhandled" />
+                            </group>
+                            <group enabled="true" name="UNION">
+                                <check enabled="true" name="UNION-overlap-assign" />
+                                <check enabled="true" name="UNION-type-punning" />
+                            </group>
+                        </package>
+                        <package enabled="false" name="CERT">
+                            <group enabled="true" name="CERT-ARR">
+                                <check enabled="true" name="CERT-ARR30-C_a" />
+                                <check enabled="true" name="CERT-ARR30-C_b" />
+                                <check enabled="true" name="CERT-ARR30-C_c" />
+                                <check enabled="true" name="CERT-ARR30-C_d" />
+                                <check enabled="true" name="CERT-ARR30-C_e" />
+                                <check enabled="true" name="CERT-ARR30-C_f" />
+                                <check enabled="true" name="CERT-ARR30-C_g" />
+                                <check enabled="true" name="CERT-ARR30-C_h" />
+                                <check enabled="true" name="CERT-ARR30-C_i" />
+                                <check enabled="true" name="CERT-ARR30-C_j" />
+                                <check enabled="true" name="CERT-ARR32-C" />
+                                <check enabled="true" name="CERT-ARR36-C_a" />
+                                <check enabled="true" name="CERT-ARR36-C_b" />
+                                <check enabled="true" name="CERT-ARR37-C" />
+                                <check enabled="true" name="CERT-ARR38-C_a" />
+                                <check enabled="true" name="CERT-ARR38-C_b" />
+                                <check enabled="true" name="CERT-ARR38-C_c" />
+                                <check enabled="true" name="CERT-ARR38-C_d" />
+                                <check enabled="true" name="CERT-ARR38-C_e" />
+                                <check enabled="true" name="CERT-ARR38-C_f" />
+                                <check enabled="true" name="CERT-ARR39-C" />
+                            </group>
+                            <group enabled="true" name="CERT-DCL">
+                                <check enabled="true" name="CERT-DCL30-C_a" />
+                                <check enabled="true" name="CERT-DCL30-C_b" />
+                                <check enabled="true" name="CERT-DCL30-C_c" />
+                                <check enabled="true" name="CERT-DCL30-C_d" />
+                                <check enabled="true" name="CERT-DCL30-C_e" />
+                                <check enabled="true" name="CERT-DCL31-C" />
+                                <check enabled="true" name="CERT-DCL36-C" />
+                                <check enabled="true" name="CERT-DCL37-C_a" />
+                                <check enabled="true" name="CERT-DCL37-C_b" />
+                                <check enabled="false" name="CERT-DCL37-C_c" />
+                                <check enabled="true" name="CERT-DCL38-C" />
+                                <check enabled="true" name="CERT-DCL39-C" />
+                                <check enabled="true" name="CERT-DCL40-C" />
+                                <check enabled="true" name="CERT-DCL41-C" />
+                            </group>
+                            <group enabled="true" name="CERT-ENV">
+                                <check enabled="true" name="CERT-ENV30-C" />
+                                <check enabled="true" name="CERT-ENV31-C" />
+                                <check enabled="true" name="CERT-ENV32-C" />
+                                <check enabled="true" name="CERT-ENV33-C" />
+                                <check enabled="true" name="CERT-ENV34-C" />
+                            </group>
+                            <group enabled="true" name="CERT-ERR">
+                                <check enabled="true" name="CERT-ERR30-C_a" />
+                                <check enabled="true" name="CERT-ERR30-C_b" />
+                                <check enabled="true" name="CERT-ERR30-C_c" />
+                                <check enabled="true" name="CERT-ERR30-C_d" />
+                                <check enabled="true" name="CERT-ERR32-C" />
+                                <check enabled="true" name="CERT-ERR33-C_a" />
+                                <check enabled="true" name="CERT-ERR33-C_b" />
+                                <check enabled="true" name="CERT-ERR33-C_c" />
+                                <check enabled="true" name="CERT-ERR33-C_d" />
+                                <check enabled="true" name="CERT-ERR34-C_a" />
+                                <check enabled="true" name="CERT-ERR34-C_b" />
+                            </group>
+                            <group enabled="true" name="CERT-EXP">
+                                <check enabled="true" name="CERT-EXP19-C" />
+                                <check enabled="true" name="CERT-EXP30-C_a" />
+                                <check enabled="true" name="CERT-EXP30-C_b" />
+                                <check enabled="true" name="CERT-EXP32-C" />
+                                <check enabled="true" name="CERT-EXP33-C_a" />
+                                <check enabled="true" name="CERT-EXP33-C_b" />
+                                <check enabled="true" name="CERT-EXP33-C_c" />
+                                <check enabled="true" name="CERT-EXP33-C_d" />
+                                <check enabled="true" name="CERT-EXP33-C_e" />
+                                <check enabled="true" name="CERT-EXP33-C_f" />
+                                <check enabled="true" name="CERT-EXP34-C_a" />
+                                <check enabled="true" name="CERT-EXP34-C_b" />
+                                <check enabled="true" name="CERT-EXP34-C_c" />
+                                <check enabled="true" name="CERT-EXP34-C_d" />
+                                <check enabled="true" name="CERT-EXP34-C_e" />
+                                <check enabled="true" name="CERT-EXP34-C_f" />
+                                <check enabled="true" name="CERT-EXP34-C_g" />
+                                <check enabled="true" name="CERT-EXP35-C" />
+                                <check enabled="true" name="CERT-EXP36-C_a" />
+                                <check enabled="true" name="CERT-EXP36-C_b" />
+                                <check enabled="true" name="CERT-EXP37-C_a" />
+                                <check enabled="true" name="CERT-EXP37-C_b" />
+                                <check enabled="true" name="CERT-EXP37-C_c" />
+                                <check enabled="true" name="CERT-EXP39-C_a" />
+                                <check enabled="true" name="CERT-EXP39-C_b" />
+                                <check enabled="true" name="CERT-EXP39-C_c" />
+                                <check enabled="true" name="CERT-EXP39-C_d" />
+                                <check enabled="true" name="CERT-EXP39-C_e" />
+                                <check enabled="true" name="CERT-EXP40-C_a" />
+                                <check enabled="true" name="CERT-EXP40-C_b" />
+                                <check enabled="true" name="CERT-EXP42-C" />
+                                <check enabled="true" name="CERT-EXP43-C_a" />
+                                <check enabled="true" name="CERT-EXP43-C_b" />
+                                <check enabled="true" name="CERT-EXP43-C_c" />
+                                <check enabled="true" name="CERT-EXP43-C_d" />
+                                <check enabled="true" name="CERT-EXP44-C" />
+                                <check enabled="true" name="CERT-EXP45-C" />
+                                <check enabled="true" name="CERT-EXP46-C" />
+                                <check enabled="true" name="CERT-EXP47-C_a" />
+                                <check enabled="true" name="CERT-EXP47-C_b" />
+                            </group>
+                            <group enabled="true" name="CERT-FIO">
+                                <check enabled="true" name="CERT-FIO30-C" />
+                                <check enabled="true" name="CERT-FIO32-C" />
+                                <check enabled="true" name="CERT-FIO34-C" />
+                                <check enabled="true" name="CERT-FIO37-C" />
+                                <check enabled="true" name="CERT-FIO38-C" />
+                                <check enabled="true" name="CERT-FIO39-C" />
+                                <check enabled="true" name="CERT-FIO40-C" />
+                                <check enabled="true" name="CERT-FIO41-C" />
+                                <check enabled="true" name="CERT-FIO42-C_a" />
+                                <check enabled="false" name="CERT-FIO42-C_b" />
+                                <check enabled="true" name="CERT-FIO44-C" />
+                                <check enabled="true" name="CERT-FIO45-C" />
+                                <check enabled="true" name="CERT-FIO46-C_a" />
+                                <check enabled="true" name="CERT-FIO46-C_b" />
+                                <check enabled="true" name="CERT-FIO46-C_c" />
+                                <check enabled="true" name="CERT-FIO47-C_a" />
+                                <check enabled="true" name="CERT-FIO47-C_b" />
+                                <check enabled="true" name="CERT-FIO47-C_c" />
+                            </group>
+                            <group enabled="true" name="CERT-FLP">
+                                <check enabled="true" name="CERT-FLP30-C_a" />
+                                <check enabled="true" name="CERT-FLP30-C_b" />
+                                <check enabled="true" name="CERT-FLP32-C_a" />
+                                <check enabled="true" name="CERT-FLP32-C_b" />
+                                <check enabled="true" name="CERT-FLP34-C" />
+                                <check enabled="true" name="CERT-FLP36-C" />
+                                <check enabled="true" name="CERT-FLP37-C" />
+                            </group>
+                            <group enabled="true" name="CERT-INT">
+                                <check enabled="true" name="CERT-INT30-C_a" />
+                                <check enabled="false" name="CERT-INT30-C_b" />
+                                <check enabled="true" name="CERT-INT31-C_a" />
+                                <check enabled="true" name="CERT-INT31-C_b" />
+                                <check enabled="true" name="CERT-INT31-C_c" />
+                                <check enabled="true" name="CERT-INT32-C_a" />
+                                <check enabled="false" name="CERT-INT32-C_b" />
+                                <check enabled="true" name="CERT-INT33-C_a" />
+                                <check enabled="true" name="CERT-INT33-C_b" />
+                                <check enabled="true" name="CERT-INT33-C_c" />
+                                <check enabled="true" name="CERT-INT33-C_d" />
+                                <check enabled="true" name="CERT-INT33-C_e" />
+                                <check enabled="true" name="CERT-INT33-C_f" />
+                                <check enabled="true" name="CERT-INT33-C_g" />
+                                <check enabled="true" name="CERT-INT33-C_h" />
+                                <check enabled="true" name="CERT-INT33-C_i" />
+                                <check enabled="true" name="CERT-INT34-C_a" />
+                                <check enabled="true" name="CERT-INT34-C_b" />
+                                <check enabled="true" name="CERT-INT34-C_c" />
+                                <check enabled="true" name="CERT-INT35-C" />
+                                <check enabled="true" name="CERT-INT36-C" />
+                            </group>
+                            <group enabled="true" name="CERT-MEM">
+                                <check enabled="true" name="CERT-MEM30-C_a" />
+                                <check enabled="true" name="CERT-MEM30-C_b" />
+                                <check enabled="true" name="CERT-MEM30-C_c" />
+                                <check enabled="true" name="CERT-MEM31-C" />
+                                <check enabled="true" name="CERT-MEM33-C_a" />
+                                <check enabled="true" name="CERT-MEM33-C_b" />
+                                <check enabled="true" name="CERT-MEM34-C_a" />
+                                <check enabled="true" name="CERT-MEM34-C_b" />
+                                <check enabled="true" name="CERT-MEM34-C_c" />
+                                <check enabled="true" name="CERT-MEM35-C_a" />
+                                <check enabled="true" name="CERT-MEM35-C_b" />
+                                <check enabled="true" name="CERT-MEM35-C_c" />
+                                <check enabled="true" name="CERT-MEM36-C" />
+                            </group>
+                            <group enabled="true" name="CERT-MSC">
+                                <check enabled="true" name="CERT-MSC30-C" />
+                                <check enabled="true" name="CERT-MSC32-C" />
+                                <check enabled="false" name="CERT-MSC33-C" />
+                                <check enabled="true" name="CERT-MSC37-C" />
+                                <check enabled="true" name="CERT-MSC38-C" />
+                                <check enabled="true" name="CERT-MSC39-C" />
+                                <check enabled="true" name="CERT-MSC40-C_a" />
+                                <check enabled="true" name="CERT-MSC40-C_b" />
+                                <check enabled="true" name="CERT-MSC40-C_c" />
+                                <check enabled="true" name="CERT-MSC40-C_d" />
+                                <check enabled="false" name="CERT-MSC40-C_e" />
+                                <check enabled="true" name="CERT-MSC41-C_a" />
+                                <check enabled="true" name="CERT-MSC41-C_b" />
+                                <check enabled="true" name="CERT-MSC41-C_c" />
+                            </group>
+                            <group enabled="true" name="CERT-PRE">
+                                <check enabled="true" name="CERT-PRE31-C" />
+                                <check enabled="true" name="CERT-PRE32-C_a" />
+                                <check enabled="true" name="CERT-PRE32-C_b" />
+                            </group>
+                            <group enabled="true" name="CERT-SIG">
+                                <check enabled="true" name="CERT-SIG30-C" />
+                                <check enabled="true" name="CERT-SIG31-C" />
+                                <check enabled="true" name="CERT-SIG34-C" />
+                                <check enabled="true" name="CERT-SIG35-C" />
+                            </group>
+                            <group enabled="true" name="CERT-STR">
+                                <check enabled="true" name="CERT-STR30-C" />
+                                <check enabled="true" name="CERT-STR31-C_a" />
+                                <check enabled="true" name="CERT-STR31-C_b" />
+                                <check enabled="true" name="CERT-STR31-C_c" />
+                                <check enabled="true" name="CERT-STR31-C_d" />
+                                <check enabled="true" name="CERT-STR31-C_e" />
+                                <check enabled="true" name="CERT-STR31-C_f" />
+                                <check enabled="true" name="CERT-STR31-C_g" />
+                                <check enabled="true" name="CERT-STR31-C_h" />
+                                <check enabled="true" name="CERT-STR32-C" />
+                                <check enabled="true" name="CERT-STR34-C" />
+                                <check enabled="true" name="CERT-STR37-C" />
+                            </group>
+                        </package>
+                        <package enabled="false" name="SECURITY">
+                            <group enabled="true" name="SEC-BUFFER">
+                                <check enabled="true" name="SEC-BUFFER-memory-leak-alias" />
+                                <check enabled="false" name="SEC-BUFFER-memory-leak" />
+                                <check enabled="false" name="SEC-BUFFER-memset-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-memset-overrun" />
+                                <check enabled="false" name="SEC-BUFFER-qsort-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-qsort-overrun" />
+                                <check enabled="true" name="SEC-BUFFER-sprintf-overrun" />
+                                <check enabled="false" name="SEC-BUFFER-std-sort-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-std-sort-overrun" />
+                                <check enabled="false" name="SEC-BUFFER-strcat-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-strcat-overrun" />
+                                <check enabled="false" name="SEC-BUFFER-strcpy-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-strcpy-overrun" />
+                                <check enabled="false" name="SEC-BUFFER-strncat-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-strncat-overrun" />
+                                <check enabled="false" name="SEC-BUFFER-strncmp-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-strncmp-overrun" />
+                                <check enabled="false" name="SEC-BUFFER-strncpy-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-strncpy-overrun" />
+                                <check enabled="true" name="SEC-BUFFER-tainted-alloc-size" />
+                                <check enabled="true" name="SEC-BUFFER-tainted-copy-length" />
+                                <check enabled="true" name="SEC-BUFFER-tainted-copy" />
+                                <check enabled="true" name="SEC-BUFFER-tainted-index" />
+                                <check enabled="true" name="SEC-BUFFER-tainted-offset" />
+                                <check enabled="true" name="SEC-BUFFER-use-after-free-all" />
+                                <check enabled="true" name="SEC-BUFFER-use-after-free-some" />
+                            </group>
+                            <group enabled="true" name="SEC-DIV-0">
+                                <check enabled="true" name="SEC-DIV-0-compare-after" />
+                                <check enabled="true" name="SEC-DIV-0-compare-before" />
+                                <check enabled="true" name="SEC-DIV-0-tainted" />
+                            </group>
+                            <group enabled="true" name="SEC-FILEOP">
+                                <check enabled="true" name="SEC-FILEOP-open-no-close" />
+                                <check enabled="false" name="SEC-FILEOP-path-traversal" />
+                                <check enabled="true" name="SEC-FILEOP-use-after-close" />
+                            </group>
+                            <group enabled="true" name="SEC-INJECTION">
+                                <check enabled="false" name="SEC-INJECTION-sql" />
+                                <check enabled="false" name="SEC-INJECTION-xpath" />
+                            </group>
+                            <group enabled="true" name="SEC-LOOP">
+                                <check enabled="true" name="SEC-LOOP-tainted-bound" />
+                            </group>
+                            <group enabled="true" name="SEC-NULL">
+                                <check enabled="false" name="SEC-NULL-assignment-fun-pos" />
+                                <check enabled="true" name="SEC-NULL-assignment" />
+                                <check enabled="true" name="SEC-NULL-cmp-aft" />
+                                <check enabled="true" name="SEC-NULL-cmp-bef-fun" />
+                                <check enabled="true" name="SEC-NULL-cmp-bef" />
+                                <check enabled="false" name="SEC-NULL-literal-pos" />
+                            </group>
+                            <group enabled="true" name="SEC-STRING">
+                                <check enabled="true" name="SEC-STRING-format-string" />
+                                <check enabled="false" name="SEC-STRING-hard-coded-credentials" />
+                            </group>
+                        </package>
+                        <package enabled="false" name="MISRAC2004">
+                            <group enabled="true" name="MISRAC2004-1">
+                                <check enabled="true" name="MISRAC2004-1.1" />
+                                <check enabled="true" name="MISRAC2004-1.2_a" />
+                                <check enabled="true" name="MISRAC2004-1.2_b" />
+                                <check enabled="true" name="MISRAC2004-1.2_c" />
+                                <check enabled="true" name="MISRAC2004-1.2_d" />
+                                <check enabled="true" name="MISRAC2004-1.2_e" />
+                                <check enabled="true" name="MISRAC2004-1.2_f" />
+                                <check enabled="true" name="MISRAC2004-1.2_g" />
+                                <check enabled="true" name="MISRAC2004-1.2_h" />
+                                <check enabled="true" name="MISRAC2004-1.2_i" />
+                                <check enabled="true" name="MISRAC2004-1.2_j" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-2">
+                                <check enabled="true" name="MISRAC2004-2.1" />
+                                <check enabled="true" name="MISRAC2004-2.2" />
+                                <check enabled="true" name="MISRAC2004-2.3" />
+                                <check enabled="false" name="MISRAC2004-2.4" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-5">
+                                <check enabled="true" name="MISRAC2004-5.1" />
+                                <check enabled="true" name="MISRAC2004-5.2" />
+                                <check enabled="true" name="MISRAC2004-5.3" />
+                                <check enabled="true" name="MISRAC2004-5.4" />
+                                <check enabled="false" name="MISRAC2004-5.5" />
+                                <check enabled="false" name="MISRAC2004-5.6" />
+                                <check enabled="false" name="MISRAC2004-5.7" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-6">
+                                <check enabled="true" name="MISRAC2004-6.1" />
+                                <check enabled="true" name="MISRAC2004-6.2" />
+                                <check enabled="false" name="MISRAC2004-6.3" />
+                                <check enabled="true" name="MISRAC2004-6.4" />
+                                <check enabled="true" name="MISRAC2004-6.5" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-7">
+                                <check enabled="true" name="MISRAC2004-7.1" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-8">
+                                <check enabled="true" name="MISRAC2004-8.1" />
+                                <check enabled="true" name="MISRAC2004-8.2" />
+                                <check enabled="true" name="MISRAC2004-8.3" />
+                                <check enabled="true" name="MISRAC2004-8.5_a" />
+                                <check enabled="true" name="MISRAC2004-8.5_b" />
+                                <check enabled="true" name="MISRAC2004-8.6" />
+                                <check enabled="true" name="MISRAC2004-8.7" />
+                                <check enabled="true" name="MISRAC2004-8.8_a" />
+                                <check enabled="true" name="MISRAC2004-8.8_b" />
+                                <check enabled="true" name="MISRAC2004-8.10" />
+                                <check enabled="true" name="MISRAC2004-8.12" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-9">
+                                <check enabled="true" name="MISRAC2004-9.1_a" />
+                                <check enabled="true" name="MISRAC2004-9.1_b" />
+                                <check enabled="true" name="MISRAC2004-9.1_c" />
+                                <check enabled="true" name="MISRAC2004-9.2" />
+                                <check enabled="true" name="MISRAC2004-9.3" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-10">
+                                <check enabled="true" name="MISRAC2004-10.1_a" />
+                                <check enabled="true" name="MISRAC2004-10.1_b" />
+                                <check enabled="true" name="MISRAC2004-10.1_c" />
+                                <check enabled="true" name="MISRAC2004-10.1_d" />
+                                <check enabled="true" name="MISRAC2004-10.2_a" />
+                                <check enabled="true" name="MISRAC2004-10.2_b" />
+                                <check enabled="true" name="MISRAC2004-10.2_c" />
+                                <check enabled="true" name="MISRAC2004-10.2_d" />
+                                <check enabled="true" name="MISRAC2004-10.3" />
+                                <check enabled="true" name="MISRAC2004-10.4" />
+                                <check enabled="true" name="MISRAC2004-10.5" />
+                                <check enabled="true" name="MISRAC2004-10.6" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-11">
+                                <check enabled="true" name="MISRAC2004-11.1" />
+                                <check enabled="false" name="MISRAC2004-11.3" />
+                                <check enabled="false" name="MISRAC2004-11.4" />
+                                <check enabled="true" name="MISRAC2004-11.5" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-12">
+                                <check enabled="false" name="MISRAC2004-12.1" />
+                                <check enabled="true" name="MISRAC2004-12.2_a" />
+                                <check enabled="true" name="MISRAC2004-12.2_b" />
+                                <check enabled="true" name="MISRAC2004-12.2_c" />
+                                <check enabled="true" name="MISRAC2004-12.3" />
+                                <check enabled="true" name="MISRAC2004-12.4" />
+                                <check enabled="true" name="MISRAC2004-12.5" />
+                                <check enabled="false" name="MISRAC2004-12.6_a" />
+                                <check enabled="false" name="MISRAC2004-12.6_b" />
+                                <check enabled="true" name="MISRAC2004-12.7" />
+                                <check enabled="true" name="MISRAC2004-12.8" />
+                                <check enabled="true" name="MISRAC2004-12.9" />
+                                <check enabled="true" name="MISRAC2004-12.10" />
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+                            <group enabled="true" name="MISRAC++2008-27-0">
+                                <check enabled="true" name="MISRAC++2008-27-0-1" />
+                            </group>
+                        </package>
+                    </checks_tree>
+                </cstat_settings>
+            </data>
+        </settings>
+        <settings>
+            <name>RuntimeChecking</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>2</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>GenRtcDebugHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcEnableBoundsChecking</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcCheckPtrsNonInstrMem</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRtcTrackPointerBounds</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRtcCheckAccesses</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRtcGenerateEntries</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcNrTrackedPointers</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>GenRtcIntOverflow</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcIncUnsigned</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcIntConversion</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcInclExplicit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcIntShiftOverflow</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcInclUnsignedShiftOverflow</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcUnhandledCase</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcDivByZero</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcCheckPtrsNonInstrFunc</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+    </configuration>
+</project>

bsp/imxrt/imxrt1060-nxp-evk/template.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\template.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/imxrt/imxrt1060-nxp-evk/xip/evkbmimxrt1060_flexspi_nor_config.c

@@ -1,48 +0,0 @@
-/*
- * Copyright 2021 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "evkbmimxrt1060_flexspi_nor_config.h"
-
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.xip_board"
-#endif
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
-#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
-__attribute__((section(".boot_hdr.conf"), used))
-#elif defined(__ICCARM__)
-#pragma location = ".boot_hdr.conf"
-#endif
-
-const flexspi_nor_config_t qspiflash_config = {
-    .memConfig =
-        {
-            .tag              = FLEXSPI_CFG_BLK_TAG,
-            .version          = FLEXSPI_CFG_BLK_VERSION,
-            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
-            .csHoldTime       = 3u,
-            .csSetupTime      = 3u,
-            .sflashPadType    = kSerialFlash_4Pads,
-            .serialClkFreq    = kFlexSpiSerialClk_100MHz,
-            .sflashA1Size     = 8u * 1024u * 1024u,
-            .lookupTable =
-                {
-                    // Read LUTs
-                    FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
-                    FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
-                },
-        },
-    .pageSize           = 256u,
-    .sectorSize         = 4u * 1024u,
-    .blockSize          = 64u * 1024u,
-    .isUniformBlockSize = false,
-};
-#endif /* XIP_BOOT_HEADER_ENABLE */

bsp/imxrt/imxrt1060-nxp-evk/xip/evkmimxrt1060_flexspi_nor_config.c

@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "evkmimxrt1060_flexspi_nor_config.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t qspiflash_config = {
+    .memConfig =
+        {
+            .tag                  = FLEXSPI_CFG_BLK_TAG,
+            .version              = FLEXSPI_CFG_BLK_VERSION,
+            .readSampleClkSrc     = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
+            .csHoldTime           = 3u,
+            .csSetupTime          = 3u,
+            .controllerMiscOption = (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable),
+            .deviceType           = kFlexSpiDeviceType_SerialNOR,
+            .sflashPadType        = kSerialFlash_4Pads,
+            .serialClkFreq        = kFlexSpiSerialClk_120MHz,
+            .sflashA1Size         = 8u * 1024u * 1024u,
+            .lookupTable =
+                {
+                    // Read LUTs
+                    [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
+                    [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
+
+                    // Read Status LUTs
+                    [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
+
+                    // Write Enable LUTs
+                    [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),
+
+                    // Erase Sector LUTs
+                    [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18),
+
+                    // Erase Block LUTs
+                    [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),
+
+                    // Pape Program LUTs
+                    [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18),
+                    [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
+
+                    // Erase Chip LUTs
+                    [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),
+                },
+        },
+    .pageSize           = 256u,
+    .sectorSize         = 4u * 1024u,
+    .ipcmdSerialClkFreq = 1u,
+    .blockSize          = 64u * 1024u,
+    .isUniformBlockSize = false,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */

bsp/imxrt/imxrt1060-nxp-evk/xip/evkbmimxrt1060_flexspi_nor_config.h → bsp/imxrt/imxrt1060-nxp-evk/xip/evkmimxrt1060_flexspi_nor_config.h

@@ -1,12 +1,12 @@
 /*
- * Copyright 2021 NXP
+ * Copyright 2018-2020 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__
-#define __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__
+#ifndef __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
+#define __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
 
 #include <stdint.h>
 #include <stdbool.h>
@@ -265,4 +265,4 @@ extern "C" {
 #ifdef __cplusplus
 }
 #endif
-#endif /* __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__ */
+#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */

bsp/imxrt/imxrt1060-nxp-evk/xip/fsl_flexspi_nor_boot.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2021 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -9,13 +9,15 @@
 #define __FLEXSPI_NOR_BOOT_H__
 
 #include <stdint.h>
-#include "board.h"
 #include "fsl_common.h"
+#ifndef BOARD_FLASH_SIZE
+#include "board.h"
+#endif
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief XIP_DEVICE driver version 2.0.2. */
-#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*! @brief XIP_DEVICE driver version 2.0.3. */
+#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
 /*@}*/
 
 /*************************************
@@ -75,8 +77,8 @@ extern uint32_t __Vectors[];
 extern uint32_t __VECTOR_TABLE[];
 #define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE)
 #elif defined(__GNUC__)
-extern uint32_t __isr_vector[];
-#define IMAGE_ENTRY_ADDRESS ((uint32_t)__isr_vector)
+extern uint32_t __VECTOR_TABLE[];
+#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE)
 #endif
 
 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE)
@@ -100,7 +102,12 @@ typedef struct _boot_data_
     uint32_t placeholder; /* placehoder to make even 0x10 size */
 } BOOT_DATA_T;
 
+#ifdef FlexSPI1_AMBA_BASE
+#define FLASH_BASE FlexSPI1_AMBA_BASE
+#else
 #define FLASH_BASE FlexSPI_AMBA_BASE
+#endif
+
 #if defined(BOARD_FLASH_SIZE)
 #define FLASH_SIZE BOARD_FLASH_SIZE
 #else

bsp/imxrt/imxrt1170-nxp-evk/m7/.config

@@ -84,8 +84,10 @@ CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
 CONFIG_RT_VER_NUM=0x50000
+
 # CONFIG_RT_USING_CACHE is not set
 # CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 # CONFIG_RT_USING_CPU_FFS is not set
 
@@ -160,9 +162,12 @@ CONFIG_RT_USING_PIN=y
 #
 # Using USB
 #
-# CONFIG_RT_USING_USB is not set
-# CONFIG_RT_USING_USB_HOST is not set
+CONFIG_RT_USING_USB=y
+CONFIG_RT_USING_USB_HOST=y
+# CONFIG_RT_USBH_MSTORAGE is not set
+# CONFIG_RT_USBH_HID is not set
 # CONFIG_RT_USING_USB_DEVICE is not set
+CONFIG_RT_USBD_THREAD_STACK_SZ=4096
 
 #
 # C/C++ and POSIX layer
@@ -308,6 +313,7 @@ CONFIG_NETDEV_IPV6=0
 # CONFIG_PKG_USING_AGILE_FTP is not set
 # CONFIG_PKG_USING_EMBEDDEDPROTO is not set
 # CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
 # CONFIG_PKG_USING_LORA_PKT_FWD is not set
 # CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
 # CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@@ -955,6 +961,7 @@ CONFIG_NETDEV_IPV6=0
 # Uncategorized
 #
 
+
 #
 # Privated Packages of RealThread
 #
@@ -1012,6 +1019,7 @@ CONFIG_NETDEV_IPV6=0
 # CONFIG_PKG_USING_UKERNEL is not set
 # CONFIG_PKG_USING_TRACE_AGENT is not set
 
+
 #
 # Hardware Drivers Config
 #
@@ -1024,7 +1032,9 @@ CONFIG_SOC_MIMXRT1176DVMAA=y
 # CONFIG_BSP_USING_DMA is not set
 CONFIG_BSP_USING_GPIO=y
 # CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USB1_HOST is not set
 # CONFIG_BSP_USING_USB is not set
+
 # CONFIG_BSP_USING_SDIO is not set
 CONFIG_BSP_USING_LPUART=y
 CONFIG_BSP_USING_LPUART1=y

bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewd

@@ -76,7 +76,7 @@
                 </option>
                 <option>
                     <name>OCDownloadVerifyAll</name>
-                    <state>1</state>
+                    <state>0</state>
                 </option>
                 <option>
                     <name>OCProductVersion</name>
@@ -84,15 +84,15 @@
                 </option>
                 <option>
                     <name>OCDynDriverList</name>
-                    <state>CMSISDAP_ID</state>
+                    <state>JLINK_ID</state>
                 </option>
                 <option>
                     <name>OCLastSavedByProductVersion</name>
-                    <state>9.20.4.46976</state>
+                    <state>9.30.1.50052</state>
                 </option>
                 <option>
                     <name>UseFlashLoader</name>
-                    <state>1</state>
+                    <state>0</state>
                 </option>
                 <option>
                     <name>CLowLevel</name>
@@ -112,7 +112,7 @@
                 </option>
                 <option>
                     <name>FlashLoadersV3</name>
-                    <state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashIMXRT1170_FlexSPI.board</state>
+                    <state>$TOOLKIT_DIR$/config/flashloader/NXP/FlashIMXRT1170_FlexSPI.board</state>
                 </option>
                 <option>
                     <name>OCImagesSuppressCheck1</name>
@@ -429,7 +429,7 @@
                 </option>
                 <option>
                     <name>OCProbeConfig</name>
-                    <state>$TOOLKIT_DIR$\config\debugger\NXP\IMXRT1170.ProbeConfig</state>
+                    <state>$TOOLKIT_DIR$/config/debugger/NXP/IMXRT1170.ProbeConfig</state>
                 </option>
                 <option>
                     <name>CMSISDAPProbeConfigRadio</name>
@@ -1417,7 +1417,7 @@
                 </option>
                 <option>
                     <name>CCXds100ResetList</name>
-                    <version>1</version>
+                    <version>0</version>
                     <state>0</state>
                 </option>
                 <option>

bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewp

@@ -10,9 +10,13 @@
       <name>General</name>
       <archiveVersion>3</archiveVersion>
       <data>
-        <version>31</version>
+        <version>35</version>
         <wantNonLocal>1</wantNonLocal>
         <debug>1</debug>
+        <option>
+          <name>BrowseInfoPath</name>
+          <state>rtthread\BrowseInfo</state>
+        </option>
         <option>
           <name>ExePath</name>
           <state>build\iar\Exe</state>
@@ -57,7 +61,7 @@
         </option>
         <option>
           <name>RTDescription</name>
-          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+          <state>A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
         </option>
         <option>
           <name>OGProductVersion</name>
@@ -65,15 +69,7 @@
         </option>
         <option>
           <name>OGLastSavedByProductVersion</name>
-          <state>8.32.1.18618</state>
-        </option>
-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
+          <state>9.30.1.50052</state>
         </option>
         <option>
           <name>OGChipSelectEditMenu</name>
@@ -95,27 +91,13 @@
           <name>GenStdoutInterface</name>
           <state>0</state>
         </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
         <option>
           <name>RTConfigPath2</name>
           <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
         </option>
         <option>
           <name>GBECoreSlave</name>
-          <version>26</version>
+          <version>32</version>
           <state>41</state>
         </option>
         <option>
@@ -132,7 +114,7 @@
         </option>
         <option>
           <name>CoreVariant</name>
-          <version>26</version>
+          <version>32</version>
           <state>41</state>
         </option>
         <option>
@@ -155,7 +137,7 @@
         </option>
         <option>
           <name>GFPUCoreSlave2</name>
-          <version>26</version>
+          <version>32</version>
           <state>41</state>
         </option>
         <option>
@@ -208,13 +190,33 @@
           <version>0</version>
           <state>0</state>
         </option>
+        <option>
+          <name>OGAarch64Abi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OG_32_64Device</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BuildFilesPath</name>
+          <state>rtthread</state>
+        </option>
+        <option>
+          <name>PointerAuthentication</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU64</name>
+          <state>1</state>
+        </option>
       </data>
     </settings>
     <settings>
       <name>ICCARM</name>
       <archiveVersion>2</archiveVersion>
       <data>
-        <version>35</version>
+        <version>37</version>
         <wantNonLocal>1</wantNonLocal>
         <debug>1</debug>
         <option>
@@ -236,6 +238,8 @@
           <state>ARM_MATH_CM7</state>
           <state>USE_SDRAM</state>
           <state>SOC_IMXRT1170_SERIES</state>
+          <state>ENDIANNESS</state>
+          <state>USE_RTOS</state>
           <state>__RTTHREAD__</state>
         </option>
         <option>
@@ -355,36 +359,36 @@
           <name>PreInclude</name>
           <state />
         </option>
-        <option>
-          <name>CompilerMisraOverride</name>
-          <state>0</state>
-        </option>
         <option>
           <name>CCIncludePath2</name>
           <state />
-          <state>$PROJ_DIR$\..\..\..\components\finsh</state>
-          <state>$PROJ_DIR$\board\MCUX_Config</state>
-          <state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
-          <state>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176</state>
-          <state>$PROJ_DIR$\xip</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\posix\ipc</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\stdio</state>
-          <state>$PROJ_DIR$\..\libraries\drivers</state>
+          <state>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\extension</state>
+          <state>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176</state>
+          <state>$PROJ_DIR$\..\..\libraries\MIMXRT1170\CMSIS\Include</state>
+          <state>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
+          <state>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost\include</state>
+          <state>$PROJ_DIR$\..\..\..\..\components\libc\posix\io\stdio</state>
+          <state>$PROJ_DIR$\..\..\..\..\components\libc\posix\io\poll</state>
+          <state>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\cm7</state>
+          <state>$PROJ_DIR$\..\..\libraries\drivers</state>
+          <state>$PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m7</state>
           <state>$PROJ_DIR$\.</state>
-          <state>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers</state>
+          <state>$PROJ_DIR$\xip</state>
           <state>$PROJ_DIR$\board</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension\fcntl\octal</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\include</state>
+          <state>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers</state>
+          <state>$PROJ_DIR$\..\..\..\..\components\net\netdev\include</state>
+          <state>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost\core</state>
+          <state>$PROJ_DIR$\..\..\..\..\components\drivers\include</state>
+          <state>$PROJ_DIR$\board\MCUX_Config</state>
+          <state>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost\class</state>
           <state>$PROJ_DIR$\board\ports</state>
           <state>$PROJ_DIR$\applications</state>
-          <state>$PROJ_DIR$\..\libraries\MIMXRT1170\CMSIS\Include</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\posix\io\poll</state>
-          <state>$PROJ_DIR$\..\..\..\include</state>
-          <state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
-          <state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7</state>
-          <state>$PROJ_DIR$\..\..\..\components\net\netdev\include</state>
-          <state>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\cm7</state>
-          <state>$PROJ_DIR$\..\..\..\components\libc\compilers\common\extension</state>
+          <state>$PROJ_DIR$\..\..\..\..\include</state>
+          <state>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\include</state>
+          <state>$PROJ_DIR$\..\..\..\..\components\libc\posix\ipc</state>
+          <state>$PROJ_DIR$\..\..\..\..\libcpu\arm\common</state>
+          <state>$PROJ_DIR$\..\..\..\..\components\finsh</state>
+          <state>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost</state>
         </option>
         <option>
           <name>CCStdIncCheck</name>
@@ -411,16 +415,6 @@
           <name>CCOptLevelSlave</name>
           <state>1</state>
         </option>
-        <option>
-          <name>CompilerMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>CompilerMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
         <option>
           <name>CCPosIndRopi</name>
           <state>0</state>
@@ -502,13 +496,17 @@
           <name>OICompilerExtraOption</name>
           <state>1</state>
         </option>
+        <option>
+          <name>CCStackProtection</name>
+          <state>0</state>
+        </option>
       </data>
     </settings>
     <settings>
       <name>AARM</name>
       <archiveVersion>2</archiveVersion>
       <data>
-        <version>10</version>
+        <version>11</version>
         <wantNonLocal>1</wantNonLocal>
         <debug>1</debug>
         <option>
@@ -664,6 +662,10 @@
           <name>AsmNoLiteralPool</name>
           <state>0</state>
         </option>
+        <option>
+          <name>PreInclude</name>
+          <state />
+        </option>
       </data>
     </settings>
     <settings>
@@ -702,14 +704,10 @@
       <data>
         <extensions />
         <cmdline />
-        <hasPrio>0</hasPrio>
+        <hasPrio>208</hasPrio>
+        <buildSequence>inputOutputBased</buildSequence>
       </data>
     </settings>
-    <settings>
-      <name>BICOMP</name>
-      <archiveVersion>0</archiveVersion>
-      <data />
-    </settings>
     <settings>
       <name>BUILDACTION</name>
       <archiveVersion>1</archiveVersion>
@@ -722,17 +720,13 @@
       <name>ILINK</name>
       <archiveVersion>0</archiveVersion>
       <data>
-        <version>22</version>
+        <version>27</version>
         <wantNonLocal>1</wantNonLocal>
         <debug>1</debug>
         <option>
           <name>IlinkLibIOConfig</name>
           <state>1</state>
         </option>
-        <option>
-          <name>XLinkMisraHandler</name>
-          <state>0</state>
-        </option>
         <option>
           <name>IlinkInputFileSlave</name>
           <state>0</state>
@@ -1042,6 +1036,58 @@
           <name>OILinkExtraOption</name>
           <state>1</state>
         </option>
+        <option>
+          <name>IlinkRawBinaryFile2</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol2</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment2</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign2</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkLogCrtRoutineSelection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogFragmentInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInlining</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogMerging</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkDemangle</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkWrapperFileEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkWrapperFile</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkFpuProcessor</name>
+          <state>1</state>
+        </option>
       </data>
     </settings>
     <settings>
@@ -1065,11 +1111,6 @@
         </option>
       </data>
     </settings>
-    <settings>
-      <name>BILINK</name>
-      <archiveVersion>0</archiveVersion>
-      <data />
-    </settings>
   </configuration>
   <group>
     <name>Applications</name>
@@ -1083,106 +1124,106 @@
   <group>
     <name>Compiler</name>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cctype.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdio.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdio.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdlib.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstring.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\ctime.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cwchar.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\environ.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_close.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_lseek.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_mem.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_open.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_read.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_remove.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_write.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscalls.c</name>
     </file>
   </group>
   <group>
     <name>CPU</name>
     <file>
-      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\libcpu\arm\common\backtrace.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\libcpu\arm\common\div0.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\libcpu\arm\common\showmem.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\context_iar.S</name>
+      <name>$PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m7\context_iar.S</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\cpu_cache.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m7\cpu_cache.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\cpuport.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m7\cpuport.c</name>
     </file>
   </group>
   <group>
     <name>DeviceDrivers</name>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\cputime\cputime.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\drivers\cputime\cputime.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\drivers\ipc\pipe.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringblk_buf.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringbuffer.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\drivers\ipc\waitqueue.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\drivers\ipc\workqueue.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\misc\pin.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\drivers\misc\pin.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\phy\phy.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\drivers\phy\phy.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\drivers\serial\serial.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\drivers\serial\serial.c</name>
     </file>
   </group>
   <group>
@@ -1200,124 +1241,166 @@
       <name>$PROJ_DIR$\board\dcd.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\libraries\drivers\drv_gpio.c</name>
+      <name>$PROJ_DIR$\..\..\libraries\drivers\drv_common.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libraries\drivers\drv_gpio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libraries\drivers\drv_uart.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libraries\drivers\drv_usbh.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libraries\drivers\usb\host\usb_host_devices.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\libraries\drivers\drv_uart.c</name>
+      <name>$PROJ_DIR$\..\..\libraries\drivers\usb\host\usb_host_ehci.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libraries\drivers\usb\host\usb_host_framework.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libraries\drivers\usb\host\usb_host_hci.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libraries\drivers\usb\phy\usb_phy.c</name>
     </file>
   </group>
   <group>
     <name>Finsh</name>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\finsh\shell.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\finsh\shell.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\finsh\msh.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\finsh\msh.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\finsh\msh_parse.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\finsh\msh_parse.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\finsh\cmd.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\finsh\cmd.c</name>
     </file>
   </group>
   <group>
     <name>Kernel</name>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\clock.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\src\clock.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\components.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\src\components.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\device.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\src\device.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\idle.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\src\idle.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\ipc.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\src\ipc.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\irq.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\src\irq.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\kservice.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\src\kservice.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\memheap.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\src\memheap.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\mempool.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\src\mempool.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\object.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\src\object.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\scheduler.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\src\scheduler.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\thread.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\src\thread.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\src\timer.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\src\timer.c</name>
     </file>
   </group>
   <group>
     <name>Libraries</name>
     <file>
-      <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_pmu.c</name>
+      <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_pmu.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\system_MIMXRT1176_cm7.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\system_MIMXRT1176_cm7.c</name>
+      <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_lpuart.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_lpuart.c</name>
+      <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_gpio.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_gpio.c</name>
+      <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_os_abstraction_rtthread.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\iar\startup_MIMXRT1176_cm7.s</name>
+      <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\iar\startup_MIMXRT1176_cm7.s</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_anatop_ai.c</name>
+      <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_anatop_ai.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_dcdc.c</name>
+      <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_dcdc.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\cm7\fsl_cache.c</name>
+      <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\cm7\fsl_cache.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_common_arm.c</name>
+      <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_common_arm.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_common.c</name>
+      <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_common.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_clock.c</name>
+      <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\generic_list.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libraries\MIMXRT1170\MIMXRT1176\drivers\fsl_clock.c</name>
     </file>
   </group>
   <group>
     <name>POSIX</name>
   </group>
+  <group>
+    <name>rt_usbh</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost\core\hub.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost\core\usbhost.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost\core\usbhost_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\..\components\drivers\usb\usbhost\core\driver.c</name>
+    </file>
+  </group>
   <group>
     <name>SAL</name>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\net\netdev\src\netdev.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\net\netdev\src\netdev.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\..\..\..\components\net\netdev\src\netdev_ipaddr.c</name>
+      <name>$PROJ_DIR$\..\..\..\..\components\net\netdev\src\netdev_ipaddr.c</name>
     </file>
   </group>
   <group>
     <name>xip</name>
     <file>
-      <name>$PROJ_DIR$\xip\fsl_flexspi_nor_boot.c</name>
+      <name>$PROJ_DIR$\xip\evkmimxrt1170_flexspi_nor_config.c</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\xip\evkmimxrt1170_flexspi_nor_config.c</name>
+      <name>$PROJ_DIR$\xip\fsl_flexspi_nor_boot.c</name>
     </file>
   </group>
 </project>

bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.h

@@ -80,6 +80,9 @@
 
 /* Using USB */
 
+#define RT_USING_USB
+#define RT_USING_USB_HOST
+#define RT_USBD_THREAD_STACK_SZ 4096
 
 /* C/C++ and POSIX layer */
 
@@ -217,23 +220,14 @@
 
 /* Device Control */
 
+/* Privated Packages of RealThread */
 
 /* Other */
 
 /* Signal IO */
 
-
 /* Uncategorized */
 
-/* Privated Packages of RealThread */
-
-
-/* Network Utilities */
-
-
-/* RT-Thread Smart */
-
-
 /* Hardware Drivers Config */
 
 #define BSP_USING_QSPIFLASH
@@ -242,6 +236,8 @@
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_GPIO
+#define BSP_USING_USB
+#define BSP_USB0_HOST
 #define BSP_USING_LPUART
 #define BSP_USING_LPUART1
 

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062_features.h

@@ -1,13 +1,13 @@
 /*
 ** ###################################################################
-**     Version:             rev. 1.0, 2018-11-16
-**     Build:               b211108
+**     Version:             rev. 2.0, 2022-03-25
+**     Build:               b220426
 **
 **     Abstract:
 **         Chip specific module features.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2021 NXP
+**     Copyright 2016-2022 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -20,6 +20,8 @@
 **         Initial version.
 **     - rev. 1.0 (2018-11-16)
 **         Update feature files to align with IMXRT1060RM Rev.0.
+**     - rev. 2.0 (2022-03-25)
+**         Add RT1060X device
 **
 ** ###################################################################
 */
@@ -72,7 +74,7 @@
 /* @brief I2S availability on the SoC. */
 #define FSL_FEATURE_SOC_I2S_COUNT (3)
 /* @brief IGPIO availability on the SoC. */
-#define FSL_FEATURE_SOC_IGPIO_COUNT (9)
+#define FSL_FEATURE_SOC_IGPIO_COUNT (10)
 /* @brief IOMUXC availability on the SoC. */
 #define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
 /* @brief IOMUXC_GPR availability on the SoC. */
@@ -89,6 +91,8 @@
 #define FSL_FEATURE_SOC_LPSPI_COUNT (4)
 /* @brief LPUART availability on the SoC. */
 #define FSL_FEATURE_SOC_LPUART_COUNT (8)
+/* @brief MPU availability on the SoC. */
+#define FSL_FEATURE_SOC_MPU_COUNT (1)
 /* @brief OCOTP availability on the SoC. */
 #define FSL_FEATURE_SOC_OCOTP_COUNT (1)
 /* @brief PIT availability on the SoC. */
@@ -338,6 +342,8 @@
 #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0)
 /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */
 #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0)
+/* @brief ENET Has Extra Clock Gate.(RW610). */
+#define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0)
 
 /* EWM module features */
 
@@ -392,6 +398,12 @@
 #define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0)
 /* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */
 #define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1)
+/* @brief FLEXSPI has no IP parallel mode. */
+#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0)
+/* @brief FLEXSPI has no AHB parallel mode. */
+#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0)
+/* @brief FLEXSPI support address shift. */
+#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0)
 
 /* GPC module features */
 
@@ -648,6 +660,8 @@
 #define FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT (1)
 /* @brief If SEMC has register DBICR2 (register DBICR2). */
 #define FSL_FEATURE_SEMC_HAS_DBICR2 (0)
+/* @brief SEMC supports hardware ECC on NAND flash interface. */
+#define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0)
 
 /* SNVS module features */
 

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_flexspi_nor.scf

@@ -5,17 +5,19 @@
 **                          MIMXRT1062CVL5A
 **                          MIMXRT1062DVJ6A
 **                          MIMXRT1062DVL6A
+**                          MIMXRT1062DVN6B
+**                          MIMXRT1062XVN5B
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b210709
+**     Reference manual:    IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+**     Version:             rev. 0.2, 2022-03-25
+**     Build:               b220401
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2021 NXP
+**     Copyright 2016-2022 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_flexspi_nor_sdram.scf

@@ -5,17 +5,19 @@
 **                          MIMXRT1062CVL5A
 **                          MIMXRT1062DVJ6A
 **                          MIMXRT1062DVL6A
+**                          MIMXRT1062DVN6B
+**                          MIMXRT1062XVN5B
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b210709
+**     Reference manual:    IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+**     Version:             rev. 0.2, 2022-03-25
+**     Build:               b220401
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2021 NXP
+**     Copyright 2016-2022 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_ram.scf

@@ -5,17 +5,19 @@
 **                          MIMXRT1062CVL5A
 **                          MIMXRT1062DVJ6A
 **                          MIMXRT1062DVL6A
+**                          MIMXRT1062DVN6B
+**                          MIMXRT1062XVN5B
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b210709
+**     Reference manual:    IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+**     Version:             rev. 0.2, 2022-03-25
+**     Build:               b220401
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2021 NXP
+**     Copyright 2016-2022 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_sdram.scf

@@ -5,17 +5,19 @@
 **                          MIMXRT1062CVL5A
 **                          MIMXRT1062DVJ6A
 **                          MIMXRT1062DVL6A
+**                          MIMXRT1062DVN6B
+**                          MIMXRT1062XVN5B
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b210709
+**     Reference manual:    IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+**     Version:             rev. 0.2, 2022-03-25
+**     Build:               b220401
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2021 NXP
+**     Copyright 2016-2022 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_sdram_txt.scf

@@ -5,17 +5,19 @@
 **                          MIMXRT1062CVL5A
 **                          MIMXRT1062DVJ6A
 **                          MIMXRT1062DVL6A
+**                          MIMXRT1062DVN6B
+**                          MIMXRT1062XVN5B
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b210709
+**     Reference manual:    IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+**     Version:             rev. 0.2, 2022-03-25
+**     Build:               b220401
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2021 NXP
+**     Copyright 2016-2022 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/startup_MIMXRT1062.S

@@ -2,13 +2,13 @@
 /*  @file:    startup_MIMXRT1062.s                                           */
 /*  @purpose: CMSIS Cortex-M7 Core Device Startup File                       */
 /*            MIMXRT1062                                                     */
-/*  @version: 1.2                                                            */
-/*  @date:    2019-4-29                                                      */
-/*  @build:   b210419                                                        */
+/*  @version: 1.4                                                            */
+/*  @date:    2022-3-25                                                      */
+/*  @build:   b220425                                                        */
 /* ------------------------------------------------------------------------- */
 /*                                                                           */
 /* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
-/* Copyright 2016-2021 NXP                                                   */
+/* Copyright 2016-2022 NXP                                                   */
 /* All rights reserved.                                                      */
 /*                                                                           */
 /* SPDX-License-Identifier: BSD-3-Clause                                     */
@@ -112,7 +112,7 @@ __Vectors:
     .long   ADC2_IRQHandler                                 /* ADC2 interrupt*/
     .long   DCDC_IRQHandler                                 /* DCDC interrupt*/
     .long   Reserved86_IRQHandler                           /* Reserved interrupt*/
-    .long   Reserved87_IRQHandler                           /* Reserved interrupt*/
+    .long   GPIO10_Combined_0_31_IRQHandler                 /* Combined interrupt indication for GPIO10 signal 0 throughout 31*/
     .long   GPIO1_INT0_IRQHandler                           /* Active HIGH Interrupt from INT0 from GPIO*/
     .long   GPIO1_INT1_IRQHandler                           /* Active HIGH Interrupt from INT1 from GPIO*/
     .long   GPIO1_INT2_IRQHandler                           /* Active HIGH Interrupt from INT2 from GPIO*/
@@ -150,7 +150,7 @@ __Vectors:
     .long   PWM1_FAULT_IRQHandler                           /* PWM1 fault or reload error interrupt*/
     .long   FLEXSPI2_IRQHandler                             /* FlexSPI2 interrupt*/
     .long   FLEXSPI_IRQHandler                              /* FlexSPI0 interrupt*/
-    .long   SEMC_IRQHandler                                 /* Reserved interrupt*/
+    .long   SEMC_IRQHandler                                 /* SEMC interrupt*/
     .long   USDHC1_IRQHandler                               /* USDHC1 interrupt*/
     .long   USDHC2_IRQHandler                               /* USDHC2 interrupt*/
     .long   USB_OTG2_IRQHandler                             /* USBO2 USB OTG2*/
@@ -301,11 +301,11 @@ Reset_Handler:
     str     r1, [r0]
     ldr     r2, [r1]
     msr     msp, r2
-    ldr   r0,=SystemInit
-    blx   r0
+    ldr     r0,=SystemInit
+    blx     r0
     cpsie   i               /* Unmask interrupts */
-    ldr   r0,=__main
-    bx    r0
+    ldr     r0,=__main
+    bx      r0
 
     .pool
     .size Reset_Handler, . - Reset_Handler
@@ -916,7 +916,7 @@ FLEXIO3_IRQHandler:
     def_irq_handler    ADC2_IRQHandler
     def_irq_handler    DCDC_IRQHandler
     def_irq_handler    Reserved86_IRQHandler
-    def_irq_handler    Reserved87_IRQHandler
+    def_irq_handler    GPIO10_Combined_0_31_IRQHandler
     def_irq_handler    GPIO1_INT0_IRQHandler
     def_irq_handler    GPIO1_INT1_IRQHandler
     def_irq_handler    GPIO1_INT2_IRQHandler

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_common.c

@@ -21,13 +21,14 @@ typedef struct _mem_align_control_block
 #define FSL_COMPONENT_ID "platform.drivers.common"
 #endif
 
+#if !((defined(__DSC__) && defined(__CW__)))
 void *SDK_Malloc(size_t size, size_t alignbytes)
 {
     mem_align_cb_t *p_cb = NULL;
     uint32_t alignedsize;
 
     /* Check overflow. */
-    alignedsize = SDK_SIZEALIGN(size, alignbytes);
+    alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes);
     if (alignedsize < size)
     {
         return NULL;
@@ -38,19 +39,15 @@ void *SDK_Malloc(size_t size, size_t alignbytes)
         return NULL;
     }
 
-    alignedsize += alignbytes + sizeof(mem_align_cb_t);
+    alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t);
 
     union
     {
         void *pointer_value;
-#if (defined(__DSC__) && defined(__CW__))
-        uint32_t unsigned_value;
-#else
         uintptr_t unsigned_value;
-#endif
     } p_align_addr, p_addr;
 
-    p_addr.pointer_value = malloc(alignedsize);
+    p_addr.pointer_value = malloc((size_t)alignedsize);
 
     if (p_addr.pointer_value == NULL)
     {
@@ -71,11 +68,7 @@ void SDK_Free(void *ptr)
     union
     {
         void *pointer_value;
-#if (defined(__DSC__) && defined(__CW__))
-        uint32_t unsigned_value;
-#else
         uintptr_t unsigned_value;
-#endif
     } p_free;
     p_free.pointer_value = ptr;
     mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
@@ -89,3 +82,4 @@ void SDK_Free(void *ptr)
 
     free(p_free.pointer_value);
 }
+#endif

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_common.h

@@ -59,7 +59,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief common driver version. */
-#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
 /*@}*/
 
 /* Debug console type definition. */
@@ -190,6 +190,11 @@ enum _status_groups
     kStatusGroup_SNT            = 157, /*!< Group number for SNT status codes. */
     kStatusGroup_QUEUEDSPI      = 158, /*!< Group number for QSPI status codes. */
     kStatusGroup_POWER_MANAGER  = 159, /*!< Group number for POWER_MANAGER status codes. */
+    kStatusGroup_IPED = 160,                  /*!< Group number for IPED status codes. */
+    kStatusGroup_CSS_PKC = 161,               /*!< Group number for CSS PKC status codes. */
+    kStatusGroup_HOSTIF      = 162, /*!< Group number for HOSTIF status codes. */
+    kStatusGroup_CLIF           = 163, /*!< Group number for CLIF status codes. */
+    kStatusGroup_BMA            = 164, /*!< Group number for BMA status codes. */
 };
 
 /*! \public
@@ -264,6 +269,7 @@ typedef int32_t status_t;
 extern "C" {
 #endif
 
+#if !((defined(__DSC__) && defined(__CW__)))
 /*!
  * @brief Allocate memory with given alignment and aligned size.
  *
@@ -281,6 +287,7 @@ void *SDK_Malloc(size_t size, size_t alignbytes);
  * @param ptr The memory to be release.
  */
 void SDK_Free(void *ptr);
+#endif
 
 /*!
  * @brief Delay at least for some time.

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_edma.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -314,19 +314,19 @@ void EDMA_SetChannelPreemptionConfig(DMA_Type *base, uint32_t channel, const edm
  *
  * param base eDMA peripheral base address.
  * param channel eDMA channel number.
- * param type A channel link type, which can be one of the following:
+ * param linkType A channel link type, which can be one of the following:
  *   arg kEDMA_LinkNone
  *   arg kEDMA_MinorLink
  *   arg kEDMA_MajorLink
  * param linkedChannel The linked channel number.
  * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
  */
-void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)
+void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t linkType, uint32_t linkedChannel)
 {
     assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
     assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
 
-    EDMA_TcdSetChannelLink((edma_tcd_t *)(uint32_t)&base->TCD[channel], type, linkedChannel);
+    EDMA_TcdSetChannelLink((edma_tcd_t *)(uint32_t)&base->TCD[channel], linkType, linkedChannel);
 }
 
 /*!
@@ -458,7 +458,7 @@ void EDMA_TcdReset(edma_tcd_t *tcd)
     tcd->CITER     = 0U;
     tcd->DLAST_SGA = 0U;
     /* Enable auto disable request feature */
-    tcd->CSR   = DMA_CSR_DREQ(true);
+    tcd->CSR   = DMA_CSR_DREQ(1U);
     tcd->BITER = 0U;
 }
 
@@ -466,7 +466,7 @@ void EDMA_TcdReset(edma_tcd_t *tcd)
  * brief Configures the eDMA TCD transfer attribute.
  *
  * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
- * The STCD is used in the scatter-gather mode.
+ * The TCD is used in the scatter-gather mode.
  * This function configures the TCD transfer attribute, including source address, destination address,
  * transfer size, address offset, and so on. It also configures the scatter gather feature if the
  * user supplies the next TCD address.
@@ -592,19 +592,19 @@ void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t
  *
  * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
  * param tcd Point to the TCD structure.
- * param type Channel link type, it can be one of:
+ * param linkType Channel link type, it can be one of:
  *   arg kEDMA_LinkNone
  *   arg kEDMA_MinorLink
  *   arg kEDMA_MajorLink
  * param linkedChannel The linked channel number.
  */
-void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)
+void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t linkType, uint32_t linkedChannel)
 {
     assert(tcd != NULL);
     assert(((uint32_t)tcd & 0x1FU) == 0U);
     assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
 
-    if (type == kEDMA_MinorLink) /* Minor link config */
+    if (linkType == kEDMA_MinorLink) /* Minor link config */
     {
         uint16_t tmpreg;
 
@@ -619,7 +619,7 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint
         tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel);
         tcd->BITER = tmpreg;
     }
-    else if (type == kEDMA_MajorLink) /* Major link config */
+    else if (linkType == kEDMA_MajorLink) /* Major link config */
     {
         uint16_t tmpreg;
 
@@ -1044,7 +1044,7 @@ void EDMA_PrepareTransferConfig(edma_transfer_config_t *config,
  * param destWidth eDMA transfer destination address width(bytes).
  * param bytesEachRequest eDMA transfer bytes per channel request.
  * param transferBytes eDMA transfer bytes to be transferred.
- * param type eDMA transfer type.
+ * param transferType eDMA transfer type.
  * note The data address and the data width must be consistent. For example, if the SRC
  *       is 4 bytes, the source address must be 4 bytes aligned, or it results in
  *       source address error (SAE).
@@ -1056,13 +1056,13 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
                           uint32_t destWidth,
                           uint32_t bytesEachRequest,
                           uint32_t transferBytes,
-                          edma_transfer_type_t type)
+                          edma_transfer_type_t transferType)
 {
     assert(config != NULL);
 
     int16_t srcOffset = 0, destOffset = 0;
 
-    switch (type)
+    switch (transferType)
     {
         case kEDMA_MemoryToMemory:
             destOffset = (int16_t)destWidth;
@@ -1468,6 +1468,15 @@ void EDMA_HandleIRQ(edma_handle_t *handle)
             {
                 tcds_done += handle->tcdSize;
             }
+            /*
+             * While code run to here, it means a TCD transfer Done and a new TCD has loaded to the hardware
+             * so clear DONE here to allow submit scatter gather transfer request in the callback to avoid TCD
+             * overwritten.
+             */
+            if (transfer_done)
+            {
+                handle->base->CDNE = handle->channel;
+            }
         }
         /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */
         handle->header = (int8_t)new_header;

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_edma.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -438,14 +438,14 @@ void EDMA_SetChannelPreemptionConfig(DMA_Type *base, uint32_t channel, const edm
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param type A channel link type, which can be one of the following:
+ * @param linkType A channel link type, which can be one of the following:
  *   @arg kEDMA_LinkNone
  *   @arg kEDMA_MinorLink
  *   @arg kEDMA_MajorLink
  * @param linkedChannel The linked channel number.
  * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
  */
-void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel);
+void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t linkType, uint32_t linkedChannel);
 
 /*!
  * @brief Sets the bandwidth for the eDMA transfer.
@@ -563,7 +563,7 @@ void EDMA_TcdReset(edma_tcd_t *tcd);
  * @brief Configures the eDMA TCD transfer attribute.
  *
  * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
- * The STCD is used in the scatter-gather mode.
+ * The TCD is used in the scatter-gather mode.
  * This function configures the TCD transfer attribute, including source address, destination address,
  * transfer size, address offset, and so on. It also configures the scatter gather feature if the
  * user supplies the next TCD address.
@@ -608,13 +608,13 @@ void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_confi
  *
  * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
  * @param tcd Point to the TCD structure.
- * @param type Channel link type, it can be one of:
+ * @param linkType Channel link type, it can be one of:
  *   @arg kEDMA_LinkNone
  *   @arg kEDMA_MinorLink
  *   @arg kEDMA_MajorLink
  * @param linkedChannel The linked channel number.
  */
-void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel);
+void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t linkType, uint32_t linkedChannel);
 
 /*!
  * @brief Sets the bandwidth for the eDMA TCD.
@@ -890,7 +890,7 @@ void EDMA_PrepareTransferConfig(edma_transfer_config_t *config,
  * @param destWidth eDMA transfer destination address width(bytes).
  * @param bytesEachRequest eDMA transfer bytes per channel request.
  * @param transferBytes eDMA transfer bytes to be transferred.
- * @param type eDMA transfer type.
+ * @param transferType eDMA transfer type.
  * @note The data address and the data width must be consistent. For example, if the SRC
  *       is 4 bytes, the source address must be 4 bytes aligned, or it results in
  *       source address error (SAE).
@@ -902,7 +902,7 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
                           uint32_t destWidth,
                           uint32_t bytesEachRequest,
                           uint32_t transferBytes,
-                          edma_transfer_type_t type);
+                          edma_transfer_type_t transferType);
 
 /*!
  * @brief Submits the eDMA transfer request.

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_enet.c

@@ -44,6 +44,9 @@ enum
 /*! @brief Pointers to enet clocks for each instance. */
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 const clock_ip_name_t s_enetClock[] = ENET_CLOCKS;
+#if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE
+const clock_ip_name_t s_enetExtraClock[] = ENET_EXTRA_CLOCKS;
+#endif
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*! @brief Pointers to enet transmit IRQ number for each instance. */
@@ -329,6 +332,11 @@ status_t ENET_Init(ENET_Type *base,
 
     /* Ungate ENET clock. */
     (void)CLOCK_EnableClock(s_enetClock[instance]);
+
+#if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE
+    /* Ungate ENET extra clock. */
+    (void)CLOCK_EnableClock(s_enetExtraClock[instance]);
+#endif
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
     /* Reset ENET module. */
     ENET_Reset(base);
@@ -374,6 +382,11 @@ void ENET_Deinit(ENET_Type *base)
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disables the clock source. */
     (void)CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]);
+
+#if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE
+    /* Disables ENET extra clock. */
+    (void)CLOCK_DisableClock(s_enetExtraClock[ENET_GetInstance(base)]);
+#endif
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
@@ -3906,14 +3919,14 @@ void ENET_1G_1588_Timer_DriverIRQHandler(void)
 #endif /* ENET_1G */
 
 #if defined(ENET1)
-void ENET1_MAC0_Rx_Tx_Done0_DriverIRQHandler(void);
-void ENET1_MAC0_Rx_Tx_Done0_DriverIRQHandler(void)
+void ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler(void);
+void ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler(void)
 {
     ENET_CommonFrame1IRQHandler(ENET1);
     SDK_ISR_EXIT_BARRIER;
 }
-void ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler(void);
-void ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler(void)
+void ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler(void);
+void ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler(void)
 {
     ENET_CommonFrame2IRQHandler(ENET1);
     SDK_ISR_EXIT_BARRIER;

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_enet.h

@@ -24,7 +24,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief Defines the driver version. */
-#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 5, 3))
+#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 5, 4))
 /*@}*/
 
 /*! @name ENET DESCRIPTOR QUEUE */
@@ -776,6 +776,9 @@ typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle);
 /*! @brief Pointers to enet clocks for each instance. */
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 extern const clock_ip_name_t s_enetClock[];
+#if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE
+extern const clock_ip_name_t s_enetExtraClock[];
+#endif
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -96,10 +96,10 @@
 
 /* Define the range of memory that needs to be initialized when the device has memory error detection feature. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
-#define CAN_INIT_RXFIR         ((uint32_t)base + 0x4Cu)
-#define CAN_INIT_MEMORY_BASE_1 (uint32_t *)((uint32_t)base + (uint32_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1)
+#define CAN_INIT_RXFIR         ((uintptr_t)base + 0x4Cu)
+#define CAN_INIT_MEMORY_BASE_1 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1)
 #define CAN_INIT_MEMORY_SIZE_1 FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1
-#define CAN_INIT_MEMORY_BASE_2 (uint32_t *)((uint32_t)base + (uint32_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2)
+#define CAN_INIT_MEMORY_BASE_2 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2)
 #define CAN_INIT_MEMORY_SIZE_2 FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2
 #endif
 
@@ -365,6 +365,23 @@ static flexcan_isr_t s_flexcanIsr = (flexcan_isr_t)DefaultISR;
 static flexcan_isr_t s_flexcanIsr;
 #endif
 
+/*******************************************************************************
+ * Implementation of 32-bit memset
+ ******************************************************************************/
+
+static void flexcan_memset(void *s, uint32_t c, size_t n)
+{
+    size_t m;
+    uint32_t *ptr = s;
+
+    m = n / sizeof(*ptr);
+
+    while ((m--) != (size_t)0)
+    {
+        *ptr++ = c;
+    }
+}
+
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -733,8 +750,8 @@ static void FLEXCAN_Reset(CAN_Type *base)
     /* Do memory initialization for all FlexCAN RAM in order to have the parity bits in memory properly
        updated. */
     *(volatile uint32_t *)CAN_INIT_RXFIR = 0x0U;
-    (void)memset((void *)CAN_INIT_MEMORY_BASE_1, 0, CAN_INIT_MEMORY_SIZE_1);
-    (void)memset((void *)CAN_INIT_MEMORY_BASE_2, 0, CAN_INIT_MEMORY_SIZE_2);
+    flexcan_memset(CAN_INIT_MEMORY_BASE_1, 0, CAN_INIT_MEMORY_SIZE_1);
+    flexcan_memset(CAN_INIT_MEMORY_BASE_2, 0, CAN_INIT_MEMORY_SIZE_2);
     /* Disable unrestricted write access to FlexCAN memory. */
     base->CTRL2 &= ~CAN_CTRL2_WRMFRZ_MASK;
 
@@ -742,7 +759,7 @@ static void FLEXCAN_Reset(CAN_Type *base)
     FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_AllMemoryErrorFlag);
 #else
     /* Only need clean all Message Buffer memory. */
-    (void)memset((void *)&base->MB[0], 0, sizeof(base->MB));
+    flexcan_memset((void *)&base->MB[0], 0, sizeof(base->MB));
 #endif
 
     /* Clean all individual Rx Mask of Message Buffers. */
@@ -818,7 +835,7 @@ static void FLEXCAN_SetBitRate(CAN_Type *base,
     }
 
     /* Update actual timing characteristic. */
-    FLEXCAN_SetTimingConfig(base, (const flexcan_timing_config_t *)(uint32_t)&timingConfig);
+    FLEXCAN_SetTimingConfig(base, (const flexcan_timing_config_t *)(uintptr_t)&timingConfig);
 }
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
@@ -869,7 +886,7 @@ static void FLEXCAN_SetFDBitRate(CAN_Type *base,
     }
 
     /* Update actual timing characteristic. */
-    FLEXCAN_SetFDTimingConfig(base, (const flexcan_timing_config_t *)(uint32_t)&timingConfig);
+    FLEXCAN_SetFDTimingConfig(base, (const flexcan_timing_config_t *)(uintptr_t)&timingConfig);
 }
 #endif
 
@@ -2692,17 +2709,12 @@ void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_rep
  */
 static void FLEXCAN_ERRATA_6032(CAN_Type *base, volatile uint32_t *mbCSAddr)
 {
-    uint32_t dbg_temp      = 0U;
-    uint32_t u32TempCS     = 0U;
-    uint32_t u32Timeout    = DELAY_BUSIDLE;
-    uint32_t u32TempIMASK1 = base->IMASK1;
-/*after backup all interruption, disable ALL interruption*/
-#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    uint32_t u32TempIMASK2 = base->IMASK2;
-    base->IMASK2           = 0;
-#endif
-    base->IMASK1 = 0;
-    dbg_temp     = (uint32_t)(base->DBG1);
+    uint32_t dbg_temp   = 0U;
+    uint32_t u32TempCS  = 0U;
+    uint32_t u32Timeout = DELAY_BUSIDLE;
+    /*disable ALL interrupts to prevent any context switching*/
+    uint32_t irqMask = DisableGlobalIRQ();
+    dbg_temp         = (uint32_t)(base->DBG1);
     switch (dbg_temp & CAN_DBG1_CFSM_MASK)
     {
         case RXINTERMISSION:
@@ -2743,10 +2755,7 @@ static void FLEXCAN_ERRATA_6032(CAN_Type *base, volatile uint32_t *mbCSAddr)
         *mbCSAddr = u32TempCS;
     }
     /*restore interruption*/
-    base->IMASK1 = u32TempIMASK1;
-#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    base->IMASK2 = u32TempIMASK2;
-#endif
+    EnableGlobalIRQ(irqMask);
 }
 #endif
 
@@ -2776,12 +2785,12 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t
     uint32_t cs_temp = 0;
     status_t status;
 
-#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
-    FLEXCAN_ERRATA_6032(base, &(base->MB[mbIdx].CS));
-#endif
     /* Check if Message Buffer is available. */
     if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK))
     {
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
+        FLEXCAN_ERRATA_6032(base, &(base->MB[mbIdx].CS));
+#endif
         /* Inactive Tx Message Buffer. */
         base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive);
 
@@ -2862,14 +2871,13 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra
     volatile uint32_t *mbAddr = &(base->MB[0].CS);
     uint32_t offset           = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
 
-#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
-    FLEXCAN_ERRATA_6032(base, &(mbAddr[offset]));
-#endif
-
     can_cs = mbAddr[offset];
     /* Check if Message Buffer is available. */
     if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (can_cs & CAN_CS_CODE_MASK))
     {
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
+        FLEXCAN_ERRATA_6032(base, &(mbAddr[offset]));
+#endif
         /* Inactive Tx Message Buffer and Fill Message ID field. */
         mbAddr[offset]      = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive);
         mbAddr[offset + 1U] = pTxFrame->id;
@@ -3226,7 +3234,7 @@ status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra
     status_t status;
 
     /* Write Tx Message Buffer to initiate a data sending. */
-    if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, (const flexcan_frame_t *)(uint32_t)pTxFrame))
+    if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, (const flexcan_frame_t *)(uintptr_t)pTxFrame))
     {
 /* Wait until CAN Message send out. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
@@ -3311,7 +3319,7 @@ status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_f
     status_t status;
 
     /* Write Tx Message Buffer to initiate a data sending. */
-    if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, (const flexcan_fd_frame_t *)(uint32_t)pTxFrame))
+    if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pTxFrame))
     {
 /* Wait until CAN Message send out. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
@@ -3563,7 +3571,7 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl
         }
 
         if (kStatus_Success ==
-            FLEXCAN_WriteTxMb(base, pMbXfer->mbIdx, (const flexcan_frame_t *)(uint32_t)pMbXfer->frame))
+            FLEXCAN_WriteTxMb(base, pMbXfer->mbIdx, (const flexcan_frame_t *)(uintptr_t)pMbXfer->frame))
         {
 /* Enable Message Buffer Interrupt. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
@@ -3680,7 +3688,7 @@ status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *han
         }
 
         if (kStatus_Success ==
-            FLEXCAN_WriteFDTxMb(base, pMbXfer->mbIdx, (const flexcan_fd_frame_t *)(uint32_t)pMbXfer->framefd))
+            FLEXCAN_WriteFDTxMb(base, pMbXfer->mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pMbXfer->framefd))
         {
 /* Enable Message Buffer Interrupt. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -22,7 +22,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief FlexCAN driver version. */
-#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 8, 2))
+#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 8, 6))
 /*@}*/
 
 #if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT)
@@ -396,7 +396,7 @@ enum _flexcan_interrupt_enable
     kFLEXCAN_ErrorInterruptEnable     = CAN_CTRL1_ERRMSK_MASK,  /*!< CAN Error interrupt, use bit 14. */
     kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt, use bit 11. */
     kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt, use bit 10. */
-    kFLEXCAN_WakeUpInterruptEnable    = CAN_MCR_WAKMSK_MASK,    /*!< Self Wake Up interrupt, use bit 22. */
+    kFLEXCAN_WakeUpInterruptEnable    = CAN_MCR_WAKMSK_MASK,    /*!< Self Wake Up interrupt, use bit 26. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
     kFLEXCAN_FDErrorInterruptEnable = CAN_CTRL2_ERRMSK_FAST_MASK, /*!< CAN FD Error interrupt, use bit 31. */
 #endif
@@ -1607,8 +1607,7 @@ static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
     /* Solve interrupt enable bits in CTRL1 register. */
     base->CTRL1 |=
         (uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
-                           (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable |
-                           (uint32_t)kFLEXCAN_WakeUpInterruptEnable));
+                           (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
 }
 
 /*!
@@ -1656,8 +1655,7 @@ static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
     /* Solve interrupt enable bits in CTRL1 register. */
     base->CTRL1 &=
         ~(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
-                            (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable |
-                            (uint32_t)kFLEXCAN_WakeUpInterruptEnable));
+                            (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
 }
 
 /*!
@@ -1730,9 +1728,9 @@ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable);
  * @param base FlexCAN peripheral base address.
  * @return FlexCAN Rx FIFO Head address.
  */
-static inline uint32_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)
+static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)
 {
-    return (uint32_t) & (base->MB[0].CS);
+    return (uintptr_t) & (base->MB[0].CS);
 }
 
 /* @} */

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan_edma.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -34,9 +34,11 @@ enum _flexcan_edma_tansfer_state
 /*******************************************************************************
  * Variables
  ******************************************************************************/
+/* Array of FlexCAN peripheral base address. */
+static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS;
 
-/*<! Private handle only used for internally. */
-static flexcan_edma_private_handle_t s_flexcanEdmaPrivateHandle[FSL_FEATURE_SOC_FLEXCAN_COUNT];
+/* Private handle only used for internally. */
+static flexcan_edma_private_handle_t s_flexcanEdmaPrivateHandle[ARRAY_SIZE(s_flexcanBases)];
 
 /*******************************************************************************
  * Prototypes
@@ -77,9 +79,9 @@ static void FLEXCAN_ReceiveFifoEDMACallback(edma_handle_t *handle, void *param,
             idHitIndex     = (DLC_LENGTH_DECODE(framefd->length) + 3U) / 4U;
             framefd->idhit = framefd->dataWord[idHitIndex];
             /* Clear the unused frame data. */
-            for (uint32_t i = idHitIndex; i < 16U; i++)
+            for (uint32_t j = idHitIndex; j < 16U; j++)
             {
-                framefd->dataWord[i] = 0x0U;
+                framefd->dataWord[j] = 0x0U;
             }
             framefd++;
         }

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan_edma.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -23,7 +23,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief FlexCAN EDMA driver version. */
-#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 8, 1))
+#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 8, 6))
 /*@}*/
 
 /* Forward declaration of the handle typedef. */

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2020 NXP
+ * Copyright 2016-2020, 2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -67,30 +67,48 @@ static uint32_t FLEXIO_SPI_GetInstance(FLEXIO_SPI_Type *base)
 
 static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
 {
-    uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
+    uint32_t tmpData = FLEXIO_SPI_DUMMYDATA;
 
     if (handle->txData != NULL)
     {
         /* Transmit data and update tx size/buff. */
         if (handle->bytePerFrame == 1U)
         {
-            tmpData = *(handle->txData);
+            tmpData = (uint32_t) * (handle->txData);
             handle->txData++;
         }
-        else
+        else if (handle->bytePerFrame == 2U)
         {
             if (handle->direction == kFLEXIO_SPI_MsbFirst)
             {
-                tmpData = (uint16_t)(handle->txData[0]) << 8U;
-                tmpData += handle->txData[1];
+                tmpData = (uint32_t)(handle->txData[0]) << 8U;
+                tmpData += (uint32_t)handle->txData[1];
             }
             else
             {
-                tmpData = (uint16_t)(handle->txData[1]) << 8U;
-                tmpData += handle->txData[0];
+                tmpData = (uint32_t)(handle->txData[1]) << 8U;
+                tmpData += (uint32_t)handle->txData[0];
             }
             handle->txData += 2U;
         }
+        else
+        {
+            if (handle->direction == kFLEXIO_SPI_MsbFirst)
+            {
+                tmpData = (uint32_t)(handle->txData[0]) << 24U;
+                tmpData += (uint32_t)(handle->txData[1]) << 16U;
+                tmpData += (uint32_t)(handle->txData[2]) << 8U;
+                tmpData += (uint32_t)handle->txData[3];
+            }
+            else
+            {
+                tmpData = (uint32_t)(handle->txData[3]) << 24U;
+                tmpData += (uint32_t)(handle->txData[2]) << 16U;
+                tmpData += (uint32_t)(handle->txData[1]) << 8U;
+                tmpData += (uint32_t)handle->txData[0];
+            }
+            handle->txData += 4U;
+        }
     }
     else
     {
@@ -109,7 +127,7 @@ static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi
 
 static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
 {
-    uint16_t tmpData;
+    uint32_t tmpData;
 
     tmpData = FLEXIO_SPI_ReadData(base, handle->direction);
 
@@ -118,11 +136,10 @@ static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_
         if (handle->bytePerFrame == 1U)
         {
             *handle->rxData = (uint8_t)tmpData;
-            handle->rxData++;
         }
-        else
+        else if (handle->bytePerFrame == 2U)
         {
-            if (handle->direction == kFLEXIO_SPI_MsbFirst)
+            if (handle->direction == kFLEXIO_SPI_LsbFirst)
             {
                 *handle->rxData = (uint8_t)(tmpData >> 8);
                 handle->rxData++;
@@ -134,8 +151,31 @@ static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_
                 handle->rxData++;
                 *handle->rxData = (uint8_t)(tmpData >> 8);
             }
-            handle->rxData++;
         }
+        else
+        {
+            if (handle->direction == kFLEXIO_SPI_LsbFirst)
+            {
+                *handle->rxData = (uint8_t)(tmpData >> 24U);
+                handle->rxData++;
+                *handle->rxData = (uint8_t)(tmpData >> 16U);
+                handle->rxData++;
+                *handle->rxData = (uint8_t)(tmpData >> 8U);
+                handle->rxData++;
+                *handle->rxData = (uint8_t)tmpData;
+            }
+            else
+            {
+                *handle->rxData = (uint8_t)tmpData;
+                handle->rxData++;
+                *handle->rxData = (uint8_t)(tmpData >> 8U);
+                handle->rxData++;
+                *handle->rxData = (uint8_t)(tmpData >> 16U);
+                handle->rxData++;
+                *handle->rxData = (uint8_t)(tmpData >> 24U);
+            }
+        }
+        handle->rxData++;
     }
     handle->rxRemainingBytes -= handle->bytePerFrame;
 }
@@ -270,10 +310,10 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma
     timerConfig.timerEnable     = kFLEXIO_TimerEnableOnTriggerHigh;
     timerConfig.timerStop       = kFLEXIO_TimerStopBitEnableOnTimerDisable;
     timerConfig.timerStart      = kFLEXIO_TimerStartBitEnabled;
-
+    /* Low 8-bits are used to configure baudrate. */
     timerDiv = (uint16_t)(srcClock_Hz / masterConfig->baudRate_Bps);
     timerDiv = timerDiv / 2U - 1U;
-
+    /* High 8-bits are used to configure shift clock edges(transfer width). */
     timerCmp = ((uint16_t)masterConfig->dataMode * 2U - 1U) << 8U;
     timerCmp |= timerDiv;
 
@@ -297,7 +337,7 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma
     timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
     timerConfig.timerStart      = kFLEXIO_TimerStartBitDisabled;
 
-    timerConfig.timerCompare = 0xFFFFU;
+    timerConfig.timerCompare = 0xFFFFU; /* Never compare. */
 
     FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
 }
@@ -473,8 +513,6 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav
     timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
     if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
     {
-        /* The configuration kFLEXIO_TimerDisableOnTimerCompare only support continuous
-        PCS access, change to kFLEXIO_TimerDisableNever to enable discontinuous PCS access. */
         timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
         timerConfig.timerStart   = kFLEXIO_TimerStartBitDisabled;
     }
@@ -768,16 +806,31 @@ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_tra
 {
     flexio_spi_shift_direction_t direction;
     uint8_t bytesPerFrame;
-    uint32_t dataMode = 0;
-    uint16_t timerCmp = (uint16_t)(base->flexioBase->TIMCMP[base->timerIndex[0]]);
-    uint16_t tmpData  = FLEXIO_SPI_DUMMYDATA;
+    uint32_t dataMode  = 0;
+    uint16_t timerCmp  = (uint16_t)(base->flexioBase->TIMCMP[base->timerIndex[0]]);
+    uint32_t tmpData   = FLEXIO_SPI_DUMMYDATA;
+    uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
 #if SPI_RETRY_TIMES
     uint32_t waitTimes;
 #endif
 
     timerCmp &= 0x00FFU;
+
+    if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] =
+            (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
+            FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled);
+    }
+    else
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] =
+            (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
+            FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable);
+    }
+
     /* Configure the values in handle. */
-    switch (xfer->flags)
+    switch (dataFormat)
     {
         case (uint8_t)kFLEXIO_SPI_8bitMsb:
             dataMode      = (8UL * 2UL - 1UL) << 8U;
@@ -803,6 +856,18 @@ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_tra
             direction     = kFLEXIO_SPI_LsbFirst;
             break;
 
+        case (uint8_t)kFLEXIO_SPI_32bitMsb:
+            dataMode      = (32UL * 2UL - 1UL) << 8U;
+            bytesPerFrame = 4U;
+            direction     = kFLEXIO_SPI_MsbFirst;
+            break;
+
+        case (uint8_t)kFLEXIO_SPI_32bitLsb:
+            dataMode      = (32UL * 2UL - 1UL) << 8U;
+            bytesPerFrame = 4U;
+            direction     = kFLEXIO_SPI_LsbFirst;
+            break;
+
         default:
             dataMode      = (8UL * 2UL - 1UL) << 8U;
             bytesPerFrame = 1U;
@@ -813,6 +878,12 @@ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_tra
 
     dataMode |= timerCmp;
 
+    /* Transfer size should be bytesPerFrame divisible. */
+    if ((xfer->dataSize % bytesPerFrame) != 0U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
     /* Configure transfer size. */
     base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
 
@@ -839,23 +910,41 @@ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_tra
             /* Transmit data and update tx size/buff. */
             if (bytesPerFrame == 1U)
             {
-                tmpData = *(xfer->txData);
+                tmpData = (uint32_t) * (xfer->txData);
                 xfer->txData++;
             }
-            else
+            else if (bytesPerFrame == 2U)
             {
                 if (direction == kFLEXIO_SPI_MsbFirst)
                 {
-                    tmpData = (uint16_t)(xfer->txData[0]) << 8U;
-                    tmpData += xfer->txData[1];
+                    tmpData = (uint32_t)(xfer->txData[0]) << 8U;
+                    tmpData += (uint32_t)xfer->txData[1];
                 }
                 else
                 {
-                    tmpData = (uint16_t)(xfer->txData[1]) << 8U;
-                    tmpData += xfer->txData[0];
+                    tmpData = (uint32_t)(xfer->txData[1]) << 8U;
+                    tmpData += (uint32_t)xfer->txData[0];
                 }
                 xfer->txData += 2U;
             }
+            else
+            {
+                if (direction == kFLEXIO_SPI_MsbFirst)
+                {
+                    tmpData = (uint32_t)(xfer->txData[0]) << 24U;
+                    tmpData += (uint32_t)(xfer->txData[1]) << 16U;
+                    tmpData += (uint32_t)(xfer->txData[2]) << 8U;
+                    tmpData += (uint32_t)xfer->txData[3];
+                }
+                else
+                {
+                    tmpData = (uint32_t)(xfer->txData[3]) << 24U;
+                    tmpData += (uint32_t)(xfer->txData[2]) << 16U;
+                    tmpData += (uint32_t)(xfer->txData[1]) << 8U;
+                    tmpData += (uint32_t)xfer->txData[0];
+                }
+                xfer->txData += 4U;
+            }
         }
         else
         {
@@ -888,11 +977,10 @@ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_tra
             if (bytesPerFrame == 1U)
             {
                 *xfer->rxData = (uint8_t)tmpData;
-                xfer->rxData++;
             }
-            else
+            else if (bytesPerFrame == 2U)
             {
-                if (direction == kFLEXIO_SPI_MsbFirst)
+                if (direction == kFLEXIO_SPI_LsbFirst)
                 {
                     *xfer->rxData = (uint8_t)(tmpData >> 8);
                     xfer->rxData++;
@@ -904,8 +992,31 @@ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_tra
                     xfer->rxData++;
                     *xfer->rxData = (uint8_t)(tmpData >> 8);
                 }
-                xfer->rxData++;
             }
+            else
+            {
+                if (direction == kFLEXIO_SPI_LsbFirst)
+                {
+                    *xfer->rxData = (uint8_t)(tmpData >> 24U);
+                    xfer->rxData++;
+                    *xfer->rxData = (uint8_t)(tmpData >> 16U);
+                    xfer->rxData++;
+                    *xfer->rxData = (uint8_t)(tmpData >> 8U);
+                    xfer->rxData++;
+                    *xfer->rxData = (uint8_t)tmpData;
+                }
+                else
+                {
+                    *xfer->rxData = (uint8_t)tmpData;
+                    xfer->rxData++;
+                    *xfer->rxData = (uint8_t)(tmpData >> 8U);
+                    xfer->rxData++;
+                    *xfer->rxData = (uint8_t)(tmpData >> 16U);
+                    xfer->rxData++;
+                    *xfer->rxData = (uint8_t)(tmpData >> 24U);
+                }
+            }
+            xfer->rxData++;
         }
     }
 
@@ -967,9 +1078,10 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
     assert(handle != NULL);
     assert(xfer != NULL);
 
-    uint32_t dataMode = 0;
-    uint16_t timerCmp = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]];
-    uint16_t tmpData  = FLEXIO_SPI_DUMMYDATA;
+    uint32_t dataMode  = 0;
+    uint16_t timerCmp  = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]];
+    uint32_t tmpData   = FLEXIO_SPI_DUMMYDATA;
+    uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
 
     timerCmp &= 0x00FFU;
 
@@ -985,8 +1097,27 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
         return kStatus_InvalidArgument;
     }
 
+    /* Timer1 controls the CS signal which enables/disables(asserts/deasserts) when timer0 enable/disable. Timer0
+       enables when tx shifter is written and disables when timer compare. The timer compare event causes the
+       transmit shift registers to load which generates a tx register empty event. Since when timer stop bit is
+       disabled, a timer enable condition can be detected in the same cycle as a timer disable condition, so if
+       software writes the tx register upon the detection of tx register empty event, the timer enable condition
+       is triggered again, then the CS signal can remain low until software no longer writes the tx register. */
+    if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] =
+            (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
+            FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled);
+    }
+    else
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] =
+            (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
+            FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable);
+    }
+
     /* Configure the values in handle */
-    switch (xfer->flags)
+    switch (dataFormat)
     {
         case (uint8_t)kFLEXIO_SPI_8bitMsb:
             dataMode             = (8UL * 2UL - 1UL) << 8U;
@@ -1008,6 +1139,16 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
             handle->bytePerFrame = 2U;
             handle->direction    = kFLEXIO_SPI_LsbFirst;
             break;
+        case (uint8_t)kFLEXIO_SPI_32bitMsb:
+            dataMode             = (32UL * 2UL - 1UL) << 8U;
+            handle->bytePerFrame = 4U;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_32bitLsb:
+            dataMode             = (32UL * 2UL - 1UL) << 8U;
+            handle->bytePerFrame = 4U;
+            handle->direction    = kFLEXIO_SPI_LsbFirst;
+            break;
         default:
             dataMode             = (8UL * 2UL - 1UL) << 8U;
             handle->bytePerFrame = 1U;
@@ -1018,6 +1159,12 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
 
     dataMode |= timerCmp;
 
+    /* Transfer size should be bytesPerFrame divisible. */
+    if ((xfer->dataSize % handle->bytePerFrame) != 0U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
     /* Configure transfer size. */
     base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
 
@@ -1035,23 +1182,41 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
         /* Transmit data and update tx size/buff. */
         if (handle->bytePerFrame == 1U)
         {
-            tmpData = *(handle->txData);
+            tmpData = (uint32_t) * (handle->txData);
             handle->txData++;
         }
-        else
+        else if (handle->bytePerFrame == 2U)
         {
             if (handle->direction == kFLEXIO_SPI_MsbFirst)
             {
-                tmpData = (uint16_t)(handle->txData[0]) << 8U;
-                tmpData += handle->txData[1];
+                tmpData = (uint32_t)(handle->txData[0]) << 8U;
+                tmpData += (uint32_t)handle->txData[1];
             }
             else
             {
-                tmpData = (uint16_t)(handle->txData[1]) << 8U;
-                tmpData += handle->txData[0];
+                tmpData = (uint32_t)(handle->txData[1]) << 8U;
+                tmpData += (uint32_t)handle->txData[0];
             }
             handle->txData += 2U;
         }
+        else
+        {
+            if (handle->direction == kFLEXIO_SPI_MsbFirst)
+            {
+                tmpData = (uint32_t)(handle->txData[0]) << 24U;
+                tmpData += (uint32_t)(handle->txData[1]) << 16U;
+                tmpData += (uint32_t)(handle->txData[2]) << 8U;
+                tmpData += (uint32_t)handle->txData[3];
+            }
+            else
+            {
+                tmpData = (uint32_t)(handle->txData[3]) << 24U;
+                tmpData += (uint32_t)(handle->txData[2]) << 16U;
+                tmpData += (uint32_t)(handle->txData[1]) << 8U;
+                tmpData += (uint32_t)handle->txData[0];
+            }
+            handle->txData += 4U;
+        }
     }
     else
     {
@@ -1220,7 +1385,8 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
     assert(handle != NULL);
     assert(xfer != NULL);
 
-    uint32_t dataMode = 0;
+    uint32_t dataMode  = 0;
+    uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
 
     /* Check if SPI is busy. */
     if (handle->state == (uint32_t)kFLEXIO_SPI_Busy)
@@ -1234,8 +1400,35 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
         return kStatus_InvalidArgument;
     }
 
+    /* SCK timer use CS pin as inverted trigger so timer should be disbaled on trigger falling edge(CS re-asserts). */
+    /* However if CPHA is first edge mode, timer will restart each time right after timer compare event occur and
+       before CS pin re-asserts, which triggers another shifter load. To avoid this, when in CS dis-continuous mode,
+       timer should disable in timer compare rather than trigger falling edge(CS re-asserts), and in CS continuous mode,
+       tx/rx shifters should be flushed after transfer finishes and before next transfer starts. */
+    FLEXIO_SPI_FlushShifters(base);
+    if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge);
+    }
+    else
+    {
+        if ((base->flexioBase->SHIFTCTL[base->shifterIndex[0]] & FLEXIO_SHIFTCTL_TIMPOL_MASK) ==
+            FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive))
+        {
+            base->flexioBase->TIMCFG[base->timerIndex[0]] =
+                (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) |
+                FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare);
+        }
+        else
+        {
+            base->flexioBase->TIMCFG[base->timerIndex[0]] =
+                (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) |
+                FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge);
+        }
+    }
+
     /* Configure the values in handle */
-    switch (xfer->flags)
+    switch (dataFormat)
     {
         case (uint8_t)kFLEXIO_SPI_8bitMsb:
             dataMode             = 8U * 2U - 1U;
@@ -1257,14 +1450,30 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
             handle->bytePerFrame = 2U;
             handle->direction    = kFLEXIO_SPI_LsbFirst;
             break;
+        case (uint8_t)kFLEXIO_SPI_32bitMsb:
+            dataMode             = 32UL * 2UL - 1UL;
+            handle->bytePerFrame = 4U;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_32bitLsb:
+            dataMode             = 32UL * 2UL - 1UL;
+            handle->bytePerFrame = 4U;
+            handle->direction    = kFLEXIO_SPI_LsbFirst;
+            break;
         default:
-            dataMode             = 8U * 2U - 1U;
+            dataMode             = 8UL * 2UL - 1UL;
             handle->bytePerFrame = 1U;
             handle->direction    = kFLEXIO_SPI_MsbFirst;
             assert(true);
             break;
     }
 
+    /* Transfer size should be bytesPerFrame divisible. */
+    if ((xfer->dataSize % handle->bytePerFrame) != 0U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
     /* Configure transfer size. */
     base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
 
@@ -1328,3 +1537,17 @@ void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)
         }
     }
 }
+
+/*!
+ * brief Flush tx/rx shifters.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ */
+void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base)
+{
+    /* Disable then re-enable to flush the tx shifter. */
+    base->flexioBase->SHIFTCTL[base->shifterIndex[0]] &= ~FLEXIO_SHIFTCTL_SMOD_MASK;
+    base->flexioBase->SHIFTCTL[base->shifterIndex[0]] |= FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit);
+    /* Read to flush the rx shifter. */
+    (void)base->flexioBase->SHIFTBUF[base->shifterIndex[1]];
+}

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2020 NXP
+ * Copyright 2016-2020, 2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -23,13 +23,13 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FlexIO SPI driver version 2.2.1. */
-#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
+/*! @brief FlexIO SPI driver version. */
+#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
 /*@}*/
 
 #ifndef FLEXIO_SPI_DUMMYDATA
 /*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */
-#define FLEXIO_SPI_DUMMYDATA (0xFFFFU)
+#define FLEXIO_SPI_DUMMYDATA (0xFFFFFFFFU)
 #endif
 
 /*! @brief Retry times for waiting flag. */
@@ -37,6 +37,9 @@
 #define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
 #endif
 
+/*! @brief Get the transfer data format of width and bit order. */
+#define FLEXIO_SPI_XFER_DATA_FORMAT(flag) ((flag) & (0x7U))
+
 /*! @brief Error codes for the FlexIO SPI driver. */
 enum
 {
@@ -68,6 +71,7 @@ typedef enum _flexio_spi_data_bitcount_mode
 {
     kFLEXIO_SPI_8BitMode  = 0x08U, /*!< 8-bit data transmission mode. */
     kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */
+    kFLEXIO_SPI_32BitMode = 0x20U, /*!< 32-bit data transmission mode. */
 } flexio_spi_data_bitcount_mode_t;
 
 /*! @brief Define FlexIO SPI interrupt mask. */
@@ -92,20 +96,25 @@ enum _flexio_spi_dma_enable
     kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/
 };
 
-/*! @brief Define FlexIO SPI transfer flags. */
+/*! @brief Define FlexIO SPI transfer flags.
+ *  @note Use kFLEXIO_SPI_csContinuous and one of the other flags to OR together to form the transfer flag. */
 enum _flexio_spi_transfer_flags
 {
-    kFLEXIO_SPI_8bitMsb  = 0x1U, /*!< FlexIO SPI 8-bit MSB first */
-    kFLEXIO_SPI_8bitLsb  = 0x2U, /*!< FlexIO SPI 8-bit LSB first */
-    kFLEXIO_SPI_16bitMsb = 0x9U, /*!< FlexIO SPI 16-bit MSB first */
-    kFLEXIO_SPI_16bitLsb = 0xaU, /*!< FlexIO SPI 16-bit LSB first */
+    kFLEXIO_SPI_8bitMsb      = 0x0U, /*!< FlexIO SPI 8-bit MSB first */
+    kFLEXIO_SPI_8bitLsb      = 0x1U, /*!< FlexIO SPI 8-bit LSB first */
+    kFLEXIO_SPI_16bitMsb     = 0x2U, /*!< FlexIO SPI 16-bit MSB first */
+    kFLEXIO_SPI_16bitLsb     = 0x3U, /*!< FlexIO SPI 16-bit LSB first */
+    kFLEXIO_SPI_32bitMsb     = 0x4U, /*!< FlexIO SPI 32-bit MSB first */
+    kFLEXIO_SPI_32bitLsb     = 0x5U, /*!< FlexIO SPI 32-bit LSB first */
+    kFLEXIO_SPI_csContinuous = 0x8U, /*!< Enable the CS signal continuous mode */
 };
 
 /*! @brief Define FlexIO SPI access structure typedef. */
 typedef struct _flexio_spi_type
 {
     FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */
-    uint8_t SDOPinIndex;     /*!< Pin select for data output. */
+    uint8_t SDOPinIndex;     /*!< Pin select for data output. To set SDO pin in Hi-Z state, user needs to mux the pin as
+                                GPIO input and disable all pull up/down in application. */
     uint8_t SDIPinIndex;     /*!< Pin select for data input. */
     uint8_t SCKPinIndex;     /*!< Pin select for clock. */
     uint8_t CSnPinIndex;     /*!< Pin select for enable. */
@@ -477,9 +486,9 @@ void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps,
  *
  * @param base Pointer to the FLEXIO_SPI_Type structure.
  * @param direction Shift direction of MSB first or LSB first.
- * @param data 8 bit/16 bit data.
+ * @param data 8/16/32 bit data.
  */
-static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint16_t data)
+static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint32_t data)
 {
     if (direction == kFLEXIO_SPI_MsbFirst)
     {
@@ -501,15 +510,15 @@ static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_
  * @param direction Shift direction of MSB first or LSB first.
  * @return 8 bit/16 bit data received.
  */
-static inline uint16_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)
+static inline uint32_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)
 {
     if (direction == kFLEXIO_SPI_MsbFirst)
     {
-        return (uint16_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]);
+        return (uint32_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]);
     }
     else
     {
-        return (uint16_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]);
+        return (uint32_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]);
     }
 }
 
@@ -560,6 +569,14 @@ status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
  */
 status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer);
 
+/*!
+ * @brief Flush tx/rx shifters.
+ *
+ * @param base Pointer to the FLEXIO_SPI_Type structure.
+ */
+void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base);
+/*@}*/
+
 /*Transactional APIs*/
 
 /*!

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi_edma.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2020 NXP
+ * Copyright 2016-2020, 2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -50,17 +50,19 @@ static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool t
  * @param base pointer to FLEXIO_SPI_Type structure.
  * @param handle pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
  * @param xfer Pointer to flexio spi transfer structure.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_InvalidArgument The transfer size is not supported.
  */
-static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
-                                  flexio_spi_master_edma_handle_t *handle,
-                                  flexio_spi_transfer_t *xfer);
+static status_t FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
+                                      flexio_spi_master_edma_handle_t *handle,
+                                      flexio_spi_transfer_t *xfer);
 
 /*******************************************************************************
  * Variables
  ******************************************************************************/
 
 /* Dummy data used to send */
-static const uint16_t s_dummyData = FLEXIO_SPI_DUMMYDATA;
+static const uint32_t s_dummyData = FLEXIO_SPI_DUMMYDATA;
 
 /*< @brief user configurable flexio spi handle count. */
 #define FLEXIO_SPI_HANDLE_COUNT 2
@@ -122,16 +124,17 @@ static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool t
     }
 }
 
-static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
-                                  flexio_spi_master_edma_handle_t *handle,
-                                  flexio_spi_transfer_t *xfer)
+static status_t FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
+                                      flexio_spi_master_edma_handle_t *handle,
+                                      flexio_spi_transfer_t *xfer)
 {
     edma_transfer_config_t xferConfig      = {0};
     flexio_spi_shift_direction_t direction = kFLEXIO_SPI_MsbFirst;
     uint8_t bytesPerFrame;
+    uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
 
     /* Configure the values in handle. */
-    switch (xfer->flags)
+    switch (dataFormat)
     {
         case (uint8_t)kFLEXIO_SPI_8bitMsb:
             bytesPerFrame = 1U;
@@ -149,6 +152,14 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
             bytesPerFrame = 2U;
             direction     = kFLEXIO_SPI_LsbFirst;
             break;
+        case (uint8_t)kFLEXIO_SPI_32bitMsb:
+            bytesPerFrame = 4U;
+            direction     = kFLEXIO_SPI_MsbFirst;
+            break;
+        case (uint8_t)kFLEXIO_SPI_32bitLsb:
+            bytesPerFrame = 4U;
+            direction     = kFLEXIO_SPI_LsbFirst;
+            break;
         default:
             bytesPerFrame = 1U;
             direction     = kFLEXIO_SPI_MsbFirst;
@@ -156,6 +167,12 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
             break;
     }
 
+    /* Transfer size should be bytesPerFrame divisible. */
+    if ((xfer->dataSize % bytesPerFrame) != 0U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
     /* Save total transfer size. */
     handle->transferSize = xfer->dataSize;
 
@@ -168,7 +185,7 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
         xferConfig.destTransferSize = kEDMA_TransferSize1Bytes;
         xferConfig.minorLoopBytes   = 1U;
     }
-    else
+    else if (bytesPerFrame == 2U)
     {
         if (direction == kFLEXIO_SPI_MsbFirst)
         {
@@ -178,6 +195,16 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
         xferConfig.destTransferSize = kEDMA_TransferSize2Bytes;
         xferConfig.minorLoopBytes   = 2U;
     }
+    else
+    {
+        if (direction == kFLEXIO_SPI_MsbFirst)
+        {
+            xferConfig.destAddr -= 3U;
+        }
+        xferConfig.srcTransferSize  = kEDMA_TransferSize4Bytes;
+        xferConfig.destTransferSize = kEDMA_TransferSize4Bytes;
+        xferConfig.minorLoopBytes   = 4U;
+    }
 
     /* Configure DMA channel. */
     if (xfer->txData != NULL)
@@ -213,6 +240,16 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
                 xferConfig.srcAddr -= 1U;
             }
         }
+        else if (bytesPerFrame == 4U)
+        {
+            if (direction == kFLEXIO_SPI_LsbFirst)
+            {
+                xferConfig.srcAddr -= 3U;
+            }
+        }
+        else
+        {
+        }
         xferConfig.srcOffset  = 0;
         xferConfig.destAddr   = (uint32_t)(xfer->rxData);
         xferConfig.destOffset = (int16_t)bytesPerFrame;
@@ -229,6 +266,8 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
         FLEXIO_SPI_EnableDMA(base, (uint32_t)kFLEXIO_SPI_TxDmaEnable, true);
         EDMA_StartTransfer(handle->txHandle);
     }
+
+    return kStatus_Success;
 }
 
 /*!
@@ -321,8 +360,9 @@ status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base,
     assert(handle != NULL);
     assert(xfer != NULL);
 
-    uint32_t dataMode = 0;
-    uint16_t timerCmp = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]];
+    uint32_t dataMode  = 0;
+    uint16_t timerCmp  = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]];
+    uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
 
     timerCmp &= 0x00FFU;
 
@@ -338,27 +378,48 @@ status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base,
         return kStatus_InvalidArgument;
     }
 
+    /* Timer1 controls the CS signal which enables/disables(asserts/deasserts) when timer0 enable/disable. Timer0
+       enables when tx shifter is written and disables when timer compare. The timer compare event causes the
+       transmit shift registers to load which generates a tx register empty event. Since when timer stop bit is
+       disabled, a timer enable condition can be detected in the same cycle as a timer disable condition, so if
+       software writes the tx register upon the detection of tx register empty event, the timer enable condition
+       is triggered again, then the CS signal can remain low until software no longer writes the tx register. */
+    if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] =
+            (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
+            FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled);
+    }
+    else
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] =
+            (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
+            FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable);
+    }
+
     /* configure data mode. */
-    if ((xfer->flags == (uint8_t)kFLEXIO_SPI_8bitMsb) || (xfer->flags == (uint8_t)kFLEXIO_SPI_8bitLsb))
+    if ((dataFormat == (uint8_t)kFLEXIO_SPI_8bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_8bitLsb))
     {
         dataMode = (8UL * 2UL - 1UL) << 8U;
     }
-    else if ((xfer->flags == (uint8_t)kFLEXIO_SPI_16bitMsb) || (xfer->flags == (uint8_t)kFLEXIO_SPI_16bitLsb))
+    else if ((dataFormat == (uint8_t)kFLEXIO_SPI_16bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_16bitLsb))
     {
         dataMode = (16UL * 2UL - 1UL) << 8U;
     }
+    else if ((dataFormat == (uint8_t)kFLEXIO_SPI_32bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_32bitLsb))
+    {
+        dataMode = (32UL * 2UL - 1UL) << 8U;
+    }
     else
     {
-        dataMode = 8UL * 2UL - 1UL;
+        dataMode = (8UL * 2UL - 1UL) << 8U;
     }
 
     dataMode |= timerCmp;
 
     base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
 
-    FLEXIO_SPI_EDMAConfig(base, handle, xfer);
-
-    return kStatus_Success;
+    return FLEXIO_SPI_EDMAConfig(base, handle, xfer);
 }
 
 /*!
@@ -438,7 +499,8 @@ status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base,
     assert(handle != NULL);
     assert(xfer != NULL);
 
-    uint32_t dataMode = 0U;
+    uint32_t dataMode  = 0U;
+    uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
 
     /* Check if the device is busy. */
     if ((handle->txInProgress) || (handle->rxInProgress))
@@ -446,6 +508,33 @@ status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base,
         return kStatus_FLEXIO_SPI_Busy;
     }
 
+    /* SCK timer use CS pin as inverted trigger so timer should be disbaled on trigger falling edge(CS re-asserts). */
+    /* However if CPHA is first edge mode, timer will restart each time right after timer compare event occur and
+       before CS pin re-asserts, which triggers another shifter load. To avoid this, when in CS dis-continuous mode,
+       timer should disable in timer compare rather than trigger falling edge(CS re-asserts), and in CS continuous mode,
+       tx/rx shifters should be flushed after transfer finishes and before next transfer starts. */
+    FLEXIO_SPI_FlushShifters(base);
+    if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
+    {
+        base->flexioBase->TIMCFG[base->timerIndex[0]] |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge);
+    }
+    else
+    {
+        if ((base->flexioBase->SHIFTCTL[base->shifterIndex[0]] & FLEXIO_SHIFTCTL_TIMPOL_MASK) ==
+            FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive))
+        {
+            base->flexioBase->TIMCFG[base->timerIndex[0]] =
+                (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) |
+                FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare);
+        }
+        else
+        {
+            base->flexioBase->TIMCFG[base->timerIndex[0]] =
+                (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) |
+                FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge);
+        }
+    }
+
     /* Check if input parameter invalid. */
     if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U))
     {
@@ -453,14 +542,18 @@ status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base,
     }
 
     /* configure data mode. */
-    if ((xfer->flags == (uint8_t)kFLEXIO_SPI_8bitMsb) || (xfer->flags == (uint8_t)kFLEXIO_SPI_8bitLsb))
+    if ((dataFormat == (uint8_t)kFLEXIO_SPI_8bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_8bitLsb))
     {
         dataMode = 8U * 2U - 1U;
     }
-    else if ((xfer->flags == (uint8_t)kFLEXIO_SPI_16bitMsb) || (xfer->flags == (uint8_t)kFLEXIO_SPI_16bitLsb))
+    else if ((dataFormat == (uint8_t)kFLEXIO_SPI_16bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_16bitLsb))
     {
         dataMode = 16U * 2U - 1U;
     }
+    else if ((dataFormat == (uint8_t)kFLEXIO_SPI_32bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_32bitLsb))
+    {
+        dataMode = 32UL * 2UL - 1UL;
+    }
     else
     {
         dataMode = 8U * 2U - 1U;
@@ -468,7 +561,5 @@ status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base,
 
     base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
 
-    FLEXIO_SPI_EDMAConfig(base, handle, xfer);
-
-    return kStatus_Success;
+    return FLEXIO_SPI_EDMAConfig(base, handle, xfer);
 }

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi_edma.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2020 NXP
+ * Copyright 2016-2020, 2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -23,7 +23,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief FlexIO SPI EDMA driver version. */
-#define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
+#define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
 /*@}*/
 
 /*! @brief  typedef for flexio_spi_master_edma_handle_t in advance. */

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2017-2021 NXP
+ * Copyright 2017-2022 NXP
  * All rights reserved.
  *
  *
@@ -128,6 +128,55 @@ void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnabl
     }
 }
 
+void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error)
+{
+    assert(error != NULL);
+
+    switch (memory)
+    {
+        case kFLEXRAM_OCRAM:
+            base->OCRAM_ECC_ERROR_INJEC =
+                FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_ERR1BIT(error->SingleBitPos) |
+                FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_ERR2BIT(error->SecondBitPos) |
+                FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FR11BI(error->Fource1BitDataInversion) |
+                FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FR1NCI(error->FourceOneNCDataInversion) |
+                FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FRC1BI(error->FourceConti1BitDataInversion) |
+                FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FRCNCI(error->FourceContiNCDataInversion);
+            break;
+        case kFLEXRAM_ITCM:
+            base->ITCM_ECC_ERROR_INJEC = FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_ERR1BIT(error->SingleBitPos) |
+                                         FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_ERR2BIT(error->SecondBitPos) |
+                                         FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FR11BI(error->Fource1BitDataInversion) |
+                                         FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FR1NCI(error->FourceOneNCDataInversion) |
+                                         FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FRC1BI(error->FourceConti1BitDataInversion) |
+                                         FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FRCNCI(error->FourceContiNCDataInversion);
+            break;
+        case kFLEXRAM_D0TCM:
+            base->D0TCM_ECC_ERROR_INJEC =
+                FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_ERR1BIT(error->SingleBitPos) |
+                FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_ERR2BIT(error->SecondBitPos) |
+                FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FR11BI(error->Fource1BitDataInversion) |
+                FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FR1NCI(error->FourceOneNCDataInversion) |
+                FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FRC1BI(error->FourceConti1BitDataInversion) |
+                FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FRCNCI(error->FourceContiNCDataInversion);
+            break;
+        case kFLEXRAM_D1TCM:
+            base->D1TCM_ECC_ERROR_INJEC =
+                FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_ERR1BIT(error->SingleBitPos) |
+                FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_ERR2BIT(error->SecondBitPos) |
+                FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FR11BI(error->Fource1BitDataInversion) |
+                FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FR1NCI(error->FourceOneNCDataInversion) |
+                FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FRC1BI(error->FourceConti1BitDataInversion) |
+                FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FRCNCI(error->FourceContiNCDataInversion);
+            break;
+        default:
+            assert(NULL);
+            break;
+    }
+
+    __DSB();
+}
+
 void FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_single_error_info_t *info)
 {
     assert(NULL != info);

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2017-2021 NXP
+ * Copyright 2017-2022 NXP
  * All rights reserved.
  *
  *
@@ -23,8 +23,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief Driver version 2.1.0. */
-#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 0U))
+/*! @brief Driver version. */
+#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 0U))
 /*@}*/
 
 /*! @brief Get ECC error detailed information. */
@@ -108,6 +108,29 @@ enum
 };
 
 #if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC)
+/*! @brief FLEXRAM memory type, such as OCRAM/ITCM/D0TCM/D1TCM */
+typedef enum _flexram_memory_type
+{
+    kFLEXRAM_OCRAM = 0U, /*!< Memory type OCRAM */
+    kFLEXRAM_ITCM  = 1U, /*!< Memory type ITCM */
+    kFLEXRAM_D0TCM = 2U, /*!< Memory type D0TCM */
+    kFLEXRAM_D1TCM = 3U, /*!< Memory type D1TCM */
+} flexram_memory_type_t;
+
+/*! @brief FLEXRAM error type, such as single bit error position, multi-bit error position */
+typedef struct _flexram_ecc_error_type
+{
+    uint8_t SingleBitPos;          /*!< Bit position of the bit to inject ECC Error. */
+    uint8_t SecondBitPos;          /*!< Bit position of the second bit to inject multi-bit ECC Error */
+    bool Fource1BitDataInversion;  /*!< Force One 1-Bit Data Inversion (single-bit ECC error) on memory write access */
+    bool FourceOneNCDataInversion; /*!< Force One Non-correctable Data Inversion(multi-bit ECC error) on memory write
+                                      access */
+    bool FourceConti1BitDataInversion; /*!< Force Continuous 1-Bit Data Inversions (single-bit ECC error) on memory
+                                          write access */
+    bool FourceContiNCDataInversion;   /*!< Force Continuous Non-correctable Data Inversions (multi-bit ECC error) on
+                                          memory write access */
+} flexram_ecc_error_type_t;
+
 /*! @brief FLEXRAM ocram ecc single error information, including single error information, error address, error data */
 typedef struct _flexram_ocram_ecc_single_error_info
 {
@@ -422,6 +445,14 @@ static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAd
  */
 void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnable);
 
+/*!
+ * @brief FLEXRAM ECC error injection.
+ * @param base  FLEXRAM base address.
+ * @param memory memory type, such as OCRAM/ITCM/DTCM.
+ * @param error ECC error type.
+ */
+void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error);
+
 /*!
  * @brief FLEXRAM get ocram ecc single error information.
  * @param base  FLEXRAM base address.

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexspi.c

@@ -33,10 +33,14 @@ enum
         FLEXSPI_STS2_ASLVLOCK_MASK, /* Flash A sample clock slave delay line locked. */
     kFLEXSPI_FlashASampleClockRefDelayLocked =
         FLEXSPI_STS2_AREFLOCK_MASK, /* Flash A sample clock reference delay line locked. */
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK))
     kFLEXSPI_FlashBSampleClockSlaveDelayLocked =
         FLEXSPI_STS2_BSLVLOCK_MASK, /* Flash B sample clock slave delay line locked. */
+#endif
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK))
     kFLEXSPI_FlashBSampleClockRefDelayLocked =
         FLEXSPI_STS2_BREFLOCK_MASK, /* Flash B sample clock reference delay line locked. */
+#endif
 };
 
 /*! @brief Common sets of flags used by the driver, _flexspi_flag_constants. */
@@ -293,10 +297,15 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
 
     /* Configure MCR2 configurations. */
     configValue = base->MCR2;
-    configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK | FLEXSPI_MCR2_SCKBDIFFOPT_MASK | FLEXSPI_MCR2_SAMEDEVICEEN_MASK |
-                     FLEXSPI_MCR2_CLRAHBBUFOPT_MASK);
+    configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK |
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
+                     FLEXSPI_MCR2_SCKBDIFFOPT_MASK |
+#endif
+                     FLEXSPI_MCR2_SAMEDEVICEEN_MASK | FLEXSPI_MCR2_CLRAHBBUFOPT_MASK);
     configValue |= FLEXSPI_MCR2_RESUMEWAIT(config->ahbConfig.resumeWaitCycle) |
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
                    FLEXSPI_MCR2_SCKBDIFFOPT(config->enableSckBDiffOpt) |
+#endif
                    FLEXSPI_MCR2_SAMEDEVICEEN(config->enableSameConfigForAll) |
                    FLEXSPI_MCR2_CLRAHBBUFOPT(config->ahbConfig.enableClearAHBBufferOpt);
 
@@ -354,9 +363,11 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
 #if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
     config->enableCombination = false;
 #endif
-    config->enableDoze             = true;
-    config->enableHalfSpeedAccess  = false;
-    config->enableSckBDiffOpt      = false;
+    config->enableDoze            = true;
+    config->enableHalfSpeedAccess = false;
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
+    config->enableSckBDiffOpt = false;
+#endif
     config->enableSameConfigForAll = false;
     config->seqTimeoutCycle        = 0xFFFFU;
     config->ipGrantTimeoutCycle    = 0xFFU;
@@ -432,12 +443,18 @@ void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config,
     base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
 
     /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
-    statusValue =
-        (index == 0U) ?
-            ((uint32_t)kFLEXSPI_FlashASampleClockSlaveDelayLocked |
-             (uint32_t)kFLEXSPI_FlashASampleClockRefDelayLocked) :
+    if (index == 0U)
+    {
+        statusValue =
+            ((uint32_t)kFLEXSPI_FlashASampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashASampleClockRefDelayLocked);
+    }
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK))
+    else
+    {
+        statusValue =
             ((uint32_t)kFLEXSPI_FlashBSampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashBSampleClockRefDelayLocked);
-
+    }
+#endif
     if (0U != (configValue & FLEXSPI_DLLCR_DLLEN_MASK))
     {
         /* Wait slave delay line locked and slave reference delay line locked. */
@@ -527,11 +544,13 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
         base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENA_MASK;
         base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENA(config->enableWriteMask);
     }
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB))
     else
     {
         base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENB_MASK;
         base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENB(config->enableWriteMask);
     }
+#endif
 
     /* Exit stop mode. */
     base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
@@ -564,8 +583,10 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd,
     }
 
     /* Unlock LUT for update. */
+#if !((defined(FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) && (FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO))
     base->LUTKEY = FLEXSPI_LUT_KEY_VAL;
-    base->LUTCR  = 0x02;
+#endif
+    base->LUTCR = 0x02;
 
     lutBase = &base->LUT[index];
     for (i = 0; i < count; i++)
@@ -574,8 +595,10 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd,
     }
 
     /* Lock LUT. */
+#if !((defined(FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) && (FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO))
     base->LUTKEY = FLEXSPI_LUT_KEY_VAL;
-    base->LUTCR  = 0x01;
+#endif
+    base->LUTCR = 0x01;
 }
 
 /*! brief Update read sample clock source

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexspi.h

@@ -25,7 +25,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief FLEXSPI driver version 2.3.5. */
-#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 5))
+#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 6))
 /*@}*/
 
 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)
@@ -190,8 +190,10 @@ typedef enum _flexspi_port
 {
     kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */
     kFLEXSPI_PortA2,        /*!< Access flash on A2 port. */
-    kFLEXSPI_PortB1,        /*!< Access flash on B1 port. */
-    kFLEXSPI_PortB2,        /*!< Access flash on B2 port. */
+#if !((defined(FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB)) && (FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB))
+    kFLEXSPI_PortB1, /*!< Access flash on B1 port. */
+    kFLEXSPI_PortB2, /*!< Access flash on B2 port. */
+#endif
     kFLEXSPI_PortCount
 } flexspi_port_t;
 
@@ -231,11 +233,13 @@ typedef struct _flexspi_config
     bool enableCombination; /*!< Enable/disable combining PORT A and B Data Pins
                             (SIOA[3:0] and SIOB[3:0]) to support Flash Octal mode. */
 #endif
-    bool enableDoze;             /*!< Enable/disable doze mode support. */
-    bool enableHalfSpeedAccess;  /*!< Enable/disable divide by 2 of the clock for half
-                                  speed commands. */
-    bool enableSckBDiffOpt;      /*!< Enable/disable SCKB pad use as SCKA differential clock
-                                  output, when enable, Port B flash access is not available. */
+    bool enableDoze;            /*!< Enable/disable doze mode support. */
+    bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half
+                                 speed commands. */
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
+    bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock
+                             output, when enable, Port B flash access is not available. */
+#endif
     bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices
                                   when enabled, same configuration in FLASHA1CRx is applied to all. */
     uint16_t seqTimeoutCycle;    /*!< Timeout wait cycle for command sequence execution,
@@ -615,10 +619,12 @@ static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *por
         *portAPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT);
     }
 
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB))
     if (portBPhase != NULL)
     {
         *portBPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT);
     }
+#endif
 }
 #endif
 
@@ -683,6 +689,7 @@ static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
  */
 void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource);
 
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN))
 /*! @brief Enables/disables the FLEXSPI IP command parallel mode.
  *
  * @param base FLEXSPI peripheral base address.
@@ -699,7 +706,9 @@ static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
         base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK;
     }
 }
+#endif
 
+#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN))
 /*! @brief Enables/disables the FLEXSPI AHB command parallel mode.
  *
  * @param base FLEXSPI peripheral base address.
@@ -716,6 +725,7 @@ static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable
         base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK;
     }
 }
+#endif
 
 /*! @brief Updates the LUT table.
  *

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpio.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017, 2020 NXP
+ * Copyright 2016-2017, 2020-2021 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -17,8 +17,10 @@
  * Variables
  ******************************************************************************/
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /* Array of GPIO peripheral base address. */
 static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
+#endif
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /* Array of GPIO clock name. */
@@ -29,6 +31,7 @@ static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS;
  * Prototypes
  ******************************************************************************/
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*!
  * @brief Gets the GPIO instance according to the GPIO base
  *
@@ -58,6 +61,7 @@ static uint32_t GPIO_GetInstance(GPIO_Type *base)
 
     return instance;
 }
+#endif
 
 /*!
  * brief Initializes the GPIO peripheral according to the specified

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpio.h

@@ -23,7 +23,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief GPIO driver version. */
-#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 6))
 /*@}*/
 
 /*! @brief GPIO direction definition. */

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpt.h

@@ -22,7 +22,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
+#define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
 /*@}*/
 
 /*!

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_iomuxc.h

@@ -1,6 +1,6 @@
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -1144,6 +1144,69 @@
 #define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U
 #define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U
 
+#define IOMUXC_GPIO_SPI_B0_00_GPIO10_IO00 0x401F865CU, 0x5U, 0, 0, 0x401F86B4U
+
+#define IOMUXC_GPIO_SPI_B0_01_FLEXSPI2_B_SCLK 0x401F8660U, 0x0U, 0x401F8754U, 0x1U, 0x401F86B8U
+#define IOMUXC_GPIO_SPI_B0_01_GPIO10_IO01 0x401F8660U, 0x5U, 0, 0, 0x401F86B8U
+
+#define IOMUXC_GPIO_SPI_B0_02_FLEXSPI2_A_DATA00 0x401F8664U, 0x0U, 0x401F8730U, 0x2U, 0x401F86BCU
+#define IOMUXC_GPIO_SPI_B0_02_GPIO10_IO02 0x401F8664U, 0x5U, 0, 0, 0x401F86BCU
+
+#define IOMUXC_GPIO_SPI_B0_03_FLEXSPI2_B_DATA02 0x401F8668U, 0x0U, 0x401F8748U, 0x1U, 0x401F86C0U
+#define IOMUXC_GPIO_SPI_B0_03_GPIO10_IO03 0x401F8668U, 0x5U, 0, 0, 0x401F86C0U
+
+#define IOMUXC_GPIO_SPI_B0_04_FLEXSPI2_B_DATA03 0x401F866CU, 0x0U, 0x401F874CU, 0x1U, 0x401F86C4U
+#define IOMUXC_GPIO_SPI_B0_04_GPIO10_IO04 0x401F866CU, 0x5U, 0, 0, 0x401F86C4U
+
+#define IOMUXC_GPIO_SPI_B0_05_FLEXSPI2_A_SS0_B 0x401F8670U, 0x0U, 0, 0, 0x401F86C8U
+#define IOMUXC_GPIO_SPI_B0_05_GPIO10_IO05 0x401F8670U, 0x5U, 0, 0, 0x401F86C8U
+
+#define IOMUXC_GPIO_SPI_B0_06_FLEXSPI2_A_DATA02 0x401F8674U, 0x0U, 0x401F8738U, 0x2U, 0x401F86CCU
+#define IOMUXC_GPIO_SPI_B0_06_GPIO10_IO06 0x401F8674U, 0x5U, 0, 0, 0x401F86CCU
+
+#define IOMUXC_GPIO_SPI_B0_07_FLEXSPI2_B_DATA01 0x401F8678U, 0x0U, 0x401F8744U, 0x1U, 0x401F86D0U
+#define IOMUXC_GPIO_SPI_B0_07_GPIO10_IO07 0x401F8678U, 0x5U, 0, 0, 0x401F86D0U
+
+#define IOMUXC_GPIO_SPI_B0_08_FLEXSPI2_A_SCLK 0x401F867CU, 0x0U, 0x401F8750U, 0x2U, 0x401F86D4U
+#define IOMUXC_GPIO_SPI_B0_08_GPIO10_IO08 0x401F867CU, 0x5U, 0, 0, 0x401F86D4U
+
+#define IOMUXC_GPIO_SPI_B0_09_FLEXSPI2_A_DQS 0x401F8680U, 0x0U, 0x401F872CU, 0x2U, 0x401F86D8U
+#define IOMUXC_GPIO_SPI_B0_09_GPIO10_IO09 0x401F8680U, 0x5U, 0, 0, 0x401F86D8U
+
+#define IOMUXC_GPIO_SPI_B0_10_FLEXSPI2_A_DATA03 0x401F8684U, 0x0U, 0x401F873CU, 0x2U, 0x401F86DCU
+#define IOMUXC_GPIO_SPI_B0_10_GPIO10_IO10 0x401F8684U, 0x5U, 0, 0, 0x401F86DCU
+
+#define IOMUXC_GPIO_SPI_B0_11_FLEXSPI2_B_DATA00 0x401F8688U, 0x0U, 0x401F8740U, 0x1U, 0x401F86E0U
+#define IOMUXC_GPIO_SPI_B0_11_GPIO10_IO11 0x401F8688U, 0x5U, 0, 0, 0x401F86E0U
+
+#define IOMUXC_GPIO_SPI_B0_12_FLEXSPI2_A_DATA01 0x401F868CU, 0x0U, 0x401F8734U, 0x2U, 0x401F86E4U
+#define IOMUXC_GPIO_SPI_B0_12_GPIO10_IO12 0x401F868CU, 0x5U, 0, 0, 0x401F86E4U
+
+#define IOMUXC_GPIO_SPI_B0_13_GPIO10_IO13 0x401F8690U, 0x5U, 0, 0, 0x401F86E8U
+
+#define IOMUXC_GPIO_SPI_B1_00_FLEXSPI2_A_DQS 0x401F8694U, 0x0U, 0x401F872CU, 0x0U, 0x401F86ECU
+#define IOMUXC_GPIO_SPI_B1_00_GPIO10_IO14 0x401F8694U, 0x5U, 0, 0, 0x401F86ECU
+
+#define IOMUXC_GPIO_SPI_B1_01_FLEXSPI2_A_DATA03 0x401F8698U, 0x0U, 0x401F873CU, 0x0U, 0x401F86F0U
+#define IOMUXC_GPIO_SPI_B1_01_GPIO10_IO15 0x401F8698U, 0x5U, 0, 0, 0x401F86F0U
+
+#define IOMUXC_GPIO_SPI_B1_02_FLEXSPI2_A_DATA02 0x401F869CU, 0x0U, 0x401F8738U, 0x0U, 0x401F86F4U
+#define IOMUXC_GPIO_SPI_B1_02_GPIO10_IO16 0x401F869CU, 0x5U, 0, 0, 0x401F86F4U
+
+#define IOMUXC_GPIO_SPI_B1_03_FLEXSPI2_A_DATA01 0x401F86A0U, 0x0U, 0x401F8734U, 0x0U, 0x401F86F8U
+#define IOMUXC_GPIO_SPI_B1_03_GPIO10_IO17 0x401F86A0U, 0x5U, 0, 0, 0x401F86F8U
+
+#define IOMUXC_GPIO_SPI_B1_04_FLEXSPI2_A_DATA00 0x401F86A4U, 0x0U, 0x401F8730U, 0x0U, 0x401F86FCU
+#define IOMUXC_GPIO_SPI_B1_04_GPIO10_IO18 0x401F86A4U, 0x5U, 0, 0, 0x401F86FCU
+
+#define IOMUXC_GPIO_SPI_B1_05_FLEXSPI2_A_SCLK 0x401F86A8U, 0x0U, 0x401F8750U, 0x0U, 0x401F8700U
+#define IOMUXC_GPIO_SPI_B1_05_GPIO10_IO19 0x401F86A8U, 0x5U, 0, 0, 0x401F8700U
+
+#define IOMUXC_GPIO_SPI_B1_06_FLEXSPI2_A_SS0_B 0x401F86ACU, 0x0U, 0, 0, 0x401F8704U
+#define IOMUXC_GPIO_SPI_B1_06_GPIO10_IO20 0x401F86ACU, 0x5U, 0, 0, 0x401F8704U
+
+#define IOMUXC_GPIO_SPI_B1_07_GPIO10_IO21 0x401F86B0U, 0x5U, 0, 0, 0x401F8708U
+
 #define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U
 #define IOMUXC_SNVS_WAKEUP_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U
 

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpi2c_freertos.c

@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_lpi2c_freertos.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpi2c_freertos"
+#endif
+
+static void LPI2C_RTOS_Callback(LPI2C_Type *base, lpi2c_master_handle_t *drv_handle, status_t status, void *userData)
+{
+    lpi2c_rtos_handle_t *handle = (lpi2c_rtos_handle_t *)userData;
+    BaseType_t reschedule;
+    handle->async_status = status;
+    (void)xSemaphoreGiveFromISR(handle->semaphore, &reschedule);
+    portYIELD_FROM_ISR(reschedule);
+}
+
+/*!
+ * brief Initializes LPI2C.
+ *
+ * This function initializes the LPI2C module and related RTOS context.
+ *
+ * param handle The RTOS LPI2C handle, the pointer to an allocated space for RTOS context.
+ * param base The pointer base address of the LPI2C instance to initialize.
+ * param masterConfig Configuration structure to set-up LPI2C in master mode.
+ * param srcClock_Hz Frequency of input clock of the LPI2C module.
+ * return status of the operation.
+ */
+status_t LPI2C_RTOS_Init(lpi2c_rtos_handle_t *handle,
+                         LPI2C_Type *base,
+                         const lpi2c_master_config_t *masterConfig,
+                         uint32_t srcClock_Hz)
+{
+    if (handle == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (base == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    (void)memset(handle, 0, sizeof(lpi2c_rtos_handle_t));
+
+    handle->mutex = xSemaphoreCreateMutex();
+    if (handle->mutex == NULL)
+    {
+        return kStatus_Fail;
+    }
+
+    handle->semaphore = xSemaphoreCreateBinary();
+    if (handle->semaphore == NULL)
+    {
+        vSemaphoreDelete(handle->mutex);
+        return kStatus_Fail;
+    }
+
+    handle->base = base;
+
+    LPI2C_MasterInit(handle->base, masterConfig, srcClock_Hz);
+    LPI2C_MasterTransferCreateHandle(base, &handle->drv_handle, LPI2C_RTOS_Callback, (void *)handle);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Deinitializes the LPI2C.
+ *
+ * This function deinitializes the LPI2C module and related RTOS context.
+ *
+ * param handle The RTOS LPI2C handle.
+ */
+status_t LPI2C_RTOS_Deinit(lpi2c_rtos_handle_t *handle)
+{
+    LPI2C_MasterDeinit(handle->base);
+
+    vSemaphoreDelete(handle->semaphore);
+    vSemaphoreDelete(handle->mutex);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Performs I2C transfer.
+ *
+ * This function performs an I2C transfer using LPI2C module according to data given in the transfer structure.
+ *
+ * param handle The RTOS LPI2C handle.
+ * param transfer Structure specifying the transfer parameters.
+ * return status of the operation.
+ */
+status_t LPI2C_RTOS_Transfer(lpi2c_rtos_handle_t *handle, lpi2c_master_transfer_t *transfer)
+{
+    status_t status;
+
+    /* Lock resource mutex */
+    if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE)
+    {
+        return kStatus_LPI2C_Busy;
+    }
+
+    status = LPI2C_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer);
+    if (status != kStatus_Success)
+    {
+        (void)xSemaphoreGive(handle->mutex);
+        return status;
+    }
+
+    /* Wait for transfer to finish */
+    (void)xSemaphoreTake(handle->semaphore, portMAX_DELAY);
+
+    /* Unlock resource mutex */
+    (void)xSemaphoreGive(handle->mutex);
+
+    /* Return status captured by callback function */
+    return handle->async_status;
+}

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpi2c_freertos.h

@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __FSL_LPI2C_FREERTOS_H__
+#define __FSL_LPI2C_FREERTOS_H__
+
+#include "FreeRTOS.h"
+#include "portable.h"
+#include "semphr.h"
+
+#include "fsl_lpi2c.h"
+
+/*!
+ * @addtogroup lpi2c_freertos_driver LPI2C FreeRTOS Driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPI2C FreeRTOS driver version. */
+#define FSL_LPI2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
+/*@}*/
+
+/*!
+ * @cond RTOS_PRIVATE
+ * @brief LPI2C FreeRTOS handle
+ */
+typedef struct _lpi2c_rtos_handle
+{
+    LPI2C_Type *base;                 /*!< LPI2C base address */
+    lpi2c_master_handle_t drv_handle; /*!< Handle of the underlying driver, treated as opaque by the RTOS layer */
+    status_t async_status;
+    SemaphoreHandle_t mutex;     /*!< Mutex to lock the handle during a trasfer */
+    SemaphoreHandle_t semaphore; /*!< Semaphore to notify and unblock task when transfer ends */
+} lpi2c_rtos_handle_t;
+/*! \endcond */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name LPI2C RTOS Operation
+ * @{
+ */
+
+/*!
+ * @brief Initializes LPI2C.
+ *
+ * This function initializes the LPI2C module and related RTOS context.
+ *
+ * @param handle The RTOS LPI2C handle, the pointer to an allocated space for RTOS context.
+ * @param base The pointer base address of the LPI2C instance to initialize.
+ * @param masterConfig Configuration structure to set-up LPI2C in master mode.
+ * @param srcClock_Hz Frequency of input clock of the LPI2C module.
+ * @return status of the operation.
+ */
+status_t LPI2C_RTOS_Init(lpi2c_rtos_handle_t *handle,
+                         LPI2C_Type *base,
+                         const lpi2c_master_config_t *masterConfig,
+                         uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes the LPI2C.
+ *
+ * This function deinitializes the LPI2C module and related RTOS context.
+ *
+ * @param handle The RTOS LPI2C handle.
+ */
+status_t LPI2C_RTOS_Deinit(lpi2c_rtos_handle_t *handle);
+
+/*!
+ * @brief Performs I2C transfer.
+ *
+ * This function performs an I2C transfer using LPI2C module according to data given in the transfer structure.
+ *
+ * @param handle The RTOS LPI2C handle.
+ * @param transfer Structure specifying the transfer parameters.
+ * @return status of the operation.
+ */
+status_t LPI2C_RTOS_Transfer(lpi2c_rtos_handle_t *handle, lpi2c_master_transfer_t *transfer);
+
+/*!
+ * @}
+ */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* __FSL_LPI2C_FREERTOS_H__ */

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_edma.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2020 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -163,11 +163,11 @@ extern "C" {
  * This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs.  Usually, for a
  * specified LPSPI instance, call this API once to get the initialized handle.
  *
- * Note that the LPSPI eDMA has a separated (Rx and Rx as two sources) or shared (Rx  and Tx are the same source) DMA
+ * Note that the LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx  and Tx are the same source) DMA
  * request source.
  * (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and
- * Tx DMAMUX source for edmaIntermediaryToTxRegHandle.
- * (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle.
+ * Tx DMAMUX source for edmaTxDataToTxRegHandle.
+ * (2) For a shared DMA request source, enable and set the Rx/Tx DMAMUX source for edmaRxRegToRxDataHandle.
  *
  * @param base LPSPI peripheral base address.
  * @param handle LPSPI handle pointer to lpspi_master_edma_handle_t.

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_freertos.c

@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_lpspi_freertos.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpspi_freertos"
+#endif
+
+static void LPSPI_RTOS_Callback(LPSPI_Type *base, lpspi_master_handle_t *drv_handle, status_t status, void *userData)
+{
+    lpspi_rtos_handle_t *handle = (lpspi_rtos_handle_t *)userData;
+    BaseType_t reschedule;
+    handle->async_status = status;
+    (void)xSemaphoreGiveFromISR(handle->event, &reschedule);
+    portYIELD_FROM_ISR(reschedule);
+}
+
+/*!
+ * brief Initializes LPSPI.
+ *
+ * This function initializes the LPSPI module and related RTOS context.
+ *
+ * param handle The RTOS LPSPI handle, the pointer to an allocated space for RTOS context.
+ * param base The pointer base address of the LPSPI instance to initialize.
+ * param masterConfig Configuration structure to set-up LPSPI in master mode.
+ * param srcClock_Hz Frequency of input clock of the LPSPI module.
+ * return status of the operation.
+ */
+status_t LPSPI_RTOS_Init(lpspi_rtos_handle_t *handle,
+                         LPSPI_Type *base,
+                         const lpspi_master_config_t *masterConfig,
+                         uint32_t srcClock_Hz)
+{
+    if (handle == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (base == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    (void)memset(handle, 0, sizeof(lpspi_rtos_handle_t));
+
+    handle->mutex = xSemaphoreCreateMutex();
+    if (handle->mutex == NULL)
+    {
+        return kStatus_Fail;
+    }
+
+    handle->event = xSemaphoreCreateBinary();
+    if (handle->event == NULL)
+    {
+        vSemaphoreDelete(handle->mutex);
+        return kStatus_Fail;
+    }
+
+    handle->base = base;
+
+    LPSPI_MasterInit(handle->base, masterConfig, srcClock_Hz);
+    LPSPI_MasterTransferCreateHandle(handle->base, &handle->drv_handle, LPSPI_RTOS_Callback, (void *)handle);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Deinitializes the LPSPI.
+ *
+ * This function deinitializes the LPSPI module and related RTOS context.
+ *
+ * param handle The RTOS LPSPI handle.
+ */
+status_t LPSPI_RTOS_Deinit(lpspi_rtos_handle_t *handle)
+{
+    LPSPI_Deinit(handle->base);
+    vSemaphoreDelete(handle->event);
+    vSemaphoreDelete(handle->mutex);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Performs SPI transfer.
+ *
+ * This function performs an SPI transfer according to data given in the transfer structure.
+ *
+ * param handle The RTOS LPSPI handle.
+ * param transfer Structure specifying the transfer parameters.
+ * return status of the operation.
+ */
+status_t LPSPI_RTOS_Transfer(lpspi_rtos_handle_t *handle, lpspi_transfer_t *transfer)
+{
+    status_t status;
+
+    /* Lock resource mutex */
+    if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE)
+    {
+        return kStatus_LPSPI_Busy;
+    }
+
+    status = LPSPI_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer);
+    if (status != kStatus_Success)
+    {
+        (void)xSemaphoreGive(handle->mutex);
+        return status;
+    }
+
+    /* Wait for transfer to finish */
+    if (xSemaphoreTake(handle->event, portMAX_DELAY) != pdTRUE)
+    {
+        return kStatus_LPSPI_Error;
+    }
+
+    /* Unlock resource mutex */
+    (void)xSemaphoreGive(handle->mutex);
+
+    /* Return status captured by callback function */
+    return handle->async_status;
+}

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_freertos.h

@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __FSL_LPSPI_FREERTOS_H__
+#define __FSL_LPSPI_FREERTOS_H__
+
+#include "FreeRTOS.h"
+#include "portable.h"
+#include "semphr.h"
+
+#include "fsl_lpspi.h"
+
+/*!
+ * @addtogroup lpspi_freertos_driver LPSPI FreeRTOS Driver
+ * @{
+ */
+
+/**********************************************************************************************************************
+ * Definitions
+ *********************************************************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPSPI FreeRTOS driver version 2.0.5. */
+#define FSL_LPSPI_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
+/*@}*/
+
+/*!
+ * @cond RTOS_PRIVATE
+ * @brief LPSPI FreeRTOS handle
+ */
+typedef struct _lpspi_rtos_handle
+{
+    LPSPI_Type *base;                 /*!< LPSPI base address */
+    lpspi_master_handle_t drv_handle; /*!< Handle of the underlying driver, treated as opaque by the RTOS layer */
+    status_t async_status;
+    SemaphoreHandle_t mutex; /*!< Mutex to lock the handle during a trasfer */
+    SemaphoreHandle_t event; /*!< Semaphore to notify and unblock task when transfer ends */
+} lpspi_rtos_handle_t;
+/*! \endcond */
+
+/**********************************************************************************************************************
+ * API
+ *********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name LPSPI RTOS Operation
+ * @{
+ */
+
+/*!
+ * @brief Initializes LPSPI.
+ *
+ * This function initializes the LPSPI module and related RTOS context.
+ *
+ * @param handle The RTOS LPSPI handle, the pointer to an allocated space for RTOS context.
+ * @param base The pointer base address of the LPSPI instance to initialize.
+ * @param masterConfig Configuration structure to set-up LPSPI in master mode.
+ * @param srcClock_Hz Frequency of input clock of the LPSPI module.
+ * @return status of the operation.
+ */
+status_t LPSPI_RTOS_Init(lpspi_rtos_handle_t *handle,
+                         LPSPI_Type *base,
+                         const lpspi_master_config_t *masterConfig,
+                         uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes the LPSPI.
+ *
+ * This function deinitializes the LPSPI module and related RTOS context.
+ *
+ * @param handle The RTOS LPSPI handle.
+ */
+status_t LPSPI_RTOS_Deinit(lpspi_rtos_handle_t *handle);
+
+/*!
+ * @brief Performs SPI transfer.
+ *
+ * This function performs an SPI transfer according to data given in the transfer structure.
+ *
+ * @param handle The RTOS LPSPI handle.
+ * @param transfer Structure specifying the transfer parameters.
+ * @return status of the operation.
+ */
+status_t LPSPI_RTOS_Transfer(lpspi_rtos_handle_t *handle, lpspi_transfer_t *transfer);
+
+/*!
+ * @}
+ */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* __FSL_LPSPI_FREERTOS_H__ */

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -700,7 +700,7 @@ void LPUART_SendAddress(LPUART_Type *base, uint8_t address)
  * endcode
  *
  * param base LPUART peripheral base address.
- * param mask The interrupts to enable. Logical OR of ref _uart_interrupt_enable.
+ * param mask The interrupts to enable. Logical OR of ref _lpuart_interrupt_enable.
  */
 void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
 {
@@ -727,7 +727,7 @@ void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
     mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable);
 #endif
 
-    /* Check int enable bits in base->CTRL */
+    /* Set int enable bits in base->CTRL */
     base->CTRL |= mask;
 }
 
@@ -851,7 +851,7 @@ uint32_t LPUART_GetStatusFlags(LPUART_Type *base)
  * can't be cleared by this function.
  * Flags that can only cleared or set by hardware are:
  *    kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
- *    kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
+ *    kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag,
  *    kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
  * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
  *

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -22,7 +22,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief LPUART driver version. */
-#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 5, 2))
+#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 5, 3))
 /*@}*/
 
 /*! @brief Retry times for waiting flag. */
@@ -564,7 +564,7 @@ uint32_t LPUART_GetStatusFlags(LPUART_Type *base);
  * can't be cleared by this function.
  * Flags that can only cleared or set by hardware are:
  *    kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
- *    kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
+ *    kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag,
  *    kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
  * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
  *
@@ -595,7 +595,7 @@ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask);
  * @endcode
  *
  * @param base LPUART peripheral base address.
- * @param mask The interrupts to enable. Logical OR of the enumeration _uart_interrupt_enable.
+ * @param mask The interrupts to enable. Logical OR of @ref _lpuart_interrupt_enable.
  */
 void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask);
 

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_edma.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2020 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -38,6 +38,18 @@ enum
  ******************************************************************************/
 
 /* Array of LPUART handle. */
+#if (defined(LPUART12))
+#define LPUART_HANDLE_ARRAY_SIZE 13
+#else /* LPUART12 */
+#if (defined(LPUART11))
+#define LPUART_HANDLE_ARRAY_SIZE 12
+#else /* LPUART11 */
+#if (defined(LPUART10))
+#define LPUART_HANDLE_ARRAY_SIZE 11
+#else /* LPUART10 */
+#if (defined(LPUART9))
+#define LPUART_HANDLE_ARRAY_SIZE 10
+#else /* LPUART9 */
 #if (defined(LPUART8))
 #define LPUART_HANDLE_ARRAY_SIZE 9
 #else /* LPUART8 */
@@ -75,6 +87,10 @@ enum
 #endif /* LPUART 6 */
 #endif /* LPUART 7 */
 #endif /* LPUART 8 */
+#endif /* LPUART 9 */
+#endif /* LPUART 10 */
+#endif /* LPUART 11 */
+#endif /* LPUART 12 */
 
 /*<! Private handle only used for internally. */
 static lpuart_edma_private_handle_t s_lpuartEdmaPrivateHandle[LPUART_HANDLE_ARRAY_SIZE];

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_freertos.c

@@ -0,0 +1,477 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_lpuart_freertos.h"
+#include <FreeRTOS.h>
+#include <event_groups.h>
+#include <semphr.h>
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpuart_freertos"
+#endif
+
+static void LPUART_RTOS_Callback(LPUART_Type *base, lpuart_handle_t *state, status_t status, void *param)
+{
+    lpuart_rtos_handle_t *handle = (lpuart_rtos_handle_t *)param;
+    BaseType_t xHigherPriorityTaskWoken, xResult;
+
+    xHigherPriorityTaskWoken = pdFALSE;
+    xResult                  = pdFAIL;
+
+    if (status == kStatus_LPUART_RxIdle)
+    {
+        xResult = xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_LPUART_RX_COMPLETE, &xHigherPriorityTaskWoken);
+    }
+    else if (status == kStatus_LPUART_TxIdle)
+    {
+        xResult = xEventGroupSetBitsFromISR(handle->txEvent, RTOS_LPUART_TX_COMPLETE, &xHigherPriorityTaskWoken);
+    }
+    else if (status == kStatus_LPUART_RxRingBufferOverrun)
+    {
+        xResult =
+            xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_LPUART_RING_BUFFER_OVERRUN, &xHigherPriorityTaskWoken);
+    }
+    else if (status == kStatus_LPUART_RxHardwareOverrun)
+    {
+        /* Clear Overrun flag (OR) in LPUART STAT register */
+        (void)LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag);
+        xResult =
+            xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_LPUART_HARDWARE_BUFFER_OVERRUN, &xHigherPriorityTaskWoken);
+    }
+    else
+    {
+        xResult = pdFAIL;
+    }
+
+    if (xResult != pdFAIL)
+    {
+        portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_RTOS_Init
+ * Description   : Initializes the LPUART instance for application
+ *
+ *END**************************************************************************/
+/*!
+ * brief Initializes an LPUART instance for operation in RTOS.
+ *
+ * param handle The RTOS LPUART handle, the pointer to an allocated space for RTOS context.
+ * param t_handle The pointer to an allocated space to store the transactional layer internal state.
+ * param cfg The pointer to the parameters required to configure the LPUART after initialization.
+ * return kStatus_Success, others failed
+ */
+int LPUART_RTOS_Init(lpuart_rtos_handle_t *handle, lpuart_handle_t *t_handle, const lpuart_rtos_config_t *cfg)
+{
+    status_t status;
+    lpuart_config_t defcfg;
+
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+    if (NULL == t_handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+    if (NULL == cfg)
+    {
+        return kStatus_InvalidArgument;
+    }
+    if (NULL == cfg->base)
+    {
+        return kStatus_InvalidArgument;
+    }
+    if (0u == cfg->srcclk)
+    {
+        return kStatus_InvalidArgument;
+    }
+    if (0u == cfg->baudrate)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    handle->base                     = cfg->base;
+    handle->t_state                  = t_handle;
+    handle->rx_timeout_constant_ms   = cfg->rx_timeout_constant_ms;
+    handle->rx_timeout_multiplier_ms = cfg->rx_timeout_multiplier_ms;
+    handle->tx_timeout_constant_ms   = cfg->tx_timeout_constant_ms;
+    handle->tx_timeout_multiplier_ms = cfg->tx_timeout_multiplier_ms;
+
+#if (configSUPPORT_STATIC_ALLOCATION == 1)
+    handle->txSemaphore = xSemaphoreCreateMutexStatic(&handle->txSemaphoreBuffer);
+#else
+    handle->txSemaphore = xSemaphoreCreateMutex();
+#endif
+    if (NULL == handle->txSemaphore)
+    {
+        return kStatus_Fail;
+    }
+#if (configSUPPORT_STATIC_ALLOCATION == 1)
+    handle->rxSemaphore = xSemaphoreCreateMutexStatic(&handle->rxSemaphoreBuffer);
+#else
+    handle->rxSemaphore = xSemaphoreCreateMutex();
+#endif
+    if (NULL == handle->rxSemaphore)
+    {
+        vSemaphoreDelete(handle->txSemaphore);
+        return kStatus_Fail;
+    }
+#if (configSUPPORT_STATIC_ALLOCATION == 1)
+    handle->txEvent = xEventGroupCreateStatic(&handle->txEventBuffer);
+#else
+    handle->txEvent     = xEventGroupCreate();
+#endif
+    if (NULL == handle->txEvent)
+    {
+        vSemaphoreDelete(handle->rxSemaphore);
+        vSemaphoreDelete(handle->txSemaphore);
+        return kStatus_Fail;
+    }
+#if (configSUPPORT_STATIC_ALLOCATION == 1)
+    handle->rxEvent = xEventGroupCreateStatic(&handle->rxEventBuffer);
+#else
+    handle->rxEvent     = xEventGroupCreate();
+#endif
+    if (NULL == handle->rxEvent)
+    {
+        vEventGroupDelete(handle->txEvent);
+        vSemaphoreDelete(handle->rxSemaphore);
+        vSemaphoreDelete(handle->txSemaphore);
+        return kStatus_Fail;
+    }
+
+    LPUART_GetDefaultConfig(&defcfg);
+
+    defcfg.baudRate_Bps = cfg->baudrate;
+    defcfg.parityMode   = cfg->parity;
+    defcfg.stopBitCount = cfg->stopbits;
+#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+    defcfg.enableRxRTS = cfg->enableRxRTS;
+    defcfg.enableTxCTS = cfg->enableTxCTS;
+    defcfg.txCtsSource = cfg->txCtsSource;
+    defcfg.txCtsConfig = cfg->txCtsConfig;
+#endif
+    status = LPUART_Init(handle->base, &defcfg, cfg->srcclk);
+    if (status != kStatus_Success)
+    {
+        vEventGroupDelete(handle->rxEvent);
+        vEventGroupDelete(handle->txEvent);
+        vSemaphoreDelete(handle->rxSemaphore);
+        vSemaphoreDelete(handle->txSemaphore);
+        return kStatus_Fail;
+    }
+    LPUART_TransferCreateHandle(handle->base, handle->t_state, LPUART_RTOS_Callback, handle);
+    LPUART_TransferStartRingBuffer(handle->base, handle->t_state, cfg->buffer, cfg->buffer_size);
+
+    LPUART_EnableTx(handle->base, true);
+    LPUART_EnableRx(handle->base, true);
+
+    return kStatus_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_RTOS_Deinit
+ * Description   : Deinitializes the LPUART instance and frees resources
+ *
+ *END**************************************************************************/
+/*!
+ * brief Deinitializes an LPUART instance for operation.
+ *
+ * This function deinitializes the LPUART module, sets all register value to the reset value,
+ * and releases the resources.
+ *
+ * param handle The RTOS LPUART handle.
+ */
+int LPUART_RTOS_Deinit(lpuart_rtos_handle_t *handle)
+{
+    LPUART_Deinit(handle->base);
+
+    vEventGroupDelete(handle->txEvent);
+    vEventGroupDelete(handle->rxEvent);
+
+    /* Give the semaphore. This is for functional safety */
+    (void)xSemaphoreGive(handle->txSemaphore);
+    (void)xSemaphoreGive(handle->rxSemaphore);
+
+    vSemaphoreDelete(handle->txSemaphore);
+    vSemaphoreDelete(handle->rxSemaphore);
+
+    /* Invalidate the handle */
+    handle->base    = NULL;
+    handle->t_state = NULL;
+
+    return 0;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : UART_RTOS_Send
+ * Description   : Send chars over LPUART
+ *
+ *END**************************************************************************/
+/*!
+ * brief Sends data in the background.
+ *
+ * This function sends data. It is an synchronous API.
+ * If the hardware buffer is full, the task is in the blocked state.
+ *
+ * param handle The RTOS LPUART handle.
+ * param buffer The pointer to buffer to send.
+ * param length The number of bytes to send.
+ */
+int LPUART_RTOS_Send(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length)
+{
+    EventBits_t ev;
+    int retval = kStatus_Fail;
+    status_t status;
+    const TickType_t txTickTimeout =
+        (length * handle->tx_timeout_multiplier_ms + handle->tx_timeout_constant_ms) / portTICK_PERIOD_MS;
+
+    if (NULL == handle->base)
+    {
+        /* Invalid handle. */
+        return kStatus_Fail;
+    }
+    if (0u == length)
+    {
+        return kStatus_Success;
+    }
+    if (NULL == buffer)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (pdFALSE == xSemaphoreTake(handle->txSemaphore, 0u))
+    {
+        /* We could not take the semaphore, exit with 0 data received */
+        return kStatus_Fail;
+    }
+
+    handle->txTransfer.data     = (uint8_t *)buffer;
+    handle->txTransfer.dataSize = (uint32_t)length;
+
+    /* Non-blocking call */
+    status = LPUART_TransferSendNonBlocking(handle->base, handle->t_state, &handle->txTransfer);
+    if (status != kStatus_Success)
+    {
+        (void)xSemaphoreGive(handle->txSemaphore);
+        return kStatus_Fail;
+    }
+
+    ev = xEventGroupWaitBits(handle->txEvent, RTOS_LPUART_TX_COMPLETE, pdTRUE, pdFALSE,
+                             (txTickTimeout > 0u) ? txTickTimeout : portMAX_DELAY);
+    if ((ev & RTOS_LPUART_TX_COMPLETE) != 0u)
+    {
+        retval = kStatus_Success;
+    }
+    else /* timeout expired or unknown error*/
+    {
+        if (txTickTimeout > 0u)
+        {
+            LPUART_TransferAbortSend(handle->base, handle->t_state);
+            (void)xEventGroupClearBits(handle->txEvent, RTOS_LPUART_TX_COMPLETE);
+            retval = kStatus_Timeout;
+        }
+        else
+        {
+            retval = kStatus_Fail;
+        }
+    }
+
+    if (pdFALSE == xSemaphoreGive(handle->txSemaphore))
+    {
+        /* We could not post the semaphore, exit with error */
+        retval = kStatus_Fail;
+    }
+
+    return retval;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_RTOS_Receive
+ * Description   : Receives chars from LPUART
+ *
+ *END**************************************************************************/
+/*!
+ * brief Receives data.
+ *
+ * This function receives data from LPUART. It is an synchronous API. If any data is immediately available
+ * it is returned immediately and the number of bytes received.
+ *
+ * param handle The RTOS LPUART handle.
+ * param buffer The pointer to buffer where to write received data.
+ * param length The number of bytes to receive.
+ * param received The pointer to a variable of size_t where the number of received data is filled.
+ */
+int LPUART_RTOS_Receive(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received)
+{
+    EventBits_t ev;
+    size_t n                = 0u;
+    int retval              = kStatus_Fail;
+    uint32_t local_received = 0u;
+    status_t status;
+    const TickType_t rxTickTimeout =
+        (length * handle->rx_timeout_multiplier_ms + handle->rx_timeout_constant_ms) / portTICK_PERIOD_MS;
+
+    if (NULL == handle->base)
+    {
+        /* Invalid handle. */
+        return kStatus_Fail;
+    }
+    if (0u == length)
+    {
+        if (received != NULL)
+        {
+            *received = n;
+        }
+        return kStatus_Success;
+    }
+    if (NULL == buffer)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* New transfer can be performed only after current one is finished */
+    if (pdFALSE == xSemaphoreTake(handle->rxSemaphore, portMAX_DELAY))
+    {
+        /* We could not take the semaphore, exit with 0 data received */
+        return kStatus_Fail;
+    }
+
+    handle->rxTransfer.data     = buffer;
+    handle->rxTransfer.dataSize = (uint32_t)length;
+
+    /* Non-blocking call */
+    status = LPUART_TransferReceiveNonBlocking(handle->base, handle->t_state, &handle->rxTransfer, &n);
+    if (status != kStatus_Success)
+    {
+        (void)xSemaphoreGive(handle->rxSemaphore);
+        return kStatus_Fail;
+    }
+
+    ev = xEventGroupWaitBits(
+        handle->rxEvent,
+        RTOS_LPUART_RX_COMPLETE | RTOS_LPUART_RING_BUFFER_OVERRUN | RTOS_LPUART_HARDWARE_BUFFER_OVERRUN, pdTRUE,
+        pdFALSE, (rxTickTimeout > 0u) ? rxTickTimeout : portMAX_DELAY);
+    if ((ev & RTOS_LPUART_HARDWARE_BUFFER_OVERRUN) != 0u)
+    {
+        /* Stop data transfer to application buffer, ring buffer is still active */
+        LPUART_TransferAbortReceive(handle->base, handle->t_state);
+        /* Prevent false indication of successful transfer in next call of LPUART_RTOS_Receive.
+           RTOS_LPUART_COMPLETE flag could be set meanwhile overrun is handled */
+        (void)xEventGroupClearBits(handle->rxEvent, RTOS_LPUART_RX_COMPLETE);
+        retval         = kStatus_LPUART_RxHardwareOverrun;
+        local_received = 0u;
+    }
+    else if ((ev & RTOS_LPUART_RING_BUFFER_OVERRUN) != 0u)
+    {
+        /* Stop data transfer to application buffer, ring buffer is still active */
+        LPUART_TransferAbortReceive(handle->base, handle->t_state);
+        /* Prevent false indication of successful transfer in next call of LPUART_RTOS_Receive.
+           RTOS_LPUART_COMPLETE flag could be set meanwhile overrun is handled */
+        (void)xEventGroupClearBits(handle->rxEvent, RTOS_LPUART_RX_COMPLETE);
+        retval         = kStatus_LPUART_RxRingBufferOverrun;
+        local_received = 0u;
+    }
+    else if ((ev & RTOS_LPUART_RX_COMPLETE) != 0u)
+    {
+        retval         = kStatus_Success;
+        local_received = length;
+    }
+    else /* timeout expired or unknown error*/
+    {
+        if (rxTickTimeout > 0u)
+        {
+            (void)LPUART_TransferGetReceiveCount(handle->base, handle->t_state, &local_received);
+            LPUART_TransferAbortReceive(handle->base, handle->t_state);
+            (void)xEventGroupClearBits(handle->rxEvent, RTOS_LPUART_RX_COMPLETE);
+            retval = kStatus_Timeout;
+        }
+        else
+        {
+            retval         = kStatus_LPUART_Error;
+            local_received = 0u;
+        }
+    }
+
+    /* Prevent repetitive NULL check */
+    if (received != NULL)
+    {
+        *received = (size_t)local_received;
+    }
+
+    /* Enable next transfer. Current one is finished */
+    if (pdFALSE == xSemaphoreGive(handle->rxSemaphore))
+    {
+        /* We could not post the semaphore, exit with error */
+        retval = kStatus_Fail;
+    }
+    return retval;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_RTOS_SetRxTimeout
+ * Description   : Modify receive timeout value in alreaty initialized LPUART RTOS handle.
+ *
+ *END**************************************************************************/
+/*!
+ * brief Set RX timeout in runtime
+ *
+ * This function can modify RX timeout between initialization and receive.
+ *
+ * param handle The RTOS LPUART handle.
+ * param rx_timeout_constant_ms RX timeout applied per receive.
+ * param rx_timeout_multiplier_ms RX timeout added for each byte of the receive.
+ */
+int LPUART_RTOS_SetRxTimeout(lpuart_rtos_handle_t *handle,
+                             uint32_t rx_timeout_constant_ms,
+                             uint32_t rx_timeout_multiplier_ms)
+{
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+    handle->rx_timeout_constant_ms   = rx_timeout_constant_ms;
+    handle->rx_timeout_multiplier_ms = rx_timeout_multiplier_ms;
+    return kStatus_Success;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : LPUART_RTOS_SetTxTimeout
+ * Description   : Modify send timeout value in alreaty initialized LPUART RTOS handle.
+ *
+ *END**************************************************************************/
+/*!
+ * brief Set TX timeout in runtime
+ *
+ * This function can modify TX timeout between initialization and send.
+ *
+ * param handle The RTOS LPUART handle.
+ * param tx_timeout_constant_ms TX timeout applied per transmition.
+ * param tx_timeout_multiplier_ms TX timeout added for each byte of the transmition.
+ */
+int LPUART_RTOS_SetTxTimeout(lpuart_rtos_handle_t *handle,
+                             uint32_t tx_timeout_constant_ms,
+                             uint32_t tx_timeout_multiplier_ms)
+{
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+    handle->tx_timeout_constant_ms   = tx_timeout_constant_ms;
+    handle->tx_timeout_multiplier_ms = tx_timeout_multiplier_ms;
+    return kStatus_Success;
+}

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_freertos.h

@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __FSL_LPUART_RTOS_H__
+#define __FSL_LPUART_RTOS_H__
+
+#include "fsl_lpuart.h"
+#include <FreeRTOS.h>
+#include <event_groups.h>
+#include <semphr.h>
+
+/*!
+ * @addtogroup lpuart_freertos_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPUART FreeRTOS driver version. */
+#define FSL_LPUART_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 6, 0))
+/*@}*/
+
+/*! @brief LPUART RTOS configuration structure. */
+typedef struct _lpuart_rtos_config
+{
+    LPUART_Type *base;                /*!< UART base address */
+    uint32_t srcclk;                  /*!< UART source clock in Hz*/
+    uint32_t baudrate;                /*!< Desired communication speed */
+    lpuart_parity_mode_t parity;      /*!< Parity setting */
+    lpuart_stop_bit_count_t stopbits; /*!< Number of stop bits to use */
+    uint8_t *buffer;                  /*!< Buffer for background reception */
+    uint32_t buffer_size;             /*!< Size of buffer for background reception */
+    /* Zero in constant and multiplier is interpreted as infinit timeout. */
+    uint32_t rx_timeout_constant_ms;   /*!< RX timeout applied per receive */
+    uint32_t rx_timeout_multiplier_ms; /*!< RX timeout added for each byte of the receive. */
+    uint32_t tx_timeout_constant_ms;   /*!< TX timeout applied per transmition */
+    uint32_t tx_timeout_multiplier_ms; /*!< TX timeout added for each byte of the transmition. */
+#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+    bool enableRxRTS;                         /*!< RX RTS enable */
+    bool enableTxCTS;                         /*!< TX CTS enable */
+    lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */
+    lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */
+#endif
+} lpuart_rtos_config_t;
+
+/*!
+ * @cond RTOS_PRIVATE
+ * @name LPUART event flags
+ *
+ * This are only valid states for txEvent and rxEvent (lpuart_rtos_handle_t).
+ */
+/*@{*/
+/*! @brief Event flag - uart transmit complete. */
+#define RTOS_LPUART_TX_COMPLETE 0x1U
+/*! @brief Event flag - uart receive complete. */
+#define RTOS_LPUART_RX_COMPLETE 0x2U
+/*! @brief Event flag - ring buffer overrun. */
+#define RTOS_LPUART_RING_BUFFER_OVERRUN 0x4U
+/*! @brief Event flag - hardware buffer overrun. */
+#define RTOS_LPUART_HARDWARE_BUFFER_OVERRUN 0x8U
+/*@}*/
+
+/*! @brief LPUART FreeRTOS transfer structure. */
+typedef struct _lpuart_rtos_handle
+{
+    LPUART_Type *base;                 /*!< UART base address */
+    lpuart_transfer_t txTransfer;      /*!< TX transfer structure */
+    lpuart_transfer_t rxTransfer;      /*!< RX transfer structure */
+    SemaphoreHandle_t rxSemaphore;     /*!< RX semaphore for resource sharing */
+    SemaphoreHandle_t txSemaphore;     /*!< TX semaphore for resource sharing */
+    EventGroupHandle_t rxEvent;        /*!< RX completion event */
+    EventGroupHandle_t txEvent;        /*!< TX completion event */
+    uint32_t rx_timeout_constant_ms;   /*!< RX Timeout applied per transfer */
+    uint32_t rx_timeout_multiplier_ms; /*!< RX Timeout added for each byte of the transfer. */
+    uint32_t tx_timeout_constant_ms;   /*!< TX Timeout applied per transfer */
+    uint32_t tx_timeout_multiplier_ms; /*!< TX Timeout added for each byte of the transfer. */
+    void *t_state;                     /*!< Transactional state of the underlying driver */
+#if (configSUPPORT_STATIC_ALLOCATION == 1)
+    StaticSemaphore_t txSemaphoreBuffer; /*!< Statically allocated memory for txSemaphore */
+    StaticSemaphore_t rxSemaphoreBuffer; /*!< Statically allocated memory for rxSemaphore */
+    StaticEventGroup_t txEventBuffer;    /*!< Statically allocated memory for txEvent */
+    StaticEventGroup_t rxEventBuffer;    /*!< Statically allocated memory for rxEvent */
+#endif
+} lpuart_rtos_handle_t;
+/*! \endcond */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name LPUART RTOS Operation
+ * @{
+ */
+
+/*!
+ * @brief Initializes an LPUART instance for operation in RTOS.
+ *
+ * @param handle The RTOS LPUART handle, the pointer to an allocated space for RTOS context.
+ * @param t_handle The pointer to an allocated space to store the transactional layer internal state.
+ * @param cfg The pointer to the parameters required to configure the LPUART after initialization.
+ * @return 0 succeed, others failed
+ */
+int LPUART_RTOS_Init(lpuart_rtos_handle_t *handle, lpuart_handle_t *t_handle, const lpuart_rtos_config_t *cfg);
+
+/*!
+ * @brief Deinitializes an LPUART instance for operation.
+ *
+ * This function deinitializes the LPUART module, sets all register value to the reset value,
+ * and releases the resources.
+ *
+ * @param handle The RTOS LPUART handle.
+ */
+int LPUART_RTOS_Deinit(lpuart_rtos_handle_t *handle);
+
+/*!
+ * @name LPUART transactional Operation
+ * @{
+ */
+
+/*!
+ * @brief Sends data in the background.
+ *
+ * This function sends data. It is an synchronous API.
+ * If the hardware buffer is full, the task is in the blocked state.
+ *
+ * @param handle The RTOS LPUART handle.
+ * @param buffer The pointer to buffer to send.
+ * @param length The number of bytes to send.
+ */
+int LPUART_RTOS_Send(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length);
+
+/*!
+ * @brief Receives data.
+ *
+ * This function receives data from LPUART. It is an synchronous API. If any data is immediately available
+ * it is returned immediately and the number of bytes received.
+ *
+ * @param handle The RTOS LPUART handle.
+ * @param buffer The pointer to buffer where to write received data.
+ * @param length The number of bytes to receive.
+ * @param received The pointer to a variable of size_t where the number of received data is filled.
+ */
+int LPUART_RTOS_Receive(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received);
+
+/*!
+ * @brief Set RX timeout in runtime
+ *
+ * This function can modify RX timeout between initialization and receive.
+ *
+ * param handle The RTOS LPUART handle.
+ * param rx_timeout_constant_ms RX timeout applied per receive.
+ * param rx_timeout_multiplier_ms RX timeout added for each byte of the receive.
+ */
+int LPUART_RTOS_SetRxTimeout(lpuart_rtos_handle_t *handle,
+                             uint32_t rx_timeout_constant_ms,
+                             uint32_t rx_timeout_multiplier_ms);
+
+/*!
+ * @brief Set TX timeout in runtime
+ *
+ * This function can modify TX timeout between initialization and send.
+ *
+ * param handle The RTOS LPUART handle.
+ * param tx_timeout_constant_ms TX timeout applied per transmition.
+ * param tx_timeout_multiplier_ms TX timeout added for each byte of the transmition.
+ */
+int LPUART_RTOS_SetTxTimeout(lpuart_rtos_handle_t *handle,
+                             uint32_t tx_timeout_constant_ms,
+                             uint32_t tx_timeout_multiplier_ms);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_LPUART_RTOS_H__ */

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_nic301.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -26,8 +26,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief NIC301 driver version 2.0.0. */
-#define FSL_NIC301_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
+/*! @brief NIC301 driver version 2.0.1. */
+#define FSL_NIC301_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
 /*@}*/
 
 #define GPV0_BASE (0x41000000UL)
@@ -177,7 +177,7 @@ extern "C" {
  */
 static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value)
 {
-    *(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET) = (value & NIC_QOS_MASK);
+    *(volatile uint32_t *)(base) = (value & NIC_QOS_MASK);
     __DSB();
 }
 
@@ -189,7 +189,7 @@ static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value)
  */
 static inline nic_qos_t NIC_GetReadQos(nic_reg_t base)
 {
-    return (nic_qos_t)((*(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET)) & NIC_QOS_MASK);
+    return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK);
 }
 
 /*!
@@ -200,7 +200,7 @@ static inline nic_qos_t NIC_GetReadQos(nic_reg_t base)
  */
 static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value)
 {
-    *(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET) = (value & NIC_QOS_MASK);
+    *(volatile uint32_t *)(base) = (value & NIC_QOS_MASK);
     __DSB();
 }
 
@@ -212,7 +212,7 @@ static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value)
  */
 static inline nic_qos_t NIC_GetWriteQos(nic_reg_t base)
 {
-    return (nic_qos_t)((*(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET)) & NIC_QOS_MASK);
+    return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK);
 }
 
 /*!
@@ -223,7 +223,7 @@ static inline nic_qos_t NIC_GetWriteQos(nic_reg_t base)
  */
 static inline void NIC_SetFnModAhb(nic_reg_t base, nic_fn_mod_ahb_t v)
 {
-    *(volatile uint32_t *)(base + NIC_FN_MOD_AHB_OFFSET) = v;
+    *(volatile uint32_t *)(base) = v;
     __DSB();
 }
 
@@ -235,7 +235,7 @@ static inline void NIC_SetFnModAhb(nic_reg_t base, nic_fn_mod_ahb_t v)
  */
 static inline nic_fn_mod_ahb_t NIC_GetFnModAhb(nic_reg_t base)
 {
-    return (nic_fn_mod_ahb_t)((*(volatile uint32_t *)(base + NIC_FN_MOD_AHB_OFFSET)) & NIC_FN_MOD_AHB_MASK);
+    return (nic_fn_mod_ahb_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_AHB_MASK);
 }
 
 /*!
@@ -246,7 +246,7 @@ static inline nic_fn_mod_ahb_t NIC_GetFnModAhb(nic_reg_t base)
  */
 static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value)
 {
-    *(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET) = (value & NIC_WR_TIDEMARK_MASK);
+    *(volatile uint32_t *)(base) = (value & NIC_WR_TIDEMARK_MASK);
     __DSB();
 }
 
@@ -258,7 +258,7 @@ static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value)
  */
 static inline uint8_t NIC_GetWrTideMark(nic_reg_t base)
 {
-    return (uint8_t)((*(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET)) & NIC_WR_TIDEMARK_MASK);
+    return (uint8_t)((*(volatile uint32_t *)(base)) & NIC_WR_TIDEMARK_MASK);
 }
 
 /*!
@@ -269,7 +269,7 @@ static inline uint8_t NIC_GetWrTideMark(nic_reg_t base)
  */
 static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value)
 {
-    *(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET) = value;
+    *(volatile uint32_t *)(base) = value;
     __DSB();
 }
 
@@ -281,7 +281,7 @@ static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value)
  */
 static inline nic_fn_mod_t NIC_GetFnMod(nic_reg_t base)
 {
-    return (nic_fn_mod_t)((*(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET)) & NIC_FN_MOD_MASK);
+    return (nic_fn_mod_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_MASK);
 }
 
 /*!
@@ -292,7 +292,7 @@ static inline nic_fn_mod_t NIC_GetFnMod(nic_reg_t base)
  */
 static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value)
 {
-    *(volatile uint32_t *)(base + NIC_FN_MOD2_OFFSET) = value;
+    *(volatile uint32_t *)(base) = value;
     __DSB();
 }
 
@@ -304,7 +304,7 @@ static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value)
  */
 static inline nic_fn_mod2_t NIC_GetFnMod2(nic_reg_t base)
 {
-    return (nic_fn_mod2_t)((*(volatile uint32_t *)(base + NIC_FN_MOD2_OFFSET)) & NIC_FN_MOD2_MASK);
+    return (nic_fn_mod2_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD2_MASK);
 }
 
 #if defined(__cplusplus)

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction.h

@@ -0,0 +1,812 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_OS_ABSTRACTION_H_
+#define _FSL_OS_ABSTRACTION_H_
+
+#include "fsl_common.h"
+#include "fsl_os_abstraction_config.h"
+#include "generic_list.h"
+
+/*!
+ * @addtogroup osa_adapter
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Type for the Task Priority*/
+typedef uint16_t osa_task_priority_t;
+/*! @brief Type for a task handler */
+typedef void *osa_task_handle_t;
+/*! @brief Type for the parameter to be passed to the task at its creation */
+typedef void *osa_task_param_t;
+/*! @brief Type for task pointer. Task prototype declaration */
+typedef void (*osa_task_ptr_t)(osa_task_param_t task_param);
+/*! @brief Type for the semaphore handler */
+typedef void *osa_semaphore_handle_t;
+/*! @brief Type for the mutex handler */
+typedef void *osa_mutex_handle_t;
+/*! @brief Type for the event handler */
+typedef void *osa_event_handle_t;
+/*! @brief Type for an event flags group, bit 32 is reserved. */
+typedef uint32_t osa_event_flags_t;
+/*! @brief Message definition. */
+typedef void *osa_msg_handle_t;
+/*! @brief Type for the message queue handler */
+typedef void *osa_msgq_handle_t;
+/*! @brief Type for the Timer handler */
+typedef void *osa_timer_handle_t;
+/*! @brief Type for the Timer callback function pointer. */
+typedef void (*osa_timer_fct_ptr_t)(void const *argument);
+/*! @brief Thread Definition structure contains startup information of a thread.*/
+typedef struct osa_task_def_tag
+{
+    osa_task_ptr_t pthread; /*!< start address of thread function*/
+    uint32_t tpriority;     /*!< initial thread priority*/
+    uint32_t instances;     /*!< maximum number of instances of that thread function*/
+    uint32_t stacksize;     /*!< stack size requirements in bytes; 0 is default stack size*/
+    uint32_t *tstack;       /*!< stack pointer*/
+    void *tlink;            /*!< link pointer*/
+    uint8_t *tname;         /*!< name pointer*/
+    uint8_t useFloat;       /*!< is use float*/
+} osa_task_def_t;
+/*! @brief Thread Link Definition structure .*/
+typedef struct osa_thread_link_tag
+{
+    uint8_t link[12];                  /*!< link*/
+    osa_task_handle_t osThreadId;      /*!< thread id*/
+    osa_task_def_t *osThreadDefHandle; /*!< pointer of thread define handle*/
+    uint32_t *osThreadStackHandle;     /*!< pointer of thread stack handle*/
+} osa_thread_link_t, *osa_thread_link_handle_t;
+
+/*! @brief Definition structure contains timer parameters.*/
+typedef struct osa_time_def_tag
+{
+    osa_timer_fct_ptr_t pfCallback; /* < start address of a timer function */
+    void *argument;                 /* < argument of a timer function */
+} osa_time_def_t;
+
+/*! @brief Type for the timer definition*/
+typedef enum _osa_timer
+{
+    KOSA_TimerOnce     = 0, /*!< one-shot timer*/
+    KOSA_TimerPeriodic = 1  /*!< repeating timer*/
+} osa_timer_t;
+
+/*! @brief Defines the return status of OSA's functions */
+typedef enum _osa_status
+{
+    KOSA_StatusSuccess = kStatus_Success,                  /*!< Success */
+    KOSA_StatusError   = MAKE_STATUS(kStatusGroup_OSA, 1), /*!< Failed */
+    KOSA_StatusTimeout = MAKE_STATUS(kStatusGroup_OSA, 2), /*!< Timeout occurs while waiting */
+    KOSA_StatusIdle    = MAKE_STATUS(kStatusGroup_OSA, 3), /*!< Used for bare metal only, the wait object is not ready
+                                                                 and timeout still not occur */
+} osa_status_t;
+
+#ifdef USE_RTOS
+#undef USE_RTOS
+#endif
+
+#define USE_RTOS (1)
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#define OSA_TASK_HANDLE_SIZE (12U)
+#else
+#define OSA_TASK_HANDLE_SIZE (16U)
+#endif
+#define OSA_EVENT_HANDLE_SIZE (8U)
+#define OSA_SEM_HANDLE_SIZE   (4U)
+#define OSA_MUTEX_HANDLE_SIZE (4U)
+#define OSA_MSGQ_HANDLE_SIZE  (4U)
+#define OSA_MSG_HANDLE_SIZE   (0U)
+
+/*! @brief Priority setting for OSA. */
+#ifndef OSA_PRIORITY_IDLE
+#define OSA_PRIORITY_IDLE (6)
+#endif
+
+#ifndef OSA_PRIORITY_LOW
+#define OSA_PRIORITY_LOW (5)
+#endif
+
+#ifndef OSA_PRIORITY_BELOW_NORMAL
+#define OSA_PRIORITY_BELOW_NORMAL (4)
+#endif
+
+#ifndef OSA_PRIORITY_NORMAL
+#define OSA_PRIORITY_NORMAL (3)
+#endif
+
+#ifndef OSA_PRIORITY_ABOVE_NORMAL
+#define OSA_PRIORITY_ABOVE_NORMAL (2)
+#endif
+
+#ifndef OSA_PRIORITY_HIGH
+#define OSA_PRIORITY_HIGH (1)
+#endif
+
+#ifndef OSA_PRIORITY_REAL_TIME
+#define OSA_PRIORITY_REAL_TIME (0)
+#endif
+
+#ifndef OSA_TASK_PRIORITY_MAX
+#define OSA_TASK_PRIORITY_MAX (0)
+#endif
+
+#ifndef OSA_TASK_PRIORITY_MIN
+#define OSA_TASK_PRIORITY_MIN (15)
+#endif
+
+#define SIZE_IN_UINT32_UNITS(size) (((size) + sizeof(uint32_t) - 1) / sizeof(uint32_t))
+
+/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
+#define osaWaitForever_c ((uint32_t)(-1))
+#define osaEventFlagsAll_c ((osa_event_flags_t)(0x00FFFFFF))
+#define osThreadStackArray(name) osThread_##name##_stack
+#define osThreadStackDef(name, stacksize, instances) \
+    uint32_t osThreadStackArray(name)[SIZE_IN_UINT32_UNITS(stacksize) * (instances)];
+
+/* ==== Thread Management ==== */
+
+/* Create a Thread Definition with function, priority, and stack requirements.
+ * \param         name         name of the thread function.
+ * \param         priority     initial priority of the thread function.
+ * \param         instances    number of possible thread instances.
+ * \param         stackSz      stack size (in bytes) requirements for the thread function.
+ * \param         useFloat
+ */
+#if defined(FSL_RTOS_MQX)
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat)                                        \
+    osa_thread_link_t osThreadLink_##name[instances]                               = {0};                    \
+    osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = {                       \
+        (name),           (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \
+        (uint8_t *)#name, (useFloat)}
+#elif defined(FSL_RTOS_UCOSII)
+#if gTaskMultipleInstancesManagement_c
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat)                                        \
+    osa_thread_link_t osThreadLink_##name[instances]                               = {0};                    \
+    osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = {                       \
+        (name),           (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \
+        (uint8_t *)#name, (useFloat)}
+#else
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat)                  \
+    osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \
+        (name), (priority), (instances), (stackSz), osThreadStackArray(name), NULL, (uint8_t *)#name, (useFloat)}
+#endif
+#else
+#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat)                             \
+    osa_task_def_t os_thread_def_##name = {(name), (priority), (instances),      (stackSz), \
+                                                 NULL,   NULL,       (uint8_t *)#name, (useFloat)}
+#endif
+/* Access a Thread defintion.
+ * \param         name          name of the thread definition object.
+ */
+#define OSA_TASK(name) &os_thread_def_##name
+
+#define OSA_TASK_PROTO(name) externosa_task_def_t os_thread_def_##name
+/*  ==== Timer Management  ====
+ * Define a Timer object.
+ * \param         name          name of the timer object.
+ * \param         function      name of the timer call back function.
+ */
+
+#define OSA_TIMER_DEF(name, function) osa_time_def_t os_timer_def_##name = {(function), NULL}
+
+/* Access a Timer definition.
+ * \param         name          name of the timer object.
+ */
+#define OSA_TIMER(name) &os_timer_def_##name
+
+/* ==== Buffer Definition ==== */
+
+/*!
+ * @brief Defines the semaphore handle
+ *
+ * This macro is used to define a 4 byte aligned semaphore handle.
+ * Then use "(osa_semaphore_handle_t)name" to get the semaphore handle.
+ *
+ * The macro should be global and could be optional. You could also define semaphore handle by yourself.
+ *
+ * This is an example,
+ * @code
+ *   OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ * @endcode
+ *
+ * @param name The name string of the semaphore handle.
+ */
+#define OSA_SEMAPHORE_HANDLE_DEFINE(name) \
+    uint32_t name[(OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+/*!
+ * @brief Defines the mutex handle
+ *
+ * This macro is used to define a 4 byte aligned mutex handle.
+ * Then use "(osa_mutex_handle_t)name" to get the mutex handle.
+ *
+ * The macro should be global and could be optional. You could also define mutex handle by yourself.
+ *
+ * This is an example,
+ * @code
+ *   OSA_MUTEX_HANDLE_DEFINE(mutexHandle);
+ * @endcode
+ *
+ * @param name The name string of the mutex handle.
+ */
+#define OSA_MUTEX_HANDLE_DEFINE(name) uint32_t name[(OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+/*!
+ * @brief Defines the event handle
+ *
+ * This macro is used to define a 4 byte aligned event handle.
+ * Then use "(osa_event_handle_t)name" to get the event handle.
+ *
+ * The macro should be global and could be optional. You could also define event handle by yourself.
+ *
+ * This is an example,
+ * @code
+ *   OSA_EVENT_HANDLE_DEFINE(eventHandle);
+ * @endcode
+ *
+ * @param name The name string of the event handle.
+ */
+#define OSA_EVENT_HANDLE_DEFINE(name) uint32_t name[(OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+/*!
+ * @brief Defines the message queue handle
+ *
+ * This macro is used to define a 4 byte aligned message queue handle.
+ * Then use "(osa_msgq_handle_t)name" to get the message queue handle.
+ *
+ * The macro should be global and could be optional. You could also define message queue handle by yourself.
+ *
+ * This is an example,
+ * @code
+ *   OSA_MSGQ_HANDLE_DEFINE(msgqHandle, 3, sizeof(msgStruct));
+ * @endcode
+ *
+ * @param name The name string of the message queue handle.
+ * @param numberOfMsgs Number of messages.
+ * @param msgSize Message size.
+ *
+ */
+
+/*< Macro For FREE_RTOS*/
+#define OSA_MSGQ_HANDLE_DEFINE(name, numberOfMsgs, msgSize) \
+    uint32_t name[(OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+/*!
+ * @brief Defines the TASK handle
+ *
+ * This macro is used to define a 4 byte aligned TASK handle.
+ * Then use "(osa_task_handle_t)name" to get the TASK handle.
+ *
+ * The macro should be global and could be optional. You could also define TASK handle by yourself.
+ *
+ * This is an example,
+ * @code
+ *   OSA_TASK_HANDLE_DEFINE(taskHandle);
+ * @endcode
+ *
+ * @param name The name string of the TASK handle.
+ */
+#define OSA_TASK_HANDLE_DEFINE(name) uint32_t name[(OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)]
+
+#include "fsl_os_abstraction_rtthread.h"
+
+extern const uint8_t gUseRtos_c;
+
+/*
+ * alloc the temporary memory to store the status
+ */
+#define OSA_SR_ALLOC() uint32_t osaCurrentSr;
+/*
+ * Enter critical mode
+ */
+#define OSA_ENTER_CRITICAL() OSA_EnterCritical(&osaCurrentSr)
+/*
+ * Exit critical mode and retore the previous mode
+ */
+#define OSA_EXIT_CRITICAL() OSA_ExitCritical(osaCurrentSr)
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Reserves the requested amount of memory in bytes.
+ *
+ * The function is used to reserve the requested amount of memory in bytes and initializes it to 0.
+ *
+ * @param length Amount of bytes to reserve.
+ *
+ * @return Pointer to the reserved memory. NULL if memory can't be allocated.
+ */
+void *OSA_MemoryAllocate(uint32_t length);
+
+/*!
+ * @brief Frees the memory previously reserved.
+ *
+ * The function is used to free the memory block previously reserved.
+ *
+ * @param p Pointer to the start of the memory block previously reserved.
+ *
+ */
+void OSA_MemoryFree(void *p);
+
+/*!
+ * @brief Enter critical with nesting mode.
+ *
+ * @param sr Store current status and return to caller.
+ */
+void OSA_EnterCritical(uint32_t *sr);
+
+/*!
+ * @brief Exit critical with nesting mode.
+ *
+ * @param sr Previous status to restore.
+ */
+void OSA_ExitCritical(uint32_t sr);
+
+/*!
+ * @name Task management
+ * @{
+ */
+
+/*!
+ * @brief Creates a task.
+ *
+ * This function is used to create task based on the resources defined
+ * by the macro OSA_TASK_DEFINE.
+ *
+ * Example below shows how to use this API to create the task handle.
+ * @code
+ *   OSA_TASK_HANDLE_DEFINE(taskHandle);
+ *   OSA_TASK_DEFINE( Job1, OSA_PRIORITY_HIGH, 1, 800, 0);
+ *   OSA_TaskCreate((osa_task_handle_t)taskHandle, OSA_TASK(Job1), (osa_task_param_t)NULL);
+ * @endcode
+ *
+ * @param taskHandle Pointer to a memory space of size OSA_TASK_HANDLE_SIZE allocated by the caller, task handle.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_TASK_HANDLE_DEFINE(taskHandle);
+ * or
+ * uint32_t taskHandle[((OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param thread_def pointer to theosa_task_def_t structure which defines the task.
+ * @param task_param Pointer to be passed to the task when it is created.
+ * @retval KOSA_StatusSuccess The task is successfully created.
+ * @retval KOSA_StatusError   The task can not be created.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, osa_task_def_t *thread_def, osa_task_param_t task_param);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Gets the handler of active task.
+ *
+ * @return Handler to current active task.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_task_handle_t OSA_TaskGetCurrentHandle(void);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Puts the active task to the end of scheduler's queue.
+ *
+ * When a task calls this function, it gives up the CPU and puts itself to the
+ * end of a task ready list.
+ *
+ * @retval KOSA_StatusSuccess The function is called successfully.
+ * @retval KOSA_StatusError   Error occurs with this function.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskYield(void);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Gets the priority of a task.
+ *
+ * @param taskHandle The handler of the task whose priority is received.
+ *
+ * @return Task's priority.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Sets the priority of a task.
+ *
+ * @param taskHandle  The handler of the task whose priority is set.
+ * @param taskPriority The priority to set.
+ *
+ * @retval KOSA_StatusSuccess Task's priority is set successfully.
+ * @retval KOSA_StatusError   Task's priority can not be set.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Destroys a previously created task.
+ *
+ * @param taskHandle The handler of the task to destroy.
+ *
+ * @retval KOSA_StatusSuccess The task was successfully destroyed.
+ * @retval KOSA_StatusError   Task destruction failed or invalid parameter.
+ */
+#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle);
+#endif /* FSL_OSA_TASK_ENABLE */
+
+/*!
+ * @brief Creates a semaphore with a given value.
+ *
+ * This function creates a semaphore and sets the value to the parameter
+ * initValue.
+ *
+ * Example below shows how to use this API to create the semaphore handle.
+ * @code
+ *   OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ *   OSA_SemaphoreCreate((osa_semaphore_handle_t)semaphoreHandle, 0xff);
+ * @endcode
+ *
+ * @param semaphoreHandle Pointer to a memory space of size OSA_SEM_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle);
+ * or
+ * uint32_t semaphoreHandle[((OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param initValue Initial value the semaphore will be set to.
+ *
+ * @retval KOSA_StatusSuccess  the new semaphore if the semaphore is created successfully.
+ * @retval KOSA_StatusError   if the semaphore can not be created.
+ */
+osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue);
+
+/*!
+ * @brief Destroys a previously created semaphore.
+ *
+ * @param semaphoreHandle The semaphore handle.
+ * The macro SEMAPHORE_HANDLE_BUFFER_GET is used to get the semaphore buffer pointer,
+ * and should not be used before the macro SEMAPHORE_HANDLE_BUFFER_DEFINE is used.
+ *
+ * @retval KOSA_StatusSuccess The semaphore is successfully destroyed.
+ * @retval KOSA_StatusError   The semaphore can not be destroyed.
+ */
+osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle);
+
+/*!
+ * @brief Pending a semaphore with timeout.
+ *
+ * This function checks the semaphore's counting value. If it is positive,
+ * decreases it and returns KOSA_StatusSuccess. Otherwise, a timeout is used
+ * to wait.
+ *
+ * @param semaphoreHandle    The semaphore handle.
+ * @param millisec The maximum number of milliseconds to wait if semaphore is not
+ *                 positive. Pass osaWaitForever_c to wait indefinitely, pass 0
+ *                 will return KOSA_StatusTimeout immediately.
+ *
+ * @retval KOSA_StatusSuccess  The semaphore is received.
+ * @retval KOSA_StatusTimeout  The semaphore is not received within the specified 'timeout'.
+ * @retval KOSA_StatusError    An incorrect parameter was passed.
+ */
+osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec);
+
+/*!
+ * @brief Signals for someone waiting on the semaphore to wake up.
+ *
+ * Wakes up one task that is waiting on the semaphore. If no task is waiting, increases
+ * the semaphore's counting value.
+ *
+ * @param semaphoreHandle The semaphore handle to signal.
+ *
+ * @retval KOSA_StatusSuccess The semaphore is successfully signaled.
+ * @retval KOSA_StatusError   The object can not be signaled or invalid parameter.
+ *
+ */
+osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle);
+
+/*!
+ * @brief Create an unlocked mutex.
+ *
+ * This function creates a non-recursive mutex and sets it to unlocked status.
+ *
+ * Example below shows how to use this API to create the mutex handle.
+ * @code
+ *   OSA_MUTEX_HANDLE_DEFINE(mutexHandle);
+ *   OSA_MutexCreate((osa_mutex_handle_t)mutexHandle);
+ * @endcode
+ *
+ * @param mutexHandle       Pointer to a memory space of size OSA_MUTEX_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_MUTEX_HANDLE_DEFINE(mutexHandle);
+ * or
+ * uint32_t mutexHandle[((OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @retval KOSA_StatusSuccess  the new mutex if the mutex is created successfully.
+ * @retval KOSA_StatusError   if the mutex can not be created.
+ */
+osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle);
+
+/*!
+ * @brief Waits for a mutex and locks it.
+ *
+ * This function checks the mutex's status. If it is unlocked, locks it and returns the
+ * KOSA_StatusSuccess. Otherwise, waits for a timeout in milliseconds to lock.
+ *
+ * @param mutexHandle The mutex handle.
+ * @param millisec The maximum number of milliseconds to wait for the mutex.
+ *                 If the mutex is locked, Pass the value osaWaitForever_c will
+ *                 wait indefinitely, pass 0 will return KOSA_StatusTimeout
+ *                 immediately.
+ *
+ * @retval KOSA_StatusSuccess The mutex is locked successfully.
+ * @retval KOSA_StatusTimeout Timeout occurred.
+ * @retval KOSA_StatusError   Incorrect parameter was passed.
+ *
+ * @note This is non-recursive mutex, a task can not try to lock the mutex it has locked.
+ */
+osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec);
+
+/*!
+ * @brief Unlocks a previously locked mutex.
+ *
+ * @param mutexHandle The mutex handle.
+ *
+ * @retval KOSA_StatusSuccess The mutex is successfully unlocked.
+ * @retval KOSA_StatusError   The mutex can not be unlocked or invalid parameter.
+ */
+osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle);
+
+/*!
+ * @brief Destroys a previously created mutex.
+ *
+ * @param mutexHandle The mutex handle.
+ *
+ * @retval KOSA_StatusSuccess The mutex is successfully destroyed.
+ * @retval KOSA_StatusError   The mutex can not be destroyed.
+ *
+ */
+osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle);
+
+/*!
+ * @brief Initializes an event object with all flags cleared.
+ *
+ * This function creates an event object and set its clear mode. If autoClear
+ * is 1, when a task gets the event flags, these flags will be
+ * cleared automatically. Otherwise these flags must
+ * be cleared manually.
+ *
+ * Example below shows how to use this API to create the event handle.
+ * @code
+ *   OSA_EVENT_HANDLE_DEFINE(eventHandle);
+ *   OSA_EventCreate((osa_event_handle_t)eventHandle, 0);
+ * @endcode
+ *
+ * @param eventHandle Pointer to a memory space of size OSA_EVENT_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_EVENT_HANDLE_DEFINE(eventHandle);
+ * or
+ * uint32_t eventHandle[((OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param autoClear 1 The event is auto-clear.
+ *                  0 The event manual-clear
+ * @retval KOSA_StatusSuccess  the new event if the event is created successfully.
+ * @retval KOSA_StatusError   if the event can not be created.
+ */
+osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear);
+
+/*!
+ * @brief Sets one or more event flags.
+ *
+ * Sets specified flags of an event object.
+ *
+ * @param eventHandle     The event handle.
+ * @param flagsToSet  Flags to be set.
+ *
+ * @retval KOSA_StatusSuccess The flags were successfully set.
+ * @retval KOSA_StatusError   An incorrect parameter was passed.
+ */
+osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet);
+
+/*!
+ * @brief Clears one or more flags.
+ *
+ * Clears specified flags of an event object.
+ *
+ * @param eventHandle       The event handle.
+ * @param flagsToClear  Flags to be clear.
+ *
+ * @retval KOSA_StatusSuccess The flags were successfully cleared.
+ * @retval KOSA_StatusError   An incorrect parameter was passed.
+ */
+osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear);
+
+/*!
+ * @brief Get event's flags.
+ *
+ * Get specified flags of an event object.
+ *
+ * @param eventHandle       The event handle.
+ * The macro EVENT_HANDLE_BUFFER_GET is used to get the event buffer pointer,
+ * and should not be used before the macro EVENT_HANDLE_BUFFER_DEFINE is used.
+ * @param flagsMask         The flags user want to get are specified by this parameter.
+ * @param pFlagsOfEvent     The event flags are obtained by this parameter.
+ *
+ * @retval KOSA_StatusSuccess The event flags were successfully got.
+ * @retval KOSA_StatusError   An incorrect parameter was passed.
+ */
+osa_status_t OSA_EventGet(osa_event_handle_t eventHandle,
+                          osa_event_flags_t flagsMask,
+                          osa_event_flags_t *pFlagsOfEvent);
+
+/*!
+ * @brief Waits for specified event flags to be set.
+ *
+ * This function waits for a combination of flags to be set in an event object.
+ * Applications can wait for any/all bits to be set. Also this function could
+ * obtain the flags who wakeup the waiting task.
+ *
+ * @param eventHandle     The event handle.
+ * @param flagsToWait Flags that to wait.
+ * @param waitAll     Wait all flags or any flag to be set.
+ * @param millisec    The maximum number of milliseconds to wait for the event.
+ *                    If the wait condition is not met, pass osaWaitForever_c will
+ *                    wait indefinitely, pass 0 will return KOSA_StatusTimeout
+ *                    immediately.
+ * @param pSetFlags    Flags that wakeup the waiting task are obtained by this parameter.
+ *
+ * @retval KOSA_StatusSuccess The wait condition met and function returns successfully.
+ * @retval KOSA_StatusTimeout Has not met wait condition within timeout.
+ * @retval KOSA_StatusError   An incorrect parameter was passed.
+ *
+ * @note    Please pay attention to the flags bit width, FreeRTOS uses the most
+ *          significant 8 bis as control bits, so do not wait these bits while using
+ *          FreeRTOS.
+ *
+ */
+osa_status_t OSA_EventWait(osa_event_handle_t eventHandle,
+                           osa_event_flags_t flagsToWait,
+                           uint8_t waitAll,
+                           uint32_t millisec,
+                           osa_event_flags_t *pSetFlags);
+
+/*!
+ * @brief Destroys a previously created event object.
+ *
+ * @param eventHandle The event handle.
+ *
+ * @retval KOSA_StatusSuccess The event is successfully destroyed.
+ * @retval KOSA_StatusError   Event destruction failed.
+ */
+osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle);
+
+/*!
+ * @brief Initializes a message queue.
+ *
+ * This function  allocates memory for and initializes a message queue. Message queue elements are hardcoded as void*.
+ *
+ * Example below shows how to use this API to create the massage queue handle.
+ * @code
+ *   OSA_MSGQ_HANDLE_DEFINE(msgqHandle);
+ *   OSA_MsgQCreate((osa_msgq_handle_t)msgqHandle, 5U, sizeof(msg));
+ * @endcode
+ *
+ * @param msgqHandle    Pointer to a memory space of size #(OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize) on bare-matel
+ * and #(OSA_MSGQ_HANDLE_SIZE) on FreeRTOS allocated by the caller, message queue handle.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #OSA_MSGQ_HANDLE_DEFINE(msgqHandle);
+ * or
+ * For bm: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * For freertos: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param msgNo :number of messages the message queue should accommodate.
+ * @param msgSize :size of a single message structure.
+ *
+ * @retval KOSA_StatusSuccess Message queue successfully Create.
+ * @retval KOSA_StatusError     Message queue create failure.
+ */
+osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize);
+
+/*!
+ * @brief Puts a message at the end of the queue.
+ *
+ * This function puts a message to the end of the message queue. If the queue
+ * is full, this function returns the KOSA_StatusError;
+ *
+ * @param msgqHandle  Message Queue handler.
+ * @param pMessage Pointer to the message to be put into the queue.
+ *
+ * @retval KOSA_StatusSuccess Message successfully put into the queue.
+ * @retval KOSA_StatusError   The queue was full or an invalid parameter was passed.
+ */
+osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage);
+
+/*!
+ * @brief Reads and remove a message at the head of the queue.
+ *
+ * This function gets a message from the head of the message queue. If the
+ * queue is empty, timeout is used to wait.
+ *
+ * @param msgqHandle   Message Queue handler.
+ * @param pMessage Pointer to a memory to save the message.
+ * @param millisec The number of milliseconds to wait for a message. If the
+ *                 queue is empty, pass osaWaitForever_c will wait indefinitely,
+ *                 pass 0 will return KOSA_StatusTimeout immediately.
+ *
+ * @retval KOSA_StatusSuccess   Message successfully obtained from the queue.
+ * @retval KOSA_StatusTimeout   The queue remains empty after timeout.
+ * @retval KOSA_StatusError     Invalid parameter.
+ */
+osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec);
+
+/*!
+ * @brief Destroys a previously created queue.
+ *
+ * @param msgqHandle Message Queue handler.
+ *
+ * @retval KOSA_StatusSuccess The queue was successfully destroyed.
+ * @retval KOSA_StatusError   Message queue destruction failed.
+ */
+osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle);
+
+/*!
+ * @brief Enable all interrupts.
+ */
+void OSA_InterruptEnable(void);
+
+/*!
+ * @brief Disable all interrupts.
+ */
+void OSA_InterruptDisable(void);
+
+/*!
+ * @brief Enable all interrupts using PRIMASK.
+ */
+void OSA_EnableIRQGlobal(void);
+
+/*!
+ * @brief Disable all interrupts using PRIMASK.
+ */
+void OSA_DisableIRQGlobal(void);
+
+/*!
+ * @brief Delays execution for a number of milliseconds.
+ *
+ * @param millisec The time in milliseconds to wait.
+ */
+void OSA_TimeDelay(uint32_t millisec);
+
+/*!
+ * @brief This function gets current time in milliseconds.
+ *
+ * @retval current time in milliseconds
+ */
+uint32_t OSA_TimeGetMsec(void);
+
+/*!
+ * @brief Installs the interrupt handler.
+ *
+ * @param IRQNumber IRQ number of the interrupt.
+ * @param handler The interrupt handler to install.
+ */
+void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void));
+
+/*! @}*/
+#ifdef __cplusplus
+}
+#endif
+/*! @}*/
+#endif

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction_config.h

@@ -0,0 +1,36 @@
+/*!
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_OS_ABSTRACTION_CONFIG_H_
+#define _FSL_OS_ABSTRACTION_CONFIG_H_
+
+#ifndef gMainThreadStackSize_c
+#define gMainThreadStackSize_c 1024
+#endif
+
+#ifndef gMainThreadPriority_c
+#define gMainThreadPriority_c 1
+#endif
+
+#ifndef gTaskMultipleInstancesManagement_c
+#define gTaskMultipleInstancesManagement_c 0
+#endif
+
+/*! @brief Definition to determine whether enable OSA's TASK module. */
+#ifndef OSA_USED
+#ifndef FSL_OSA_TASK_ENABLE
+#define FSL_OSA_TASK_ENABLE 0U
+#endif
+#else
+#if defined(FSL_OSA_TASK_ENABLE)
+#undef FSL_OSA_TASK_ENABLE
+#endif
+#define FSL_OSA_TASK_ENABLE 1U
+#endif /* OSA_USED */
+
+#endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction_rtthread.c

@@ -0,0 +1,917 @@
+/*! *********************************************************************************
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2019 NXP
+ * All rights reserved.
+ *
+ *
+ * This is the source file for the OS Abstraction layer for freertos.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ********************************************************************************** */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Include
+*************************************************************************************
+********************************************************************************** */
+#include "fsl_common.h"
+#include "fsl_os_abstraction.h"
+#include "fsl_os_abstraction_rtthread.h"
+#include <string.h>
+#include "generic_list.h"
+
+/*! *********************************************************************************
+*************************************************************************************
+* Private macros
+*************************************************************************************
+********************************************************************************** */
+
+/* Weak function. */
+#if defined(__GNUC__)
+#define __WEAK_FUNC __attribute__((weak))
+#elif defined(__ICCARM__)
+#define __WEAK_FUNC __weak
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#define __WEAK_FUNC __attribute__((weak))
+#endif
+
+#define millisecToTicks(millisec) (((millisec)*configTICK_RATE_HZ + 999U) / 1000U)
+
+#ifdef DEBUG_ASSERT
+#define OS_ASSERT(condition) \
+    if (!(condition))        \
+        while (1)            \
+            ;
+#else
+#define OS_ASSERT(condition) (void)(condition);
+#endif
+
+/*! @brief Converts milliseconds to ticks*/
+#define MSEC_TO_TICK(msec) \
+    (((uint32_t)(msec) + 500uL / (uint32_t)configTICK_RATE_HZ) * (uint32_t)configTICK_RATE_HZ / 1000uL)
+#define TICKS_TO_MSEC(tick) ((uint32_t)((uint64_t)(tick)*1000uL / (uint64_t)configTICK_RATE_HZ))
+/************************************************************************************
+*************************************************************************************
+* Private type definitions
+*************************************************************************************
+************************************************************************************/
+typedef struct osa_freertos_task
+{
+    list_element_t link;
+    rt_thread_t taskHandle;
+} osa_freertos_task_t;
+
+typedef struct _osa_event_struct
+{
+    rt_event_t handle;    /* The event handle */
+    uint8_t autoClear;  /*!< Auto clear or manual clear   */
+} osa_event_struct_t;
+
+/*! @brief State structure for bm osa manager. */
+typedef struct _osa_state
+{
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+    list_label_t taskList;
+    OSA_TASK_HANDLE_DEFINE(mainTaskHandle);
+#endif
+    uint32_t basePriority;
+    int32_t basePriorityNesting;
+    uint32_t interruptDisableCount;
+} osa_state_t;
+
+/*! *********************************************************************************
+*************************************************************************************
+* Private prototypes
+*************************************************************************************
+********************************************************************************** */
+__WEAK_FUNC void main_task(void const *argument);
+__WEAK_FUNC void main_task(void const *argument)
+{
+}
+
+void startup_task(void *argument);
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public memory declarations
+*************************************************************************************
+********************************************************************************** */
+const uint8_t gUseRtos_c = USE_RTOS; // USE_RTOS = 0 for BareMetal and 1 for OS
+
+static osa_state_t s_osaState = {0};
+/*! *********************************************************************************
+*************************************************************************************
+* Private memory declarations
+*************************************************************************************
+********************************************************************************** */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public functions
+*************************************************************************************
+********************************************************************************** */
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MemoryAllocate
+ * Description   : Reserves the requested amount of memory in bytes.
+ *
+ *END**************************************************************************/
+void *OSA_MemoryAllocate(uint32_t length)
+{
+    void *p = rt_malloc(length);
+
+    if (RT_NULL != p)
+    {
+        rt_memset(p, 0, length);
+    }
+
+    return p;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MemoryFree
+ * Description   : Frees the memory previously reserved.
+ *
+ *END**************************************************************************/
+void OSA_MemoryFree(void *p)
+{
+    rt_free(p);
+}
+
+void OSA_EnterCritical(uint32_t *sr)
+{
+    if (rt_thread_self() != RT_NULL)
+        rt_enter_critical();
+}
+
+void OSA_ExitCritical(uint32_t sr)
+{
+    if (rt_thread_self() != RT_NULL)
+        rt_exit_critical();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : startup_task
+ * Description   : Wrapper over main_task..
+ *
+ *END**************************************************************************/
+void startup_task(void *argument)
+{
+    main_task(argument);
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskGetCurrentHandle
+ * Description   : This function is used to get current active task's handler.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_task_handle_t OSA_TaskGetCurrentHandle(void)
+{
+    list_element_handle_t list_element;
+    osa_freertos_task_t *ptask;
+
+    list_element = LIST_GetHead(&s_osaState.taskList);
+    while (NULL != list_element)
+    {
+        ptask = (osa_freertos_task_t *)(void *)list_element;
+        if (ptask->taskHandle == xTaskGetCurrentTaskHandle())
+        {
+            return (osa_task_handle_t)ptask;
+        }
+        list_element = LIST_GetNext(list_element);
+    }
+    return NULL;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskYield
+ * Description   : When a task calls this function, it will give up CPU and put
+ * itself to the tail of ready list.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskYield(void)
+{
+    taskYIELD();
+    return KOSA_StatusSuccess;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskGetPriority
+ * Description   : This function returns task's priority by task handler.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle)
+{
+    assert(taskHandle);
+    osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle;
+    return (osa_task_priority_t)(PRIORITY_RTOS_TO_OSA(uxTaskPriorityGet(ptask->taskHandle)));
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskSetPriority
+ * Description   : This function sets task's priority by task handler.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority)
+{
+    assert(taskHandle);
+    osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle;
+    vTaskPrioritySet((task_handler_t)ptask->taskHandle, PRIORITY_OSA_TO_RTOS(taskPriority));
+    return KOSA_StatusSuccess;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskCreate
+ * Description   : This function is used to create a task and make it ready.
+ * Param[in]     :  threadDef  - Definition of the thread.
+ *                  task_param - Parameter to pass to the new thread.
+ * Return Thread handle of the new thread, or NULL if failed.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, osa_task_def_t *thread_def, osa_task_param_t task_param)
+{
+    assert(sizeof(osa_freertos_task_t) == OSA_TASK_HANDLE_SIZE);
+    assert(taskHandle);
+    TaskHandle_t pxCreatedTask;
+    osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle;
+
+    if (xTaskCreate((TaskFunction_t)thread_def->pthread, /* pointer to the task */
+                    (char const *)thread_def->tname,     /* task name for kernel awareness debugging */
+                    (configSTACK_DEPTH_TYPE)thread_def->stacksize / sizeof(portSTACK_TYPE), /* task stack size */
+                    (task_param_t)task_param,                    /* optional task startup argument */
+                    PRIORITY_OSA_TO_RTOS(thread_def->tpriority), /* initial priority */
+                    &pxCreatedTask                               /* optional task handle to create */
+                    ) == pdPASS)
+    {
+        ptask->taskHandle = pxCreatedTask;
+        OSA_InterruptDisable();
+        (void)LIST_AddTail(&s_osaState.taskList, (list_element_handle_t) & (ptask->link));
+        OSA_InterruptEnable();
+        return KOSA_StatusSuccess;
+    }
+    return KOSA_StatusError;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TaskDestroy
+ * Description   : This function destroy a task.
+ * Param[in]     :taskHandle - Thread handle.
+ * Return KOSA_StatusSuccess if the task is destroied, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle)
+{
+    assert(taskHandle);
+    osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle;
+    osa_status_t status;
+    uint16_t oldPriority;
+    /*Change priority to avoid context switches*/
+    oldPriority = OSA_TaskGetPriority(OSA_TaskGetCurrentHandle());
+    (void)OSA_TaskSetPriority(OSA_TaskGetCurrentHandle(), OSA_PRIORITY_REAL_TIME);
+#if INCLUDE_vTaskDelete /* vTaskDelete() enabled */
+    vTaskDelete((task_handler_t)ptask->taskHandle);
+    status = KOSA_StatusSuccess;
+#else
+    status = KOSA_StatusError; /* vTaskDelete() not available */
+#endif
+    (void)OSA_TaskSetPriority(OSA_TaskGetCurrentHandle(), oldPriority);
+    OSA_InterruptDisable();
+    (void)LIST_RemoveElement(taskHandle);
+    OSA_InterruptEnable();
+    return status;
+}
+#endif
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TimeDelay
+ * Description   : This function is used to suspend the active thread for the given number of milliseconds.
+ *
+ *END**************************************************************************/
+void OSA_TimeDelay(uint32_t millisec)
+{
+    rt_thread_mdelay(millisec);
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_TimeGetMsec
+ * Description   : This function gets current time in milliseconds.
+ *
+ *END**************************************************************************/
+uint32_t OSA_TimeGetMsec(void)
+{
+    return rt_tick_get_millisecond();
+}
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphoreCreate
+ * Description   : This function is used to create a semaphore.
+ * Return         : Semaphore handle of the new semaphore, or NULL if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue)
+{
+    assert(sizeof(osa_semaphore_handle_t) == OSA_SEM_HANDLE_SIZE);
+    assert(semaphoreHandle);
+
+    union
+    {
+        rt_sem_t sem;
+        uint32_t semhandle;
+    } xSemaHandle;
+
+    xSemaHandle.sem = rt_sem_create("osa_sem", initValue, RT_IPC_FLAG_PRIO);
+    if (NULL != xSemaHandle.sem)
+    {
+        *(uint32_t *)semaphoreHandle = xSemaHandle.semhandle;
+        return KOSA_StatusSuccess;
+    }
+    return KOSA_StatusError;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphoreDestroy
+ * Description   : This function is used to destroy a semaphore.
+ * Return        : KOSA_StatusSuccess if the semaphore is destroyed successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle)
+{
+    assert(semaphoreHandle);
+    rt_sem_t sem = (rt_sem_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle);
+
+    rt_sem_delete(sem);
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphoreWait
+ * Description   : This function checks the semaphore's counting value, if it is
+ * positive, decreases it and returns KOSA_StatusSuccess, otherwise, timeout
+ * will be used for wait. The parameter timeout indicates how long should wait
+ * in milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will
+ * return KOSA_StatusTimeout immediately if semaphore is not positive.
+ * This function returns KOSA_StatusSuccess if the semaphore is received, returns
+ * KOSA_StatusTimeout if the semaphore is not received within the specified
+ * 'timeout', returns KOSA_StatusError if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec)
+{
+    int32_t timeoutTicks;
+    assert(semaphoreHandle);
+    rt_sem_t sem = (rt_sem_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle);
+
+    /* Convert timeout from millisecond to tick. */
+    if (millisec == osaWaitForever_c)
+    {
+        timeoutTicks = RT_WAITING_FOREVER;
+    }
+    else
+    {
+        timeoutTicks = rt_tick_from_millisecond(millisec);
+    }
+
+    if (RT_EOK != rt_sem_take(sem, timeoutTicks))
+    {
+        return KOSA_StatusTimeout; /* timeout */
+    }
+    else
+    {
+        return KOSA_StatusSuccess; /* semaphore taken */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_SemaphorePost
+ * Description   : This function is used to wake up one task that wating on the
+ * semaphore. If no task is waiting, increase the semaphore. The function returns
+ * KOSA_StatusSuccess if the semaphre is post successfully, otherwise returns
+ * KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle)
+{
+    assert(semaphoreHandle);
+    rt_sem_t sem   = (rt_sem_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle);
+    rt_sem_release(sem);
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexCreate
+ * Description   : This function is used to create a mutex.
+ * Return        : Mutex handle of the new mutex, or NULL if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle)
+{
+    assert(sizeof(osa_mutex_handle_t) == OSA_MUTEX_HANDLE_SIZE);
+    assert(mutexHandle);
+
+    union
+    {
+        rt_mutex_t mutex;
+        uint32_t pmutexHandle;
+    } xMutexHandle;
+
+    xMutexHandle.mutex = rt_mutex_create("osa_mutex", RT_IPC_FLAG_PRIO);
+    if (RT_NULL != xMutexHandle.mutex)
+    {
+        *(uint32_t *)mutexHandle = xMutexHandle.pmutexHandle;
+        return KOSA_StatusSuccess;
+    }
+    return KOSA_StatusError;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexLock
+ * Description   : This function checks the mutex's status, if it is unlocked,
+ * lock it and returns KOSA_StatusSuccess, otherwise, wait for the mutex.
+ * This function returns KOSA_StatusSuccess if the mutex is obtained, returns
+ * KOSA_StatusError if any errors occur during waiting. If the mutex has been
+ * locked, pass 0 as timeout will return KOSA_StatusTimeout immediately.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec)
+{
+    assert(mutexHandle);
+    int32_t timeoutTicks;
+    rt_mutex_t mutex = (rt_mutex_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle);
+
+    /* Convert timeout from millisecond to tick. */
+    if (millisec == osaWaitForever_c)
+    {
+        timeoutTicks = RT_WAITING_FOREVER;
+    }
+    else
+    {
+        timeoutTicks = rt_tick_from_millisecond(millisec);
+    }
+
+    if (RT_EOK != rt_mutex_take(mutex, timeoutTicks))
+    {
+        return KOSA_StatusTimeout; /* timeout */
+    }
+    else
+    {
+        return KOSA_StatusSuccess; /* semaphore taken */
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexUnlock
+ * Description   : This function is used to unlock a mutex.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle)
+{
+    assert(mutexHandle);
+    rt_mutex_t mutex = (rt_mutex_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle);
+    rt_mutex_release(mutex);
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MutexDestroy
+ * Description   : This function is used to destroy a mutex.
+ * Return        : KOSA_StatusSuccess if the lock object is destroyed successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle)
+{
+    assert(mutexHandle);
+    rt_mutex_t mutex = (rt_mutex_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle);
+
+    rt_mutex_delete(mutex);
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventCreate
+ * Description   : This function is used to create a event object.
+ * Return        : Event handle of the new event, or NULL if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear)
+{
+    assert(eventHandle);
+    osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+
+    pEventStruct->handle = rt_event_create("osa_event", RT_IPC_FLAG_PRIO);
+    if (RT_NULL != pEventStruct->handle)
+    {
+        pEventStruct->autoClear = autoClear;
+    }
+    else
+    {
+        return KOSA_StatusError;
+    }
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventSet
+ * Description   : Set one or more event flags of an event object.
+ * Return        : KOSA_StatusSuccess if set successfully, KOSA_StatusError if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet)
+{
+    rt_err_t result;
+    assert(eventHandle);
+    osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+
+    if (RT_NULL == pEventStruct->handle)
+    {
+        return KOSA_StatusError;
+    }
+
+    rt_event_send(pEventStruct->handle, (rt_uint32_t)flagsToSet);
+
+    (void)result;
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventClear
+ * Description   : Clear one or more event flags of an event object.
+ * Return        :KOSA_StatusSuccess if clear successfully, KOSA_StatusError if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear)
+{
+    assert(eventHandle);
+    osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+
+    if (RT_NULL == pEventStruct->handle)
+    {
+        return KOSA_StatusError;
+    }
+
+    rt_uint32_t recved;
+    rt_event_recv(pEventStruct->handle, (rt_uint32_t)flagsToClear, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, 0, &recved);
+
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventGet
+ * Description   : This function is used to get event's flags that specified by prameter
+ * flagsMask, and the flags (user specified) are obatianed by parameter pFlagsOfEvent. So
+ * you should pass the parameter 0xffffffff to specify you want to check all.
+ * Return        :KOSA_StatusSuccess if event flags were successfully got, KOSA_StatusError if failed.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventGet(osa_event_handle_t eventHandle, osa_event_flags_t flagsMask, osa_event_flags_t *pFlagsOfEvent)
+{
+    assert(eventHandle);
+    osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+    rt_uint32_t eventFlags;
+
+    if (RT_NULL == pEventStruct->handle)
+    {
+        return KOSA_StatusError;
+    }
+
+    if (RT_NULL == pFlagsOfEvent)
+    {
+        return KOSA_StatusError;
+    }
+
+    if (RT_EOK != rt_event_recv(pEventStruct->handle, (rt_uint32_t)flagsMask, RT_EVENT_FLAG_OR, 0, &eventFlags))
+    {
+        eventFlags = 0;
+    }
+
+    *pFlagsOfEvent = (osa_event_flags_t)eventFlags & flagsMask;
+
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventWait
+ * Description   : This function checks the event's status, if it meets the wait
+ * condition, return KOSA_StatusSuccess, otherwise, timeout will be used for
+ * wait. The parameter timeout indicates how long should wait in milliseconds.
+ * Pass osaWaitForever_c to wait indefinitely, pass 0 will return the value
+ * KOSA_StatusTimeout immediately if wait condition is not met. The event flags
+ * will be cleared if the event is auto clear mode. Flags that wakeup waiting
+ * task could be obtained from the parameter setFlags.
+ * This function returns KOSA_StatusSuccess if wait condition is met, returns
+ * KOSA_StatusTimeout if wait condition is not met within the specified
+ * 'timeout', returns KOSA_StatusError if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventWait(osa_event_handle_t eventHandle,
+                           osa_event_flags_t flagsToWait,
+                           uint8_t waitAll,
+                           uint32_t millisec,
+                           osa_event_flags_t *pSetFlags)
+{
+    assert(eventHandle);
+    rt_uint8_t option = 0;
+    rt_int32_t timeoutTicks;
+    rt_uint32_t flagsSave;
+    osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+
+    /* Clean FreeRTOS cotrol flags */
+    flagsToWait = flagsToWait & 0x00FFFFFFU;
+    if (RT_NULL == pEventStruct->handle)
+    {
+        return KOSA_StatusError;
+    }
+
+    /* Convert timeout from millisecond to tick. */
+    if (millisec == osaWaitForever_c)
+    {
+        timeoutTicks = RT_WAITING_FOREVER;
+    }
+    else
+    {
+        timeoutTicks = rt_tick_from_millisecond(millisec);
+    }
+
+    if (pEventStruct->autoClear != 0U)
+    {
+        option |= RT_EVENT_FLAG_CLEAR;
+    }
+    option |= waitAll ? RT_EVENT_FLAG_AND : RT_EVENT_FLAG_OR;
+
+    rt_err_t status = rt_event_recv(pEventStruct->handle, (rt_uint32_t)flagsToWait, option, timeoutTicks, &flagsSave);
+
+    flagsSave &= (rt_uint32_t)flagsToWait;
+    if (RT_NULL != pSetFlags)
+    {
+        *pSetFlags = (osa_event_flags_t)flagsSave;
+    }
+
+    if (RT_EOK != status)
+    {
+        return KOSA_StatusTimeout;
+    }
+    else
+    {
+        return KOSA_StatusSuccess;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EventDestroy
+ * Description   : This function is used to destroy a event object. Return
+ * KOSA_StatusSuccess if the event object is destroyed successfully, otherwise
+ * return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle)
+{
+    assert(eventHandle);
+    osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle;
+
+    if (RT_NULL == pEventStruct->handle)
+    {
+        return KOSA_StatusError;
+    }
+    rt_event_delete(pEventStruct->handle);
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQCreate
+ * Description   : This function is used to create a message queue.
+ * Return        : the handle to the message queue if create successfully, otherwise
+ * return NULL.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize)
+{
+    assert(sizeof(osa_msgq_handle_t) == OSA_MSGQ_HANDLE_SIZE);
+    assert(msgqHandle);
+
+    union
+    {
+        rt_mq_t msgq;
+        uint32_t pmsgqHandle;
+    } xMsgqHandle;
+
+    /* Create the message queue where the number and size is specified by msgNo and msgSize */
+    xMsgqHandle.msgq = rt_mq_create("osa_mq", msgSize, msgNo, RT_IPC_FLAG_PRIO);
+    if (RT_NULL != xMsgqHandle.msgq)
+    {
+        *(uint32_t *)msgqHandle = xMsgqHandle.pmsgqHandle;
+        return KOSA_StatusSuccess;
+    }
+    return KOSA_StatusError;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQPut
+ * Description   : This function is used to put a message to a message queue.
+ * Return         : KOSA_StatusSuccess if the message is put successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage)
+{
+    assert(msgqHandle);
+    rt_mq_t handler    = (rt_mq_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle);
+
+    if (RT_EOK == rt_mq_send(handler, pMessage, handler->msg_size))
+    {
+        return KOSA_StatusSuccess;
+    }
+    else
+    {
+        return KOSA_StatusError;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQGet
+ * Description   : This function checks the queue's status, if it is not empty,
+ * get message from it and return KOSA_StatusSuccess, otherwise, timeout will
+ * be used for wait. The parameter timeout indicates how long should wait in
+ * milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will return
+ * KOSA_StatusTimeout immediately if queue is empty.
+ * This function returns KOSA_StatusSuccess if message is got successfully,
+ * returns KOSA_StatusTimeout if message queue is empty within the specified
+ * 'timeout', returns KOSA_StatusError if any errors occur during waiting.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec)
+{
+    osa_status_t osaStatus;
+    assert(msgqHandle);
+    rt_mq_t handler = (rt_mq_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle);
+
+    int32_t timeoutTicks;
+
+    if (millisec == osaWaitForever_c)
+    {
+        timeoutTicks = RT_WAITING_FOREVER;
+    }
+    else
+    {
+        timeoutTicks = rt_tick_from_millisecond(millisec);
+    }
+    if (RT_EOK != rt_mq_recv(handler, pMessage, handler->msg_size, timeoutTicks))
+    {
+        osaStatus = KOSA_StatusTimeout; /* not able to send it to the queue? */
+    }
+    else
+    {
+        osaStatus = KOSA_StatusSuccess;
+    }
+    return osaStatus;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_MsgQDestroy
+ * Description   : This function is used to destroy the message queue.
+ * Return        : KOSA_StatusSuccess if the message queue is destroyed successfully, otherwise return KOSA_StatusError.
+ *
+ *END**************************************************************************/
+osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle)
+{
+    assert(msgqHandle);
+    rt_mq_t handler = (rt_mq_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle);
+
+    rt_mq_delete(handler);
+    return KOSA_StatusSuccess;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_InterruptEnable
+ * Description   : self explanatory.
+ *
+ *END**************************************************************************/
+void OSA_InterruptEnable(void)
+{
+    rt_exit_critical();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_InterruptDisable
+ * Description   : self explanatory.
+ *
+ *END**************************************************************************/
+void OSA_InterruptDisable(void)
+{
+    rt_enter_critical();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_EnableIRQGlobal
+ * Description   : enable interrupts using PRIMASK register.
+ *
+ *END**************************************************************************/
+void OSA_EnableIRQGlobal(void)
+{
+    if (s_osaState.interruptDisableCount > 0U)
+    {
+        s_osaState.interruptDisableCount--;
+
+        if (0U == s_osaState.interruptDisableCount)
+        {
+            __enable_irq();
+        }
+        /* call core API to enable the global interrupt*/
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_DisableIRQGlobal
+ * Description   : disable interrupts using PRIMASK register.
+ *
+ *END**************************************************************************/
+void OSA_DisableIRQGlobal(void)
+{
+    /* call core API to disable the global interrupt*/
+    __disable_irq();
+
+    /* update counter*/
+    s_osaState.interruptDisableCount++;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : OSA_InstallIntHandler
+ * Description   : This function is used to install interrupt handler.
+ *
+ *END**************************************************************************/
+void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void))
+{
+#if defined(__IAR_SYSTEMS_ICC__)
+    _Pragma("diag_suppress = Pm138")
+#endif
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+        (void) InstallIRQHandler((IRQn_Type)IRQNumber, (uint32_t) * (uint32_t *)&handler);
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+#if defined(__IAR_SYSTEMS_ICC__)
+    _Pragma("diag_remark = PM138")
+#endif
+}
+
+/*!*********************************************************************************
+*************************************************************************************
+* Private functions
+*************************************************************************************
+********************************************************************************** */
+#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
+
+static OSA_TASK_DEFINE(startup_task, gMainThreadPriority_c, 1, gMainThreadStackSize_c, 0);
+
+int main(void)
+{
+    extern void BOARD_InitHardware(void);
+    /* Initialize MCU clock */
+    BOARD_InitHardware();
+    LIST_Init((&s_osaState.taskList), 0);
+
+    s_osaState.basePriorityNesting   = 0;
+    s_osaState.interruptDisableCount = 0;
+    (void)OSA_TaskCreate((osa_task_handle_t)s_osaState.mainTaskHandle, OSA_TASK(startup_task), NULL);
+
+    vTaskStartScheduler();
+    return 0;
+}
+#endif /* FSL_OSA_TASK_ENABLE */

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction_rtthread.h

@@ -0,0 +1,130 @@
+/*! *********************************************************************************
+ * Copyright (c) 2013-2014, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * ile
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ********************************************************************************** */
+#if !defined(__FSL_OS_ABSTRACTION_RTTHREAD_H__)
+#define __FSL_OS_ABSTRACTION_RTTHREAD_H__
+
+#if defined(__IAR_SYSTEMS_ICC__)
+/**
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ */
+// http://supp.iar.com/Support/?note=24725
+
+#define MISRAC_DISABLE \
+    _Pragma(           \
+        "diag_suppress=                       \
+    Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
+    Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
+    Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
+    Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
+    Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
+    Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
+    Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
+    Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
+    Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
+    Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
+    Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
+    Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
+    Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
+    Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
+    Pm155")
+
+#define MISRAC_ENABLE \
+    _Pragma(          \
+        "diag_default=                         \
+    Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
+    Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
+    Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
+    Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
+    Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
+    Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
+    Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
+    Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
+    Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
+    Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
+    Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
+    Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
+    Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
+    Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
+    Pm155")
+#else
+/* Empty MISRA C macros for other toolchains. */
+#define MISRAC_DISABLE
+#define MISRAC_ENABLE
+#endif
+
+MISRAC_DISABLE
+#include <rtthread.h>
+MISRAC_ENABLE
+
+/*!
+ * @addtogroup os_abstraction_free_rtos
+ * @{
+ */
+
+/*******************************************************************************
+ * Declarations
+ ******************************************************************************/
+/*! @brief Type for a task handler, returned by the OSA_TaskCreate function. */
+typedef rt_thread_t task_handler_t;
+
+/*! @brief Type for a task stack.*/
+typedef rt_uint32_t task_stack_t;
+
+/*! @brief Type for task parameter */
+typedef void *task_param_t;
+
+/*! @brief Type for an event flags object.*/
+typedef rt_uint32_t event_flags_t;
+
+/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
+#define OSA_WAIT_FOREVER 0xFFFFFFFFU
+
+/*! @brief OSA's time range in millisecond, OSA time wraps if exceeds this value. */
+#define FSL_OSA_TIME_RANGE 0xFFFFFFFFU
+
+/*! @brief The default interrupt handler installed in vector table. */
+#define OSA_DEFAULT_INT_HANDLER ((osa_int_handler_t)(&DefaultISR))
+
+extern void DefaultISR(void);
+
+/*!
+ * @name Thread management
+ * @{
+ */
+
+/*!
+ * @brief To provide unified task piority for upper layer, OSA layer makes conversion.
+ */
+#define PRIORITY_OSA_TO_RTOS(osa_prio)  ((UBaseType_t)configMAX_PRIORITIES - (osa_prio)-2U)
+#define PRIORITY_RTOS_TO_OSA(rtos_prio) ((UBaseType_t)configMAX_PRIORITIES - (rtos_prio)-2U)
+
+/* @}*/
+
+/*!
+ * @name Message queues
+ * @{
+ */
+
+/*!
+ * @brief This macro statically reserves the memory required for the queue.
+ *
+ * @param name Identifier for the memory region.
+ * @param number Number of elements in the queue.
+ * @param size Size of every elements in words.
+ */
+#define MSG_QUEUE_DECLARE(name, number, size) msg_queue_t *name = NULL
+
+/* @}*/
+
+/*! @}*/
+/*! @}*/
+/*! @}*/
+
+#endif // __FSL_OS_ABSTRACTION_RTTHREAD_H__

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_pxp.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2017-2021 NXP
+ * Copyright 2017-2022 NXP
  * All rights reserved.
  *
  *
@@ -48,6 +48,30 @@
 #define PXP_ADDR_CPU_2_IP(addr) (addr)
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
 
+#if !(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL)
+#define S1_COLOR_MODE           PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE
+#define S1_ALPHA_MODE           PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE
+#define S1_GLOBAL_ALPHA_MODE    PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE
+#define S1_S0_FACTOR_MODE       PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE
+#define S0_COLOR_MODE           PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE
+#define S0_ALPHA_MODE           PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE
+#define S0_GLOBAL_ALPHA_MODE    PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE
+#define S0_S1_FACTOR_MODE       PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE
+#define PORTER_DUFF_ENABLE_MASK PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK
+#endif /* FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL */
+
+#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
+#define S1_COLOR_MODE           PXP_ALPHA_A_CTRL_S1_COLOR_MODE
+#define S1_ALPHA_MODE           PXP_ALPHA_A_CTRL_S1_ALPHA_MODE
+#define S1_GLOBAL_ALPHA_MODE    PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE
+#define S1_S0_FACTOR_MODE       PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE
+#define S0_COLOR_MODE           PXP_ALPHA_A_CTRL_S0_COLOR_MODE
+#define S0_ALPHA_MODE           PXP_ALPHA_A_CTRL_S0_ALPHA_MODE
+#define S0_GLOBAL_ALPHA_MODE    PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE
+#define S0_S1_FACTOR_MODE       PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE
+#define PORTER_DUFF_ENABLE_MASK PXP_ALPHA_A_CTRL_PORTER_DUFF_ENABLE_MASK
+#endif /* FSL_FEATURE_PXP_V3 */
+
 typedef union _u32_f32
 {
     float f32;
@@ -168,17 +192,17 @@ static uint32_t PXP_GetInstance(PXP_Type *base)
 static uint32_t PXP_ConvertFloat(float floatValue, uint8_t intBits, uint8_t fracBits)
 {
     /* One bit reserved for sign bit. */
-    assert(intBits + fracBits < 32);
+    assert(intBits + fracBits < 32U);
 
     u32_f32_t u32_f32;
     uint32_t ret;
 
     u32_f32.f32        = floatValue;
     uint32_t floatBits = u32_f32.u32;
-    int32_t expValue   = (int32_t)((floatBits & 0x7F800000U) >> 23U) - 127;
+    int32_t expValue   = (int32_t)((uint16_t)((floatBits & 0x7F800000UL) >> 23U)) - 127;
 
     ret = (floatBits & 0x007FFFFFU) | 0x00800000U;
-    expValue += fracBits;
+    expValue += (int32_t)fracBits;
 
     if (expValue < 0)
     {
@@ -188,17 +212,17 @@ static uint32_t PXP_ConvertFloat(float floatValue, uint8_t intBits, uint8_t frac
     {
         /* should not exceed 31-bit when left shift. */
         assert((expValue - 23) <= 7);
-        ret <<= (expValue - 23);
+        ret <<= ((uint16_t)expValue - 23U);
     }
     else
     {
-        ret >>= (23 - expValue);
+        ret >>= (23U - (uint16_t)expValue);
     }
 
     /* Set the sign bit. */
-    if (floatBits & 0x80000000U)
+    if ((floatBits & 0x80000000UL) != 0U)
     {
-        ret = ((~ret) + 1U) & ~(((uint32_t)-1) << (intBits + fracBits + 1));
+        ret = ((~ret) + 1UL) & ~(((uint32_t)-1) << ((uint32_t)intBits + (uint32_t)fracBits + 1UL));
     }
 
     return ret;
@@ -359,6 +383,32 @@ void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t
     base->AS_CTRL = reg;
 }
 
+#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
+/*!
+ * brief Set the alpha surface blending configuration for the secondary engine.
+ *
+ * param base PXP peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
+void PXP_SetAlphaSurfaceBlendSecondaryConfig(PXP_Type *base, const pxp_as_blend_secondary_config_t *config)
+{
+    assert(NULL != config);
+
+    base->ALPHA_B_CTRL_1 =
+        (base->ALPHA_B_CTRL_1 & ~(PXP_ALPHA_B_CTRL_1_ROP_MASK | PXP_ALPHA_B_CTRL_1_ROP_ENABLE_MASK)) |
+        PXP_ALPHA_B_CTRL_1_ROP((uint32_t)config->ropMode) | PXP_ALPHA_B_CTRL_1_ROP_ENABLE((uint32_t)config->ropEnable);
+
+    if (config->invertAlpha)
+    {
+        base->AS_CTRL |= PXP_AS_CTRL_ALPHA1_INVERT_MASK;
+    }
+    else
+    {
+        base->AS_CTRL &= ~PXP_AS_CTRL_ALPHA1_INVERT_MASK;
+    }
+}
+#endif /* FSL_FEATURE_PXP_V3 */
+
 /*!
  * brief Set the alpha surface position in output buffer.
  *
@@ -375,6 +425,43 @@ void PXP_SetAlphaSurfacePosition(
     base->OUT_AS_LRC = PXP_OUT_AS_LRC_Y(lowerRightY) | PXP_OUT_AS_LRC_X(lowerRightX);
 }
 
+#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
+/*!
+ * brief Set the alpha surface overlay color key.
+ *
+ * If a pixel in the current overlay image with a color that falls in the range
+ * from the p colorKeyLow to p colorKeyHigh range, it will use the process surface
+ * pixel value for that location. If no PS image is present or if the PS image also
+ * matches its colorkey range, the PS background color is used.
+ *
+ * param base PXP peripheral base address.
+ * param num instance number. 0 for alpha engine A, 1 for alpha engine B.
+ * param colorKeyLow Color key low range.
+ * param colorKeyHigh Color key high range.
+ *
+ * note Colorkey operations are higher priority than alpha or ROP operations
+ */
+void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh)
+{
+    switch (num)
+    {
+        case 0:
+            base->AS_CLRKEYLOW  = colorKeyLow;
+            base->AS_CLRKEYHIGH = colorKeyHigh;
+            break;
+
+        case 1:
+            base->AS_CLRKEYLOW_1  = colorKeyLow;
+            base->AS_CLRKEYHIGH_1 = colorKeyHigh;
+            break;
+
+        default:
+            /* Only 2 alpha process engine instances are supported. */
+            assert(false);
+            break;
+    }
+}
+#else
 /*!
  * brief Set the alpha surface overlay color key.
  *
@@ -394,6 +481,7 @@ void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t colorKeyLow, ui
     base->AS_CLRKEYLOW  = colorKeyLow;
     base->AS_CLRKEYHIGH = colorKeyHigh;
 }
+#endif /* FSL_FEATURE_PXP_V3 */
 
 /*!
  * brief Set the process surface input buffer configuration.
@@ -456,6 +544,39 @@ void PXP_SetProcessSurfacePosition(
     base->OUT_PS_LRC = PXP_OUT_PS_LRC_Y(lowerRightY) | PXP_OUT_PS_LRC_X(lowerRightX);
 }
 
+#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
+/*!
+ * brief Set the process surface color key.
+ *
+ * If the PS image matches colorkey range, the PS background color is output. Set
+ * p colorKeyLow to 0xFFFFFFFF and p colorKeyHigh to 0 will disable the colorkeying.
+ *
+ * param base PXP peripheral base address.
+ * param num instance number. 0 for alpha engine A, 1 for alpha engine B.
+ * param colorKeyLow Color key low range.
+ * param colorKeyHigh Color key high range.
+ */
+void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh)
+{
+    switch (num)
+    {
+        case 0:
+            base->PS_CLRKEYLOW  = colorKeyLow;
+            base->PS_CLRKEYHIGH = colorKeyHigh;
+            break;
+
+        case 1:
+            base->PS_CLRKEYLOW_1  = colorKeyLow;
+            base->PS_CLRKEYHIGH_1 = colorKeyHigh;
+            break;
+
+        default:
+            /* Only 2 alpha process engine instances are supported. */
+            assert(false);
+            break;
+    }
+}
+#else
 /*!
  * brief Set the process surface color key.
  *
@@ -471,6 +592,7 @@ void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_
     base->PS_CLRKEYLOW  = colorKeyLow;
     base->PS_CLRKEYHIGH = colorKeyHigh;
 }
+#endif /* FSL_FEATURE_PXP_V3 */
 
 /*!
  * brief Set the PXP outpt buffer configuration.
@@ -496,9 +618,101 @@ void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t
  * otherwise the dither engine could not work.
  */
 #if defined(PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK)
-    base->DITHER_STORE_SIZE_CH0 = PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(config->width - 1U) |
-                                  PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(config->height - 1U);
+    base->DITHER_STORE_SIZE_CH0 = PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH((uint32_t)config->width - 1U) |
+                                  PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT((uint32_t)config->height - 1U);
+#endif
+}
+
+/*!
+ * brief Build a solid rectangle of given pixel value.
+ *
+ * param base PXP peripheral base address.
+ * param outFormat output pixel format.
+ * param value The value of the pixel to be filled in the rectangle in ARGB8888 format.
+ * param width width of the rectangle.
+ * param height height of the rectangle.
+ * param pitch output pitch in byte.
+ * param outAddr address of the memory to store the rectangle.
+ */
+void PXP_BuildRect(PXP_Type *base,
+                   pxp_output_pixel_format_t outFormat,
+                   uint32_t value,
+                   uint16_t width,
+                   uint16_t height,
+                   uint16_t pitch,
+                   uint32_t outAddr)
+{
+    /* Only support RGB format output. */
+    assert((uint8_t)outFormat <= (uint8_t)kPXP_OutputPixelFormatRGB565);
+
+    /* PS configuration */
+#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
+    PXP_SetProcessSurfaceBackGroundColor(base, 0U, value);
+#else
+    PXP_SetProcessSurfaceBackGroundColor(base, value);
+#endif
+    PXP_SetProcessSurfacePosition(base, 0xFFFF, 0xFFFF, 0, 0);
+
+    if ((outFormat == kPXP_OutputPixelFormatARGB8888) || (outFormat == kPXP_OutputPixelFormatARGB1555) ||
+        (outFormat == kPXP_OutputPixelFormatARGB4444))
+    {
+        uint8_t alpha                         = (uint8_t)(value >> 24U);
+        pxp_as_buffer_config_t asBufferConfig = {
+            .pixelFormat = kPXP_AsPixelFormatARGB8888,
+            .bufferAddr  = outAddr,
+            .pitchBytes  = pitch,
+        };
+        PXP_SetAlphaSurfaceBufferConfig(base, &asBufferConfig);
+
+        pxp_as_blend_config_t asBlendConfig = {
+            .alpha = alpha, .invertAlpha = false, .alphaMode = kPXP_AlphaOverride, .ropMode = kPXP_RopMergeAs};
+        PXP_SetAlphaSurfaceBlendConfig(base, &asBlendConfig);
+#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
+        PXP_SetAlphaSurfaceOverlayColorKey(base, 0U, 0U, 0xFFFFFFFFUL);
+        PXP_EnableAlphaSurfaceOverlayColorKey(base, 0U, true);
+#else
+        PXP_SetAlphaSurfaceOverlayColorKey(base, 0U, 0xFFFFFFFFUL);
+        PXP_EnableAlphaSurfaceOverlayColorKey(base, true);
+#endif
+        PXP_SetAlphaSurfacePosition(base, 0, 0, width, height);
+    }
+    else
+    {
+        /* No need to configure AS for formats that do not have alpha value. */
+        PXP_SetAlphaSurfacePosition(base, 0xFFFFU, 0xFFFFU, 0, 0);
+    }
+
+    /* Output config. */
+    pxp_output_buffer_config_t outputBufferConfig;
+    outputBufferConfig.pixelFormat    = outFormat;
+    outputBufferConfig.interlacedMode = kPXP_OutputProgressive;
+    outputBufferConfig.buffer0Addr    = outAddr;
+    outputBufferConfig.buffer1Addr    = 0U;
+    outputBufferConfig.pitchBytes     = pitch;
+    outputBufferConfig.width          = width;
+    outputBufferConfig.height         = height;
+    PXP_SetOutputBufferConfig(base, &outputBufferConfig);
+
+    PXP_EnableCsc1(base, false);
+
+#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
+    PXP_SetPath(PXP, kPXP_Mux3SelectCsc1Engine);
+    PXP_SetPath(PXP, kPXP_Mux8SelectAlphaBlending0);
+    PXP_SetPath(PXP, kPXP_Mux11SelectMux8);
+    PXP_SetPath(PXP, kPXP_Mux14SelectMux11);
+    PXP_SetPath(PXP, kPXP_Mux0SelectNone);
+    PXP_SetPath(PXP, kPXP_Mux6SelectNone);
+    PXP_SetPath(PXP, kPXP_Mux9SelectNone);
+    PXP_SetPath(PXP, kPXP_Mux12SelectNone);
 #endif
+
+    PXP_ClearStatusFlags(base, (uint32_t)kPXP_CompleteFlag);
+    /* Start PXP. */
+    PXP_Start(base);
+    /* Wait for process complete. */
+    while (0UL == ((uint32_t)kPXP_CompleteFlag & PXP_GetStatusFlags(base)))
+    {
+    }
 }
 
 /*!
@@ -547,28 +761,33 @@ void PXP_SetNextCommand(PXP_Type *base, void *commandAddr)
 void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config)
 {
     assert(NULL != config);
+    uint32_t tempReg;
 
     base->CSC2_CTRL = (base->CSC2_CTRL & ~PXP_CSC2_CTRL_CSC_MODE_MASK) | PXP_CSC2_CTRL_CSC_MODE(config->mode);
 
-    base->CSC2_COEF0 =
-        (PXP_ConvertFloat(config->A1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF0_A1_SHIFT) |
-        (PXP_ConvertFloat(config->A2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF0_A2_SHIFT);
+    tempReg =
+        (PXP_ConvertFloat(config->A1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF0_A1_SHIFT);
+    base->CSC2_COEF0 = tempReg | (PXP_ConvertFloat(config->A2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH)
+                                  << PXP_CSC2_COEF0_A2_SHIFT);
 
-    base->CSC2_COEF1 =
-        (PXP_ConvertFloat(config->A3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF1_A3_SHIFT) |
-        (PXP_ConvertFloat(config->B1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF1_B1_SHIFT);
+    tempReg =
+        (PXP_ConvertFloat(config->A3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF1_A3_SHIFT);
+    base->CSC2_COEF1 = tempReg | (PXP_ConvertFloat(config->B1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH)
+                                  << PXP_CSC2_COEF1_B1_SHIFT);
 
-    base->CSC2_COEF2 =
-        (PXP_ConvertFloat(config->B2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF2_B2_SHIFT) |
-        (PXP_ConvertFloat(config->B3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF2_B3_SHIFT);
+    tempReg =
+        (PXP_ConvertFloat(config->B2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF2_B2_SHIFT);
+    base->CSC2_COEF2 = tempReg | (PXP_ConvertFloat(config->B3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH)
+                                  << PXP_CSC2_COEF2_B3_SHIFT);
 
-    base->CSC2_COEF3 =
-        (PXP_ConvertFloat(config->C1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF3_C1_SHIFT) |
-        (PXP_ConvertFloat(config->C2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF3_C2_SHIFT);
+    tempReg =
+        (PXP_ConvertFloat(config->C1, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF3_C1_SHIFT);
+    base->CSC2_COEF3 = tempReg | (PXP_ConvertFloat(config->C2, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH)
+                                  << PXP_CSC2_COEF3_C2_SHIFT);
 
-    base->CSC2_COEF4 =
-        (PXP_ConvertFloat(config->C3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF4_C3_SHIFT) |
-        PXP_CSC2_COEF4_D1(config->D1);
+    tempReg =
+        (PXP_ConvertFloat(config->C3, PXP_CSC2_COEF_INT_WIDTH, PXP_CSC2_COEF_FRAC_WIDTH) << PXP_CSC2_COEF4_C3_SHIFT);
+    base->CSC2_COEF4 = tempReg | PXP_CSC2_COEF4_D1(config->D1);
 
     base->CSC2_COEF5 = PXP_CSC2_COEF5_D2(config->D2) | PXP_CSC2_COEF5_D3(config->D3);
 }
@@ -685,8 +904,8 @@ status_t PXP_LoadLutTable(
     else
     {
         /* Number of bytes must be divisable by 8. */
-        if ((bytesNum & 0x07U) || (bytesNum < 8U) || (lutStartAddr & 0x07U) ||
-            (bytesNum + lutStartAddr > PXP_LUT_TABLE_BYTE))
+        if (((bytesNum & 0x07U) != 0U) || (bytesNum < 8U) || ((lutStartAddr & 0x07U) != 0U) ||
+            (bytesNum + (uint32_t)lutStartAddr > PXP_LUT_TABLE_BYTE))
         {
             return kStatus_InvalidArgument;
         }
@@ -702,7 +921,7 @@ status_t PXP_LoadLutTable(
         __DSB();
 
         /* Wait for transfer completed. */
-        while (!(base->STAT & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK))
+        while (0U == (base->STAT & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK))
         {
         }
     }
@@ -723,12 +942,12 @@ status_t PXP_LoadLutTable(
  */
 void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr)
 {
-    assert((memStartAddr + bytesNum) <= PXP_INTERNAL_RAM_LUT_BYTE);
+    assert(((uint32_t)memStartAddr + bytesNum) <= (uint32_t)PXP_INTERNAL_RAM_LUT_BYTE);
 
     base->INIT_MEM_CTRL =
         PXP_INIT_MEM_CTRL_ADDR(memStartAddr) | PXP_INIT_MEM_CTRL_SELECT(ram) | PXP_INIT_MEM_CTRL_START_MASK;
 
-    while (bytesNum--)
+    while (0U != bytesNum--)
     {
         base->INIT_MEM_DATA = (uint32_t)(*data);
         data++;
@@ -773,18 +992,53 @@ void PXP_EnableDither(PXP_Type *base, bool enable)
     if (enable)
     {
         base->CTRL_SET = PXP_CTRL_ENABLE_DITHER_MASK;
-        /* Route dither output to output buffer. */
-        base->DATA_PATH_CTRL0 &= ~PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK;
     }
     else
     {
         base->CTRL_CLR = PXP_CTRL_ENABLE_DITHER_MASK;
-        /* Route MUX 12 output to output buffer. */
-        base->DATA_PATH_CTRL0 |= PXP_DATA_PATH_CTRL0_MUX14_SEL(1U);
     }
 }
 #endif /* FSL_FEATURE_PXP_HAS_DITHER */
 
+#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
+/*!
+ * brief Set the Porter Duff configuration for one of the alpha process engine.
+ *
+ * param base PXP peripheral base address.
+ * param num instance number.
+ * param config Pointer to the configuration.
+ */
+void PXP_SetPorterDuffConfig(PXP_Type *base, uint8_t num, const pxp_porter_duff_config_t *config)
+{
+    assert(NULL != config);
+
+    union
+    {
+        pxp_porter_duff_config_t pdConfigStruct;
+        uint32_t u32;
+    } pdConfig;
+
+    pdConfig.pdConfigStruct = *config;
+
+    switch (num)
+    {
+        case 0:
+            base->ALPHA_A_CTRL = pdConfig.u32;
+            break;
+
+        case 1:
+            base->ALPHA_B_CTRL = pdConfig.u32;
+            break;
+
+        default:
+            /* Only 2 alpha process engine instances are supported. */
+            assert(false);
+            break;
+    }
+}
+#endif /* FSL_FEATURE_PXP_V3 */
+
+#if !(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL)
 /*!
  * brief Set the Porter Duff configuration.
  *
@@ -805,7 +1059,10 @@ void PXP_SetPorterDuffConfig(PXP_Type *base, const pxp_porter_duff_config_t *con
 
     base->PORTER_DUFF_CTRL = pdConfig.u32;
 }
+#endif /* FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL */
 
+#if (!(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL)) || \
+    (defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3)
 /*!
  * brief Get the Porter Duff configuration by blend mode.
  *
@@ -826,64 +1083,52 @@ status_t PXP_GetPorterDuffConfig(pxp_porter_duff_blend_mode_t mode, pxp_porter_d
 
     static const uint32_t pdCtrl[] = {
         /* kPXP_PorterDuffSrc */
-        PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK |
-            PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorOne) |
-            PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero),
+        PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorOne) |
+            S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero),
 
         /* kPXP_PorterDuffAtop */
-        PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK |
-            PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorStraight) |
-            PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed),
+        PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorStraight) |
+            S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed),
 
         /* kPXP_PorterDuffOver */
-        PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK |
-            PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorOne) |
-            PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed),
+        PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorOne) |
+            S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed),
 
         /* kPXP_PorterDuffIn */
-        PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK |
-            PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorStraight) |
-            PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero),
+        PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorStraight) |
+            S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero),
 
         /* kPXP_PorterDuffOut */
-        PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK |
-            PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) |
-            PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero),
+        PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) |
+            S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero),
 
         /* kPXP_PorterDuffDst */
-        PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK |
-            PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) |
-            PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorOne),
+        PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) |
+            S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorOne),
 
         /* kPXP_PorterDuffDstAtop */
-        PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK |
-            PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) |
-            PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorStraight),
+        PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) |
+            S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorStraight),
 
         /* kPXP_PorterDuffDstOver */
-        PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK |
-            PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) |
-            PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorOne),
+        PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) |
+            S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorOne),
 
         /* kPXP_PorterDuffDstIn */
-        PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK |
-            PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) |
-            PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorStraight),
+        PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) |
+            S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorStraight),
 
         /* kPXP_PorterDuffDstOut */
-        PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK |
-            PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) |
-            PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed),
+        PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) |
+            S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed),
 
         /* kPXP_PorterDuffXor */
-        PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK |
-            PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) |
-            PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed),
+        PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorInversed) |
+            S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorInversed),
 
         /* kPXP_PorterDuffClear */
-        PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK |
-            PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) |
-            PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero),
+        PORTER_DUFF_ENABLE_MASK | S0_S1_FACTOR_MODE(kPXP_PorterDuffFactorZero) |
+            S1_S0_FACTOR_MODE(kPXP_PorterDuffFactorZero),
     };
 
     if (mode >= kPXP_PorterDuffMax)
@@ -892,12 +1137,10 @@ status_t PXP_GetPorterDuffConfig(pxp_porter_duff_blend_mode_t mode, pxp_porter_d
     }
     else
     {
-        pdConfig.u32 = pdCtrl[(uint32_t)mode] | PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(kPXP_PorterDuffLocalAlpha) |
-                       PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(kPXP_PorterDuffLocalAlpha) |
-                       PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(kPXP_PorterDuffColorWithAlpha) |
-                       PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(kPXP_PorterDuffColorWithAlpha) |
-                       PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(kPXP_PorterDuffAlphaStraight) |
-                       PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(kPXP_PorterDuffAlphaStraight);
+        pdConfig.u32 = pdCtrl[(uint32_t)mode] | S0_GLOBAL_ALPHA_MODE(kPXP_PorterDuffLocalAlpha) |
+                       S1_GLOBAL_ALPHA_MODE(kPXP_PorterDuffLocalAlpha) | S0_COLOR_MODE(kPXP_PorterDuffColorWithAlpha) |
+                       S1_COLOR_MODE(kPXP_PorterDuffColorWithAlpha) | S0_ALPHA_MODE(kPXP_PorterDuffAlphaStraight) |
+                       S1_ALPHA_MODE(kPXP_PorterDuffAlphaStraight);
 
         *config = pdConfig.pdConfigStruct;
 
@@ -906,6 +1149,7 @@ status_t PXP_GetPorterDuffConfig(pxp_porter_duff_blend_mode_t mode, pxp_porter_d
 
     return status;
 }
+#endif /* FSL_FEATURE_PXP_V3 || FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL  */
 
 static void PXP_StartRectCopy(PXP_Type *base,
                               uint32_t srcAddr,
@@ -943,7 +1187,7 @@ static void PXP_StartRectCopy(PXP_Type *base,
     PXP_SetAlphaSurfaceBufferConfig(base, &asBufferConfig);
     PXP_SetAlphaSurfacePosition(base, 0U, 0U, width - 1U, height - 1U);
 
-    /* Alpha mode set to ROP, AS OR PS*/
+    /* Alpha mode set to ROP, AS OR PS */
     const pxp_as_blend_config_t asBlendConfig = {
         .alpha = 0U, .invertAlpha = false, .alphaMode = kPXP_AlphaRop, .ropMode = kPXP_RopMergeAs};
 
@@ -1049,3 +1293,898 @@ status_t PXP_StartMemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, u
 
     return kStatus_Success;
 }
+
+/*!
+ * brief Copy continous memory.
+ *
+ * param base PXP peripheral base address.
+ * retval kStatus_Success Successfully started the copy process.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t PXP_MemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32_t size)
+{
+    uint16_t pitchBytes;
+    uint32_t height;
+    uint32_t unalignedSize;
+
+    if (0U == size)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* For 512 not aligned part, copy by CPU. */
+    unalignedSize = size % 512U;
+
+    if (0UL != unalignedSize)
+    {
+        (void)memcpy((uint8_t *)destAddr, (uint8_t *)srcAddr, unalignedSize);
+
+        destAddr += unalignedSize;
+        srcAddr += unalignedSize;
+        size -= unalignedSize;
+    }
+
+    if (0UL != size)
+    {
+        /*
+         * By default, PXP process block is 8x8. For better performance, choose
+         * width and height dividable by block size.
+         */
+        if (size < 8U * 512U)
+        {
+            height     = 8U;
+            pitchBytes = (uint16_t)(size / height);
+        }
+        else
+        {
+            pitchBytes = 512U;
+            height     = size / pitchBytes;
+        }
+
+        if (height > PXP_MAX_HEIGHT)
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        PXP_StartRectCopy(base, srcAddr, pitchBytes, destAddr, pitchBytes, pitchBytes / 4U, (uint16_t)height,
+                          kPXP_AsPixelFormatARGB8888);
+
+        while (0UL == ((uint32_t)kPXP_CompleteFlag & PXP_GetStatusFlags(base)))
+        {
+        }
+
+        PXP_ClearStatusFlags(base, (uint32_t)kPXP_CompleteFlag);
+    }
+
+    return kStatus_Success;
+}
+
+#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
+
+/*!
+ * brief Configures one channle of some block's fetch engine.
+ *
+ * Fetch engine is 64-bit input and 32-bit output per channel
+ *
+ * param base PXP peripheral base address.
+ * param name which block the fetch engine belongs to.
+ * param channel channel number.
+ * param config pointer to the configuration structure.
+ * retval kStatus_Success Successfully configured the engine.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t PXP_SetFetchEngineConfig(PXP_Type *base,
+                                  pxp_fetch_engine_name_t name,
+                                  uint8_t channel,
+                                  const pxp_fetch_engine_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Check fetch address */
+    if ((config->inputBaseAddr0 == 0U) ||
+        ((config->inputBaseAddr1 == 0U) && (config->pixelFormat == kPXP_FetchFormatYUV422_2P)))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Must enable expand when input pixel format is YUV422_2P, to combine Y and UV buffer to one output. */
+    if ((config->expandEnable == false) && (config->pixelFormat == kPXP_FetchFormatYUV422_2P))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Must enable block if flip or rotation is enabled. */
+    if ((config->fetchFormat.enableblock == false) &&
+        ((config->flipMode != kPXP_FlipDisable) || (config->rotateDegree != kPXP_Rotate0)))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Block mode cannot work in 64-bit mode */
+    if ((config->fetchFormat.enableblock == true) && (config->activeBits == kPXP_Active64Bits))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    uint32_t ctrlReg        = 0U;
+    uint32_t ulcReg         = 0U;
+    uint32_t lrcReg         = 0U;
+    uint32_t fetchSizeReg   = 0U;
+    uint32_t shiftCtrlReg   = 0U;
+    uint32_t shiftOffsetReg = 0U;
+    uint32_t shiftWidthReg  = 0U;
+    uint8_t scanlineNum     = 0U;
+
+    /* When block disabled, handshake scanline mode can only use 1 line mode where scanlineNum = 0. */
+    if (config->fetchFormat.enableblock)
+    {
+        /*  */
+        if (config->fetchFormat.blockSize16)
+        {
+            scanlineNum = 2;
+        }
+        else
+        {
+            scanlineNum = 1;
+        }
+    }
+
+    ctrlReg = PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM((uint32_t)scanlineNum) |
+              PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES(config->fetchFormat.burstLength) |
+              PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE((uint32_t)config->rotateDegree) |
+              ((uint32_t)config->flipMode << PXP_INPUT_FETCH_CTRL_CH0_HFLIP_SHIFT) |
+              PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE((uint32_t)config->wordOrder) |
+              ((uint32_t)config->interface << PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN_SHIFT) |
+              PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN((uint32_t)config->fetchFormat.enableblock) |
+              PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16((uint32_t)config->fetchFormat.blockSize16) |
+              PXP_INPUT_FETCH_CTRL_CH0_CH_EN((uint32_t)config->channelEnable);
+    ulcReg       = (((uint32_t)config->ulcY) << 16U) | (uint32_t)config->ulcX;
+    lrcReg       = (((uint32_t)config->lrcY) << 16U) | (uint32_t)config->lrcX;
+    fetchSizeReg = (((uint32_t)config->totalHeight) << 16U) | ((uint32_t)config->totalWidth);
+    shiftCtrlReg = PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP((uint32_t)config->activeBits) |
+                   PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT((uint32_t)config->pixelFormat) |
+                   PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN((uint32_t)config->expandEnable) |
+                   PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS((uint32_t)config->shiftConfig.shiftBypass);
+    if (!config->shiftConfig.shiftBypass)
+    {
+        shiftOffsetReg = (uint32_t)config->shiftConfig.component0.offset |
+                         ((uint32_t)(config->shiftConfig.component1.offset) << 8U) |
+                         ((uint32_t)(config->shiftConfig.component2.offset) << 16U) |
+                         ((uint32_t)(config->shiftConfig.component3.offset) << 24U);
+        shiftWidthReg = (uint32_t)config->shiftConfig.component0.width |
+                        ((uint32_t)(config->shiftConfig.component1.width) << 4U) |
+                        ((uint32_t)(config->shiftConfig.component2.width) << 8U) |
+                        ((uint32_t)(config->shiftConfig.component3.width) << 12U);
+    }
+
+    if (name == kPXP_FetchInput)
+    {
+        switch (channel)
+        {
+            case 0:
+                base->INPUT_FETCH_CTRL_CH0            = ctrlReg;
+                base->INPUT_FETCH_ACTIVE_SIZE_ULC_CH0 = ulcReg;
+                base->INPUT_FETCH_ACTIVE_SIZE_LRC_CH0 = lrcReg;
+                base->INPUT_FETCH_SIZE_CH0            = fetchSizeReg;
+                base->INPUT_FETCH_PITCH = (base->INPUT_FETCH_PITCH & PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_MASK) |
+                                          (uint32_t)config->pitchBytes;
+                base->INPUT_FETCH_SHIFT_CTRL_CH0 = shiftCtrlReg;
+                base->INPUT_FETCH_ADDR_0_CH0     = config->inputBaseAddr0;
+                base->INPUT_FETCH_ADDR_1_CH0     = config->inputBaseAddr1;
+                if (!config->shiftConfig.shiftBypass)
+                {
+                    base->INPUT_FETCH_SHIFT_OFFSET_CH0 = shiftOffsetReg;
+                    base->INPUT_FETCH_SHIFT_WIDTH_CH0  = shiftWidthReg;
+                }
+                break;
+
+            case 1:
+                base->INPUT_FETCH_CTRL_CH1            = ctrlReg;
+                base->INPUT_FETCH_ACTIVE_SIZE_ULC_CH1 = ulcReg;
+                base->INPUT_FETCH_ACTIVE_SIZE_LRC_CH1 = lrcReg;
+                base->INPUT_FETCH_SIZE_CH1            = fetchSizeReg;
+                base->INPUT_FETCH_PITCH = (base->INPUT_FETCH_PITCH & PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_MASK) |
+                                          ((uint32_t)config->pitchBytes << 16U);
+                base->INPUT_FETCH_SHIFT_CTRL_CH1 = shiftCtrlReg;
+                base->INPUT_FETCH_ADDR_0_CH1     = config->inputBaseAddr0;
+                base->INPUT_FETCH_ADDR_1_CH1     = config->inputBaseAddr1;
+                if (!config->shiftConfig.shiftBypass)
+                {
+                    base->INPUT_FETCH_SHIFT_OFFSET_CH1 = shiftOffsetReg;
+                    base->INPUT_FETCH_SHIFT_WIDTH_CH1  = shiftWidthReg;
+                }
+                break;
+
+            default:
+                /* Only 2 channels are supported per fetch engine. */
+                assert(false);
+                break;
+        }
+    }
+    else
+    {
+        switch (channel)
+        {
+            case 0:
+                base->DITHER_FETCH_CTRL_CH0            = ctrlReg;
+                base->DITHER_FETCH_ACTIVE_SIZE_ULC_CH0 = ulcReg;
+                base->DITHER_FETCH_ACTIVE_SIZE_LRC_CH0 = lrcReg;
+                base->DITHER_FETCH_SIZE_CH0            = fetchSizeReg;
+                base->DITHER_FETCH_PITCH = (base->INPUT_FETCH_PITCH & PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_MASK) |
+                                           (uint32_t)config->pitchBytes;
+                base->DITHER_FETCH_SHIFT_CTRL_CH0 = shiftCtrlReg;
+                base->DITHER_FETCH_ADDR_0_CH0     = config->inputBaseAddr0;
+                base->DITHER_FETCH_ADDR_1_CH0     = config->inputBaseAddr1;
+                if (!config->shiftConfig.shiftBypass)
+                {
+                    base->DITHER_FETCH_SHIFT_OFFSET_CH0 = shiftOffsetReg;
+                    base->DITHER_FETCH_SHIFT_WIDTH_CH0  = shiftWidthReg;
+                }
+                break;
+
+            case 1:
+                base->DITHER_FETCH_CTRL_CH1            = ctrlReg;
+                base->DITHER_FETCH_ACTIVE_SIZE_ULC_CH1 = ulcReg;
+                base->DITHER_FETCH_ACTIVE_SIZE_LRC_CH1 = lrcReg;
+                base->DITHER_FETCH_SIZE_CH1            = fetchSizeReg;
+                base->DITHER_FETCH_PITCH = (base->INPUT_FETCH_PITCH & PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_MASK) |
+                                           ((uint32_t)config->pitchBytes << 16U);
+                base->DITHER_FETCH_SHIFT_CTRL_CH1 = shiftCtrlReg;
+                base->DITHER_FETCH_ADDR_0_CH1     = config->inputBaseAddr0;
+                base->DITHER_FETCH_ADDR_1_CH1     = config->inputBaseAddr1;
+                if (!config->shiftConfig.shiftBypass)
+                {
+                    base->DITHER_FETCH_SHIFT_OFFSET_CH1 = shiftOffsetReg;
+                    base->DITHER_FETCH_SHIFT_WIDTH_CH1  = shiftWidthReg;
+                }
+                break;
+
+            default:
+                /* Only 2 channels are supported per fetch engine. */
+                assert(false);
+                break;
+        }
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configures one channel of some block's store engine.
+ *
+ * Store engine is 32-bit input and 64-bit output per channel.
+ * note: If there is only one channel used for data input, channel 0 must be used rather than channel 1.
+ *
+ * param base PXP peripheral base address.
+ * param name the store engine belongs to which block.
+ * param channel channel number.
+ * param config pointer to the configuration structure.
+ * retval kStatus_Success Successfully configured the engine.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t PXP_SetStoreEngineConfig(PXP_Type *base,
+                                  pxp_store_engine_name_t name,
+                                  uint8_t channel,
+                                  const pxp_store_engine_config_t *config)
+{
+    assert(NULL != config);
+    /* Can only choose one plane for YUV422_2p for one channel output */
+    if ((uint32_t)config->yuvMode == 0x3U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Block mode cannot work in 64-bit mode or YUV422_2p mode */
+    if ((config->storeFormat.enableblock == true) &&
+        ((config->activeBits == kPXP_Active64Bits) || (config->yuvMode != kPXP_StoreYUVDisable)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* When block mode is disabled the interface array size can only be 1. TODO. The availiable fetch engine now are
+       only input&fetch that can only use handshake 1x1, no need to check */
+    // if ((config->storeFormat.enableblock == false) && (config->arraySize != kPXP_StoreHandshake1x1))
+    // {
+    //     return kStatus_InvalidArgument;
+    // }
+
+    uint32_t ctrlReg               = 0U;
+    uint32_t shiftCtrlReg          = 0U;
+    uint32_t sizeReg               = 0U;
+    uint32_t dataShiftMaskRegAddr  = 0U;
+    uint32_t dataShiftWidthRegAddr = 0U;
+    uint32_t flagShiftMaskRegAddr  = 0U;
+    uint32_t flagShiftWidthRegAddr = 0U;
+
+    ctrlReg = PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES((uint32_t)config->storeFormat.burstLength) |
+              PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN((uint32_t)config->useFixedData) |
+              PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL((uint32_t)config->packInSelect) |
+              ((uint32_t)config->interface << PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT) |
+              // PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM((uint32_t)config->arraySize) |
+              PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM(0U) |
+              PXP_INPUT_STORE_CTRL_CH0_BLOCK_16((uint32_t)config->storeFormat.enableblock) |
+              PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN((uint32_t)config->storeFormat.blockSize16) |
+              PXP_INPUT_STORE_CTRL_CH0_CH_EN((uint32_t)config->channelEnable);
+    shiftCtrlReg = PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS((uint32_t)config->shiftConfig.shiftBypass) |
+                   ((uint32_t)config->yuvMode << PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT) |
+                   PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP((uint32_t)config->activeBits);
+    sizeReg = (((uint32_t)config->totalHeight) << 16U) | ((uint32_t)config->totalWidth);
+
+    if (name == kPXP_StoreInput)
+    {
+        switch (channel)
+        {
+            case 0:
+                base->INPUT_STORE_CTRL_CH0 = ctrlReg;
+                base->INPUT_STORE_SIZE_CH0 = sizeReg;
+                base->INPUT_STORE_PITCH    = (base->INPUT_STORE_PITCH & PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_MASK) |
+                                          (uint32_t)(config->pitchBytes);
+                base->INPUT_STORE_SHIFT_CTRL_CH0 = shiftCtrlReg;
+                base->INPUT_STORE_ADDR_0_CH0     = config->outputBaseAddr0;
+                base->INPUT_STORE_ADDR_1_CH0     = config->outputBaseAddr1;
+                base->INPUT_STORE_FILL_DATA_CH0  = config->fixedData;
+                dataShiftMaskRegAddr             = (uint32_t) & (base->INPUT_STORE_D_MASK0_H_CH0);
+                dataShiftWidthRegAddr            = (uint32_t) & (base->INPUT_STORE_D_SHIFT_L_CH0);
+                flagShiftMaskRegAddr             = (uint32_t) & (base->INPUT_STORE_F_MASK_L_CH0);
+                flagShiftWidthRegAddr            = (uint32_t) & (base->INPUT_STORE_F_SHIFT_L_CH0);
+                break;
+
+            case 1:
+                base->INPUT_STORE_CTRL_CH1 = ctrlReg;
+                base->INPUT_STORE_SIZE_CH1 = sizeReg;
+                base->INPUT_STORE_PITCH    = (base->INPUT_STORE_PITCH & PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_MASK) |
+                                          ((uint32_t)(config->pitchBytes) << 16U);
+                base->INPUT_STORE_SHIFT_CTRL_CH1 = shiftCtrlReg;
+                base->INPUT_STORE_ADDR_0_CH1     = config->outputBaseAddr0;
+                base->INPUT_STORE_ADDR_1_CH1     = config->outputBaseAddr1;
+                dataShiftMaskRegAddr             = (uint32_t) & (base->INPUT_STORE_D_MASK0_H_CH0);
+                dataShiftWidthRegAddr            = (uint32_t) & (base->INPUT_STORE_D_SHIFT_L_CH0);
+                flagShiftMaskRegAddr             = (uint32_t) & (base->INPUT_STORE_F_MASK_L_CH0);
+                flagShiftWidthRegAddr            = (uint32_t) & (base->INPUT_STORE_F_SHIFT_L_CH0);
+                break;
+
+            default:
+                /* Only 2 channels are supported per fetch engine. */
+                assert(false);
+                break;
+        }
+    }
+    else
+    {
+        switch (channel)
+        {
+            case 0:
+                base->DITHER_STORE_CTRL_CH0 = ctrlReg;
+                base->DITHER_STORE_SIZE_CH0 = sizeReg;
+                base->DITHER_STORE_PITCH    = (base->DITHER_STORE_PITCH & PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_MASK) |
+                                           (uint32_t)(config->pitchBytes);
+                base->DITHER_STORE_SHIFT_CTRL_CH0 = shiftCtrlReg;
+                base->DITHER_STORE_ADDR_0_CH0     = config->outputBaseAddr0;
+                base->DITHER_STORE_ADDR_1_CH0     = config->outputBaseAddr1;
+                base->DITHER_STORE_FILL_DATA_CH0  = config->fixedData;
+                dataShiftMaskRegAddr              = (uint32_t) & (base->DITHER_STORE_D_MASK0_H_CH0);
+                dataShiftWidthRegAddr             = (uint32_t) & (base->DITHER_STORE_D_SHIFT_L_CH0);
+                flagShiftMaskRegAddr              = (uint32_t) & (base->DITHER_STORE_F_MASK_L_CH0);
+                flagShiftWidthRegAddr             = (uint32_t) & (base->DITHER_STORE_F_SHIFT_L_CH0);
+                break;
+
+            case 1:
+                base->DITHER_STORE_CTRL_CH1 = ctrlReg;
+                base->DITHER_STORE_SIZE_CH1 = sizeReg;
+                base->DITHER_STORE_PITCH    = (base->DITHER_STORE_PITCH & PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_MASK) |
+                                           ((uint32_t)(config->pitchBytes) << 16U);
+                base->DITHER_STORE_SHIFT_CTRL_CH1 = shiftCtrlReg;
+                base->DITHER_STORE_ADDR_0_CH1     = config->outputBaseAddr0;
+                base->DITHER_STORE_ADDR_1_CH1     = config->outputBaseAddr1;
+                dataShiftMaskRegAddr              = (uint32_t) & (base->DITHER_STORE_D_MASK0_H_CH0);
+                dataShiftWidthRegAddr             = (uint32_t) & (base->DITHER_STORE_D_SHIFT_L_CH0);
+                flagShiftMaskRegAddr              = (uint32_t) & (base->DITHER_STORE_F_MASK_L_CH0);
+                flagShiftWidthRegAddr             = (uint32_t) & (base->DITHER_STORE_F_SHIFT_L_CH0);
+                break;
+
+            default:
+                /* Only 2 channels are supported per fetch engine. */
+                assert(false);
+                break;
+        }
+    }
+
+    /* Shift configuration */
+    if (!config->shiftConfig.shiftBypass)
+    {
+        uint8_t i;
+        uint32_t dataShiftMaskAddr  = (uint32_t) & (config->shiftConfig.pDataShiftMask);
+        uint32_t dataShiftWidthAddr = (uint32_t) & (config->shiftConfig.pDataShiftWidth);
+        uint32_t flagShiftMaskAddr  = (uint32_t) & (config->shiftConfig.pFlagShiftMask);
+        uint32_t flagShiftWidthAddr = (uint32_t) & (config->shiftConfig.pFlagShiftWidth);
+
+        /* Configure data shift mask */
+        for (i = 0U; i < 8U; i++)
+        {
+            *(uint32_t *)dataShiftMaskRegAddr = (uint32_t)(*(uint64_t *)dataShiftMaskAddr >> 32U);
+            dataShiftMaskRegAddr += 0x10U;
+            *(uint32_t *)dataShiftMaskRegAddr = (uint32_t)(*(uint64_t *)dataShiftMaskAddr);
+            dataShiftMaskRegAddr += 0x10U;
+            dataShiftMaskAddr += 8U;
+        }
+
+        /* Configure data shift width, flag shift mask/width */
+        for (i = 0U; i < 8U; i++)
+        {
+            *(uint8_t *)dataShiftWidthRegAddr = *(uint8_t *)dataShiftWidthAddr;
+            *(uint8_t *)flagShiftMaskRegAddr  = *(uint8_t *)flagShiftMaskAddr;
+            *(uint8_t *)flagShiftWidthRegAddr = *(uint8_t *)flagShiftWidthAddr;
+            dataShiftWidthRegAddr++;
+            flagShiftMaskRegAddr++;
+            flagShiftWidthRegAddr++;
+            dataShiftWidthAddr++;
+            flagShiftMaskAddr++;
+            flagShiftWidthAddr++;
+            if (i == 3U)
+            {
+                dataShiftWidthRegAddr += 12U;
+                flagShiftMaskRegAddr += 12U;
+                flagShiftWidthRegAddr += 12U;
+            }
+        }
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configures the pre-dither CFA engine.
+ *
+ * param base PXP peripheral base address.
+ * param config pointer to the configuration structure.
+ * retval kStatus_Success Successfully configured the engine.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t PXP_SetCfaConfig(PXP_Type *base, const pxp_cfa_config_t *config)
+{
+    assert(NULL != config);
+    /* The CFA array cannot be larger than 15x15. */
+    if ((config->arrayWidth > 15U) || (config->arrayHeight > 15U))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    uint32_t cfaArrayRegAddr = (uint32_t) & (base->CFA_ARRAY0);
+    uint32_t cfaValueAddr    = (uint32_t) & (config->cfaValue);
+    uint8_t wordCount        = 0U; /* How many 32-bit word does the CFA array need. */
+
+    base->CFA_CTRL = PXP_CFA_CTRL_CFA_ARRAY_HSIZE((uint32_t)config->arrayWidth) |
+                     PXP_CFA_CTRL_CFA_ARRAY_VSIZE((uint32_t)config->arrayHeight) |
+                     PXP_CFA_CTRL_CFA_IN_RGB444((uint32_t)config->pixelInFormat) |
+                     PXP_CFA_CTRL_CFA_BYPASS((uint32_t)config->bypass);
+    base->CFA_SIZE = ((uint32_t)(config->totalWidth) << 16U) | (uint32_t)(config->totalHeight);
+
+    /* Configure the CFA array value. */
+    wordCount = (config->arrayWidth * config->arrayHeight * 2U + 32U) / 32U;
+
+    for (uint8_t i = 0U; i < wordCount; i++)
+    {
+        *(uint32_t *)cfaArrayRegAddr = *(uint32_t *)cfaValueAddr;
+        cfaArrayRegAddr += 0x10U;
+        cfaValueAddr += 4U;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Configures histogram engine.
+ *
+ * param base PXP peripheral base address.
+ * param num instance number.
+ * param config pointer to the configuration structure.
+ * retval kStatus_Success Successfully configured the engine.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t PXP_SetHistogramConfig(PXP_Type *base, uint8_t num, const pxp_histogram_config_t *config)
+{
+    assert(NULL != config);
+    /* The LUT value width can not be larger than 6. */
+    if ((uint32_t)config->lutValueWidth > 6U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    uint32_t ctrlReg = 0U;
+    uint32_t maskReg = 0U;
+
+    ctrlReg = PXP_HIST_A_CTRL_ENABLE((uint32_t)config->enable) |
+              PXP_HIST_A_CTRL_PIXEL_OFFSET((uint32_t)config->lutValueOffset) |
+              PXP_HIST_A_CTRL_PIXEL_WIDTH((uint32_t)config->lutValueWidth);
+    maskReg = PXP_HIST_A_MASK_MASK_EN((uint32_t)config->enableMask) |
+              PXP_HIST_A_MASK_MASK_MODE((uint32_t)config->condition) |
+              PXP_HIST_A_MASK_MASK_OFFSET((uint32_t)config->maskOffset) |
+              PXP_HIST_A_MASK_MASK_WIDTH((uint32_t)config->maskWidth) |
+              PXP_HIST_A_MASK_MASK_VALUE0((uint32_t)config->maskValue0) |
+              PXP_HIST_A_MASK_MASK_VALUE1((uint32_t)config->maskValue1);
+
+    switch (num)
+    {
+        case 0:
+            base->HIST_A_CTRL     = ctrlReg;
+            base->HIST_A_MASK     = maskReg;
+            base->HIST_A_BUF_SIZE = ((uint32_t)(config->totalHeight) << 16U) | (uint32_t)config->totalWidth;
+            break;
+
+        case 1:
+            base->HIST_B_CTRL     = ctrlReg;
+            base->HIST_B_MASK     = maskReg;
+            base->HIST_B_BUF_SIZE = ((uint32_t)(config->totalHeight) << 16U) | (uint32_t)config->totalWidth;
+            break;
+
+        default:
+            /* Only 2 histogram instances are supported. */
+            assert(false);
+            break;
+    }
+
+    /* Only configure the histogram params when user choose to, otherwise use the registers' reset value as default. */
+    if (config->pParamValue != NULL)
+    {
+        uint32_t paramRegAddr   = (uint32_t) & (base->HIST2_PARAM);
+        uint32_t paramValueAddr = (uint32_t) & (config->pParamValue);
+        /* Configure the 2/4/8/16/32-level histogram params. */
+        for (uint8_t i = 0; i < 62U; i++)
+        {
+            *(uint8_t *)paramRegAddr = *(uint8_t *)paramValueAddr;
+            paramValueAddr += 1U;
+            paramRegAddr++;
+            if ((i % 4U) == 1U)
+            {
+                paramRegAddr += 12U;
+                if (i == 1U)
+                {
+                    paramRegAddr += 2U;
+                }
+            }
+        }
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Gets the results of histogram mask operation.
+ *
+ * param base PXP peripheral base address.
+ * param num instance number.
+ * param result pointer to the result structure.
+ */
+void PXP_GetHistogramMaskResult(PXP_Type *base, uint8_t num, pxp_histogram_mask_result_t *result)
+{
+    assert(NULL != result);
+    /* Initializes the result structure to zero. */
+    (void)memset(result, 0, sizeof(*result));
+
+    switch (num)
+    {
+        case 0:
+            result->pixelCount = base->HIST_A_TOTAL_PIXEL;
+            result->minX       = (uint16_t)base->HIST_A_ACTIVE_AREA_X;
+            result->maxX       = (uint16_t)(base->HIST_A_ACTIVE_AREA_X >> 16U);
+            result->minY       = (uint16_t)base->HIST_A_ACTIVE_AREA_Y;
+            result->maxY       = (uint16_t)(base->HIST_A_ACTIVE_AREA_Y >> 16U);
+            result->lutlist    = (uint64_t)base->HIST_A_RAW_STAT0 | ((uint64_t)base->HIST_A_RAW_STAT1 << 32U);
+            break;
+
+        case 1:
+            result->pixelCount = base->HIST_B_TOTAL_PIXEL;
+            result->minX       = (uint16_t)base->HIST_B_ACTIVE_AREA_X;
+            result->maxX       = (uint16_t)(base->HIST_B_ACTIVE_AREA_X >> 16U);
+            result->minY       = (uint16_t)base->HIST_B_ACTIVE_AREA_Y;
+            result->maxY       = (uint16_t)(base->HIST_B_ACTIVE_AREA_Y >> 16U);
+            result->lutlist    = (uint64_t)base->HIST_B_RAW_STAT0 | ((uint64_t)base->HIST_B_RAW_STAT1 << 32U);
+            break;
+
+        default:
+            /* Only 2 histogram instances are supported. */
+            assert(false);
+            break;
+    }
+}
+
+/*!
+ * brief Initializes the WFE-A engine for waveform process.
+ *
+ * param base PXP peripheral base address.
+ * param ditherHandshake true to enable handshake mode with upstream dither store engine.
+ */
+void PXP_WfeaInit(PXP_Type *base, bool ditherHandshake)
+{
+    /* FETCH engine configuration, user fetch buffer1 for Y4 data buffer and buffer2 for working buffer. */
+    /* Enable buffer1&2 fetch. 2 bytes in each pixel for the buffer2.
+       Other default configurations: fetch data from external axi bus, normal(not hanshake or by pass) mode, burst
+       length 4, normal border pixels select(not sw reg mode), 1 line fetch, done IRQ disabled. */
+    base->WFA_FETCH_CTRL = PXP_WFA_FETCH_CTRL_BF1_EN(1UL) | PXP_WFA_FETCH_CTRL_BF2_EN(1UL) |
+                           PXP_WFA_FETCH_CTRL_BF2_BYTES_PP(1UL) |
+                           PXP_WFA_FETCH_CTRL_BF1_HSK_MODE((uint32_t)ditherHandshake);
+    /* Select pixel from bufer 2, set the right/left bit position on the original pixel as 0/3 */
+    /* Other default configurations: x/y offset=0, positive offset. */
+    base->WFA_ARRAY_PIXEL0_MASK = PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(1UL) | PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(3UL);
+    /* Select pixel from bufer 2, set the right/left bit position on the original pixel as 4/7 */
+    base->WFA_ARRAY_PIXEL1_MASK = PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(1UL) | PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(4UL) |
+                                  PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(7UL);
+    /* Select pixel from bufer 2, set the right/left bit position on the original pixel as 8/9 */
+    base->WFA_ARRAY_PIXEL2_MASK = PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(1UL) | PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(8UL) |
+                                  PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(9UL);
+    /* Select pixel from bufer 2, set the right/left bit position on the original pixel as 10/15 */
+    base->WFA_ARRAY_PIXEL3_MASK = PXP_WFA_ARRAY_PIXEL0_MASK_BUF_SEL(1UL) | PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(10UL) |
+                                  PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(15UL);
+    /* Select pixel from bufer 1, set the right/left bit position on the original pixel as 4/7 */
+    base->WFA_ARRAY_PIXEL4_MASK = PXP_WFA_ARRAY_PIXEL0_MASK_H_OFS(4UL) | PXP_WFA_ARRAY_PIXEL0_MASK_L_OFS(7UL);
+    /* Software define flag0=1, other flags 1~15 =0 */
+    base->WFA_ARRAY_REG2 = 1UL;
+
+    /* STORE engine configuration */
+    /* Channel 0 y4, channel 1 wb */
+    /* Enable channel 0, store data to memory, select low 32 bit shift out data to pack, enable combine 2 channel. */
+    /* Other default configurations: Arbitration disable(if using 2 channels, will output 2 axi bus sets), 8 bytes in a
+       burst, fill data mode disable, block mode disable. */
+    base->WFE_A_STORE_CTRL_CH0 = PXP_WFE_A_STORE_CTRL_CH0_CH_EN(1UL) | PXP_WFE_A_STORE_CTRL_CH0_STORE_MEMORY_EN(1UL) |
+                                 PXP_WFE_A_STORE_CTRL_CH0_PACK_IN_SEL(1UL) |
+                                 PXP_WFE_A_STORE_CTRL_CH0_COMBINE_2CHANNEL(1UL);
+    /* Enable channel 1, store data to memory, select low 32 bit shift out data to pack, 16 bytes in a write burst. */
+    base->WFE_A_STORE_CTRL_CH1 = PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1UL) | PXP_WFE_A_STORE_CTRL_CH1_STORE_MEMORY_EN(1UL) |
+                                 PXP_WFE_A_STORE_CTRL_CH1_PACK_IN_SEL(1UL) | PXP_WFE_A_STORE_CTRL_CH1_WR_NUM_BYTES(1UL);
+    /* 8 Bpp, disable YUV planes, disable shift bypass. */
+    base->WFE_A_STORE_SHIFT_CTRL_CH0 = 0UL;
+    /* 16 Bpp, disable YUV planes, disable shift bypass. */
+    base->WFE_A_STORE_SHIFT_CTRL_CH1 = PXP_WFE_A_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(1);
+    base->WFE_A_STORE_FILL_DATA_CH0  = 0UL;
+    /* 8 data masks, mask 0-7. Only use mask 0-4 */
+    /* mask 0: 0xF << 32; mask 1: 0xF00 << 28; mask 2: 0x0 << 24; mask 3: 0x3F00'0000 << 18; mask 4: 0xF'0000'0000 >> 28
+     */
+    base->WFE_A_STORE_D_MASK0_H_CH0 = 0UL;
+    base->WFE_A_STORE_D_MASK0_L_CH0 = PXP_WFE_A_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(0xfUL); /* fetch CP */
+    base->WFE_A_STORE_D_MASK1_H_CH0 = 0UL;
+    base->WFE_A_STORE_D_MASK1_L_CH0 = PXP_WFE_A_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(0xf00UL); /* fetch NP */
+    base->WFE_A_STORE_D_MASK2_H_CH0 = 0UL;
+    base->WFE_A_STORE_D_MASK2_L_CH0 = 0UL;
+    base->WFE_A_STORE_D_MASK3_H_CH0 = 0UL;
+    base->WFE_A_STORE_D_MASK3_L_CH0 = PXP_WFE_A_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(0x3f000000UL); /* fetch LUT */
+    base->WFE_A_STORE_D_MASK4_H_CH0 = PXP_WFE_A_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(0xfUL);
+    base->WFE_A_STORE_D_MASK4_L_CH0 = 0UL; /* fetch Y4 */
+    base->WFE_A_STORE_D_SHIFT_L_CH0 =
+        PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(32UL) | PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(1UL) |
+        PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(28UL) | PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(1UL) |
+        PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(24UL) | PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(1UL) |
+        PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(18UL) | PXP_WFE_A_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(1UL);
+    base->WFE_A_STORE_D_SHIFT_H_CH0 = PXP_WFE_A_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(28UL);
+
+    /* 8 flag masks, mask 0-7. Only use mask 0-3 */
+    /* mask 0: 0x1 << 1; mask 1: 0x2 >> 1; mask 2: 0x4 << 38; mask 3: 0x8 << 38 */
+    /* Switch flag bit 0&1, bit 2&3 << 38 */
+    base->WFE_A_STORE_F_MASK_H_CH0 = 0UL;
+    base->WFE_A_STORE_F_MASK_L_CH0 =
+        PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK0(0x1UL) | PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK1(0x2UL) |
+        PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK2(0x4UL) | PXP_WFE_A_STORE_F_MASK_L_CH0_F_MASK3(0x8UL);
+    base->WFE_A_STORE_F_SHIFT_H_CH0 = 0UL;
+    base->WFE_A_STORE_F_SHIFT_L_CH0 =
+        PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(1UL) | PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(1UL) |
+        PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(1UL) | PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(0UL) |
+        PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(32UL + 6UL) | PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(1UL) |
+        PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(32UL + 6UL) | PXP_WFE_A_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(1UL);
+
+    /* Enable and bypass the ALU process. */
+    base->ALU_A_INST_ENTRY = 0UL;
+    base->ALU_A_PARAM      = 0UL;
+    base->ALU_A_CONFIG     = 0UL;
+    base->ALU_A_LUT_CONFIG = 0UL;
+    base->ALU_A_LUT_DATA0  = 0UL;
+    base->ALU_A_LUT_DATA1  = 0UL;
+    base->ALU_A_CTRL       = PXP_ALU_A_CTRL_BYPASS(1UL) | PXP_ALU_A_CTRL_ENABLE(1UL);
+
+    /* WFE A */
+    base->WFE_A_STAGE1_MUX0  = 0x3F3F0303UL;
+    base->WFE_A_STAGE1_MUX1  = 0x0C00000CUL;
+    base->WFE_A_STAGE1_MUX2  = 0x01040000UL;
+    base->WFE_A_STAGE1_MUX3  = 0x0A0A0904UL;
+    base->WFE_A_STAGE1_MUX4  = 0x00000B0BUL;
+    base->WFE_A_STAGE2_MUX0  = 0x1800280EUL;
+    base->WFE_A_STAGE2_MUX1  = 0x00280E01UL;
+    base->WFE_A_STAGE2_MUX2  = 0x280E0118UL;
+    base->WFE_A_STAGE2_MUX3  = 0x00011800UL;
+    base->WFE_A_STAGE2_MUX4  = 0UL;
+    base->WFE_A_STAGE2_MUX5  = 0x1800280EUL;
+    base->WFE_A_STAGE2_MUX6  = 0x00280E01UL;
+    base->WFE_A_STAGE2_MUX7  = 0x1A0E0118UL;
+    base->WFE_A_STAGE2_MUX8  = 0x1B012911UL;
+    base->WFE_A_STAGE2_MUX9  = 0x00002911UL;
+    base->WFE_A_STAGE2_MUX10 = 0UL;
+    base->WFE_A_STAGE2_MUX11 = 0UL;
+    base->WFE_A_STAGE2_MUX12 = 0UL;
+    base->WFE_A_STAGE3_MUX0  = 0x07060504UL;
+    base->WFE_A_STAGE3_MUX1  = 0x3F3F3F08UL;
+    base->WFE_A_STAGE3_MUX2  = 0x03020100UL;
+    base->WFE_A_STAGE3_MUX3  = 0x3F3F3F3FUL;
+
+    /* WFE_A_STG1_8X1_OUT0_0/1 is used to store LUT occupation status */
+    /* Set LUT64-255 to occupied since we only have 64 LUTs in EPDC */
+    base->WFE_A_STG1_8X1_OUT0_2 = 0xFFFFFFFFUL;
+    base->WFE_A_STG1_8X1_OUT0_3 = 0xFFFFFFFFUL;
+    base->WFE_A_STG1_8X1_OUT0_4 = 0xFFFFFFFFUL;
+    base->WFE_A_STG1_8X1_OUT0_5 = 0xFFFFFFFFUL;
+    base->WFE_A_STG1_8X1_OUT0_6 = 0xFFFFFFFFUL;
+    base->WFE_A_STG1_8X1_OUT0_7 = 0xFFFFFFFFUL;
+    /* OUT1.2.3 LUT0-255 */
+    base->WFE_A_STG1_8X1_OUT1_0 = 0UL;
+    base->WFE_A_STG1_8X1_OUT1_1 = 0UL;
+    base->WFE_A_STG1_8X1_OUT1_2 = 0UL;
+    base->WFE_A_STG1_8X1_OUT1_3 = 0UL;
+    base->WFE_A_STG1_8X1_OUT1_4 = 0UL;
+    base->WFE_A_STG1_8X1_OUT1_5 = 0UL;
+    base->WFE_A_STG1_8X1_OUT1_6 = 0UL;
+    base->WFE_A_STG1_8X1_OUT1_7 = 0UL;
+    base->WFE_A_STG1_8X1_OUT2_0 = 0UL;
+    base->WFE_A_STG1_8X1_OUT2_1 = 0UL;
+    base->WFE_A_STG1_8X1_OUT2_2 = 0UL;
+    base->WFE_A_STG1_8X1_OUT2_3 = 0UL;
+    base->WFE_A_STG1_8X1_OUT2_4 = 0UL;
+    base->WFE_A_STG1_8X1_OUT2_5 = 0UL;
+    base->WFE_A_STG1_8X1_OUT2_6 = 0UL;
+    base->WFE_A_STG1_8X1_OUT2_7 = 0UL;
+    base->WFE_A_STG1_8X1_OUT3_0 = 0UL;
+    base->WFE_A_STG1_8X1_OUT3_1 = 0UL;
+    base->WFE_A_STG1_8X1_OUT3_2 = 0UL;
+    base->WFE_A_STG1_8X1_OUT3_3 = 0UL;
+    base->WFE_A_STG1_8X1_OUT3_4 = 0UL;
+    base->WFE_A_STG1_8X1_OUT3_5 = 0UL;
+    base->WFE_A_STG1_8X1_OUT3_6 = 0UL;
+    base->WFE_A_STG1_8X1_OUT3_7 = 0UL;
+    /* LUTOUT0-31 for OUT0-3.
+       The 5x6 LUT output value for input value n. This output value determines which input to select (flag, data). */
+    base->WFE_A_STG2_5X6_OUT0_0 = 0x04040404UL;
+    base->WFE_A_STG2_5X6_OUT0_1 = 0x04040404UL;
+    base->WFE_A_STG2_5X6_OUT0_2 = 0x04050505UL;
+    base->WFE_A_STG2_5X6_OUT0_3 = 0x04040404UL;
+    base->WFE_A_STG2_5X6_OUT0_4 = 0x04040404UL;
+    base->WFE_A_STG2_5X6_OUT0_5 = 0x04040404UL;
+    base->WFE_A_STG2_5X6_OUT0_6 = 0x04040404UL;
+    base->WFE_A_STG2_5X6_OUT0_7 = 0x04040404UL;
+    base->WFE_A_STG2_5X6_OUT1_0 = 0x05050505UL;
+    base->WFE_A_STG2_5X6_OUT1_1 = 0x05050505UL;
+    base->WFE_A_STG2_5X6_OUT1_2 = 0x05080808UL;
+    base->WFE_A_STG2_5X6_OUT1_3 = 0x05050505UL;
+    base->WFE_A_STG2_5X6_OUT1_4 = 0x05050505UL;
+    base->WFE_A_STG2_5X6_OUT1_5 = 0x05050505UL;
+    base->WFE_A_STG2_5X6_OUT1_6 = 0x05050505UL;
+    base->WFE_A_STG2_5X6_OUT1_7 = 0x05050505UL;
+    base->WFE_A_STG2_5X6_OUT2_0 = 0x07070707UL;
+    base->WFE_A_STG2_5X6_OUT2_1 = 0x07070707UL;
+    base->WFE_A_STG2_5X6_OUT2_2 = 0x070C0C0CUL;
+    base->WFE_A_STG2_5X6_OUT2_3 = 0x07070707UL;
+    base->WFE_A_STG2_5X6_OUT2_4 = 0X0F0F0F0FUL;
+    base->WFE_A_STG2_5X6_OUT2_5 = 0X0F0F0F0FUL;
+    base->WFE_A_STG2_5X6_OUT2_6 = 0X0F0F0F0FUL;
+    base->WFE_A_STG2_5X6_OUT2_7 = 0X0F0F0F0FUL;
+    base->WFE_A_STG2_5X6_OUT3_0 = 0UL;
+    base->WFE_A_STG2_5X6_OUT3_1 = 0UL;
+    base->WFE_A_STG2_5X6_OUT3_2 = 0UL;
+    base->WFE_A_STG2_5X6_OUT3_3 = 0UL;
+    base->WFE_A_STG2_5X6_OUT3_4 = 0UL;
+    base->WFE_A_STG2_5X6_OUT3_5 = 0UL;
+    base->WFE_A_STG2_5X6_OUT3_6 = 0UL;
+    base->WFE_A_STG2_5X6_OUT3_7 = 0UL;
+    /* MASK0-3, 5 bits each mask.
+       Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x6 LUT. */
+    base->WFE_A_STAGE2_5X6_MASKS_0 = 0x001F1F1FUL;
+    /* MUXADDR 0-3, 6 bits each.
+       Each Address specifies the MUX position in the MUX array. There is one MUXADDR per 5x6 LUT.*/
+    base->WFE_A_STAGE2_5X6_ADDR_0 = 0x3f030100UL;
+    /* Flag of LUTOUT0-31 for OUT0-3.
+       The 5x1 LUT output value for input value n. This output value results in a flag that is added to the flag array.
+     */
+    base->WFE_A_STG2_5X1_OUT0 = 0x00000700UL;
+    base->WFE_A_STG2_5X1_OUT1 = 0x00007000UL;
+    base->WFE_A_STG2_5X1_OUT2 = 0x0000A000UL;
+    base->WFE_A_STG2_5X1_OUT3 = 0x000000C0UL;
+    /* MASK0-3, 5 bits each mask.
+       Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT. */
+    base->WFE_A_STG2_5X1_MASKS = 0x071F1F1FUL;
+}
+
+/*!
+ * brief Configure the WFE-A engine
+ *
+ * param base PXP peripheral base address.
+ * param config pointer to the configuration structure.
+ */
+void PXP_SetWfeaConfig(PXP_Type *base, const pxp_wfea_engine_config_t *config)
+{
+    /* Fetch */
+    base->WFA_FETCH_BUF1_ADDR  = config->y4Addr;
+    base->WFA_FETCH_BUF1_PITCH = config->updatePitch;
+    base->WFA_FETCH_BUF1_SIZE  = PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT((uint32_t)config->updateHeight - 1UL) |
+                                PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH((uint32_t)config->updateWidth - 1UL);
+    base->WFA_FETCH_BUF1_CORD  = 0UL;
+    base->WFA_FETCH_BUF2_ADDR  = config->wbAddr;
+    base->WFA_FETCH_BUF2_PITCH = (uint32_t)config->resX * 2U; /* 2 bytes per pixel */
+    base->WFA_FETCH_BUF2_SIZE  = PXP_WFA_FETCH_BUF1_SIZE_BUF_HEIGHT((uint32_t)config->updateHeight - 1UL) |
+                                PXP_WFA_FETCH_BUF1_SIZE_BUF_WIDTH((uint32_t)config->updateWidth - 1UL);
+    base->WFA_FETCH_BUF2_CORD =
+        PXP_WFA_FETCH_BUF2_CORD_YCORD((uint32_t)config->ulcY) | PXP_WFA_FETCH_BUF2_CORD_XCORD((uint32_t)config->ulcX);
+
+    /* Store */
+    base->WFE_A_STORE_SIZE_CH0 = PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH((uint32_t)config->updateWidth - 1UL) |
+                                 PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT((uint32_t)config->updateHeight - 1UL);
+    base->WFE_A_STORE_SIZE_CH1 = PXP_WFE_A_STORE_SIZE_CH0_OUT_WIDTH((uint32_t)config->updateWidth - 1UL) |
+                                 PXP_WFE_A_STORE_SIZE_CH0_OUT_HEIGHT((uint32_t)config->updateHeight - 1UL);
+    /* Channel 1: 2 byte per pixel. */
+    base->WFE_A_STORE_PITCH = PXP_WFE_A_STORE_PITCH_CH0_OUT_PITCH((uint32_t)config->resX) |
+                              PXP_WFE_A_STORE_PITCH_CH1_OUT_PITCH((uint32_t)config->resX * 2U);
+    base->WFE_A_STORE_ADDR_0_CH0 = PXP_WFE_A_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(config->y4cAddr);
+    base->WFE_A_STORE_ADDR_1_CH0 = 0U;
+    /* Channel 1: 2 bytes per pixel. */
+    base->WFE_A_STORE_ADDR_0_CH1 = PXP_WFE_A_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(
+        (uint32_t)config->wbAddr + ((uint32_t)config->ulcX + (uint32_t)config->ulcY * (uint32_t)config->resX) * 2UL);
+    base->WFE_A_STORE_ADDR_1_CH1 = 0U;
+
+    /* ALU */
+    base->ALU_A_BUF_SIZE = PXP_ALU_A_BUF_SIZE_BUF_WIDTH((uint32_t)config->updateWidth) |
+                           PXP_ALU_A_BUF_SIZE_BUF_HEIGHT((uint32_t)config->updateHeight);
+
+    /* WFE */
+    /* Height and width of the updete region */
+    base->WFE_A_DIMENSIONS =
+        PXP_WFE_A_DIMENSIONS_WIDTH(config->updateWidth) | PXP_WFE_A_DIMENSIONS_HEIGHT(config->updateHeight);
+    /* The distance from the frame origin to the update region origin in the X/Y direction. */
+    base->WFE_A_OFFSET = PXP_WFE_A_OFFSET_X_OFFSET(config->ulcX) | PXP_WFE_A_OFFSET_Y_OFFSET(config->ulcY);
+    /* val3,val2=0, val1=F, val0=lutNum */
+    base->WFE_A_SW_DATA_REGS = (config->lutNum & 0x000000FFUL) | 0x00000F00UL;
+    /* val3,val2=0, val1=0(disable reagl/-d), val0=partial(1)full(0) */
+    base->WFE_A_SW_FLAG_REGS = ((uint32_t)(!config->fullUpdateEnable) | (0U << 1U));
+    /* Enable and reset WFE-A state. Disable register of ALU inside waveform as default. */
+    base->WFE_A_CTRL = PXP_WFE_A_CTRL_ENABLE(1UL) | PXP_WFE_A_CTRL_SW_RESET(1UL);
+
+    if (config->alphaEnable)
+    {
+        base->WFA_ARRAY_FLAG0_MASK = 0U;
+    }
+    else
+    {
+        base->WFA_ARRAY_FLAG0_MASK = PXP_WFA_ARRAY_FLAG0_MASK_BUF_SEL(2UL);
+    }
+
+    /* disable CH1 when only doing detection */
+    if (config->detectionOnly)
+    {
+        base->WFE_A_STORE_CTRL_CH1 &= ~PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1UL);
+    }
+    else
+    {
+        base->WFE_A_STORE_CTRL_CH1 |= PXP_WFE_A_STORE_CTRL_CH1_CH_EN(1UL);
+    }
+    /* Enable engine */
+    base->CTRL_SET = PXP_CTRL_ENABLE_WFE_A(1UL);
+}
+#endif /* FSL_FEATURE_PXP_V3 */
+
+#if PXP_USE_PATH
+/*!
+ * brief Sets the path for one of the MUX
+ *
+ * param base PXP peripheral base address.
+ * param path the path configuration for one of the mux.
+ */
+void PXP_SetPath(PXP_Type *base, pxp_path_t path)
+{
+    volatile uint32_t *pathReg;
+    uint32_t mux = PXP_GET_MUX_FROM_PATH((uint32_t)path);
+    uint32_t sel = PXP_GET_SEL_FROM_PATH((uint32_t)path);
+
+    if (mux > 15U)
+    {
+        pathReg = &(base->DATA_PATH_CTRL1);
+        mux -= 15U;
+    }
+    else
+    {
+        pathReg = &(base->DATA_PATH_CTRL0);
+    }
+
+    /* Convert mux to the register shift. */
+    mux *= 2U;
+    *pathReg = (*pathReg & ~(3UL << mux)) | (sel << mux);
+}
+#endif /* PXP_USE_PATH */

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_qtmr.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -525,6 +525,8 @@ void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uin
  *    depending on the count direction
  * 2. User can call the utility macros provided in fsl_common.h to convert to ticks
  * 3. This function supports cases, providing only primary source clock without secondary source clock.
+ * 4. The load register is reset before the counter is reinitialized to the value
+      specified in the load register.
  *
  * param base     Quad Timer peripheral base address
  * param channel  Quad Timer channel number
@@ -535,6 +537,34 @@ void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint1
     /* Set the length bit to reinitialize the counters on a match */
     base->CHANNEL[channel].CTRL |= TMR_CTRL_LENGTH_MASK;
 
+    /* Reset LOAD register to reinitialize the counters */
+    base->CHANNEL[channel].LOAD &= (uint16_t)(~TMR_LOAD_LOAD_MASK);
+
+    if ((base->CHANNEL[channel].CTRL & TMR_CTRL_DIR_MASK) != 0U)
+    {
+        /* Counting down */
+        base->CHANNEL[channel].COMP2 = ticks - 1U;
+    }
+    else
+    {
+        /* Counting up */
+        base->CHANNEL[channel].COMP1 = ticks - 1U;
+    }
+}
+
+/*!
+ * brief Set compare value.
+ *
+ * This function sets the value used for comparison with the counter value.
+ *
+ * param base     Quad Timer peripheral base address
+ * param channel  Quad Timer channel number
+ * param ticks    Timer period in units of ticks.
+ */
+void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks)
+{
+    base->CHANNEL[channel].CTRL |= TMR_CTRL_LENGTH_MASK;
+
     if ((base->CHANNEL[channel].CTRL & TMR_CTRL_DIR_MASK) != 0U)
     {
         /* Counting down */

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_qtmr.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -20,7 +20,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_QTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version */
+#define FSL_QTMR_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version */
 /*@}*/
 
 /*! @brief Quad Timer primary clock source selection*/
@@ -348,6 +348,32 @@ void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uin
  */
 void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks);
 
+/*!
+ * @brief Set compare value.
+ *
+ * This function sets the value used for comparison with the counter value.
+ *
+ * @param base     Quad Timer peripheral base address
+ * @param channel  Quad Timer channel number
+ * @param ticks    Timer period in units of ticks.
+ */
+void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks);
+
+/*!
+ * @brief Set load value.
+ *
+ * This function sets the value used to initialize the counter after a counter comparison.
+ *
+ * @param base     Quad Timer peripheral base address
+ * @param channel  Quad Timer channel number
+ * @param value    Load register initialization value.
+ */
+static inline void QTMR_SetLoadValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t value)
+{
+    base->CHANNEL[channel].LOAD &= (uint16_t)(~TMR_LOAD_LOAD_MASK);
+    base->CHANNEL[channel].LOAD = value;
+}
+
 /*!
  * @brief Reads the current timer counting value.
  *

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -363,7 +363,7 @@ static void SAI_GetCommonConfig(sai_transceiver_t *config,
     /* frame sync default configurations */
     config->frameSync.frameSyncWidth = (uint8_t)bitWidth;
     config->frameSync.frameSyncEarly = true;
-#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND
+#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
     config->frameSync.frameSyncGenerateOnDemand = false;
 #endif
     config->frameSync.frameSyncPolarity = kSAI_PolarityActiveLow;
@@ -865,11 +865,11 @@ void SAI_RxEnable(I2S_Type *base, bool enable)
  * This function will also clear all the error flags such as FIFO error, sync error etc.
  *
  * param base SAI base pointer
- * param type Reset type, FIFO reset or software reset
+ * param resetType Reset type, FIFO reset or software reset
  */
-void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type)
+void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)
 {
-    base->TCSR |= (uint32_t)type;
+    base->TCSR |= (uint32_t)resetType;
 
     /* Clear the software reset */
     base->TCSR &= ~I2S_TCSR_SR_MASK;
@@ -884,11 +884,11 @@ void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type)
  * This function will also clear all the error flags such as FIFO error, sync error etc.
  *
  * param base SAI base pointer
- * param type Reset type, FIFO reset or software reset
+ * param resetType Reset type, FIFO reset or software reset
  */
-void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type)
+void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)
 {
-    base->RCSR |= (uint32_t)type;
+    base->RCSR |= (uint32_t)resetType;
 
     /* Clear the software reset */
     base->RCSR &= ~I2S_RCSR_SR_MASK;
@@ -1318,7 +1318,7 @@ void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sa
 
     tcr4 &= ~(I2S_TCR4_FSE_MASK | I2S_TCR4_FSP_MASK | I2S_TCR4_FSD_MASK | I2S_TCR4_SYWD_MASK);
 
-#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND
+#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
     tcr4 &= ~I2S_TCR4_ONDEM_MASK;
     tcr4 |= I2S_TCR4_ONDEM(config->frameSyncGenerateOnDemand);
 #endif
@@ -1347,7 +1347,7 @@ void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sa
 
     rcr4 &= ~(I2S_RCR4_FSE_MASK | I2S_RCR4_FSP_MASK | I2S_RCR4_FSD_MASK | I2S_RCR4_SYWD_MASK);
 
-#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND
+#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
     rcr4 &= ~I2S_RCR4_ONDEM_MASK;
     rcr4 |= I2S_RCR4_ONDEM(config->frameSyncGenerateOnDemand);
 #endif
@@ -2133,7 +2133,7 @@ void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint
         }
 
         SAI_WriteNonBlocking(base, channel, 1UL << channel, channel, (uint8_t)bitWidth, buffer, bytesPerWord);
-        buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord);
+        buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord);
         i += bytesPerWord;
     }
 
@@ -2188,7 +2188,7 @@ void SAI_WriteMultiChannelBlocking(
 
         SAI_WriteNonBlocking(base, channel, channelMask, endChannel, (uint8_t)bitWidth, buffer,
                              bytesPerWord * channelNums);
-        buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord * channelNums);
+        buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord * channelNums);
         j += bytesPerWord * channelNums;
     }
 
@@ -2241,7 +2241,7 @@ void SAI_ReadMultiChannelBlocking(
 
         SAI_ReadNonBlocking(base, channel, channelMask, endChannel, (uint8_t)bitWidth, buffer,
                             bytesPerWord * channelNums);
-        buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord * channelNums);
+        buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord * channelNums);
         j += bytesPerWord * channelNums;
     }
 }
@@ -2273,7 +2273,7 @@ void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8
         }
 
         SAI_ReadNonBlocking(base, channel, 1UL << channel, channel, (uint8_t)bitWidth, buffer, bytesPerWord);
-        buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord);
+        buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord);
         i += bytesPerWord;
     }
 }
@@ -2745,7 +2745,7 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
 
         /* Update the internal counter */
         handle->saiQueue[handle->queueDriver].dataSize -= size;
-        handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size);
+        handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size);
     }
 #else
     if (IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK))
@@ -2757,7 +2757,7 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
 
         /* Update internal counter */
         handle->saiQueue[handle->queueDriver].dataSize -= size;
-        handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size);
+        handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size);
     }
 #endif /* FSL_FEATURE_SAI_FIFO_COUNT */
 
@@ -2821,7 +2821,7 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
 
         /* Update the internal counter */
         handle->saiQueue[handle->queueDriver].dataSize -= size;
-        handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size);
+        handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size);
     }
 #else
     if (IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FWF_MASK))
@@ -2833,7 +2833,7 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
 
         /* Update internal state */
         handle->saiQueue[handle->queueDriver].dataSize -= size;
-        handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size);
+        handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size);
     }
 #endif /* FSL_FEATURE_SAI_FIFO_COUNT */
 

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2020 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -22,7 +22,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 3, 4)) /*!< Version 2.3.4 */
+#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 3, 6)) /*!< Version 2.3.6 */
 /*@}*/
 
 /*! @brief _sai_status_t, SAI return status.*/
@@ -365,7 +365,7 @@ typedef struct _sai_frame_sync
     bool frameSyncEarly;    /*!< TRUE is frame sync assert one bit before the first bit of frame
                                 FALSE is frame sync assert with the first bit of the frame */
 
-#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND
+#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
     bool frameSyncGenerateOnDemand; /*!< internal frame sync is generated when FIFO waring flag is clear */
 #endif
 
@@ -940,9 +940,9 @@ static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask)
  * This function will also clear all the error flags such as FIFO error, sync error etc.
  *
  * @param base SAI base pointer
- * @param type Reset type, FIFO reset or software reset
+ * @param tresetType Reset type, FIFO reset or software reset
  */
-void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type);
+void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType);
 
 /*!
  * @brief Do software reset or FIFO reset .
@@ -953,9 +953,9 @@ void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type);
  * This function will also clear all the error flags such as FIFO error, sync error etc.
  *
  * @param base SAI base pointer
- * @param type Reset type, FIFO reset or software reset
+ * @param resetType Reset type, FIFO reset or software reset
  */
-void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type);
+void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType);
 
 /*!
  * @brief Set the Tx channel FIFO enable mask.
@@ -1218,9 +1218,9 @@ static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)
  * @param channel Which data channel used.
  * @return data register address.
  */
-static inline uint32_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)
+static inline uintptr_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)
 {
-    return (uint32_t)(&(base->TDR)[channel]);
+    return (uintptr_t)(&(base->TDR)[channel]);
 }
 
 /*!
@@ -1232,9 +1232,9 @@ static inline uint32_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t cha
  * @param channel Which data channel used.
  * @return data register address.
  */
-static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)
+static inline uintptr_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)
 {
-    return (uint32_t)(&(base->RDR)[channel]);
+    return (uintptr_t)(&(base->RDR)[channel]);
 }
 
 /*! @} */

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai_edma.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2021 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai_edma.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2021 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_semc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -24,11 +24,15 @@
 #else
 #define SEMC_IOCR_PINMUXBITWIDTH (0x3UL)
 #endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */
-#define SEMC_IOCR_NAND_CE                     (4UL)
-#define SEMC_IOCR_NOR_CE                      (5UL)
-#define SEMC_IOCR_NOR_CE_A8                   (2UL)
-#define SEMC_IOCR_PSRAM_CE                    (6UL)
-#define SEMC_IOCR_PSRAM_CE_A8                 (3UL)
+#define SEMC_IOCR_NAND_CE   (4UL)
+#define SEMC_IOCR_NOR_CE    (5UL)
+#define SEMC_IOCR_NOR_CE_A8 (2UL)
+#define SEMC_IOCR_PSRAM_CE  (6UL)
+#if defined(SEMC_IOCR_PINMUXBITWIDTH) && (SEMC_IOCR_PINMUXBITWIDTH == 0x4UL)
+#define SEMC_IOCR_PSRAM_CE_A8 (6UL)
+#else
+#define SEMC_IOCR_PSRAM_CE_A8 (3UL)
+#endif /* SEMC_IOCR_PINMUXBITWIDTH */
 #define SEMC_IOCR_DBI_CSX                     (7UL)
 #define SEMC_IOCR_DBI_CSX_A8                  (4UL)
 #define SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE (24U)
@@ -63,12 +67,11 @@ static uint32_t SEMC_GetInstance(SEMC_Type *base);
 /*!
  * @brief Covert the input memory size to internal register set value.
  *
- * @param base SEMC peripheral base address
  * @param size_kbytes SEMC memory size in unit of kbytes.
  * @param sizeConverted SEMC converted memory size to 0 ~ 0x1F.
  * @return Execution status.
  */
-static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted);
+static status_t SEMC_CovertMemorySize(uint32_t size_kbytes, uint8_t *sizeConverted);
 
 /*!
  * @brief Covert the external timing nanosecond to internal clock cycle.
@@ -131,7 +134,7 @@ static uint32_t SEMC_GetInstance(SEMC_Type *base)
     return instance;
 }
 
-static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted)
+static status_t SEMC_CovertMemorySize(uint32_t size_kbytes, uint8_t *sizeConverted)
 {
     assert(sizeConverted != NULL);
     uint32_t memsize;
@@ -408,7 +411,7 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con
     uint32_t iocReg = base->IOCR & (~(SEMC_IOCR_PINMUXBITWIDTH << (uint32_t)config->csxPinMux));
 
     /* Base control. */
-    result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize);
+    result = SEMC_CovertMemorySize(config->memsize_kbytes, &memsize);
     if (result != kStatus_Success)
     {
         return result;
@@ -541,14 +544,14 @@ status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_
     {
         base->MCR &= ~SEMC_MCR_WPOL1_MASK;
     }
-    result = SEMC_CovertMemorySize(base, config->axiMemsize_kbytes, &memsize);
+    result = SEMC_CovertMemorySize(config->axiMemsize_kbytes, &memsize);
     if (result != kStatus_Success)
     {
         return result;
     }
     base->BR[4] = (config->axiAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK;
 
-    result = SEMC_CovertMemorySize(base, config->ipgMemsize_kbytes, &memsize);
+    result = SEMC_CovertMemorySize(config->ipgMemsize_kbytes, &memsize);
     if (result != kStatus_Success)
     {
         return result;
@@ -689,7 +692,7 @@ status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t
     {
         base->MCR &= ~SEMC_MCR_WPOL0_MASK;
     }
-    result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize);
+    result = SEMC_CovertMemorySize(config->memsize_kbytes, &memsize);
     if (result != kStatus_Success)
     {
         return result;
@@ -843,7 +846,7 @@ status_t SEMC_ConfigureSRAMWithChipSelection(SEMC_Type *base,
         }
     }
     /* Base control. */
-    result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize);
+    result = SEMC_CovertMemorySize(config->memsize_kbytes, &memsize);
     if (result != kStatus_Success)
     {
         return result;
@@ -1076,7 +1079,7 @@ status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t
     /* IOMUX setting. */
     base->IOCR = iocReg | (muxCsx << (uint32_t)config->csxPinMux);
     /* Base control. */
-    result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize);
+    result = SEMC_CovertMemorySize(config->memsize_kbytes, &memsize);
     if (result != kStatus_Success)
     {
         return result;
@@ -1114,7 +1117,7 @@ status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t
  * brief SEMC IP command access.
  *
  * param base  SEMC peripheral base address.
- * param type  SEMC memory type. refer to "semc_mem_type_t"
+ * param memType  SEMC memory type. refer to "semc_mem_type_t"
  * param address  SEMC device address.
  * param command  SEMC IP command.
  * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command.
@@ -1125,7 +1128,7 @@ status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t
  * param read   Data pointer for read data out.
  */
 status_t SEMC_SendIPCommand(
-    SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint32_t command, uint32_t write, uint32_t *read)
+    SEMC_Type *base, semc_mem_type_t memType, uint32_t address, uint32_t command, uint32_t write, uint32_t *read)
 {
     uint32_t cmdMode;
     bool readCmd  = false;
@@ -1139,7 +1142,7 @@ status_t SEMC_SendIPCommand(
 
     /* Check command mode. */
     cmdMode = (uint32_t)command & 0x0FU;
-    switch (type)
+    switch (memType)
     {
         case kSEMC_MemType_NAND:
             readCmd = (cmdMode == (uint32_t)kSEMC_NANDCM_CommandAddressRead) ||

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_semc.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -20,8 +20,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief SEMC driver version 2.3.1. */
-#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
+/*! @brief SEMC driver version. */
+#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 4, 3))
 /*@}*/
 
 /*! @brief SEMC status, _semc_status. */
@@ -479,7 +479,7 @@ typedef struct _semc_nor_config
     uint8_t latencyCount; /*!< Latency count for sync mode. */
 #endif
 #if defined(FSL_FEATURE_SEMC_HAS_NOR_RD_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_RD_TIME)
-    uint8_t readCycle;    /*!< Read cycle time for sync mode. */
+    uint8_t readCycle; /*!< Read cycle time for sync mode. */
 #endif
 #if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
     uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than
@@ -832,7 +832,7 @@ static inline bool SEMC_IsInIdle(SEMC_Type *base)
  * @brief SEMC IP command access.
  *
  * @param base  SEMC peripheral base address.
- * @param type  SEMC memory type. refer to "semc_mem_type_t"
+ * @param memType  SEMC memory type. refer to "semc_mem_type_t"
  * @param address  SEMC device address.
  * @param command  SEMC IP command.
  * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command.
@@ -843,7 +843,7 @@ static inline bool SEMC_IsInIdle(SEMC_Type *base)
  * @param read   Data pointer for read data out.
  */
 status_t SEMC_SendIPCommand(
-    SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint32_t command, uint32_t write, uint32_t *read);
+    SEMC_Type *base, semc_mem_type_t memType, uint32_t address, uint32_t command, uint32_t write, uint32_t *read);
 
 /*!
  * @brief Build SEMC IP command for NAND.

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_hp.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2017-2019, 2021 NXP
+ * Copyright 2017-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -278,11 +278,7 @@ void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config)
 {
     assert(config != NULL);
 
-#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \
-     defined(SNVS_HP_CLOCKS))
-    uint32_t instance = SNVS_HP_GetInstance(base);
-    CLOCK_EnableClock(s_snvsHpClock[instance]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    SNVS_HP_Init(base);
 
     base->HPCOMR |= SNVS_HPCOMR_NPSWA_EN_MASK;
 
@@ -304,11 +300,7 @@ void SNVS_HP_RTC_Deinit(SNVS_Type *base)
 {
     base->HPCR &= ~SNVS_HPCR_RTC_EN_MASK;
 
-#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \
-     defined(SNVS_HP_CLOCKS))
-    uint32_t instance = SNVS_HP_GetInstance(base);
-    CLOCK_DisableClock(s_snvsHpClock[instance]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    SNVS_HP_Deinit(base);
 }
 
 /*!

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_hp.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2017-2021, NXP
+ * Copyright 2017-2022, NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -22,7 +22,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SNVS_HP_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1 */
+#define FSL_SNVS_HP_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) /*!< Version 2.3.2 */
 /*@}*/
 
 /*! @brief List of SNVS interrupts */

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_lp.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2017-2021, NXP
+ * Copyright 2017-2022, NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -285,11 +285,7 @@ void SNVS_LP_SRTC_Init(SNVS_Type *base, const snvs_lp_srtc_config_t *config)
 {
     assert(config != NULL);
 
-#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \
-     defined(SNVS_LP_CLOCKS))
-    uint32_t instance = SNVS_LP_GetInstance(base);
-    CLOCK_EnableClock(s_snvsLpClock[instance]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    SNVS_LP_Init(base);
 
     if (config->srtcCalEnable)
     {
@@ -318,11 +314,7 @@ void SNVS_LP_SRTC_Deinit(SNVS_Type *base)
 {
     base->LPCR &= ~SNVS_LPCR_SRTC_ENV_MASK;
 
-#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \
-     defined(SNVS_LP_CLOCKS))
-    uint32_t instance = SNVS_LP_GetInstance(base);
-    CLOCK_DisableClock(s_snvsLpClock[instance]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    SNVS_LP_Deinit(base);
 }
 
 /*!

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_lp.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2017-2021, NXP
+ * Copyright 2017-2022, NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -22,7 +22,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SNVS_LP_DRIVER_VERSION (MAKE_VERSION(2, 4, 3)) /*!< Version 2.4.3 */
+#define FSL_SNVS_LP_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version 2.4.4 */
 /*@}*/
 
 /*! @brief Define of SNVS_LP Zeroizable Master Key registers */

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_xbara.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2019, 2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -28,6 +28,9 @@
 /* Set the XBARA_SELx_SELx field to a new value. */
 #define XBARA_WR_SELx_SELx(base, input, output) XBARA_SetSignalsConnection((base), (input), (output))
 
+/* For driver backward compatibility.  */
+#define kXBARA_RequestInterruptEnalbe kXBARA_RequestInterruptEnable
+
 /*!
  * @brief XBARA active edge for detection
  */
@@ -46,7 +49,7 @@ typedef enum _xbar_request
 {
     kXBARA_RequestDisable         = 0U, /*!< Interrupt and DMA are disabled. */
     kXBARA_RequestDMAEnable       = 1U, /*!< DMA enabled, interrupt disabled. */
-    kXBARA_RequestInterruptEnalbe = 2U  /*!< Interrupt enabled, DMA disabled. */
+    kXBARA_RequestInterruptEnable = 2U  /*!< Interrupt enabled, DMA disabled. */
 } xbara_request_t;
 
 /*!

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/generic_list.c

@@ -0,0 +1,475 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Include
+*************************************************************************************
+********************************************************************************** */
+#include "generic_list.h"
+
+static list_status_t LIST_Error_Check(list_handle_t list, list_element_handle_t newElement)
+{
+    list_status_t listStatus      = kLIST_Ok;
+    list_element_handle_t element = list->head;
+
+    if ((list->max != 0U) && (list->max == list->size))
+    {
+        listStatus = kLIST_Full; /*List is full*/
+    }
+    else
+    {
+        while (element != NULL) /*Scan list*/
+        {
+            /* Determine if element is duplicated */
+            if (element == newElement)
+            {
+                listStatus = kLIST_DuplicateError;
+                break;
+            }
+            element = element->next;
+        }
+    }
+
+    return listStatus;
+}
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public functions
+*************************************************************************************
+********************************************************************************** */
+/*! *********************************************************************************
+ * \brief     Initialises the list descriptor.
+ *
+ * \param[in] list - LIST_ handle to init.
+ *            max - Maximum number of elements in list. 0 for unlimited.
+ *
+ * \return void.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+void LIST_Init(list_handle_t list, uint32_t max)
+{
+    list->head = NULL;
+    list->tail = NULL;
+    list->max  = (uint16_t)max;
+    list->size = 0;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets the list that contains the given element.
+ *
+ * \param[in] element - Handle of the element.
+ *
+ * \return NULL if element is orphan.
+ *         Handle of the list the element is inserted into.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_handle_t LIST_GetList(list_element_handle_t element)
+{
+    return element->list;
+}
+
+/*! *********************************************************************************
+ * \brief     Links element to the tail of the list.
+ *
+ * \param[in] list - ID of list to insert into.
+ *            element - element to add
+ *
+ * \return kLIST_Full if list is full.
+ *         kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element)
+{
+    uint32_t regPrimask      = DisableGlobalIRQ();
+    list_status_t listStatus = kLIST_Ok;
+
+    listStatus = LIST_Error_Check(list, element);
+    if (listStatus == kLIST_Ok) /* Avoiding list status error */
+    {
+        if (list->size == 0U)
+        {
+            list->head = element;
+        }
+        else
+        {
+            list->tail->next = element;
+        }
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#else
+        element->prev = list->tail;
+#endif
+        element->list = list;
+        element->next = NULL;
+        list->tail    = element;
+        list->size++;
+    }
+
+    EnableGlobalIRQ(regPrimask);
+    return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief     Links element to the head of the list.
+ *
+ * \param[in] list - ID of list to insert into.
+ *            element - element to add
+ *
+ * \return kLIST_Full if list is full.
+ *         kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element)
+{
+    uint32_t regPrimask      = DisableGlobalIRQ();
+    list_status_t listStatus = kLIST_Ok;
+
+    listStatus = LIST_Error_Check(list, element);
+    if (listStatus == kLIST_Ok) /* Avoiding list status error */
+    {
+        /* Links element to the head of the list */
+        if (list->size == 0U)
+        {
+            list->tail = element;
+        }
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#else
+        else
+        {
+            list->head->prev = element;
+        }
+        element->prev = NULL;
+#endif
+        element->list = list;
+        element->next = list->head;
+        list->head    = element;
+        list->size++;
+    }
+
+    EnableGlobalIRQ(regPrimask);
+    return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief     Unlinks element from the head of the list.
+ *
+ * \param[in] list - ID of list to remove from.
+ *
+ * \return NULL if list is empty.
+ *         ID of removed element(pointer) if removal was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_RemoveHead(list_handle_t list)
+{
+    list_element_handle_t element;
+
+    uint32_t regPrimask = DisableGlobalIRQ();
+
+    if ((NULL == list) || (list->size == 0U))
+    {
+        element = NULL; /*LIST_ is empty*/
+    }
+    else
+    {
+        element = list->head;
+        list->size--;
+        if (list->size == 0U)
+        {
+            list->tail = NULL;
+        }
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+#else
+        else
+        {
+            element->next->prev = NULL;
+        }
+#endif
+        element->list = NULL;
+        list->head    = element->next; /*Is NULL if element is head*/
+    }
+
+    EnableGlobalIRQ(regPrimask);
+    return element;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets head element ID.
+ *
+ * \param[in] list - ID of list.
+ *
+ * \return NULL if list is empty.
+ *         ID of head element if list is not empty.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetHead(list_handle_t list)
+{
+    return list->head;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets next element ID.
+ *
+ * \param[in] element - ID of the element.
+ *
+ * \return NULL if element is tail.
+ *         ID of next element if exists.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetNext(list_element_handle_t element)
+{
+    return element->next;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets previous element ID.
+ *
+ * \param[in] element - ID of the element.
+ *
+ * \return NULL if element is head.
+ *         ID of previous element if exists.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetPrev(list_element_handle_t element)
+{
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+    return NULL;
+#else
+    return element->prev;
+#endif
+}
+
+/*! *********************************************************************************
+ * \brief     Unlinks an element from its list.
+ *
+ * \param[in] element - ID of the element to remove.
+ *
+ * \return kLIST_OrphanElement if element is not part of any list.
+ *         kLIST_Ok if removal was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_RemoveElement(list_element_handle_t element)
+{
+    list_status_t listStatus = kLIST_Ok;
+    uint32_t regPrimask      = DisableGlobalIRQ();
+
+    if (element->list == NULL)
+    {
+        listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/
+    }
+    else
+    {
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+        list_element_handle_t element_list = element->list->head;
+        while (element_list)
+        {
+            if (element->list->head == element)
+            {
+                element->list->head = element_list->next;
+                break;
+            }
+            if (element_list->next == element)
+            {
+                element_list->next = element->next;
+                break;
+            }
+            element_list = element_list->next;
+        }
+#else
+        if (element->prev == NULL) /*Element is head or solo*/
+        {
+            element->list->head = element->next; /*is null if solo*/
+        }
+        if (element->next == NULL) /*Element is tail or solo*/
+        {
+            element->list->tail = element->prev; /*is null if solo*/
+        }
+        if (element->prev != NULL) /*Element is not head*/
+        {
+            element->prev->next = element->next;
+        }
+        if (element->next != NULL) /*Element is not tail*/
+        {
+            element->next->prev = element->prev;
+        }
+#endif
+        element->list->size--;
+        element->list = NULL;
+    }
+
+    EnableGlobalIRQ(regPrimask);
+    return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief     Links an element in the previous position relative to a given member
+ *            of a list.
+ *
+ * \param[in] element - ID of a member of a list.
+ *            newElement - new element to insert before the given member.
+ *
+ * \return kLIST_OrphanElement if element is not part of any list.
+ *         kLIST_Full if list is full.
+ *         kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement)
+{
+    list_status_t listStatus = kLIST_Ok;
+    uint32_t regPrimask      = DisableGlobalIRQ();
+
+    if (element->list == NULL)
+    {
+        listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/
+    }
+    else
+    {
+        listStatus = LIST_Error_Check(element->list, newElement);
+        if (listStatus == kLIST_Ok)
+        {
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+            list_element_handle_t element_list = element->list->head;
+            while (element_list)
+            {
+                if ((element_list->next == element) || (element_list == element))
+                {
+                    if (element_list == element)
+                    {
+                        element->list->head = newElement;
+                    }
+                    else
+                    {
+                        element_list->next = newElement;
+                    }
+                    newElement->list = element->list;
+                    newElement->next = element;
+                    element->list->size++;
+                    break;
+                }
+                element_list = element_list->next;
+            }
+
+#else
+            if (element->prev == NULL) /*Element is list head*/
+            {
+                element->list->head = newElement;
+            }
+            else
+            {
+                element->prev->next = newElement;
+            }
+            newElement->list = element->list;
+            element->list->size++;
+            newElement->next = element;
+            newElement->prev = element->prev;
+            element->prev = newElement;
+#endif
+        }
+    }
+
+    EnableGlobalIRQ(regPrimask);
+    return listStatus;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets the current size of a list.
+ *
+ * \param[in] list - ID of the list.
+ *
+ * \return Current size of the list.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+uint32_t LIST_GetSize(list_handle_t list)
+{
+    return list->size;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets the number of free places in the list.
+ *
+ * \param[in] list - ID of the list.
+ *
+ * \return Available size of the list.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+uint32_t LIST_GetAvailableSize(list_handle_t list)
+{
+    return ((uint32_t)list->max - (uint32_t)list->size); /*Gets the number of free places in the list*/
+}

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/generic_list.h

@@ -0,0 +1,203 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _GENERIC_LIST_H_
+#define _GENERIC_LIST_H_
+
+#include "fsl_common.h"
+/*!
+ * @addtogroup GenericList
+ * @{
+ */
+
+/*!*********************************************************************************
+*************************************************************************************
+* Include
+*************************************************************************************
+********************************************************************************** */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public macro definitions
+*************************************************************************************
+********************************************************************************** */
+#ifndef GENERIC_LIST_LIGHT
+#define GENERIC_LIST_LIGHT (0)
+#endif
+/*! *********************************************************************************
+*************************************************************************************
+* Public type definitions
+*************************************************************************************
+********************************************************************************** */
+/*! @brief The list status */
+typedef enum _list_status
+{
+    kLIST_Ok             = kStatus_Success,                   /*!< Success */
+    kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */
+    kLIST_Full           = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */
+    kLIST_Empty          = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */
+    kLIST_OrphanElement  = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */
+    kLIST_NotSupport     = MAKE_STATUS(kStatusGroup_LIST, 5), /*!< Not Support  */
+} list_status_t;
+
+/*! @brief The list structure*/
+typedef struct list_label
+{
+    struct list_element_tag *head; /*!< list head */
+    struct list_element_tag *tail; /*!< list tail */
+    uint16_t size;                 /*!< list size */
+    uint16_t max;                  /*!< list max number of elements */
+} list_label_t, *list_handle_t;
+#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
+/*! @brief The list element*/
+typedef struct list_element_tag
+{
+    struct list_element_tag *next; /*!< next list element   */
+    struct list_label *list;       /*!< pointer to the list */
+} list_element_t, *list_element_handle_t;
+#else
+/*! @brief The list element*/
+typedef struct list_element_tag
+{
+    struct list_element_tag *next; /*!< next list element   */
+    struct list_element_tag *prev; /*!< previous list element */
+    struct list_label *list;       /*!< pointer to the list */
+} list_element_t, *list_element_handle_t;
+#endif
+/*! *********************************************************************************
+*************************************************************************************
+* Public prototypes
+*************************************************************************************
+********************************************************************************** */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+/*!
+ * @brief Initialize the list.
+ *
+ * This function initialize the list.
+ *
+ * @param list - List handle to initialize.
+ * @param max - Maximum number of elements in list. 0 for unlimited.
+ */
+void LIST_Init(list_handle_t list, uint32_t max);
+
+/*!
+ * @brief Gets the list that contains the given element.
+ *
+ *
+ * @param element - Handle of the element.
+ * @retval NULL if element is orphan, Handle of the list the element is inserted into.
+ */
+list_handle_t LIST_GetList(list_element_handle_t element);
+
+/*!
+ * @brief Links element to the head of the list.
+ *
+ * @param list - Handle of the list.
+ * @param element - Handle of the element.
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
+ */
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element);
+
+/*!
+ * @brief Links element to the tail of the list.
+ *
+ * @param list - Handle of the list.
+ * @param element - Handle of the element.
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
+ */
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element);
+
+/*!
+ * @brief Unlinks element from the head of the list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_RemoveHead(list_handle_t list);
+
+/*!
+ * @brief Gets head element handle.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetHead(list_handle_t list);
+
+/*!
+ * @brief Gets next element handle for given element handle.
+ *
+ * @param element - Handle of the element.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetNext(list_element_handle_t element);
+
+/*!
+ * @brief Gets previous element handle for given element handle.
+ *
+ * @param element - Handle of the element.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetPrev(list_element_handle_t element);
+
+/*!
+ * @brief Unlinks an element from its list.
+ *
+ * @param element - Handle of the element.
+ *
+ * @retval kLIST_OrphanElement if element is not part of any list.
+ * @retval kLIST_Ok if removal was successful.
+ */
+list_status_t LIST_RemoveElement(list_element_handle_t element);
+
+/*!
+ * @brief Links an element in the previous position relative to a given member of a list.
+ *
+ * @param list - Handle of the list.
+ * @param element - Handle of the element.
+ * @param newElement - New element to insert before the given member.
+ *
+ * @retval kLIST_OrphanElement if element is not part of any list.
+ * @retval kLIST_Ok if removal was successful.
+ */
+list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement);
+
+/*!
+ * @brief Gets the current size of a list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval Current size of the list.
+ */
+uint32_t LIST_GetSize(list_handle_t list);
+
+/*!
+ * @brief Gets the number of free places in the list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval Available size of the list.
+ */
+uint32_t LIST_GetAvailableSize(list_handle_t list);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @}*/
+#endif /*_GENERIC_LIST_H_*/

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/fsl_device_registers.h

@@ -1,6 +1,6 @@
 /*
  * Copyright 2014-2016 Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2022 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -16,7 +16,7 @@
  * The CPU macro should be declared in the project or makefile.
  */
 #if (defined(CPU_MIMXRT1062CVJ5A) || defined(CPU_MIMXRT1062CVL5A) || defined(CPU_MIMXRT1062DVJ6A) || \
-    defined(CPU_MIMXRT1062DVL6A))
+    defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1062DVN6B) || defined(CPU_MIMXRT1062XVN5B))
 
 #define MIMXRT1062_SERIES
 

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_flexspi_nor.ld

@@ -4,17 +4,19 @@
 **                          MIMXRT1062CVL5A
 **                          MIMXRT1062DVJ6A
 **                          MIMXRT1062DVL6A
+**                          MIMXRT1062DVN6B
+**                          MIMXRT1062XVN5B
 **
 **     Compiler:            GNU C Compiler
-**     Reference manual:    IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b210709
+**     Reference manual:    IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+**     Version:             rev. 0.2, 2022-03-25
+**     Build:               b220401
 **
 **     Abstract:
 **         Linker file for the GNU C Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2021 NXP
+**     Copyright 2016-2022 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause

bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_flexspi_nor_sdram.ld

@@ -4,17 +4,19 @@
 **                          MIMXRT1062CVL5A
 **                          MIMXRT1062DVJ6A
 **                          MIMXRT1062DVL6A
+**                          MIMXRT1062DVN6B
+**                          MIMXRT1062XVN5B
 **
 **     Compiler:            GNU C Compiler
-**     Reference manual:    IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b210709
+**     Reference manual:    IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
+**     Version:             rev. 0.2, 2022-03-25
+**     Build:               b220401
 **
 **     Abstract:
 **         Linker file for the GNU C Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2021 NXP
+**     Copyright 2016-2022 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause