add nv32f100x bsp.

bsp/nv32f100x/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/nv32f100x/SConstruct

@@ -0,0 +1,34 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-stm32f0xx.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/nv32f100x/app/SConscript

@@ -0,0 +1,15 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'app')
+
+src	= Glob('./src/*.c')
+
+path = [cwd + '/inc',
+	cwd + '/..',
+	]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/nv32f100x/app/src/application.c

@@ -0,0 +1,69 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ * 2013-11-15     bright       add init thread and components initial
+ * 2017-09-19     Quintin.Z    modify for nv32f100xxx version and components initial
+ */
+
+/**
+ * @addtogroup STM32
+ */
+/*@{*/
+
+#include <stdio.h>
+#include <rthw.h>
+#include <rtdevice.h>
+#include "board.h"
+#include <rtthread.h>
+#ifdef  RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif  /* RT_USING_COMPONENTS_INIT */
+
+static void rt_init_thread_entry(void* parameter)
+{
+extern void led_thread_entry(void* parameter);
+	rt_thread_t thread;
+
+/* Initialization RT-Thread Components */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_init();
+#endif
+
+/* Set finsh device */
+#ifdef  RT_USING_FINSH
+    finsh_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif  /* RT_USING_FINSH */
+
+    
+    /* Create led thread */
+    thread = rt_thread_create("led",
+		led_thread_entry, RT_NULL,
+		256, 20, 20);
+    if(thread != RT_NULL)
+	rt_thread_startup(thread);
+}
+
+int rt_application_init()
+{
+	rt_thread_t init_thread;
+    init_thread = rt_thread_create("init",
+                                   rt_init_thread_entry, RT_NULL,
+                                   512, 8, 20);
+
+    if(init_thread != RT_NULL)
+	rt_thread_startup(init_thread);
+
+    return 0;
+}
+
+
+/*@}*/

bsp/nv32f100x/app/src/ledapp.c

@@ -0,0 +1,39 @@
+/*
+ * File      : ledapp.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-19     Quintin.Z    the first version
+ */
+ 
+#include <stdio.h>
+#include <rthw.h>
+#include <rtdevice.h>
+#include "board.h"
+#include <rtthread.h>
+
+#ifdef  RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif  /* RT_USING_COMPONENTS_INIT */
+
+#include "gpio.h"
+
+
+void led_thread_entry(void* parameter)
+{
+
+    GPIO_Init  (GPIOA, GPIO_PTB5_MASK, GPIO_PinOutput);
+    
+	while(1)
+	{
+        GPIO_Toggle  (GPIOA, GPIO_PTB5_MASK);
+        rt_thread_delay(RT_TICK_PER_SECOND / 10);
+
+	}
+}

bsp/nv32f100x/app/src/startup.c

@@ -0,0 +1,116 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-08-31     Bernard      first implementation
+ * 2013-11-15     bright       modify for stm32f0xx version and components initial
+ * 2017-09-19     Quintin.Z    modify for nv32f100xxx version and components initial
+ */
+
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+
+extern int  rt_application_init(void);
+#ifdef RT_USING_FINSH
+extern int finsh_system_init(void);
+extern void finsh_set_device(const char* device);
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define NV32_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define NV32_SRAM_BEGIN    (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define NV32_SRAM_BEGIN    (&__bss_end)
+#endif
+
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(uint8_t* file, uint32_t line)
+{
+	rt_kprintf("\n\r Wrong parameter value detected on\r\n");
+	rt_kprintf("       file  %s\r\n", file);
+	rt_kprintf("       line  %d\r\n", line);
+
+	while (1) ;
+}
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+	/* init board */
+	rt_hw_board_init();
+
+	/* show version */
+	rt_show_version();
+
+	/* init tick */
+	rt_system_tick_init();
+
+	/* init kernel object */
+	rt_system_object_init();
+
+	/* init timer system */
+	rt_system_timer_init();
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void*)NV32_SRAM_BEGIN, (void*)NV32_SRAM_END);
+#endif
+
+	/* init scheduler system */
+	rt_system_scheduler_init();
+
+	/* init application */
+	rt_application_init();
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+	/* init idle thread */
+	rt_thread_idle_init();
+
+	/* start scheduler */
+	rt_system_scheduler_start();
+
+	/* never reach here */
+    
+	return ;
+}
+
+
+
+int main(void)
+{
+	/* disable interrupt first */
+	rt_hw_interrupt_disable();
+
+	/* startup RT-Thread RTOS */
+	rtthread_startup();
+    
+	return 0;
+}
+
+/*@}*/

bsp/nv32f100x/board/SConscript

@@ -0,0 +1,12 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'board')
+src	= Glob('./src/*.c')
+path = [cwd + '/inc'
+	]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/nv32f100x/board/inc/board.h

@@ -0,0 +1,30 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2017, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-19     Quintin.Z    the first version
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+
+// <o> Internal SRAM memory size[Kbytes] <8>
+#define NV32_SRAM_SIZE         8
+#define NV32_SRAM_END          (0x1FFFF800 + NV32_SRAM_SIZE * 1024)
+
+void rt_hw_board_init(void);
+
+
+#endif

bsp/nv32f100x/board/inc/drv_uart.h

@@ -0,0 +1,23 @@
+/*
+ * File      : drv_uart.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2017, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-19     Quintin.Z    the first version
+ */
+
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+void rt_hw_uart_init(void);
+
+#endif

bsp/nv32f100x/board/inc/start.h

@@ -0,0 +1,9 @@
+/******************************************************************************
+* @brief provide high-level startup routines for NV32Fxx.
+*
+*******************************************************************************/
+
+/* Function prototypes */
+void cpu_identify(void);
+void flash_identify(void);
+void start(void);

bsp/nv32f100x/board/inc/sysinit.h

@@ -0,0 +1,38 @@
+/******************************************************************************
+* @brief provide system init routine/configuration for KExx.
+*
+*******************************************************************************/
+
+/********************************************************************/
+
+#ifndef SYSINIT_H_
+#define SYSINIT_H_
+
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+
+/******************************************************************************
+* Macros
+******************************************************************************/ 
+#define SIM_SCGC_VALUE      0x00003000L  
+
+  
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void sysinit (void);
+void enable_abort_button(void);
+void end_test(void);
+
+/********************************************************************/
+#endif /* SYSINIT_H_ */

bsp/nv32f100x/board/src/board.c

@@ -0,0 +1,91 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2017, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-19     Quintin.Z    the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "sysinit.h"
+#include "board.h"
+#include "drv_uart.h"
+#include "nv32.h"
+
+/* RT_USING_COMPONENTS_INIT */
+#ifdef  RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif
+
+
+#define portNVIC_SYSTICK_CTRL           ( ( volatile uint32_t *) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD           ( ( volatile uint32_t *) 0xe000e014 )
+#define portNVIC_INT_CTRL               ( ( volatile uint32_t *) 0xe000ed04 )
+#define portNVIC_SYSPRI2                ( ( volatile uint32_t *) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK            0x00000004
+#define portNVIC_SYSTICK_INT            0x00000002
+#define portNVIC_SYSTICK_ENABLE         0x00000001
+#define portNVIC_PENDSVSET              0x10000000
+#define portMIN_INTERRUPT_PRIORITY      ( 255UL )
+#define portNVIC_PENDSV_PRI             ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI            ( portMIN_INTERRUPT_PRIORITY << 24UL )
+
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+
+/**
+ * This function will initial STM32 board.
+ */
+void rt_hw_board_init()
+{
+    /* Configure the SysTick */
+    *(portNVIC_SYSTICK_LOAD) = ( 40000000 / RT_TICK_PER_SECOND ) - 1UL;
+    *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+
+    rt_hw_uart_init();
+
+    /* Call components board initial (use INIT_BOARD_EXPORT()) */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+}
+
+long cmd_reset(int argc, char** argv)
+{
+    NVIC_SystemReset();
+
+    return 0;
+}
+
+FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, Reset Board.);
+
+
+
+/*@}*/

bsp/nv32f100x/board/src/drv_spi.c

@@ -0,0 +1,10 @@
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+#ifdef RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif
+
+/* TODO */

bsp/nv32f100x/board/src/drv_uart.c

@@ -0,0 +1,189 @@
+/*
+ * File      : drv_uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2017, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-19     Quintin.Z    the first version
+ */
+
+#include <rtdevice.h>
+#include <board.h>
+#include "drv_uart.h"
+#include "nv32.h"
+#include "uart.h"
+#include "sim.h"
+
+/* NV32 uart driver */
+struct nv32_uart
+{
+    UART_Type* uart_device;
+    IRQn_Type irq;
+};
+
+static rt_err_t nv32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct nv32_uart* uart;
+
+    UART_ConfigBaudrateType uart_config;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart = (struct nv32_uart *)serial->parent.user_data;
+
+    uart_config.u32SysClkHz = BUS_CLK_HZ;
+    uart_config.u32Baudrate = cfg->baud_rate;
+
+    UART_SetBaudrate(uart->uart_device, &uart_config);
+
+
+    if (cfg->data_bits == DATA_BITS_8)
+    {
+        UART_Set8BitMode(uart->uart_device);
+    }
+    else if(cfg->data_bits == DATA_BITS_9)
+    {
+        UART_Set9BitMode(uart->uart_device);
+    }
+
+    if (cfg->stop_bits == STOP_BITS_1)
+    {
+        uart->uart_device->BDH  &= (~UART_BDH_SBNS_MASK);
+    }
+    else if (cfg->stop_bits == STOP_BITS_2)
+    {
+        uart->uart_device->BDH  |= UART_BDH_SBNS_MASK;
+    }
+
+    /* Enable receiver and transmitter */
+    uart->uart_device->C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK );
+
+
+    UART_EnableInterrupt(UART0, UART_RxBuffFullInt);
+    NVIC_EnableIRQ(UART0_IRQn);
+
+
+    return RT_EOK;
+}
+
+static rt_err_t nv32_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct nv32_uart* uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct nv32_uart *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+        case RT_DEVICE_CTRL_CLR_INT:
+            /* disable rx irq */
+            NVIC_DisableIRQ(uart->irq);
+            break;
+        case RT_DEVICE_CTRL_SET_INT:
+            /* enable rx irq */
+            NVIC_EnableIRQ(uart->irq);
+            break;
+    }
+
+    return RT_EOK;
+}
+
+static int nv32_putc(struct rt_serial_device *serial, char c)
+{
+    struct nv32_uart* uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct nv32_uart *)serial->parent.user_data;
+
+    while (!(uart->uart_device->S1 & UART_S1_TDRE_MASK));
+
+    uart->uart_device->D = (uint8_t)c;
+
+    return 1;
+}
+
+
+static int nv32_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct nv32_uart* uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct nv32_uart *)serial->parent.user_data;
+
+    ch = -1;
+    if (uart->uart_device->S1 & UART_S1_RDRF_MASK)
+    {
+        ch = uart->uart_device->D;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops nv32_uart_ops =
+{
+    nv32_configure,
+    nv32_control,
+    nv32_putc,
+    nv32_getc,
+};
+
+#ifdef RT_USING_UART0
+
+struct nv32_uart uart0 =
+{
+    UART0,
+    UART0_IRQn,
+};
+
+struct rt_serial_device serial0;
+
+void UART0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if(UART0->S1 & UART_S1_RDRF_MASK)
+    {
+        rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+#endif
+
+
+void rt_hw_uart_init(void)
+{
+    struct nv32_uart* uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef RT_USING_UART0
+    uart = &uart0;
+
+    serial0.ops    = &nv32_uart_ops;
+    serial0.config = config;
+
+
+    SIM->PINSEL |= SIM_PINSEL_UART0PS_MASK;
+
+    SIM->SCGC |= SIM_SCGC_UART0_MASK;
+
+    uart->uart_device->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK );
+
+    /* Configure the UART for 8-bit mode, no parity */
+    uart->uart_device->C1 = 0;
+
+    rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
+#endif
+
+}
+

bsp/nv32f100x/board/src/start.c

@@ -0,0 +1,36 @@
+/******************************************************************************
+* @brief provide high-level startup routines for NV32Fxx.
+*
+*******************************************************************************/
+
+#include "start.h"
+#include "common.h"
+#include "wdog.h"
+#include "sysinit.h"
+
+/********************************************************************/
+/********************************************************************/
+/*!
+ * \brief   flash SystemInit
+ * \return  None
+ *
+ * this is a system initialization function which dediu16Cated in Keil
+ * others complier don't use it.
+ * it is similar to start function
+ */
+void SystemInit( void )
+{
+#if !defined(ENABLE_WDOG)
+    /* Disable the watchdog ETMer */
+    WDOG_Disable();
+#else
+    /* Disable the watchdog ETMer but enable update */
+    WDOG_DisableWDOGEnableUpdate();
+#endif
+
+    sysinit();
+
+}
+
+
+

bsp/nv32f100x/board/src/sysinit.c

@@ -0,0 +1,124 @@
+/*****************************************************************************
+* @brief provide system init routine/configuration for NV32Fxx.
+*
+*******************************************************************************/
+
+#include "common.h"
+#include "sysinit.h"
+#include "sim.h"
+#include "uart.h"
+#include "ics.h"
+
+/********************************************************************/
+
+uint16_t global_pass_count = 0;
+uint16_t global_fail_count = 0;
+
+
+void print_sys_log(void);
+void UART_InitPrint(void);
+
+/*****************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+* @function name: sysinit
+*
+* @brief  initalize system including SIM, ICS, UART, etc
+*
+* @param  none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void sysinit (void)
+{
+    SIM_ConfigType  sSIMConfig = {{0}, 0};
+    ICS_ConfigType  sICSConfig = {0};
+
+    /* initialize the Pass/Fail counts to 0 */
+    global_pass_count = 0;
+    global_fail_count = 0;
+
+    EFMCR &= 0xFFFF0001; // set wait state 1
+
+#if defined(TRIM_IRC)
+    /* if not trimmed, do trim first */
+    ICS_Trim(ICS_TRIM_VALUE);
+#endif
+    /*
+     * Enable SWD pin, RESET pin
+     */
+    /*
+     * NOTE: please make sure other register bits are also write-once and
+     * need add other bit mask here if needed.
+     */
+#if defined(SPI0_PINREMAP)
+    sSIMConfig.u32PinSel |= SIM_PINSEL_SPI0PS_MASK;
+#endif
+
+#if defined(OUTPUT_BUSCLK)
+    sSIMConfig.sBits.bEnableCLKOUT = 1;      /* output bus clock if enabled */
+#endif
+
+#if defined(DISABLE_NMI)
+    sSIMConfig.sBits.bDisableNMI = 1;
+#endif
+
+#if !defined(CPU_NV32M3)
+    /* make sure clocks to peripheral modules are enabled */
+    sSIMConfig.u32SCGC |= SIM_SCGC_SWD_MASK | SIM_SCGC_FLASH_MASK |
+                          SIM_SCGC_UART0_MASK | SIM_SCGC_UART1_MASK |
+                          SIM_SCGC_UART2_MASK
+                          ;
+#else
+    sSIMConfig.u32SCGC |= SIM_SCGC_SWD_MASK | SIM_SCGC_FLASH_MASK |
+                          SIM_SCGC_UART0_MASK
+                          ;
+#endif
+
+#if !defined(CPU_NV32)
+    /* bus clock divided by 2 */
+    // sSIMConfig.u32BusDiv |= SIM_CLKDIV_OUTDIV2_MASK;
+#endif
+
+//  sSIMConfig.sBits.bBusDiv |= SIM_BUSDIV_BUSDIV_MASK;
+
+    SIM_Init(&sSIMConfig);                   /* initialize SIM */
+
+#if defined(XOSC_STOP_ENABLE)
+    sICSConfig.oscConfig.bStopEnable = 1;    /*  enabled in stop mode */
+#endif
+
+#if defined(CRYST_HIGH_GAIN)
+    sICSConfig.oscConfig.bGain = 1;           /* high gain */
+#endif
+
+
+#if  (EXT_CLK_FREQ_KHZ >=4000)
+    sICSConfig.oscConfig.bRange = 1;           /* high range */
+#endif
+
+    sICSConfig.oscConfig.bEnable = 1;          /* enable OSC */
+    sICSConfig.u32ClkFreq = EXT_CLK_FREQ_KHZ;
+
+#if     defined(USE_FEE)
+    sICSConfig.u8ClkMode = ICS_CLK_MODE_FEE;
+#elif   defined(USE_FBE_OSC)
+    sICSConfig.u8ClkMode = ICS_CLK_MODE_FBE_OSC;
+#elif   defined(USE_FEE_OSC)
+    sICSConfig.u8ClkMode = ICS_CLK_MODE_FEE_OSC;
+#elif   defined(USE_FBILP)
+    sICSConfig.u8ClkMode = ICS_CLK_MODE_FBILP;
+#elif   defined(USE_FBELP)
+    sICSConfig.u8ClkMode = ICS_CLK_MODE_FBELP;
+#endif
+
+    ICS_Init(&sICSConfig);   /* initialize ICS */
+
+
+}
+
+void NMI_Handler(void)
+{
+    while(1);
+}

bsp/nv32f100x/lib/SConscript

@@ -0,0 +1,16 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'lib')
+src	= Glob('./src/*.c')
+
+src += Glob('./src/*.s')
+path = [cwd + '/inc'
+	]
+
+CPPDEFINES = ['NV32', 'KEIL']
+
+group = DefineGroup('Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/nv32f100x/lib/inc/BME.h

@@ -0,0 +1,606 @@
+
+/******************************************************************************
+******************************************************************************/
+
+#ifndef __BME_H
+#define __BME_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* BME operation code
+*
+*//*! @addtogroup BME_OPCode
+* @{
+*******************************************************************************/
+
+#define BME_OPCODE_AND		1               /*!< AND opcode */
+#define BME_OPCODE_OR		2               /*!< OR opcode */
+#define BME_OPCODE_XOR		3               /*!< XOR opcode */
+#define BME_OPCODE_BITFIELD	4               /*!< Bit field opcode */
+
+#define BME_OPCODE_BIT_CLEAR    2           /*!< Bit clear opcode */
+#define BME_OPCODE_BIT_SET      3           /*!< Bit set opcode */
+/*! @} End of BME_OPCode                                                   */
+
+/******************************************************************************
+* BME macro used to generate hardcoded BME addresses
+*
+*//*! @addtogroup BME_Utilities
+* @{
+*******************************************************************************/
+
+/******************************************************************************
+* macro used to generate hardcoded AND address.
+*
+*******************************************************************************/
+
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME AND operation addresss (hardcoded 32-bit address).
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+#define BME_AND(ADDR)           (*(volatile uint32_t *)(((uint32_t)ADDR) | (BME_OPCODE_AND<<26)))  
+
+/******************************************************************************
+* macro used to generate hardcoded OR address.
+*
+*******************************************************************************/
+
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME OR operation addresss (hardcoded 32-bit address).
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_OR(ADDR)           (*(volatile uint32_t *)(((uint32_t)ADDR) | (BME_OPCODE_OR<<26)))     
+
+
+/******************************************************************************
+* macro used to generate hardcoded XOR address.
+*
+*******************************************************************************/
+
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME XOR operation addresss (hardcoded 32-bit address).
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_XOR(ADDR)           (*(volatile uint32_t *)(((uint32_t)ADDR) | (BME_OPCODE_XOR<<26)))   
+
+#if !defined(BME_SANITY_CHECK)
+   /*!
+     * @brief This is fastest way for BME without sanity check.
+     */
+  /******************************************************************************
+    * macro used to generate hardcoded load 1 bit clear address (LAC1).
+    *
+    *******************************************************************************/
+  /*****************************************************************************//*!
+       *
+       * @brief  generates BME bit clear operation addresss (hardcoded 32-bit address).
+       *        
+       * @param[in]   ADDR  32-bit address.
+       * @param[in]   bit     bit number, 0-based.
+       *  
+       * @return  hardcoded 32-bit address.
+       *
+       * @ Pass/ Fail criteria: none.
+       *
+    *****************************************************************************/
+    
+    #define BME_BIT_CLEAR(ADDR,bit)        (*(volatile uint32_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_CLEAR <<26)  \
+                                  | ((bit)<<21)))                                                
+
+  /******************************************************************************
+    * macro used to generate hardcoded load 1 bit set address (LAS1).
+    *
+    *******************************************************************************/
+   /*****************************************************************************//*!
+         *
+         * @brief  generates BME bit set operation addresss (hardcoded 32-bit address).
+         *        
+         * @param[in]   ADDR  32-bit address.
+         * @param[in]   bit     bit number, 0-based.
+         *  
+         * @return  hardcoded 32-bit address.
+         *
+         * @ Pass/ Fail criteria: none.
+         *
+      *****************************************************************************/
+
+    #define BME_BIT_SET(ADDR,bit)        (*(volatile uint32_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_SET <<26)  \
+                                  | ((bit)<<21)))                                                
+
+  /******************************************************************************
+    * macro used to generate hardcoded bit field insert address (BFI).
+    *
+    *******************************************************************************/
+   /*****************************************************************************//*!
+         *
+         * @brief  generates BME bitfield insert operation addresss (hardcoded 32-bit address).
+         *        
+         * @param[in]   ADDR  32-bit address.
+         * @param[in]   bit      bit number, 0-based.
+         * @param[in]   width  bitfield width, 1-based.
+         *  
+         * @return  hardcoded 32-bit address.
+         *
+         * @ Pass/ Fail criteria: none.
+         *
+      *****************************************************************************/    
+    #define BME_BITFIELD_INSERT(ADDR,bit,width)        (*(volatile uint32_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit)<<23) | ((width-1))<<19))                        
+
+
+  /******************************************************************************
+    * macro used to generate hardcoded bit field extract address (UBFX).
+    *
+    *******************************************************************************/
+      /*****************************************************************************//*!
+              *
+              * @brief  generates BME bitfield extract operation addresss (hardcoded 32-bit address).
+              *        
+              * @param[in]   ADDR  32-bit address.
+              * @param[in]   bit      bit number, 0-based.
+              * @param[in]   width  bitfield width, 1-based.
+              *  
+              * @return  hardcoded 32-bit address.
+              *
+              * @ Pass/ Fail criteria: none.
+              *
+           *****************************************************************************/    
+
+    #define BME_BITFIELD_EXTRACT(ADDR,bit,width)        (*(volatile uint32_t *)(((uint32_t)ADDR)    \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit)<<23) | ((width-1))<<19))                            
+#else
+    /*!
+     * @brief This is slow way for BME as it has sanity check.
+     */
+    /******************************************************************************
+    * macro used to generate hardcoded load 1 bit clear address (LAC1).
+    *
+    *******************************************************************************/
+    #define BME_BIT_CLEAR(ADDR,bit)        (*(volatile uint32_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_CLEAR <<26)  \
+                                  | ((bit & 0x1F)<<21)))                                                /*!< Bit clear operation */
+
+    /******************************************************************************
+    * macro used to generate hardcoded load 1 bit set address (LAS1).
+    *
+    *******************************************************************************/
+    #define BME_BIT_SET(ADDR,bit)        (*(volatile uint32_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_SET <<26)  \
+                                  | ((bit & 0x1F)<<21)))                                                /*!< Bit set operation */
+
+    /******************************************************************************
+    * macro used to generate hardcoded bit field insert address (BFI).
+    *
+    *******************************************************************************/
+    #define BME_BITFIELD_INSERT(ADDR,bit,width)        (*(volatile uint32_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit & 0x1F)<<23) | ((width-1) & 0xF)<<19))                        /*!< Bitfield insert operation */
+
+
+    /******************************************************************************
+    * macro used to generate hardcoded bit field extract address (UBFX).
+    *
+    *******************************************************************************/
+    #define BME_BITFIELD_EXTRACT(ADDR,bit,width)        (*(volatile uint32_t *)(((uint32_t)ADDR)    \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit & 0x1F)<<23) | ((width-1) & 0xF)<<19))                        /*!< Bitfield extract operation */
+
+#endif
+
+/******************************************************************************
+* The following macros are used to generate hardcoded address for 8-bit operation.
+*
+*******************************************************************************/
+
+/******************************************************************************
+* macro used to generate hardcoded AND address for 8-bit operation.
+*
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME AND operation addresss (hardcoded 32-bit address) for 8-bit data.
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_AND_8b(ADDR)           (*(volatile uint8_t *)(((uint32_t)ADDR) | (BME_OPCODE_AND<<26)))   
+
+/******************************************************************************
+* macro used to generate hardcoded OR address.
+*
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME OR operation addresss (hardcoded 32-bit address) for 8-bit data.
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_OR_8b(ADDR)           (*(volatile uint8_t *)(((uint32_t)ADDR) | (BME_OPCODE_OR<<26)))    
+
+
+/******************************************************************************
+* macro used to generate hardcoded XOR address.
+*
+*******************************************************************************/
+
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME XOR operation addresss (hardcoded 32-bit address) for 8-bit data.
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_XOR_8b(ADDR)           (*(volatile uint8_t *)(((uint32_t)ADDR) | (BME_OPCODE_XOR<<26)))   
+
+#if !defined(BME_SANITY_CHECK)
+     /*!
+         * @brief This is fastest way for BME without sanity check.
+         */
+    /******************************************************************************
+        * macro used to generate hardcoded load 1 bit clear address (LAC1).
+        *
+        *******************************************************************************/
+
+    /*****************************************************************************//*!
+         *
+         * @brief  generates BME bit clear operation addresss (hardcoded 32-bit address) for 8-bit data.
+         *        
+         * @param[in]   ADDR  32-bit address.
+         * @param[in]   bit     bit number, 0-based.
+         *  
+         * @return  hardcoded 32-bit address.
+         *
+         * @ Pass/ Fail criteria: none.
+         *
+      *****************************************************************************/
+    
+    #define BME_BIT_CLEAR_8b(ADDR,bit)        (*(volatile uint8_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_CLEAR <<26)  \
+                                  | ((bit)<<21)))                                                
+
+    /******************************************************************************
+        * macro used to generate hardcoded load 1 bit set address (LAS1).
+        *
+        *******************************************************************************/
+    /*****************************************************************************//*!
+             *
+             * @brief  generates BME bit set operation addresss (hardcoded 32-bit address) for 8-bit data.
+             *        
+             * @param[in]   ADDR  32-bit address.
+             * @param[in]   bit     bit number, 0-based.
+             *  
+             * @return  hardcoded 32-bit address.
+             *
+             * @ Pass/ Fail criteria: none.
+             *
+        *****************************************************************************/
+    
+    #define BME_BIT_SET_8b(ADDR,bit)        (*(volatile uint8_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_SET <<26)  \
+                                  | ((bit)<<21)))                                                
+
+  /******************************************************************************
+    * macro used to generate hardcoded bit field insert address (BFI).
+    *
+    *******************************************************************************/
+
+    /*****************************************************************************//*!
+          *
+          * @brief  generates BME bitfield insert operation addresss (hardcoded 32-bit address) for 8-bit data.
+          *        
+          * @param[in]   ADDR  32-bit address.
+          * @param[in]   bit      bit number, 0-based.
+          * @param[in]   width  bitfield width, 1-based.
+          *  
+          * @return  hardcoded 32-bit address.
+          *
+          * @ Pass/ Fail criteria: none.
+          *
+       *****************************************************************************/        
+
+    #define BME_BITFIELD_INSERT_8b(ADDR,bit,width)        (*(volatile uint8_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit)<<23) | ((width-1))<<19))                        
+  /******************************************************************************
+    * macro used to generate hardcoded bit field extract address (UBFX).
+    *
+    *******************************************************************************/
+   /*****************************************************************************//*!
+         *
+         * @brief  generates BME bitfield extract operation addresss (hardcoded 32-bit address) for 8-bit data.
+         *        
+         * @param[in]   ADDR  32-bit address.
+         * @param[in]   bit      bit number, 0-based.
+         * @param[in]   width  bitfield width, 1-based.
+         *  
+         * @return  hardcoded 32-bit address.
+         *
+         * @ Pass/ Fail criteria: none.
+         *
+      *****************************************************************************/        
+    #define BME_BITFIELD_EXTRACT_8b(ADDR,bit,width)        (*(volatile uint8_t *)(((uint32_t)ADDR)    \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit<<23) | ((width-1))<<19))                        
+#else
+    /*!
+     * @brief This is slow way for BME as it has sanity check.
+     */
+    /******************************************************************************
+    * macro used to generate hardcoded load 1 bit clear address (LAC1).
+    *
+    *******************************************************************************/
+    #define BME_BIT_CLEAR_8b(ADDR,bit)        (*(volatile uint8_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_CLEAR <<26)  \
+                                  | ((bit & 0x1F)<<21)))                                                /*!< Bit clear operation on 8-bit*/
+
+    /******************************************************************************
+    * macro used to generate hardcoded load 1 bit set address (LAS1).
+    *
+    *******************************************************************************/
+    #define BME_BIT_SET_8b(ADDR,bit)        (*(volatile uint8_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_SET <<26)  \
+                                  | ((bit & 0x1F)<<21)))                                                /*!< Bit set operation on 8-bit */
+
+    /******************************************************************************
+    * macro used to generate hardcoded bit field insert address (BFI).
+    *
+    *******************************************************************************/
+    #define BME_BITFIELD_INSERT_8b(ADDR,bit,width)        (*(volatile uint8_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit & 0x1F)<<23) | ((width-1) & 0xF)<<19))                        /*!< Bitfield insert operation on 8-bit */
+
+  /******************************************************************************
+    * macro used to generate hardcoded bit field extract address (UBFX).
+    *
+    *******************************************************************************/
+
+    #define BME_BITFIELD_EXTRACT_8b(ADDR,bit,width)        (*(volatile uint8_t *)(((uint32_t)ADDR)    \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit & 0x1F)<<23) | ((width-1) & 0xF)<<19))                        /*!< Bitfield extract operation on 8-bit*/
+#endif
+
+
+/******************************************************************************
+* The following macros are used to generate hardcoded address for 16-bit operation.
+*
+*******************************************************************************/
+
+/******************************************************************************
+* macro used to generate hardcoded AND address for 16-bit operation.
+*
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME AND operation addresss (hardcoded 32-bit address) for 16-bit data.
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_AND_16b(ADDR)           (*(volatile uint16_t *)(((uint32_t)ADDR) | (BME_OPCODE_AND<<26)))   
+
+/******************************************************************************
+* macro used to generate hardcoded OR address.
+*
+*******************************************************************************/
+
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME OR operation addresss (hardcoded 32-bit address) for 16-bit data.
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_OR_16b(ADDR)           (*(volatile uint16_t *)(((uint32_t)ADDR) | (BME_OPCODE_OR<<26)))    
+
+
+/******************************************************************************
+* macro used to generate hardcoded XOR address.
+*
+*******************************************************************************/
+
+/*****************************************************************************//*!
+   *
+   * @brief  generates BME XOR operation addresss (hardcoded 32-bit address) for 16-bit data.
+   *        
+   * @param[in]   ADDR  32-bit address.
+   *  
+   * @return  hardcoded 32-bit address.
+   *
+   * @ Pass/ Fail criteria: none.
+   *
+*****************************************************************************/
+
+#define BME_XOR_16b(ADDR)           (*(volatile uint16_t *)(((uint32_t)ADDR) | (BME_OPCODE_XOR<<26)))   
+
+
+#if !defined(BME_SANITY_CHECK)
+  /*!
+     * @brief This is fastest way for BME without sanity check.
+     */
+
+  /******************************************************************************
+    * macro used to generate hardcoded load 1 bit clear address (LAC1).
+    *
+    *******************************************************************************/
+    /*****************************************************************************//*!
+             *
+             * @brief  generates BME bit clear operation addresss (hardcoded 32-bit address) for 16-bit data.
+             *        
+             * @param[in]   ADDR  32-bit address.
+             * @param[in]   bit     bit number, 0-based.
+             *  
+             * @return  hardcoded 32-bit address.
+             *
+             * @ Pass/ Fail criteria: none.
+             *
+        *****************************************************************************/
+    
+    #define BME_BIT_CLEAR_16b(ADDR,bit)        (*(volatile uint16_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_CLEAR <<26)  \
+                                  | ((bit)<<21)))                                               
+
+    /******************************************************************************
+        * macro used to generate hardcoded load 1 bit set address (LAS1).
+        *
+        *******************************************************************************/
+    /*****************************************************************************//*!
+             *
+             * @brief  generates BME bit set operation addresss (hardcoded 32-bit address) for 16-bit data.
+             *        
+             * @param[in]   ADDR  32-bit address.
+             * @param[in]   bit     bit number, 0-based.
+             *  
+             * @return  hardcoded 32-bit address.
+             *
+             * @ Pass/ Fail criteria: none.
+             *
+        *****************************************************************************/
+    
+    #define BME_BIT_SET_16b(ADDR,bit)        (*(volatile uint16_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_SET <<26)  \
+                                  | ((bit)<<21)))                                                
+
+  /******************************************************************************
+    * macro used to generate hardcoded bit field insert address (BFI).
+    *
+    *******************************************************************************/
+    /*****************************************************************************//*!
+          *
+          * @brief  generates BME bitfield insert operation addresss (hardcoded 32-bit address) for 16-bit data.
+          *        
+          * @param[in]   ADDR  32-bit address.
+          * @param[in]   bit      bit number, 0-based.
+          * @param[in]   width  bitfield width, 1-based.
+          *  
+          * @return  hardcoded 32-bit address.
+          *
+          * @ Pass/ Fail criteria: none.
+          *
+       *****************************************************************************/        
+    
+    #define BME_BITFIELD_INSERT_16b(ADDR,bit,width)        (*(volatile uint16_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit)<<23) | ((width-1))<<19))                        
+
+
+  /******************************************************************************
+    * macro used to generate hardcoded bit field extract address (UBFX).
+    *
+    *******************************************************************************/
+    /*****************************************************************************//*!
+          *
+          * @brief  generates BME bitfield extract operation addresss (hardcoded 32-bit address) for 16-bit data.
+          *        
+          * @param[in]   ADDR  32-bit address.
+          * @param[in]   bit      bit number, 0-based.
+          * @param[in]   width  bitfield width, 1-based.
+          *  
+          * @return  hardcoded 32-bit address.
+          *
+          * @ Pass/ Fail criteria: none.
+          *
+       *****************************************************************************/        
+
+    #define BME_BITFIELD_EXTRACT_16b(ADDR,bit,width)        (*(volatile uint16_t *)(((uint32_t)ADDR)    \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit)<<23) | ((width-1))<<19))                        
+
+#else
+    /*!
+     * @brief This is slow way for BME as it has sanity check.
+     */
+    /******************************************************************************
+    * macro used to generate hardcoded load 1 bit clear address (LAC1).
+    *
+    *******************************************************************************/
+    #define BME_BIT_CLEAR_16b(ADDR,bit)        (*(volatile uint16_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_CLEAR <<26)  \
+                                  | ((bit & 0x1F)<<21)))                                                /*!< Bit clear operation on 16-bit*/
+
+    /******************************************************************************
+    * macro used to generate hardcoded load 1 bit set address (LAS1).
+    *
+    *******************************************************************************/
+    #define BME_BIT_SET_16b(ADDR,bit)        (*(volatile uint16_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BIT_SET <<26)  \
+                                  | ((bit & 0x1F)<<21)))                                                /*!< Bit set operation on 16-bit */
+
+    /******************************************************************************
+    * macro used to generate hardcoded bit field insert address (BFI).
+    *
+    *******************************************************************************/
+    #define BME_BITFIELD_INSERT_16b(ADDR,bit,width)        (*(volatile uint16_t *)(((uint32_t)ADDR)   \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit & 0x1F)<<23) | ((width-1) & 0xF)<<19))                        /*!< Bitfield insert operation on 16-bit */
+
+
+    /******************************************************************************
+    * macro used to generate hardcoded bit field extract address (UBFX).
+    *
+    *******************************************************************************/
+    #define BME_BITFIELD_EXTRACT_16b(ADDR,bit,width)        (*(volatile uint16_t *)(((uint32_t)ADDR)    \
+                                  | (BME_OPCODE_BITFIELD <<26)  \
+                                  | ((bit & 0x1F)<<23) | ((width-1) & 0xF)<<19))                        /*!< Bitfield extract operation on 16-bit*/
+#endif
+
+/*! @} End of BME_Utilities                                                   */
+#ifdef __cplusplus
+}
+#endif
+#endif /* __BME_H */
+
+

bsp/nv32f100x/lib/inc/NV32.h

@@ -0,0 +1,2829 @@
+/*
+ * @brief CMSIS Peripheral Access Layer for NV32
+ *
+ * CMSIS Peripheral Access Layer for NV32
+ */
+
+#if !defined(NV32_H_)
+#define NV32_H_                               /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0004u
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M0 SV Hard Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M0 SV Call Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M0 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M0 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  Reserved16_IRQn              = 0,                /**< Reserved interrupt 16 */
+  Reserved17_IRQn              = 1,                /**< Reserved interrupt 17 */
+  Reserved18_IRQn              = 2,                /**< Reserved interrupt 18 */
+  Reserved19_IRQn              = 3,                /**< Reserved interrupt 19 */
+  Reserved20_IRQn              = 4,                /**< Reserved interrupt 20 */
+  ETMRH_IRQn                   = 5,                /**< ETMRH command complete/read collision interrupt */
+  LVD_LVW_IRQn                 = 6,                /**< Low Voltage Detect, Low Voltage Warning */
+  IRQ_IRQn                     = 7,                /**< External interrupt */
+  I2C0_IRQn                    = 8,                /**< I2C0 interrupt */
+  Reserved25_IRQn              = 9,                /**< Reserved interrupt 25 */
+  SPI0_IRQn                    = 10,               /**< SPI0 interrupt */
+  SPI1_IRQn                    = 11,               /**< SPI1 interrupt */
+  UART0_IRQn                   = 12,               /**< UART0 status/error interrupt */
+  UART1_IRQn                   = 13,               /**< UART1 status/error interrupt */
+  UART2_IRQn                   = 14,               /**< UART2 status/error interrupt */
+  ADC0_IRQn                    = 15,               /**< ADC0 interrupt */
+  ACMP0_IRQn                   = 16,               /**< ACMP0 interrupt */
+  ETM0_IRQn                    = 17,               /**< ETM0 Single interrupt vector for all sources */
+  ETM1_IRQn                    = 18,               /**< ETM1 Single interrupt vector for all sources */
+  ETM2_IRQn                    = 19,               /**< ETM2 Single interrupt vector for all sources */
+  RTC_IRQn                     = 20,               /**< RTC overflow */
+  ACMP1_IRQn                   = 21,               /**< ACMP1 interrupt */
+  PIT_CH0_IRQn                 = 22,               /**< PIT CH0 overflow */
+  PIT_CH1_IRQn                 = 23,               /**< PIT CH1 overflow */
+  KBI0_IRQn                    = 24,               /**< Keyboard interrupt 0 */
+  KBI1_IRQn                    = 25,               /**< Keyboard interrupt 1 */
+  Reserved42_IRQn              = 26,               /**< Reserved interrupt 42 */
+  ICS_IRQn                     = 27,               /**< ICS interrupt */
+  Watchdog_IRQn                = 28,               /**< WDOG Interrupt */
+  Reserved45_IRQn              = 29,               /**< Reserved interrupt 45 */
+  Reserved46_IRQn              = 30,               /**< Reserved interrupt 46 */
+  Reserved47_IRQn              = 31                /**< Reserved interrupt 47 */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M0 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV                  0x0000    /**< Core revision r0p0 */
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT                 1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               2         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h"              /* Core Peripheral Access Layer */
+//#include "system_nv32.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ACMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ACMP_Peripheral_Access_Layer ACMP Peripheral Access Layer
+ * @{
+ */
+
+/** ACMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CS;                                 /**< ACMP Control and Status Register, offset: 0x0 */
+  __IO uint8_t C0;                                 /**< ACMP Control Register 0, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< ACMP Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< ACMP Control Register 2, offset: 0x3 */
+} ACMP_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ACMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ACMP_Register_Masks ACMP Register Masks
+ * @{
+ */
+
+/* CS Bit Fields */
+#define ACMP_CS_ACMOD_MASK                       0x3u
+#define ACMP_CS_ACMOD_SHIFT                      0
+#define ACMP_CS_ACMOD(x)                         (((uint8_t)(((uint8_t)(x))<<ACMP_CS_ACMOD_SHIFT))&ACMP_CS_ACMOD_MASK)
+#define ACMP_CS_ACOPE_MASK                       0x4u
+#define ACMP_CS_ACOPE_SHIFT                      2
+#define ACMP_CS_ACO_MASK                         0x8u
+#define ACMP_CS_ACO_SHIFT                        3
+#define ACMP_CS_ACIE_MASK                        0x10u
+#define ACMP_CS_ACIE_SHIFT                       4
+#define ACMP_CS_ACF_MASK                         0x20u
+#define ACMP_CS_ACF_SHIFT                        5
+#define ACMP_CS_HYST_MASK                        0x40u
+#define ACMP_CS_HYST_SHIFT                       6
+#define ACMP_CS_ACE_MASK                         0x80u
+#define ACMP_CS_ACE_SHIFT                        7
+/* C0 Bit Fields */
+#define ACMP_C0_ACNSEL_MASK                      0x3u
+#define ACMP_C0_ACNSEL_SHIFT                     0
+#define ACMP_C0_ACNSEL(x)                        (((uint8_t)(((uint8_t)(x))<<ACMP_C0_ACNSEL_SHIFT))&ACMP_C0_ACNSEL_MASK)
+#define ACMP_C0_ACPSEL_MASK                      0x30u
+#define ACMP_C0_ACPSEL_SHIFT                     4
+#define ACMP_C0_ACPSEL(x)                        (((uint8_t)(((uint8_t)(x))<<ACMP_C0_ACPSEL_SHIFT))&ACMP_C0_ACPSEL_MASK)
+/* C1 Bit Fields */
+#define ACMP_C1_DACVAL_MASK                      0x3Fu
+#define ACMP_C1_DACVAL_SHIFT                     0
+#define ACMP_C1_DACVAL(x)                        (((uint8_t)(((uint8_t)(x))<<ACMP_C1_DACVAL_SHIFT))&ACMP_C1_DACVAL_MASK)
+#define ACMP_C1_DACREF_MASK                      0x40u
+#define ACMP_C1_DACREF_SHIFT                     6
+#define ACMP_C1_DACEN_MASK                       0x80u
+#define ACMP_C1_DACEN_SHIFT                      7
+/* C2 Bit Fields */
+#define ACMP_C2_ACIPE_MASK                       0x7u
+#define ACMP_C2_ACIPE_SHIFT                      0
+#define ACMP_C2_ACIPE(x)                         (((uint8_t)(((uint8_t)(x))<<ACMP_C2_ACIPE_SHIFT))&ACMP_C2_ACIPE_MASK)
+
+/*!
+ * @}
+ */ /* end of group ACMP_Register_Masks */
+
+
+/* ACMP - Peripheral instance base addresses */
+/** Peripheral ACMP0 base address */
+#define ACMP0_BASE                               (0x40073000u)
+/** Peripheral ACMP0 base pointer */
+#define ACMP0                                    ((ACMP_Type *)ACMP0_BASE)
+/** Peripheral ACMP1 base address */
+#define ACMP1_BASE                               (0x40074000u)
+/** Peripheral ACMP1 base pointer */
+#define ACMP1                                    ((ACMP_Type *)ACMP1_BASE)
+/** Array initializer of ACMP peripheral base pointers */
+#define ACMP_BASES                               { ACMP0, ACMP1 }
+
+/*!
+ * @}
+ */ /* end of group ACMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1;                               /**< Status and Control Register 1, offset: 0x0 */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x4 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x8 */
+  __IO uint32_t SC4;                               /**< Status and Control Register 4, offset: 0xC */
+  __I  uint32_t R;                                 /**< Conversion Result Register, offset: 0x10 */
+  __IO uint32_t CV;                                /**< Compare Value Register, offset: 0x14 */
+  __IO uint32_t APCTL1;                            /**< Pin Control 1 Register, offset: 0x18 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK                        0x1Fu
+#define ADC_SC1_ADCH_SHIFT                       0
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_ADCO_MASK                        0x20u
+#define ADC_SC1_ADCO_SHIFT                       5
+#define ADC_SC1_AIEN_MASK                        0x40u
+#define ADC_SC1_AIEN_SHIFT                       6
+#define ADC_SC1_COCO_MASK                        0x80u
+#define ADC_SC1_COCO_SHIFT                       7
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK                      0x3u
+#define ADC_SC2_REFSEL_SHIFT                     0
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_FFULL_MASK                       0x4u
+#define ADC_SC2_FFULL_SHIFT                      2
+#define ADC_SC2_FEMPTY_MASK                      0x8u
+#define ADC_SC2_FEMPTY_SHIFT                     3
+#define ADC_SC2_ACFGT_MASK                       0x10u
+#define ADC_SC2_ACFGT_SHIFT                      4
+#define ADC_SC2_ACFE_MASK                        0x20u
+#define ADC_SC2_ACFE_SHIFT                       5
+#define ADC_SC2_ADTRG_MASK                       0x40u
+#define ADC_SC2_ADTRG_SHIFT                      6
+#define ADC_SC2_ADACT_MASK                       0x80u
+#define ADC_SC2_ADACT_SHIFT                      7
+/* SC3 Bit Fields */
+#define ADC_SC3_ADICLK_MASK                      0x3u
+#define ADC_SC3_ADICLK_SHIFT                     0
+#define ADC_SC3_ADICLK(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADICLK_SHIFT))&ADC_SC3_ADICLK_MASK)
+#define ADC_SC3_MODE_MASK                        0xCu
+#define ADC_SC3_MODE_SHIFT                       2
+#define ADC_SC3_MODE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_MODE_SHIFT))&ADC_SC3_MODE_MASK)
+#define ADC_SC3_ADLSMP_MASK                      0x10u
+#define ADC_SC3_ADLSMP_SHIFT                     4
+#define ADC_SC3_ADIV_MASK                        0x60u
+#define ADC_SC3_ADIV_SHIFT                       5
+#define ADC_SC3_ADIV(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADIV_SHIFT))&ADC_SC3_ADIV_MASK)
+#define ADC_SC3_ADLPC_MASK                       0x80u
+#define ADC_SC3_ADLPC_SHIFT                      7
+/* SC4 Bit Fields */
+#define ADC_SC4_AFDEP_MASK                       0x7u
+#define ADC_SC4_AFDEP_SHIFT                      0
+#define ADC_SC4_AFDEP(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC4_AFDEP_SHIFT))&ADC_SC4_AFDEP_MASK)
+#define ADC_SC4_ACFSEL_MASK                      0x20u
+#define ADC_SC4_ACFSEL_SHIFT                     5
+#define ADC_SC4_ASCANE_MASK                      0x40u
+#define ADC_SC4_ASCANE_SHIFT                     6
+/* R Bit Fields */
+#define ADC_R_ADR_MASK                           0xFFFu
+#define ADC_R_ADR_SHIFT                          0
+#define ADC_R_ADR(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_R_ADR_SHIFT))&ADC_R_ADR_MASK)
+/* CV Bit Fields */
+#define ADC_CV_CV_MASK                           0xFFFu
+#define ADC_CV_CV_SHIFT                          0
+#define ADC_CV_CV(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_CV_CV_SHIFT))&ADC_CV_CV_MASK)
+/* APCTL1 Bit Fields */
+#define ADC_APCTL1_ADPC_MASK                     0xFFFFFFFFu
+#define ADC_APCTL1_ADPC_SHIFT                    0
+#define ADC_APCTL1_ADPC(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_APCTL1_ADPC_SHIFT))&ADC_APCTL1_ADPC_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC base address */
+#define ADC_BASE                                 (0x4003B000u)
+/** Peripheral ADC base pointer */
+#define ADC                                      ((ADC_Type *)ADC_BASE)
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASES                                { ADC }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t DATAL;                             /**< CRC_DATAL register., offset: 0x0 */
+      __IO uint16_t DATAH;                             /**< CRC_DATAH register., offset: 0x2 */
+    } ACCESS16BIT;
+    __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t DATALL;                             /**< CRC_DATALL register., offset: 0x0 */
+      __IO uint8_t DATALU;                             /**< CRC_DATALU register., offset: 0x1 */
+      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register., offset: 0x2 */
+      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register., offset: 0x3 */
+    } ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register., offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register., offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register., offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register., offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register., offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register., offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x8 */
+    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+           uint8_t RESERVED_0[3];
+      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
+    } CTRL_ACCESS8BIT;
+  };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* DATAL Bit Fields */
+#define CRC_DATAL_DATAL_MASK                     0xFFFFu
+#define CRC_DATAL_DATAL_SHIFT                    0
+#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
+/* DATAH Bit Fields */
+#define CRC_DATAH_DATAH_MASK                     0xFFFFu
+#define CRC_DATAH_DATAH_SHIFT                    0
+#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
+/* DATA Bit Fields */
+#define CRC_DATA_LL_MASK                         0xFFu
+#define CRC_DATA_LL_SHIFT                        0
+#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK                         0xFF00u
+#define CRC_DATA_LU_SHIFT                        8
+#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK                         0xFF0000u
+#define CRC_DATA_HL_SHIFT                        16
+#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK                         0xFF000000u
+#define CRC_DATA_HU_SHIFT                        24
+#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
+/* DATALL Bit Fields */
+#define CRC_DATALL_DATALL_MASK                   0xFFu
+#define CRC_DATALL_DATALL_SHIFT                  0
+#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
+/* DATALU Bit Fields */
+#define CRC_DATALU_DATALU_MASK                   0xFFu
+#define CRC_DATALU_DATALU_SHIFT                  0
+#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
+/* DATAHL Bit Fields */
+#define CRC_DATAHL_DATAHL_MASK                   0xFFu
+#define CRC_DATAHL_DATAHL_SHIFT                  0
+#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
+/* DATAHU Bit Fields */
+#define CRC_DATAHU_DATAHU_MASK                   0xFFu
+#define CRC_DATAHU_DATAHU_SHIFT                  0
+#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK                   0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT                  0
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK                   0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT                  0
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK                       0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT                      0
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT                     16
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                0
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                0
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                0
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                0
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK                       0x1000000u
+#define CRC_CTRL_TCRC_SHIFT                      24
+#define CRC_CTRL_WAS_MASK                        0x2000000u
+#define CRC_CTRL_WAS_SHIFT                       25
+#define CRC_CTRL_FXOR_MASK                       0x4000000u
+#define CRC_CTRL_FXOR_SHIFT                      26
+#define CRC_CTRL_TOTR_MASK                       0x30000000u
+#define CRC_CTRL_TOTR_SHIFT                      28
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        0xC0000000u
+#define CRC_CTRL_TOT_SHIFT                       30
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK                     0x1u
+#define CRC_CTRLHU_TCRC_SHIFT                    0
+#define CRC_CTRLHU_WAS_MASK                      0x2u
+#define CRC_CTRLHU_WAS_SHIFT                     1
+#define CRC_CTRLHU_FXOR_MASK                     0x4u
+#define CRC_CTRLHU_FXOR_SHIFT                    2
+#define CRC_CTRLHU_TOTR_MASK                     0x30u
+#define CRC_CTRLHU_TOTR_SHIFT                    4
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK                      0xC0u
+#define CRC_CTRLHU_TOT_SHIFT                     6
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE                                 (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0                                     ((CRC_Type *)CRC_BASE)
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASES                                { CRC0 }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FGPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
+ * @{
+ */
+
+/** FGPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+  __IO uint32_t PIDR;                              /**< Port Input Disable Register, offset: 0x18 */
+} FGPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FGPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define FGPIO_PDOR_PDO_MASK                      0xFFFFFFFFu
+#define FGPIO_PDOR_PDO_SHIFT                     0
+#define FGPIO_PDOR_PDO(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define FGPIO_PSOR_PTSO_MASK                     0xFFFFFFFFu
+#define FGPIO_PSOR_PTSO_SHIFT                    0
+#define FGPIO_PSOR_PTSO(x)                       (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define FGPIO_PCOR_PTCO_MASK                     0xFFFFFFFFu
+#define FGPIO_PCOR_PTCO_SHIFT                    0
+#define FGPIO_PCOR_PTCO(x)                       (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define FGPIO_PTOR_PTTO_MASK                     0xFFFFFFFFu
+#define FGPIO_PTOR_PTTO_SHIFT                    0
+#define FGPIO_PTOR_PTTO(x)                       (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define FGPIO_PDIR_PDI_MASK                      0xFFFFFFFFu
+#define FGPIO_PDIR_PDI_SHIFT                     0
+#define FGPIO_PDIR_PDI(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define FGPIO_PDDR_PDD_MASK                      0xFFFFFFFFu
+#define FGPIO_PDDR_PDD_SHIFT                     0
+#define FGPIO_PDDR_PDD(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
+/* PIDR Bit Fields */
+#define FGPIO_PIDR_PID_MASK                      0xFFFFFFFFu
+#define FGPIO_PIDR_PID_SHIFT                     0
+#define FGPIO_PIDR_PID(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PIDR_PID_SHIFT))&FGPIO_PIDR_PID_MASK)
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Register_Masks */
+
+
+/* FGPIO - Peripheral instance base addresses */
+/** Peripheral FGPIOA base address */
+#define FGPIOA_BASE                              (0xF8000000u)
+/** Peripheral FGPIOA base pointer */
+#define FGPIOA                                   ((FGPIO_Type *)FGPIOA_BASE)
+/** Peripheral FGPIOB base address */
+#define FGPIOB_BASE                              (0xF8000040u)
+/** Peripheral FGPIOB base pointer */
+#define FGPIOB                                   ((FGPIO_Type *)FGPIOB_BASE)
+/** Array initializer of FGPIO peripheral base pointers */
+#define FGPIO_BASES                              { FGPIOA, FGPIOB }
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ETM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETM_Peripheral_Access_Layer ETM Peripheral Access Layer
+ * @{
+ */
+
+/** ETM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status And Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[6];
+       uint8_t RESERVED_0[16];
+  __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
+  __I  uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
+  __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
+  __IO uint32_t SYNC;                              /**< Synchronization, offset: 0x58 */
+  __IO uint32_t OUTINIT;                           /**< Initial State For Channels Output, offset: 0x5C */
+  __IO uint32_t OUTMASK;                           /**< Output Mask, offset: 0x60 */
+  __IO uint32_t COMBINE;                           /**< Function For Linked Channels, offset: 0x64 */
+  __IO uint32_t DEADETME;                          /**< DeadETMe Insertion Control, offset: 0x68 */
+  __IO uint32_t EXTTRIG;                           /**< ETM External Trigger, offset: 0x6C */
+  __IO uint32_t POL;                               /**< Channels Polarity, offset: 0x70 */
+  __IO uint32_t FMS;                               /**< Fault Mode Status, offset: 0x74 */
+  __IO uint32_t FILTER;                            /**< Input Capture Filter Control, offset: 0x78 */
+  __IO uint32_t FLTCTRL;                           /**< Fault Control, offset: 0x7C */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+  __IO uint32_t FLTPOL;                            /**< ETM Fault Input Polarity, offset: 0x88 */
+  __IO uint32_t SYNCONF;                           /**< Synchronization Configuration, offset: 0x8C */
+  __IO uint32_t INVCTRL;                           /**< ETM Inverting Control, offset: 0x90 */
+  __IO uint32_t SWOCTRL;                           /**< ETM Software Output Control, offset: 0x94 */
+  __IO uint32_t PWMLOAD;                           /**< ETM PWM Load, offset: 0x98 */
+} ETM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ETM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETM_Register_Masks ETM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define ETM_SC_PS_MASK                           0x7u
+#define ETM_SC_PS_SHIFT                          0
+#define ETM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<ETM_SC_PS_SHIFT))&ETM_SC_PS_MASK)
+#define ETM_SC_CLKS_MASK                         0x18u
+#define ETM_SC_CLKS_SHIFT                        3
+#define ETM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x))<<ETM_SC_CLKS_SHIFT))&ETM_SC_CLKS_MASK)
+#define ETM_SC_CPWMS_MASK                        0x20u
+#define ETM_SC_CPWMS_SHIFT                       5
+#define ETM_SC_TOIE_MASK                         0x40u
+#define ETM_SC_TOIE_SHIFT                        6
+#define ETM_SC_TOF_MASK                          0x80u
+#define ETM_SC_TOF_SHIFT                         7
+/* CNT Bit Fields */
+#define ETM_CNT_COUNT_MASK                       0xFFFFu
+#define ETM_CNT_COUNT_SHIFT                      0
+#define ETM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<ETM_CNT_COUNT_SHIFT))&ETM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define ETM_MOD_MOD_MASK                         0xFFFFu
+#define ETM_MOD_MOD_SHIFT                        0
+#define ETM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<ETM_MOD_MOD_SHIFT))&ETM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define ETM_CnSC_ELSA_MASK                       0x4u
+#define ETM_CnSC_ELSA_SHIFT                      2
+#define ETM_CnSC_ELSB_MASK                       0x8u
+#define ETM_CnSC_ELSB_SHIFT                      3
+#define ETM_CnSC_MSA_MASK                        0x10u
+#define ETM_CnSC_MSA_SHIFT                       4
+#define ETM_CnSC_MSB_MASK                        0x20u
+#define ETM_CnSC_MSB_SHIFT                       5
+#define ETM_CnSC_CHIE_MASK                       0x40u
+#define ETM_CnSC_CHIE_SHIFT                      6
+#define ETM_CnSC_CHF_MASK                        0x80u
+#define ETM_CnSC_CHF_SHIFT                       7
+/* CnV Bit Fields */
+#define ETM_CnV_VAL_MASK                         0xFFFFu
+#define ETM_CnV_VAL_SHIFT                        0
+#define ETM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<ETM_CnV_VAL_SHIFT))&ETM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define ETM_CNTIN_INIT_MASK                      0xFFFFu
+#define ETM_CNTIN_INIT_SHIFT                     0
+#define ETM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x))<<ETM_CNTIN_INIT_SHIFT))&ETM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define ETM_STATUS_CH0F_MASK                     0x1u
+#define ETM_STATUS_CH0F_SHIFT                    0
+#define ETM_STATUS_CH1F_MASK                     0x2u
+#define ETM_STATUS_CH1F_SHIFT                    1
+#define ETM_STATUS_CH2F_MASK                     0x4u
+#define ETM_STATUS_CH2F_SHIFT                    2
+#define ETM_STATUS_CH3F_MASK                     0x8u
+#define ETM_STATUS_CH3F_SHIFT                    3
+#define ETM_STATUS_CH4F_MASK                     0x10u
+#define ETM_STATUS_CH4F_SHIFT                    4
+#define ETM_STATUS_CH5F_MASK                     0x20u
+#define ETM_STATUS_CH5F_SHIFT                    5
+#define ETM_STATUS_CH6F_MASK                     0x40u
+#define ETM_STATUS_CH6F_SHIFT                    6
+#define ETM_STATUS_CH7F_MASK                     0x80u
+#define ETM_STATUS_CH7F_SHIFT                    7
+/* MODE Bit Fields */
+#define ETM_MODE_ETMEN_MASK                      0x1u
+#define ETM_MODE_ETMEN_SHIFT                     0
+#define ETM_MODE_INIT_MASK                       0x2u
+#define ETM_MODE_INIT_SHIFT                      1
+#define ETM_MODE_WPDIS_MASK                      0x4u
+#define ETM_MODE_WPDIS_SHIFT                     2
+#define ETM_MODE_PWMSYNC_MASK                    0x8u
+#define ETM_MODE_PWMSYNC_SHIFT                   3
+#define ETM_MODE_CAPTEST_MASK                    0x10u
+#define ETM_MODE_CAPTEST_SHIFT                   4
+#define ETM_MODE_FAULTM_MASK                     0x60u
+#define ETM_MODE_FAULTM_SHIFT                    5
+#define ETM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x))<<ETM_MODE_FAULTM_SHIFT))&ETM_MODE_FAULTM_MASK)
+#define ETM_MODE_FAULTIE_MASK                    0x80u
+#define ETM_MODE_FAULTIE_SHIFT                   7
+/* SYNC Bit Fields */
+#define ETM_SYNC_CNTMIN_MASK                     0x1u
+#define ETM_SYNC_CNTMIN_SHIFT                    0
+#define ETM_SYNC_CNTMAX_MASK                     0x2u
+#define ETM_SYNC_CNTMAX_SHIFT                    1
+#define ETM_SYNC_REINIT_MASK                     0x4u
+#define ETM_SYNC_REINIT_SHIFT                    2
+#define ETM_SYNC_SYNCHOM_MASK                    0x8u
+#define ETM_SYNC_SYNCHOM_SHIFT                   3
+#define ETM_SYNC_TRIG0_MASK                      0x10u
+#define ETM_SYNC_TRIG0_SHIFT                     4
+#define ETM_SYNC_TRIG1_MASK                      0x20u
+#define ETM_SYNC_TRIG1_SHIFT                     5
+#define ETM_SYNC_TRIG2_MASK                      0x40u
+#define ETM_SYNC_TRIG2_SHIFT                     6
+#define ETM_SYNC_SWSYNC_MASK                     0x80u
+#define ETM_SYNC_SWSYNC_SHIFT                    7
+/* OUTINIT Bit Fields */
+#define ETM_OUTINIT_CH0OI_MASK                   0x1u
+#define ETM_OUTINIT_CH0OI_SHIFT                  0
+#define ETM_OUTINIT_CH1OI_MASK                   0x2u
+#define ETM_OUTINIT_CH1OI_SHIFT                  1
+#define ETM_OUTINIT_CH2OI_MASK                   0x4u
+#define ETM_OUTINIT_CH2OI_SHIFT                  2
+#define ETM_OUTINIT_CH3OI_MASK                   0x8u
+#define ETM_OUTINIT_CH3OI_SHIFT                  3
+#define ETM_OUTINIT_CH4OI_MASK                   0x10u
+#define ETM_OUTINIT_CH4OI_SHIFT                  4
+#define ETM_OUTINIT_CH5OI_MASK                   0x20u
+#define ETM_OUTINIT_CH5OI_SHIFT                  5
+#define ETM_OUTINIT_CH6OI_MASK                   0x40u
+#define ETM_OUTINIT_CH6OI_SHIFT                  6
+#define ETM_OUTINIT_CH7OI_MASK                   0x80u
+#define ETM_OUTINIT_CH7OI_SHIFT                  7
+/* OUTMASK Bit Fields */
+#define ETM_OUTMASK_CH0OM_MASK                   0x1u
+#define ETM_OUTMASK_CH0OM_SHIFT                  0
+#define ETM_OUTMASK_CH1OM_MASK                   0x2u
+#define ETM_OUTMASK_CH1OM_SHIFT                  1
+#define ETM_OUTMASK_CH2OM_MASK                   0x4u
+#define ETM_OUTMASK_CH2OM_SHIFT                  2
+#define ETM_OUTMASK_CH3OM_MASK                   0x8u
+#define ETM_OUTMASK_CH3OM_SHIFT                  3
+#define ETM_OUTMASK_CH4OM_MASK                   0x10u
+#define ETM_OUTMASK_CH4OM_SHIFT                  4
+#define ETM_OUTMASK_CH5OM_MASK                   0x20u
+#define ETM_OUTMASK_CH5OM_SHIFT                  5
+#define ETM_OUTMASK_CH6OM_MASK                   0x40u
+#define ETM_OUTMASK_CH6OM_SHIFT                  6
+#define ETM_OUTMASK_CH7OM_MASK                   0x80u
+#define ETM_OUTMASK_CH7OM_SHIFT                  7
+/* COMBINE Bit Fields */
+#define ETM_COMBINE_COMBINE0_MASK                0x1u
+#define ETM_COMBINE_COMBINE0_SHIFT               0
+#define ETM_COMBINE_COMP0_MASK                   0x2u
+#define ETM_COMBINE_COMP0_SHIFT                  1
+#define ETM_COMBINE_DECAPEN0_MASK                0x4u
+#define ETM_COMBINE_DECAPEN0_SHIFT               2
+#define ETM_COMBINE_DECAP0_MASK                  0x8u
+#define ETM_COMBINE_DECAP0_SHIFT                 3
+#define ETM_COMBINE_DTEN0_MASK                   0x10u
+#define ETM_COMBINE_DTEN0_SHIFT                  4
+#define ETM_COMBINE_SYNCEN0_MASK                 0x20u
+#define ETM_COMBINE_SYNCEN0_SHIFT                5
+#define ETM_COMBINE_FAULTEN0_MASK                0x40u
+#define ETM_COMBINE_FAULTEN0_SHIFT               6
+#define ETM_COMBINE_COMBINE1_MASK                0x100u
+#define ETM_COMBINE_COMBINE1_SHIFT               8
+#define ETM_COMBINE_COMP1_MASK                   0x200u
+#define ETM_COMBINE_COMP1_SHIFT                  9
+#define ETM_COMBINE_DECAPEN1_MASK                0x400u
+#define ETM_COMBINE_DECAPEN1_SHIFT               10
+#define ETM_COMBINE_DECAP1_MASK                  0x800u
+#define ETM_COMBINE_DECAP1_SHIFT                 11
+#define ETM_COMBINE_DTEN1_MASK                   0x1000u
+#define ETM_COMBINE_DTEN1_SHIFT                  12
+#define ETM_COMBINE_SYNCEN1_MASK                 0x2000u
+#define ETM_COMBINE_SYNCEN1_SHIFT                13
+#define ETM_COMBINE_FAULTEN1_MASK                0x4000u
+#define ETM_COMBINE_FAULTEN1_SHIFT               14
+#define ETM_COMBINE_COMBINE2_MASK                0x10000u
+#define ETM_COMBINE_COMBINE2_SHIFT               16
+#define ETM_COMBINE_COMP2_MASK                   0x20000u
+#define ETM_COMBINE_COMP2_SHIFT                  17
+#define ETM_COMBINE_DECAPEN2_MASK                0x40000u
+#define ETM_COMBINE_DECAPEN2_SHIFT               18
+#define ETM_COMBINE_DECAP2_MASK                  0x80000u
+#define ETM_COMBINE_DECAP2_SHIFT                 19
+#define ETM_COMBINE_DTEN2_MASK                   0x100000u
+#define ETM_COMBINE_DTEN2_SHIFT                  20
+#define ETM_COMBINE_SYNCEN2_MASK                 0x200000u
+#define ETM_COMBINE_SYNCEN2_SHIFT                21
+#define ETM_COMBINE_FAULTEN2_MASK                0x400000u
+#define ETM_COMBINE_FAULTEN2_SHIFT               22
+#define ETM_COMBINE_COMBINE3_MASK                0x1000000u
+#define ETM_COMBINE_COMBINE3_SHIFT               24
+#define ETM_COMBINE_COMP3_MASK                   0x2000000u
+#define ETM_COMBINE_COMP3_SHIFT                  25
+#define ETM_COMBINE_DECAPEN3_MASK                0x4000000u
+#define ETM_COMBINE_DECAPEN3_SHIFT               26
+#define ETM_COMBINE_DECAP3_MASK                  0x8000000u
+#define ETM_COMBINE_DECAP3_SHIFT                 27
+#define ETM_COMBINE_DTEN3_MASK                   0x10000000u
+#define ETM_COMBINE_DTEN3_SHIFT                  28
+#define ETM_COMBINE_SYNCEN3_MASK                 0x20000000u
+#define ETM_COMBINE_SYNCEN3_SHIFT                29
+#define ETM_COMBINE_FAULTEN3_MASK                0x40000000u
+#define ETM_COMBINE_FAULTEN3_SHIFT               30
+/* DEADETME Bit Fields */
+#define ETM_DEADETME_DTVAL_MASK                  0x3Fu
+#define ETM_DEADETME_DTVAL_SHIFT                 0
+#define ETM_DEADETME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x))<<ETM_DEADETME_DTVAL_SHIFT))&ETM_DEADETME_DTVAL_MASK)
+#define ETM_DEADETME_DTPS_MASK                   0xC0u
+#define ETM_DEADETME_DTPS_SHIFT                  6
+#define ETM_DEADETME_DTPS(x)                     (((uint32_t)(((uint32_t)(x))<<ETM_DEADETME_DTPS_SHIFT))&ETM_DEADETME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define ETM_EXTTRIG_CH2TRIG_MASK                 0x1u
+#define ETM_EXTTRIG_CH2TRIG_SHIFT                0
+#define ETM_EXTTRIG_CH3TRIG_MASK                 0x2u
+#define ETM_EXTTRIG_CH3TRIG_SHIFT                1
+#define ETM_EXTTRIG_CH4TRIG_MASK                 0x4u
+#define ETM_EXTTRIG_CH4TRIG_SHIFT                2
+#define ETM_EXTTRIG_CH5TRIG_MASK                 0x8u
+#define ETM_EXTTRIG_CH5TRIG_SHIFT                3
+#define ETM_EXTTRIG_CH0TRIG_MASK                 0x10u
+#define ETM_EXTTRIG_CH0TRIG_SHIFT                4
+#define ETM_EXTTRIG_CH1TRIG_MASK                 0x20u
+#define ETM_EXTTRIG_CH1TRIG_SHIFT                5
+#define ETM_EXTTRIG_INITTRIGEN_MASK              0x40u
+#define ETM_EXTTRIG_INITTRIGEN_SHIFT             6
+#define ETM_EXTTRIG_TRIGF_MASK                   0x80u
+#define ETM_EXTTRIG_TRIGF_SHIFT                  7
+/* POL Bit Fields */
+#define ETM_POL_POL0_MASK                        0x1u
+#define ETM_POL_POL0_SHIFT                       0
+#define ETM_POL_POL1_MASK                        0x2u
+#define ETM_POL_POL1_SHIFT                       1
+#define ETM_POL_POL2_MASK                        0x4u
+#define ETM_POL_POL2_SHIFT                       2
+#define ETM_POL_POL3_MASK                        0x8u
+#define ETM_POL_POL3_SHIFT                       3
+#define ETM_POL_POL4_MASK                        0x10u
+#define ETM_POL_POL4_SHIFT                       4
+#define ETM_POL_POL5_MASK                        0x20u
+#define ETM_POL_POL5_SHIFT                       5
+#define ETM_POL_POL6_MASK                        0x40u
+#define ETM_POL_POL6_SHIFT                       6
+#define ETM_POL_POL7_MASK                        0x80u
+#define ETM_POL_POL7_SHIFT                       7
+/* FMS Bit Fields */
+#define ETM_FMS_FAULTF0_MASK                     0x1u
+#define ETM_FMS_FAULTF0_SHIFT                    0
+#define ETM_FMS_FAULTF1_MASK                     0x2u
+#define ETM_FMS_FAULTF1_SHIFT                    1
+#define ETM_FMS_FAULTF2_MASK                     0x4u
+#define ETM_FMS_FAULTF2_SHIFT                    2
+#define ETM_FMS_FAULTF3_MASK                     0x8u
+#define ETM_FMS_FAULTF3_SHIFT                    3
+#define ETM_FMS_FAULTIN_MASK                     0x20u
+#define ETM_FMS_FAULTIN_SHIFT                    5
+#define ETM_FMS_WPEN_MASK                        0x40u
+#define ETM_FMS_WPEN_SHIFT                       6
+#define ETM_FMS_FAULTF_MASK                      0x80u
+#define ETM_FMS_FAULTF_SHIFT                     7
+/* FILTER Bit Fields */
+#define ETM_FILTER_CH0FVAL_MASK                  0xFu
+#define ETM_FILTER_CH0FVAL_SHIFT                 0
+#define ETM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<ETM_FILTER_CH0FVAL_SHIFT))&ETM_FILTER_CH0FVAL_MASK)
+#define ETM_FILTER_CH1FVAL_MASK                  0xF0u
+#define ETM_FILTER_CH1FVAL_SHIFT                 4
+#define ETM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<ETM_FILTER_CH1FVAL_SHIFT))&ETM_FILTER_CH1FVAL_MASK)
+#define ETM_FILTER_CH2FVAL_MASK                  0xF00u
+#define ETM_FILTER_CH2FVAL_SHIFT                 8
+#define ETM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<ETM_FILTER_CH2FVAL_SHIFT))&ETM_FILTER_CH2FVAL_MASK)
+#define ETM_FILTER_CH3FVAL_MASK                  0xF000u
+#define ETM_FILTER_CH3FVAL_SHIFT                 12
+#define ETM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<ETM_FILTER_CH3FVAL_SHIFT))&ETM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define ETM_FLTCTRL_FAULT0EN_MASK                0x1u
+#define ETM_FLTCTRL_FAULT0EN_SHIFT               0
+#define ETM_FLTCTRL_FAULT1EN_MASK                0x2u
+#define ETM_FLTCTRL_FAULT1EN_SHIFT               1
+#define ETM_FLTCTRL_FAULT2EN_MASK                0x4u
+#define ETM_FLTCTRL_FAULT2EN_SHIFT               2
+#define ETM_FLTCTRL_FAULT3EN_MASK                0x8u
+#define ETM_FLTCTRL_FAULT3EN_SHIFT               3
+#define ETM_FLTCTRL_FFLTR0EN_MASK                0x10u
+#define ETM_FLTCTRL_FFLTR0EN_SHIFT               4
+#define ETM_FLTCTRL_FFLTR1EN_MASK                0x20u
+#define ETM_FLTCTRL_FFLTR1EN_SHIFT               5
+#define ETM_FLTCTRL_FFLTR2EN_MASK                0x40u
+#define ETM_FLTCTRL_FFLTR2EN_SHIFT               6
+#define ETM_FLTCTRL_FFLTR3EN_MASK                0x80u
+#define ETM_FLTCTRL_FFLTR3EN_SHIFT               7
+#define ETM_FLTCTRL_FFVAL_MASK                   0xF00u
+#define ETM_FLTCTRL_FFVAL_SHIFT                  8
+#define ETM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x))<<ETM_FLTCTRL_FFVAL_SHIFT))&ETM_FLTCTRL_FFVAL_MASK)
+/* CONF Bit Fields */
+#define ETM_CONF_NUMTOF_MASK                     0x1Fu
+#define ETM_CONF_NUMTOF_SHIFT                    0
+#define ETM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x))<<ETM_CONF_NUMTOF_SHIFT))&ETM_CONF_NUMTOF_MASK)
+#define ETM_CONF_BDMMODE_MASK                    0xC0u
+#define ETM_CONF_BDMMODE_SHIFT                   6
+#define ETM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x))<<ETM_CONF_BDMMODE_SHIFT))&ETM_CONF_BDMMODE_MASK)
+#define ETM_CONF_GTBEEN_MASK                     0x200u
+#define ETM_CONF_GTBEEN_SHIFT                    9
+#define ETM_CONF_GTBEOUT_MASK                    0x400u
+#define ETM_CONF_GTBEOUT_SHIFT                   10
+/* FLTPOL Bit Fields */
+#define ETM_FLTPOL_FLT0POL_MASK                  0x1u
+#define ETM_FLTPOL_FLT0POL_SHIFT                 0
+#define ETM_FLTPOL_FLT1POL_MASK                  0x2u
+#define ETM_FLTPOL_FLT1POL_SHIFT                 1
+#define ETM_FLTPOL_FLT2POL_MASK                  0x4u
+#define ETM_FLTPOL_FLT2POL_SHIFT                 2
+#define ETM_FLTPOL_FLT3POL_MASK                  0x8u
+#define ETM_FLTPOL_FLT3POL_SHIFT                 3
+/* SYNCONF Bit Fields */
+#define ETM_SYNCONF_HWTRIGMODE_MASK              0x1u
+#define ETM_SYNCONF_HWTRIGMODE_SHIFT             0
+#define ETM_SYNCONF_CNTINC_MASK                  0x4u
+#define ETM_SYNCONF_CNTINC_SHIFT                 2
+#define ETM_SYNCONF_INVC_MASK                    0x10u
+#define ETM_SYNCONF_INVC_SHIFT                   4
+#define ETM_SYNCONF_SWOC_MASK                    0x20u
+#define ETM_SYNCONF_SWOC_SHIFT                   5
+#define ETM_SYNCONF_SYNCMODE_MASK                0x80u
+#define ETM_SYNCONF_SYNCMODE_SHIFT               7
+#define ETM_SYNCONF_SWRSTCNT_MASK                0x100u
+#define ETM_SYNCONF_SWRSTCNT_SHIFT               8
+#define ETM_SYNCONF_SWWRBUF_MASK                 0x200u
+#define ETM_SYNCONF_SWWRBUF_SHIFT                9
+#define ETM_SYNCONF_SWOM_MASK                    0x400u
+#define ETM_SYNCONF_SWOM_SHIFT                   10
+#define ETM_SYNCONF_SWINVC_MASK                  0x800u
+#define ETM_SYNCONF_SWINVC_SHIFT                 11
+#define ETM_SYNCONF_SWSOC_MASK                   0x1000u
+#define ETM_SYNCONF_SWSOC_SHIFT                  12
+#define ETM_SYNCONF_HWRSTCNT_MASK                0x10000u
+#define ETM_SYNCONF_HWRSTCNT_SHIFT               16
+#define ETM_SYNCONF_HWWRBUF_MASK                 0x20000u
+#define ETM_SYNCONF_HWWRBUF_SHIFT                17
+#define ETM_SYNCONF_HWOM_MASK                    0x40000u
+#define ETM_SYNCONF_HWOM_SHIFT                   18
+#define ETM_SYNCONF_HWINVC_MASK                  0x80000u
+#define ETM_SYNCONF_HWINVC_SHIFT                 19
+#define ETM_SYNCONF_HWSOC_MASK                   0x100000u
+#define ETM_SYNCONF_HWSOC_SHIFT                  20
+/* INVCTRL Bit Fields */
+#define ETM_INVCTRL_INV0EN_MASK                  0x1u
+#define ETM_INVCTRL_INV0EN_SHIFT                 0
+#define ETM_INVCTRL_INV1EN_MASK                  0x2u
+#define ETM_INVCTRL_INV1EN_SHIFT                 1
+#define ETM_INVCTRL_INV2EN_MASK                  0x4u
+#define ETM_INVCTRL_INV2EN_SHIFT                 2
+#define ETM_INVCTRL_INV3EN_MASK                  0x8u
+#define ETM_INVCTRL_INV3EN_SHIFT                 3
+/* SWOCTRL Bit Fields */
+#define ETM_SWOCTRL_CH0OC_MASK                   0x1u
+#define ETM_SWOCTRL_CH0OC_SHIFT                  0
+#define ETM_SWOCTRL_CH1OC_MASK                   0x2u
+#define ETM_SWOCTRL_CH1OC_SHIFT                  1
+#define ETM_SWOCTRL_CH2OC_MASK                   0x4u
+#define ETM_SWOCTRL_CH2OC_SHIFT                  2
+#define ETM_SWOCTRL_CH3OC_MASK                   0x8u
+#define ETM_SWOCTRL_CH3OC_SHIFT                  3
+#define ETM_SWOCTRL_CH4OC_MASK                   0x10u
+#define ETM_SWOCTRL_CH4OC_SHIFT                  4
+#define ETM_SWOCTRL_CH5OC_MASK                   0x20u
+#define ETM_SWOCTRL_CH5OC_SHIFT                  5
+#define ETM_SWOCTRL_CH6OC_MASK                   0x40u
+#define ETM_SWOCTRL_CH6OC_SHIFT                  6
+#define ETM_SWOCTRL_CH7OC_MASK                   0x80u
+#define ETM_SWOCTRL_CH7OC_SHIFT                  7
+#define ETM_SWOCTRL_CH0OCV_MASK                  0x100u
+#define ETM_SWOCTRL_CH0OCV_SHIFT                 8
+#define ETM_SWOCTRL_CH1OCV_MASK                  0x200u
+#define ETM_SWOCTRL_CH1OCV_SHIFT                 9
+#define ETM_SWOCTRL_CH2OCV_MASK                  0x400u
+#define ETM_SWOCTRL_CH2OCV_SHIFT                 10
+#define ETM_SWOCTRL_CH3OCV_MASK                  0x800u
+#define ETM_SWOCTRL_CH3OCV_SHIFT                 11
+#define ETM_SWOCTRL_CH4OCV_MASK                  0x1000u
+#define ETM_SWOCTRL_CH4OCV_SHIFT                 12
+#define ETM_SWOCTRL_CH5OCV_MASK                  0x2000u
+#define ETM_SWOCTRL_CH5OCV_SHIFT                 13
+#define ETM_SWOCTRL_CH6OCV_MASK                  0x4000u
+#define ETM_SWOCTRL_CH6OCV_SHIFT                 14
+#define ETM_SWOCTRL_CH7OCV_MASK                  0x8000u
+#define ETM_SWOCTRL_CH7OCV_SHIFT                 15
+/* PWMLOAD Bit Fields */
+#define ETM_PWMLOAD_CH0SEL_MASK                  0x1u
+#define ETM_PWMLOAD_CH0SEL_SHIFT                 0
+#define ETM_PWMLOAD_CH1SEL_MASK                  0x2u
+#define ETM_PWMLOAD_CH1SEL_SHIFT                 1
+#define ETM_PWMLOAD_CH2SEL_MASK                  0x4u
+#define ETM_PWMLOAD_CH2SEL_SHIFT                 2
+#define ETM_PWMLOAD_CH3SEL_MASK                  0x8u
+#define ETM_PWMLOAD_CH3SEL_SHIFT                 3
+#define ETM_PWMLOAD_CH4SEL_MASK                  0x10u
+#define ETM_PWMLOAD_CH4SEL_SHIFT                 4
+#define ETM_PWMLOAD_CH5SEL_MASK                  0x20u
+#define ETM_PWMLOAD_CH5SEL_SHIFT                 5
+#define ETM_PWMLOAD_CH6SEL_MASK                  0x40u
+#define ETM_PWMLOAD_CH6SEL_SHIFT                 6
+#define ETM_PWMLOAD_CH7SEL_MASK                  0x80u
+#define ETM_PWMLOAD_CH7SEL_SHIFT                 7
+#define ETM_PWMLOAD_LDOK_MASK                    0x200u
+#define ETM_PWMLOAD_LDOK_SHIFT                   9
+
+/*!
+ * @}
+ */ /* end of group ETM_Register_Masks */
+
+
+/* ETM - Peripheral instance base addresses */
+/** Peripheral ETM0 base address */
+#define ETM0_BASE                                (0x40038000u)
+/** Peripheral ETM0 base pointer */
+#define ETM0                                     ((ETM_Type *)ETM0_BASE)
+/** Peripheral ETM1 base address */
+#define ETM1_BASE                                (0x40039000u)
+/** Peripheral ETM1 base pointer */
+#define ETM1                                     ((ETM_Type *)ETM1_BASE)
+/** Peripheral ETM2 base address */
+#define ETM2_BASE                                (0x4003A000u)
+/** Peripheral ETM2 base pointer */
+#define ETM2                                     ((ETM_Type *)ETM2_BASE)
+/** Array initializer of ETM peripheral base pointers */
+#define ETM_BASES                                { ETM0, ETM1, ETM2 }
+
+/*!
+ * @}
+ */ /* end of group ETM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ETMRH Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETMRH_Peripheral_Access_Layer ETMRH Peripheral Access Layer
+ * @{
+ */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV
+   ---------------------------------------------------------------------------- */
+typedef struct ETMRA_MemMap {
+  volatile unsigned long EFMCR;
+	volatile unsigned long EFMSEC0;
+	volatile unsigned long EFMSEC1;
+	volatile unsigned long EFMSEC2;
+	volatile unsigned long EFMETM0;
+	volatile unsigned long EFMETM1;
+	volatile unsigned long EFMCMD;
+} *ETMRH_MemMapPtr;
+
+#define EFM_CR_reg(base)    ((base)->EFMCR)
+#define EFM_SEC0_reg(base)  ((base)->EFMSEC0)
+#define EFM_SEC1_reg(base)  ((base)->EFMSEC1)
+#define EFM_SEC2_reg(base)  ((base)->EFMSEC2)   
+#define EFM_ETM0_reg(base)  ((base)->EFMETM0)
+#define EFM_ETM1_reg(base)  ((base)->EFMETM1)
+#define EFM_CMD_reg(base)		((base)->EFMCMD)
+
+/** Peripheral Map **/
+#define ETMRH                           ((ETMRH_MemMapPtr)0x40020000u)
+
+
+#define ETMRH_FCLKDIV_FDIVLD_MASK                0x80u
+#define ETMRH_FSTAT_CCIF_MASK                    0x80u
+#define ETMRH_FSTAT_ACCERR_MASK                  0x20u
+#define ETMRH_FSTAT_FPVIOL_MASK                  0x10u
+#define ETMRH_FSTAT_MGSTAT_MASK                  0x3u
+#define ETMRH_ERROR                              (ETMRH_FSTAT_ACCERR_MASK | ETMRH_FSTAT_FPVIOL_MASK | ETMRH_FSTAT_MGSTAT_MASK)
+#define ETMRH_FCCOB                              *((volatile uint16_t *)(0x0a + 0x40020000))
+
+#define EFMCR      EFM_CR_reg(ETMRH)
+#define EFMSEC0    EFM_SEC0_reg(ETMRH)
+#define EFMSEC1    EFM_SEC1_reg(ETMRH)
+#define EFMSEC2    EFM_SEC2_reg(ETMRH)
+#define EFMETM0    EFM_ETM0_reg(ETMRH)
+#define EFMETM1    EFM_ETM1_reg(ETMRH)
+#define EFMCMD     EFM_CMD_reg(ETMRH)
+
+typedef struct NVR_BKDOOR_MemMap{
+	  volatile unsigned long Custombkd;
+} *NVR_BKDOOR_MemMapPtr;
+
+
+#define Custombkd_reg(base)    ((base)->Custombkd)
+#define NVR_BKDOOR             ((NVR_BKDOOR_MemMapPtr)0x40020038u)
+
+#define Custombkd             Custombkd_reg(NVR_BKDOOR)
+
+/*!
+ * @}
+ */ /* end of group ETMRH_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+  __IO uint32_t PIDR;                              /**< Port Input Disable Register, offset: 0x18 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT                      0
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT                     0
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT                     0
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT                     0
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT                      0
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT                      0
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+/* PIDR Bit Fields */
+#define GPIO_PIDR_PID_MASK                       0xFFFFFFFFu
+#define GPIO_PIDR_PID_SHIFT                      0
+#define GPIO_PIDR_PID(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PIDR_PID_SHIFT))&GPIO_PIDR_PID_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE                               (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA                                    ((GPIO_Type *)GPIOA_BASE)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE                               (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB                                    ((GPIO_Type *)GPIOB_BASE)
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASES                               { GPIOA, GPIOB }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
+  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /**< I2C SCL Low ETMeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /**< I2C SCL Low ETMeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK                           0xFEu
+#define I2C_A1_AD_SHIFT                          1
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK                           0x3Fu
+#define I2C_F_ICR_SHIFT                          0
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          0xC0u
+#define I2C_F_MULT_SHIFT                         6
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_WUEN_MASK                         0x2u
+#define I2C_C1_WUEN_SHIFT                        1
+#define I2C_C1_RSTA_MASK                         0x4u
+#define I2C_C1_RSTA_SHIFT                        2
+#define I2C_C1_TXAK_MASK                         0x8u
+#define I2C_C1_TXAK_SHIFT                        3
+#define I2C_C1_TX_MASK                           0x10u
+#define I2C_C1_TX_SHIFT                          4
+#define I2C_C1_MST_MASK                          0x20u
+#define I2C_C1_MST_SHIFT                         5
+#define I2C_C1_IICIE_MASK                        0x40u
+#define I2C_C1_IICIE_SHIFT                       6
+#define I2C_C1_IICEN_MASK                        0x80u
+#define I2C_C1_IICEN_SHIFT                       7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK                          0x1u
+#define I2C_S_RXAK_SHIFT                         0
+#define I2C_S_IICIF_MASK                         0x2u
+#define I2C_S_IICIF_SHIFT                        1
+#define I2C_S_SRW_MASK                           0x4u
+#define I2C_S_SRW_SHIFT                          2
+#define I2C_S_RAM_MASK                           0x8u
+#define I2C_S_RAM_SHIFT                          3
+#define I2C_S_ARBL_MASK                          0x10u
+#define I2C_S_ARBL_SHIFT                         4
+#define I2C_S_BUSY_MASK                          0x20u
+#define I2C_S_BUSY_SHIFT                         5
+#define I2C_S_IAAS_MASK                          0x40u
+#define I2C_S_IAAS_SHIFT                         6
+#define I2C_S_TCF_MASK                           0x80u
+#define I2C_S_TCF_SHIFT                          7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK                          0xFFu
+#define I2C_D_DATA_SHIFT                         0
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK                           0x7u
+#define I2C_C2_AD_SHIFT                          0
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK                         0x8u
+#define I2C_C2_RMEN_SHIFT                        3
+#define I2C_C2_ADEXT_MASK                        0x40u
+#define I2C_C2_ADEXT_SHIFT                       6
+#define I2C_C2_GCAEN_MASK                        0x80u
+#define I2C_C2_GCAEN_SHIFT                       7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK                         0x1Fu
+#define I2C_FLT_FLT_SHIFT                        0
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK                          0xFEu
+#define I2C_RA_RAD_SHIFT                         1
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK                     0x1u
+#define I2C_SMB_SHTF2IE_SHIFT                    0
+#define I2C_SMB_SHTF2_MASK                       0x2u
+#define I2C_SMB_SHTF2_SHIFT                      1
+#define I2C_SMB_SHTF1_MASK                       0x4u
+#define I2C_SMB_SHTF1_SHIFT                      2
+#define I2C_SMB_SLTF_MASK                        0x8u
+#define I2C_SMB_SLTF_SHIFT                       3
+#define I2C_SMB_TCKSEL_MASK                      0x10u
+#define I2C_SMB_TCKSEL_SHIFT                     4
+#define I2C_SMB_SIICAEN_MASK                     0x20u
+#define I2C_SMB_SIICAEN_SHIFT                    5
+#define I2C_SMB_ALERTEN_MASK                     0x40u
+#define I2C_SMB_ALERTEN_SHIFT                    6
+#define I2C_SMB_FACK_MASK                        0x80u
+#define I2C_SMB_FACK_SHIFT                       7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK                          0xFEu
+#define I2C_A2_SAD_SHIFT                         1
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK                       0xFFu
+#define I2C_SLTH_SSLT_SHIFT                      0
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK                       0xFFu
+#define I2C_SLTL_SSLT_SHIFT                      0
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASES                                { I2C0 }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ICS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ICS_Peripheral_Access_Layer ICS Peripheral Access Layer
+ * @{
+ */
+
+/** ICS - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< ICS Control Register 1, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< ICS Control Register 2, offset: 0x1 */
+  __IO uint8_t C3;                                 /**< ICS Control Register 3, offset: 0x2 */
+  __IO uint8_t C4;                                 /**< ICS Control Register 4, offset: 0x3 */
+  __IO uint8_t S;                                  /**< ICS Status Register, offset: 0x4 */
+} ICS_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ICS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ICS_Register_Masks ICS Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define ICS_C1_IREFSTEN_MASK                     0x1u
+#define ICS_C1_IREFSTEN_SHIFT                    0
+#define ICS_C1_IRCLKEN_MASK                      0x2u
+#define ICS_C1_IRCLKEN_SHIFT                     1
+#define ICS_C1_IREFS_MASK                        0x4u
+#define ICS_C1_IREFS_SHIFT                       2
+#define ICS_C1_RDIV_MASK                         0x38u
+#define ICS_C1_RDIV_SHIFT                        3
+#define ICS_C1_RDIV(x)                           (((uint8_t)(((uint8_t)(x))<<ICS_C1_RDIV_SHIFT))&ICS_C1_RDIV_MASK)
+#define ICS_C1_CLKS_MASK                         0xC0u
+#define ICS_C1_CLKS_SHIFT                        6
+#define ICS_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<ICS_C1_CLKS_SHIFT))&ICS_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define ICS_C2_LP_MASK                           0x10u
+#define ICS_C2_LP_SHIFT                          4
+#define ICS_C2_BDIV_MASK                         0xE0u
+#define ICS_C2_BDIV_SHIFT                        5
+#define ICS_C2_BDIV(x)                           (((uint8_t)(((uint8_t)(x))<<ICS_C2_BDIV_SHIFT))&ICS_C2_BDIV_MASK)
+/* C3 Bit Fields */
+#define ICS_C3_SCTRIM_MASK                       0xFFu
+#define ICS_C3_SCTRIM_SHIFT                      0
+#define ICS_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<ICS_C3_SCTRIM_SHIFT))&ICS_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define ICS_C4_SCFTRIM_MASK                      0x1u
+#define ICS_C4_SCFTRIM_SHIFT                     0
+#define ICS_C4_CME_MASK                          0x20u
+#define ICS_C4_CME_SHIFT                         5
+#define ICS_C4_LOLIE_MASK                        0x80u
+#define ICS_C4_LOLIE_SHIFT                       7
+/* S Bit Fields */
+#define ICS_S_CLKST_MASK                         0xCu
+#define ICS_S_CLKST_SHIFT                        2
+#define ICS_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<ICS_S_CLKST_SHIFT))&ICS_S_CLKST_MASK)
+#define ICS_S_IREFST_MASK                        0x10u
+#define ICS_S_IREFST_SHIFT                       4
+#define ICS_S_LOCK_MASK                          0x40u
+#define ICS_S_LOCK_SHIFT                         6
+#define ICS_S_LOLS_MASK                          0x80u
+#define ICS_S_LOLS_SHIFT                         7
+
+/*!
+ * @}
+ */ /* end of group ICS_Register_Masks */
+
+
+/* ICS - Peripheral instance base addresses */
+/** Peripheral ICS base address */
+#define ICS_BASE                                 (0x40064000u)
+/** Peripheral ICS base pointer */
+#define ICS                                      ((ICS_Type *)ICS_BASE)
+/** Array initializer of ICS peripheral base pointers */
+#define ICS_BASES                                { ICS }
+
+/*!
+ * @}
+ */ /* end of group ICS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- IRQ Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IRQ_Peripheral_Access_Layer IRQ Peripheral Access Layer
+ * @{
+ */
+
+/** IRQ - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t SC;                                 /**< Interrupt Pin Request Status and Control Register, offset: 0x0 */
+} IRQ_Type;
+
+/* ----------------------------------------------------------------------------
+   -- IRQ Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IRQ_Register_Masks IRQ Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define IRQ_SC_IRQMOD_MASK                       0x1u
+#define IRQ_SC_IRQMOD_SHIFT                      0
+#define IRQ_SC_IRQIE_MASK                        0x2u
+#define IRQ_SC_IRQIE_SHIFT                       1
+#define IRQ_SC_IRQACK_MASK                       0x4u
+#define IRQ_SC_IRQACK_SHIFT                      2
+#define IRQ_SC_IRQF_MASK                         0x8u
+#define IRQ_SC_IRQF_SHIFT                        3
+#define IRQ_SC_IRQPE_MASK                        0x10u
+#define IRQ_SC_IRQPE_SHIFT                       4
+#define IRQ_SC_IRQEDG_MASK                       0x20u
+#define IRQ_SC_IRQEDG_SHIFT                      5
+#define IRQ_SC_IRQPDD_MASK                       0x40u
+#define IRQ_SC_IRQPDD_SHIFT                      6
+
+/*!
+ * @}
+ */ /* end of group IRQ_Register_Masks */
+
+
+/* IRQ - Peripheral instance base addresses */
+/** Peripheral IRQ base address */
+#define IRQ_BASE                                 (0x40031000u)
+/** Peripheral IRQ base pointer */
+#define IRQ                                      ((IRQ_Type *)IRQ_BASE)
+/** Array initializer of IRQ peripheral base pointers */
+#define IRQ_BASES                                { IRQ }
+
+/*!
+ * @}
+ */ /* end of group IRQ_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- KBI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup KBI_Peripheral_Access_Layer KBI Peripheral Access Layer
+ * @{
+ */
+
+/** KBI - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t SC;                                 /**< KBI Status and Control Register, offset: 0x0 */
+  __IO uint8_t PE;                                 /**< KBIx Pin Enable Register, offset: 0x1 */
+  __IO uint8_t ES;                                 /**< KBIx Edge Select Register, offset: 0x2 */
+} KBI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- KBI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup KBI_Register_Masks KBI Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define KBI_SC_KBMOD_MASK                        0x1u
+#define KBI_SC_KBMOD_SHIFT                       0
+#define KBI_SC_KBIE_MASK                         0x2u
+#define KBI_SC_KBIE_SHIFT                        1
+#define KBI_SC_KBACK_MASK                        0x4u
+#define KBI_SC_KBACK_SHIFT                       2
+#define KBI_SC_KBF_MASK                          0x8u
+#define KBI_SC_KBF_SHIFT                         3
+/* PE Bit Fields */
+#define KBI_PE_KBIPE_MASK                        0xFFu
+#define KBI_PE_KBIPE_SHIFT                       0
+#define KBI_PE_KBIPE(x)                          (((uint8_t)(((uint8_t)(x))<<KBI_PE_KBIPE_SHIFT))&KBI_PE_KBIPE_MASK)
+/* ES Bit Fields */
+#define KBI_ES_KBEDG_MASK                        0xFFu
+#define KBI_ES_KBEDG_SHIFT                       0
+#define KBI_ES_KBEDG(x)                          (((uint8_t)(((uint8_t)(x))<<KBI_ES_KBEDG_SHIFT))&KBI_ES_KBEDG_MASK)
+
+/*!
+ * @}
+ */ /* end of group KBI_Register_Masks */
+
+
+/* KBI - Peripheral instance base addresses */
+/** Peripheral KBI0 base address */
+#define KBI0_BASE                                (0x40079000u)
+/** Peripheral KBI0 base pointer */
+#define KBI0                                     ((KBI_Type *)KBI0_BASE)
+/** Peripheral KBI1 base address */
+#define KBI1_BASE                                (0x4007A000u)
+/** Peripheral KBI1 base pointer */
+#define KBI1                                     ((KBI_Type *)KBI1_BASE)
+/** Array initializer of KBI peripheral base pointers */
+#define KBI_BASES                                { KBI0, KBI1 }
+
+/*!
+ * @}
+ */ /* end of group KBI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t PLACR;                             /**< Platform Control Register, offset: 0xC */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK                       0xFFu
+#define MCM_PLASC_ASC_SHIFT                      0
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK                       0xFFu
+#define MCM_PLAMC_AMC_SHIFT                      0
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_CFCC_MASK                      0x400u
+#define MCM_PLACR_CFCC_SHIFT                     10
+#define MCM_PLACR_DFCDA_MASK                     0x800u
+#define MCM_PLACR_DFCDA_SHIFT                    11
+#define MCM_PLACR_DFCIC_MASK                     0x1000u
+#define MCM_PLACR_DFCIC_SHIFT                    12
+#define MCM_PLACR_DFCC_MASK                      0x2000u
+#define MCM_PLACR_DFCC_SHIFT                     13
+#define MCM_PLACR_EFDS_MASK                      0x4000u
+#define MCM_PLACR_EFDS_SHIFT                     14
+#define MCM_PLACR_DFCS_MASK                      0x8000u
+#define MCM_PLACR_DFCS_SHIFT                     15
+#define MCM_PLACR_ESFC_MASK                      0x10000u
+#define MCM_PLACR_ESFC_SHIFT                     16
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE                                 (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM                                      ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASES                                { MCM }
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0, offset: 0x0 */
+  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1, offset: 0x1 */
+  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2, offset: 0x2 */
+  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3, offset: 0x3 */
+  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4, offset: 0x4 */
+  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5, offset: 0x5 */
+  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6, offset: 0x6 */
+  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7, offset: 0x7 */
+       uint8_t RESERVED_0[4];
+  __I  uint8_t EEPROT;                             /**< Non-volatile E-Flash Protection Register, offset: 0xC */
+  __I  uint8_t FPROT;                              /**< Non-volatile P-Flash Protection Register, offset: 0xD */
+  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xE */
+  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xF */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK                     0xFFu
+#define NV_BACKKEY0_KEY_SHIFT                    0
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK                     0xFFu
+#define NV_BACKKEY1_KEY_SHIFT                    0
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK                     0xFFu
+#define NV_BACKKEY2_KEY_SHIFT                    0
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK                     0xFFu
+#define NV_BACKKEY3_KEY_SHIFT                    0
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK                     0xFFu
+#define NV_BACKKEY4_KEY_SHIFT                    0
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK                     0xFFu
+#define NV_BACKKEY5_KEY_SHIFT                    0
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK                     0xFFu
+#define NV_BACKKEY6_KEY_SHIFT                    0
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK                     0xFFu
+#define NV_BACKKEY7_KEY_SHIFT                    0
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* EEPROT Bit Fields */
+#define NV_EEPROT_DPS_MASK                       0x7u
+#define NV_EEPROT_DPS_SHIFT                      0
+#define NV_EEPROT_DPS(x)                         (((uint8_t)(((uint8_t)(x))<<NV_EEPROT_DPS_SHIFT))&NV_EEPROT_DPS_MASK)
+#define NV_EEPROT_DPOPEN_MASK                    0x80u
+#define NV_EEPROT_DPOPEN_SHIFT                   7
+/* FPROT Bit Fields */
+#define NV_FPROT_FPLS_MASK                       0x3u
+#define NV_FPROT_FPLS_SHIFT                      0
+#define NV_FPROT_FPLS(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FPROT_FPLS_SHIFT))&NV_FPROT_FPLS_MASK)
+#define NV_FPROT_FPLDIS_MASK                     0x4u
+#define NV_FPROT_FPLDIS_SHIFT                    2
+#define NV_FPROT_FPHS_MASK                       0x18u
+#define NV_FPROT_FPHS_SHIFT                      3
+#define NV_FPROT_FPHS(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FPROT_FPHS_SHIFT))&NV_FPROT_FPHS_MASK)
+#define NV_FPROT_FPHDIS_MASK                     0x20u
+#define NV_FPROT_FPHDIS_SHIFT                    5
+#define NV_FPROT_FPOPEN_MASK                     0x80u
+#define NV_FPROT_FPOPEN_SHIFT                    7
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK                         0x3u
+#define NV_FSEC_SEC_SHIFT                        0
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_KEYEN_MASK                       0xC0u
+#define NV_FSEC_KEYEN_SHIFT                      6
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral ETMRH_FlashConfig base address */
+#define ETMRH_FlashConfig_BASE                   (0x400u)
+/** Peripheral ETMRH_FlashConfig base pointer */
+#define ETMRH_FlashConfig                        ((NV_Type *)ETMRH_FlashConfig_BASE)
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASES                                 { ETMRH_FlashConfig }
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_OSCINIT_MASK                      0x1u
+#define OSC_CR_OSCINIT_SHIFT                     0
+#define OSC_CR_HGO_MASK                          0x2u
+#define OSC_CR_HGO_SHIFT                         1
+#define OSC_CR_RANGE_MASK                        0x4u
+#define OSC_CR_RANGE_SHIFT                       2
+#define OSC_CR_OSCOS_MASK                        0x10u
+#define OSC_CR_OSCOS_SHIFT                       4
+#define OSC_CR_OSCSTEN_MASK                      0x20u
+#define OSC_CR_OSCSTEN_SHIFT                     5
+#define OSC_CR_OSCEN_MASK                        0x80u
+#define OSC_CR_OSCEN_SHIFT                       7
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE                                 (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC                                      ((OSC_Type *)OSC_BASE)
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASES                                { OSC }
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[252];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /**< ETMer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current ETMer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< ETMer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /**< ETMer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[2];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK                         0x1u
+#define PIT_MCR_FRZ_SHIFT                        0
+#define PIT_MCR_MDIS_MASK                        0x2u
+#define PIT_MCR_MDIS_SHIFT                       1
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT                      0
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT                       0
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK                       0x1u
+#define PIT_TCTRL_TEN_SHIFT                      0
+#define PIT_TCTRL_TIE_MASK                       0x2u
+#define PIT_TCTRL_TIE_SHIFT                      1
+#define PIT_TCTRL_CHN_MASK                       0x4u
+#define PIT_TCTRL_CHN_SHIFT                      2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK                        0x1u
+#define PIT_TFLG_TIF_SHIFT                       0
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE                                 (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT                                      ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASES                                { PIT }
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t SPMSC1;                             /**< System Power Management Status and Control 1 Register, offset: 0x0 */
+  __IO uint8_t SPMSC2;                             /**< System Power Management Status and Control 2 Register, offset: 0x1 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* SPMSC1 Bit Fields */
+#define PMC_SPMSC1_BGBE_MASK                     0x1u
+#define PMC_SPMSC1_BGBE_SHIFT                    0
+#define PMC_SPMSC1_BGBDS_MASK                    0x2u
+#define PMC_SPMSC1_BGBDS_SHIFT                   1
+#define PMC_SPMSC1_LVDE_MASK                     0x4u
+#define PMC_SPMSC1_LVDE_SHIFT                    2
+#define PMC_SPMSC1_LVDSE_MASK                    0x8u
+#define PMC_SPMSC1_LVDSE_SHIFT                   3
+#define PMC_SPMSC1_LVDRE_MASK                    0x10u
+#define PMC_SPMSC1_LVDRE_SHIFT                   4
+#define PMC_SPMSC1_LVWIE_MASK                    0x20u
+#define PMC_SPMSC1_LVWIE_SHIFT                   5
+#define PMC_SPMSC1_LVWACK_MASK                   0x40u
+#define PMC_SPMSC1_LVWACK_SHIFT                  6
+#define PMC_SPMSC1_LVWF_MASK                     0x80u
+#define PMC_SPMSC1_LVWF_SHIFT                    7
+/* SPMSC2 Bit Fields */
+#define PMC_SPMSC2_LVWV_MASK                     0x30u
+#define PMC_SPMSC2_LVWV_SHIFT                    4
+#define PMC_SPMSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_SPMSC2_LVWV_SHIFT))&PMC_SPMSC2_LVWV_MASK)
+#define PMC_SPMSC2_LVDV_MASK                     0x40u
+#define PMC_SPMSC2_LVDV_SHIFT                    6
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC                                      ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASES                                { PMC }
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t IOFLT;                             /**< Port Filter Register, offset: 0x0 */
+  __IO uint32_t PUEL;                              /**< Port Pullup Enable Low Register, offset: 0x4 */
+  __IO uint32_t PUEH;                              /**< Port Pullup Enable High Register, offset: 0x8 */
+  __IO uint32_t HDRVE;                             /**< Port High Drive Enable Register, offset: 0xC */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* IOFLT Bit Fields */
+#define PORT_IOFLT_FLTA_MASK                     0x3u
+#define PORT_IOFLT_FLTA_SHIFT                    0
+#define PORT_IOFLT_FLTA(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTA_SHIFT))&PORT_IOFLT_FLTA_MASK)
+#define PORT_IOFLT_FLTB_MASK                     0xCu
+#define PORT_IOFLT_FLTB_SHIFT                    2
+#define PORT_IOFLT_FLTB(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTB_SHIFT))&PORT_IOFLT_FLTB_MASK)
+#define PORT_IOFLT_FLTC_MASK                     0x30u
+#define PORT_IOFLT_FLTC_SHIFT                    4
+#define PORT_IOFLT_FLTC(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTC_SHIFT))&PORT_IOFLT_FLTC_MASK)
+#define PORT_IOFLT_FLTD_MASK                     0xC0u
+#define PORT_IOFLT_FLTD_SHIFT                    6
+#define PORT_IOFLT_FLTD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTD_SHIFT))&PORT_IOFLT_FLTD_MASK)
+#define PORT_IOFLT_FLTE_MASK                     0x300u
+#define PORT_IOFLT_FLTE_SHIFT                    8
+#define PORT_IOFLT_FLTE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTE_SHIFT))&PORT_IOFLT_FLTE_MASK)
+#define PORT_IOFLT_FLTF_MASK                     0xC00u
+#define PORT_IOFLT_FLTF_SHIFT                    10
+#define PORT_IOFLT_FLTF(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTF_SHIFT))&PORT_IOFLT_FLTF_MASK)
+#define PORT_IOFLT_FLTG_MASK                     0x3000u
+#define PORT_IOFLT_FLTG_SHIFT                    12
+#define PORT_IOFLT_FLTG(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTG_SHIFT))&PORT_IOFLT_FLTG_MASK)
+#define PORT_IOFLT_FLTH_MASK                     0xC000u
+#define PORT_IOFLT_FLTH_SHIFT                    14
+#define PORT_IOFLT_FLTH(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTH_SHIFT))&PORT_IOFLT_FLTH_MASK)
+#define PORT_IOFLT_FLTRST_MASK                   0x30000u
+#define PORT_IOFLT_FLTRST_SHIFT                  16
+#define PORT_IOFLT_FLTRST(x)                     (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTRST_SHIFT))&PORT_IOFLT_FLTRST_MASK)
+#define PORT_IOFLT_FLTKBI0_MASK                  0xC0000u
+#define PORT_IOFLT_FLTKBI0_SHIFT                 18
+#define PORT_IOFLT_FLTKBI0(x)                    (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTKBI0_SHIFT))&PORT_IOFLT_FLTKBI0_MASK)
+#define PORT_IOFLT_FLTKBI1_MASK                  0x300000u
+#define PORT_IOFLT_FLTKBI1_SHIFT                 20
+#define PORT_IOFLT_FLTKBI1(x)                    (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTKBI1_SHIFT))&PORT_IOFLT_FLTKBI1_MASK)
+#define PORT_IOFLT_FLTNMI_MASK                   0xC00000u
+#define PORT_IOFLT_FLTNMI_SHIFT                  22
+#define PORT_IOFLT_FLTNMI(x)                     (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTNMI_SHIFT))&PORT_IOFLT_FLTNMI_MASK)
+#define PORT_IOFLT_FLTDIV1_MASK                  0x3000000u
+#define PORT_IOFLT_FLTDIV1_SHIFT                 24
+#define PORT_IOFLT_FLTDIV1(x)                    (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTDIV1_SHIFT))&PORT_IOFLT_FLTDIV1_MASK)
+#define PORT_IOFLT_FLTDIV2_MASK                  0x1C000000u
+#define PORT_IOFLT_FLTDIV2_SHIFT                 26
+#define PORT_IOFLT_FLTDIV2(x)                    (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTDIV2_SHIFT))&PORT_IOFLT_FLTDIV2_MASK)
+#define PORT_IOFLT_FLTDIV3_MASK                  0xE0000000u
+#define PORT_IOFLT_FLTDIV3_SHIFT                 29
+#define PORT_IOFLT_FLTDIV3(x)                    (((uint32_t)(((uint32_t)(x))<<PORT_IOFLT_FLTDIV3_SHIFT))&PORT_IOFLT_FLTDIV3_MASK)
+/* PUEL Bit Fields */
+#define PORT_PUEL_PTAPE0_MASK                    0x1u
+#define PORT_PUEL_PTAPE0_SHIFT                   0
+#define PORT_PUEL_PTAPE1_MASK                    0x2u
+#define PORT_PUEL_PTAPE1_SHIFT                   1
+#define PORT_PUEL_PTAPE2_MASK                    0x4u
+#define PORT_PUEL_PTAPE2_SHIFT                   2
+#define PORT_PUEL_PTAPE3_MASK                    0x8u
+#define PORT_PUEL_PTAPE3_SHIFT                   3
+#define PORT_PUEL_PTAPE4_MASK                    0x10u
+#define PORT_PUEL_PTAPE4_SHIFT                   4
+#define PORT_PUEL_PTAPE5_MASK                    0x20u
+#define PORT_PUEL_PTAPE5_SHIFT                   5
+#define PORT_PUEL_PTAPE6_MASK                    0x40u
+#define PORT_PUEL_PTAPE6_SHIFT                   6
+#define PORT_PUEL_PTAPE7_MASK                    0x80u
+#define PORT_PUEL_PTAPE7_SHIFT                   7
+#define PORT_PUEL_PTBPE0_MASK                    0x100u
+#define PORT_PUEL_PTBPE0_SHIFT                   8
+#define PORT_PUEL_PTBPE1_MASK                    0x200u
+#define PORT_PUEL_PTBPE1_SHIFT                   9
+#define PORT_PUEL_PTBPE2_MASK                    0x400u
+#define PORT_PUEL_PTBPE2_SHIFT                   10
+#define PORT_PUEL_PTBPE3_MASK                    0x800u
+#define PORT_PUEL_PTBPE3_SHIFT                   11
+#define PORT_PUEL_PTBPE4_MASK                    0x1000u
+#define PORT_PUEL_PTBPE4_SHIFT                   12
+#define PORT_PUEL_PTBPE5_MASK                    0x2000u
+#define PORT_PUEL_PTBPE5_SHIFT                   13
+#define PORT_PUEL_PTBPE6_MASK                    0x4000u
+#define PORT_PUEL_PTBPE6_SHIFT                   14
+#define PORT_PUEL_PTBPE7_MASK                    0x8000u
+#define PORT_PUEL_PTBPE7_SHIFT                   15
+#define PORT_PUEL_PTCPE0_MASK                    0x10000u
+#define PORT_PUEL_PTCPE0_SHIFT                   16
+#define PORT_PUEL_PTCPE1_MASK                    0x20000u
+#define PORT_PUEL_PTCPE1_SHIFT                   17
+#define PORT_PUEL_PTCPE2_MASK                    0x40000u
+#define PORT_PUEL_PTCPE2_SHIFT                   18
+#define PORT_PUEL_PTCPE3_MASK                    0x80000u
+#define PORT_PUEL_PTCPE3_SHIFT                   19
+#define PORT_PUEL_PTCPE4_MASK                    0x100000u
+#define PORT_PUEL_PTCPE4_SHIFT                   20
+#define PORT_PUEL_PTCPE5_MASK                    0x200000u
+#define PORT_PUEL_PTCPE5_SHIFT                   21
+#define PORT_PUEL_PTCPE6_MASK                    0x400000u
+#define PORT_PUEL_PTCPE6_SHIFT                   22
+#define PORT_PUEL_PTCPE7_MASK                    0x800000u
+#define PORT_PUEL_PTCPE7_SHIFT                   23
+#define PORT_PUEL_PTDPE0_MASK                    0x1000000u
+#define PORT_PUEL_PTDPE0_SHIFT                   24
+#define PORT_PUEL_PTDPE1_MASK                    0x2000000u
+#define PORT_PUEL_PTDPE1_SHIFT                   25
+#define PORT_PUEL_PTDPE2_MASK                    0x4000000u
+#define PORT_PUEL_PTDPE2_SHIFT                   26
+#define PORT_PUEL_PTDPE3_MASK                    0x8000000u
+#define PORT_PUEL_PTDPE3_SHIFT                   27
+#define PORT_PUEL_PTDPE4_MASK                    0x10000000u
+#define PORT_PUEL_PTDPE4_SHIFT                   28
+#define PORT_PUEL_PTDPE5_MASK                    0x20000000u
+#define PORT_PUEL_PTDPE5_SHIFT                   29
+#define PORT_PUEL_PTDPE6_MASK                    0x40000000u
+#define PORT_PUEL_PTDPE6_SHIFT                   30
+#define PORT_PUEL_PTDPE7_MASK                    0x80000000u
+#define PORT_PUEL_PTDPE7_SHIFT                   31
+/* PUEH Bit Fields */
+#define PORT_PUEH_PTEPE0_MASK                    0x1u
+#define PORT_PUEH_PTEPE0_SHIFT                   0
+#define PORT_PUEH_PTEPE1_MASK                    0x2u
+#define PORT_PUEH_PTEPE1_SHIFT                   1
+#define PORT_PUEH_PTEPE2_MASK                    0x4u
+#define PORT_PUEH_PTEPE2_SHIFT                   2
+#define PORT_PUEH_PTEPE3_MASK                    0x8u
+#define PORT_PUEH_PTEPE3_SHIFT                   3
+#define PORT_PUEH_PTEPE4_MASK                    0x10u
+#define PORT_PUEH_PTEPE4_SHIFT                   4
+#define PORT_PUEH_PTEPE5_MASK                    0x20u
+#define PORT_PUEH_PTEPE5_SHIFT                   5
+#define PORT_PUEH_PTEPE6_MASK                    0x40u
+#define PORT_PUEH_PTEPE6_SHIFT                   6
+#define PORT_PUEH_PTEPE7_MASK                    0x80u
+#define PORT_PUEH_PTEPE7_SHIFT                   7
+#define PORT_PUEH_PTFPE0_MASK                    0x100u
+#define PORT_PUEH_PTFPE0_SHIFT                   8
+#define PORT_PUEH_PTFPE1_MASK                    0x200u
+#define PORT_PUEH_PTFPE1_SHIFT                   9
+#define PORT_PUEH_PTFPE2_MASK                    0x400u
+#define PORT_PUEH_PTFPE2_SHIFT                   10
+#define PORT_PUEH_PTFPE3_MASK                    0x800u
+#define PORT_PUEH_PTFPE3_SHIFT                   11
+#define PORT_PUEH_PTFPE4_MASK                    0x1000u
+#define PORT_PUEH_PTFPE4_SHIFT                   12
+#define PORT_PUEH_PTFPE5_MASK                    0x2000u
+#define PORT_PUEH_PTFPE5_SHIFT                   13
+#define PORT_PUEH_PTFPE6_MASK                    0x4000u
+#define PORT_PUEH_PTFPE6_SHIFT                   14
+#define PORT_PUEH_PTFPE7_MASK                    0x8000u
+#define PORT_PUEH_PTFPE7_SHIFT                   15
+#define PORT_PUEH_PTGPE0_MASK                    0x10000u
+#define PORT_PUEH_PTGPE0_SHIFT                   16
+#define PORT_PUEH_PTGPE1_MASK                    0x20000u
+#define PORT_PUEH_PTGPE1_SHIFT                   17
+#define PORT_PUEH_PTGPE2_MASK                    0x40000u
+#define PORT_PUEH_PTGPE2_SHIFT                   18
+#define PORT_PUEH_PTGPE3_MASK                    0x80000u
+#define PORT_PUEH_PTGPE3_SHIFT                   19
+#define PORT_PUEH_PTHPE0_MASK                    0x1000000u
+#define PORT_PUEH_PTHPE0_SHIFT                   24
+#define PORT_PUEH_PTHPE1_MASK                    0x2000000u
+#define PORT_PUEH_PTHPE1_SHIFT                   25
+#define PORT_PUEH_PTHPE2_MASK                    0x4000000u
+#define PORT_PUEH_PTHPE2_SHIFT                   26
+#define PORT_PUEH_PTHPE6_MASK                    0x40000000u
+#define PORT_PUEH_PTHPE6_SHIFT                   30
+#define PORT_PUEH_PTHPE7_MASK                    0x80000000u
+#define PORT_PUEH_PTHPE7_SHIFT                   31
+/* HDRVE Bit Fields */
+#define PORT_HDRVE_PTB4_MASK                     0x1u
+#define PORT_HDRVE_PTB4_SHIFT                    0
+#define PORT_HDRVE_PTB5_MASK                     0x2u
+#define PORT_HDRVE_PTB5_SHIFT                    1
+#define PORT_HDRVE_PTD0_MASK                     0x4u
+#define PORT_HDRVE_PTD0_SHIFT                    2
+#define PORT_HDRVE_PTD1_MASK                     0x8u
+#define PORT_HDRVE_PTD1_SHIFT                    3
+#define PORT_HDRVE_PTE0_MASK                     0x10u
+#define PORT_HDRVE_PTE0_SHIFT                    4
+#define PORT_HDRVE_PTE1_MASK                     0x20u
+#define PORT_HDRVE_PTE1_SHIFT                    5
+#define PORT_HDRVE_PTH0_MASK                     0x40u
+#define PORT_HDRVE_PTH0_SHIFT                    6
+#define PORT_HDRVE_PTH1_MASK                     0x80u
+#define PORT_HDRVE_PTH1_SHIFT                    7
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORT base address */
+#define PORT_BASE                                (0x40049000u)
+/** Peripheral PORT base pointer */
+#define PORT                                     ((PORT_Type *)PORT_BASE)
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASES                               { PORT }
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< RTC Status and Control Register, offset: 0x0 */
+  __IO uint32_t MOD;                               /**< RTC Modulo Register, offset: 0x4 */
+  __I  uint32_t CNT;                               /**< RTC Counter Register, offset: 0x8 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define RTC_SC_RTCO_MASK                         0x10u
+#define RTC_SC_RTCO_SHIFT                        4
+#define RTC_SC_RTIE_MASK                         0x40u
+#define RTC_SC_RTIE_SHIFT                        6
+#define RTC_SC_RTIF_MASK                         0x80u
+#define RTC_SC_RTIF_SHIFT                        7
+#define RTC_SC_RTCPS_MASK                        0x700u
+#define RTC_SC_RTCPS_SHIFT                       8
+#define RTC_SC_RTCPS(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_SC_RTCPS_SHIFT))&RTC_SC_RTCPS_MASK)
+#define RTC_SC_RTCLKS_MASK                       0xC000u
+#define RTC_SC_RTCLKS_SHIFT                      14
+#define RTC_SC_RTCLKS(x)                         (((uint32_t)(((uint32_t)(x))<<RTC_SC_RTCLKS_SHIFT))&RTC_SC_RTCLKS_MASK)
+/* MOD Bit Fields */
+#define RTC_MOD_MOD_MASK                         0xFFFFu
+#define RTC_MOD_MOD_SHIFT                        0
+#define RTC_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_MOD_MOD_SHIFT))&RTC_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define RTC_CNT_CNT_MASK                         0xFFFFu
+#define RTC_CNT_CNT_SHIFT                        0
+#define RTC_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CNT_CNT_SHIFT))&RTC_CNT_CNT_MASK)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASES                                { RTC }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t SRSID;                             /**< System Reset Status and ID Register, offset: 0x0 */
+  __IO uint32_t SOPT;                              /**< System Options Register, offset: 0x4 */
+  __IO uint32_t PINSEL;                            /**< Pin Selection Register, offset: 0x8 */
+  __IO uint32_t SCGC;                              /**< System Clock Gating Control Register, offset: 0xC */
+  __I  uint32_t UUIDL;                             /**< Universally Unique Identifier Low Register, offset: 0x10 */
+  __I  uint32_t UUIDM; 
+  __I  uint32_t UUIDH;                             /**< Universally Unique Identifier High Register, offset: 0x14 */
+  __IO uint32_t BUSDIV;                            /**< BUS Clock Divider Register, offset: 0x18 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SRSID Bit Fields */
+#define SIM_SRSID_LVD_MASK                       0x2u
+#define SIM_SRSID_LVD_SHIFT                      1
+#define SIM_SRSID_LOC_MASK                       0x4u
+#define SIM_SRSID_LOC_SHIFT                      2
+#define SIM_SRSID_WDOG_MASK                      0x20u
+#define SIM_SRSID_WDOG_SHIFT                     5
+#define SIM_SRSID_PIN_MASK                       0x40u
+#define SIM_SRSID_PIN_SHIFT                      6
+#define SIM_SRSID_POR_MASK                       0x80u
+#define SIM_SRSID_POR_SHIFT                      7
+#define SIM_SRSID_LOCKUP_MASK                    0x200u
+#define SIM_SRSID_LOCKUP_SHIFT                   9
+#define SIM_SRSID_SW_MASK                        0x400u
+#define SIM_SRSID_SW_SHIFT                       10
+#define SIM_SRSID_MDMAP_MASK                     0x800u
+#define SIM_SRSID_MDMAP_SHIFT                    11
+#define SIM_SRSID_SACKERR_MASK                   0x2000u
+#define SIM_SRSID_SACKERR_SHIFT                  13
+#define SIM_SRSID_PINID_MASK                     0xF0000u
+#define SIM_SRSID_PINID_SHIFT                    16
+#define SIM_SRSID_PINID(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SRSID_PINID_SHIFT))&SIM_SRSID_PINID_MASK)
+#define SIM_SRSID_RevID_MASK                     0xF00000u
+#define SIM_SRSID_RevID_SHIFT                    20
+#define SIM_SRSID_RevID(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SRSID_RevID_SHIFT))&SIM_SRSID_RevID_MASK)
+#define SIM_SRSID_SUBFAMID_MASK                  0xF000000u
+#define SIM_SRSID_SUBFAMID_SHIFT                 24
+#define SIM_SRSID_SUBFAMID(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SRSID_SUBFAMID_SHIFT))&SIM_SRSID_SUBFAMID_MASK)
+#define SIM_SRSID_FAMID_MASK                     0xF0000000u
+#define SIM_SRSID_FAMID_SHIFT                    28
+#define SIM_SRSID_FAMID(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SRSID_FAMID_SHIFT))&SIM_SRSID_FAMID_MASK)
+/* SOPT Bit Fields */
+#define SIM_SOPT_NMIE_MASK                       0x2u
+#define SIM_SOPT_NMIE_SHIFT                      1
+#define SIM_SOPT_RSTPE_MASK                      0x4u
+#define SIM_SOPT_RSTPE_SHIFT                     2
+#define SIM_SOPT_SWDE_MASK                       0x8u
+#define SIM_SOPT_SWDE_SHIFT                      3
+#define SIM_SOPT_ADHWT_MASK                      0x300u
+#define SIM_SOPT_ADHWT_SHIFT                     8
+#define SIM_SOPT_ADHWT(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SOPT_ADHWT_SHIFT))&SIM_SOPT_ADHWT_MASK)
+#define SIM_SOPT_RTCC_MASK                       0x400u
+#define SIM_SOPT_RTCC_SHIFT                      10
+#define SIM_SOPT_ACIC_MASK                       0x800u
+#define SIM_SOPT_ACIC_SHIFT                      11
+#define SIM_SOPT_RXDCE_MASK                      0x1000u
+#define SIM_SOPT_RXDCE_SHIFT                     12
+#define SIM_SOPT_RXDFE_MASK                      0x2000u
+#define SIM_SOPT_RXDFE_SHIFT                     13
+#define SIM_SOPT_ETMSYNC_MASK                    0x4000u
+#define SIM_SOPT_ETMSYNC_SHIFT                   14
+#define SIM_SOPT_TXDME_MASK                      0x8000u
+#define SIM_SOPT_TXDME_SHIFT                     15
+#define SIM_SOPT_BUSREF_MASK                     0x70000u
+#define SIM_SOPT_BUSREF_SHIFT                    16
+#define SIM_SOPT_BUSREF(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SOPT_BUSREF_SHIFT))&SIM_SOPT_BUSREF_MASK)
+#define SIM_SOPT_CLKOE_MASK                      0x80000u
+#define SIM_SOPT_CLKOE_SHIFT                     19
+#define SIM_SOPT_DLYACT_MASK                     0x800000u
+#define SIM_SOPT_DLYACT_SHIFT                    23
+#define SIM_SOPT_DELAY_MASK                      0xFF000000u
+#define SIM_SOPT_DELAY_SHIFT                     24
+#define SIM_SOPT_DELAY(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SOPT_DELAY_SHIFT))&SIM_SOPT_DELAY_MASK)
+/* PINSEL Bit Fields */
+#define SIM_PINSEL_RTCPS_MASK                    0x10u
+#define SIM_PINSEL_RTCPS_SHIFT                   4
+#define SIM_PINSEL_IICPS_MASK                    0x20u
+#define SIM_PINSEL_IICPS_SHIFT                   5
+#define SIM_PINSEL_SPI0PS_MASK                   0x40u
+#define SIM_PINSEL_SPI0PS_SHIFT                  6
+#define SIM_PINSEL_UART0PS_MASK                  0x80u
+#define SIM_PINSEL_UART0PS_SHIFT                 7
+#define SIM_PINSEL_ETM0PS0_MASK                  0x100u
+#define SIM_PINSEL_ETM0PS0_SHIFT                 8
+#define SIM_PINSEL_ETM0PS1_MASK                  0x200u
+#define SIM_PINSEL_ETM0PS1_SHIFT                 9
+#define SIM_PINSEL_ETM1PS0_MASK                  0x400u
+#define SIM_PINSEL_ETM1PS0_SHIFT                 10
+#define SIM_PINSEL_ETM1PS1_MASK                  0x800u
+#define SIM_PINSEL_ETM1PS1_SHIFT                 11
+#define SIM_PINSEL_ETM2PS0_MASK                  0x1000u
+#define SIM_PINSEL_ETM2PS0_SHIFT                 12
+#define SIM_PINSEL_ETM2PS1_MASK                  0x2000u
+#define SIM_PINSEL_ETM2PS1_SHIFT                 13
+#define SIM_PINSEL_ETM2PS2_MASK                  0x4000u
+#define SIM_PINSEL_ETM2PS2_SHIFT                 14
+#define SIM_PINSEL_ETM2PS3_MASK                  0x8000u
+#define SIM_PINSEL_ETM2PS3_SHIFT                 15
+/* SCGC Bit Fields */
+#define SIM_SCGC_RTC_MASK                        0x1u
+#define SIM_SCGC_RTC_SHIFT                       0
+#define SIM_SCGC_PIT_MASK                        0x2u
+#define SIM_SCGC_PIT_SHIFT                       1
+#define SIM_SCGC_ETM0_MASK                       0x20u
+#define SIM_SCGC_ETM0_SHIFT                      5
+#define SIM_SCGC_ETM1_MASK                       0x40u
+#define SIM_SCGC_ETM1_SHIFT                      6
+#define SIM_SCGC_ETM2_MASK                       0x80u
+#define SIM_SCGC_ETM2_SHIFT                      7
+#define SIM_SCGC_CRC_MASK                        0x400u
+#define SIM_SCGC_CRC_SHIFT                       10
+#define SIM_SCGC_FLASH_MASK                      0x1000u
+#define SIM_SCGC_FLASH_SHIFT                     12
+#define SIM_SCGC_SWD_MASK                        0x2000u
+#define SIM_SCGC_SWD_SHIFT                       13
+#define SIM_SCGC_IIC_MASK                        0x20000u
+#define SIM_SCGC_IIC_SHIFT                       17
+#define SIM_SCGC_SPI0_MASK                       0x40000u
+#define SIM_SCGC_SPI0_SHIFT                      18
+#define SIM_SCGC_SPI1_MASK                       0x80000u
+#define SIM_SCGC_SPI1_SHIFT                      19
+#define SIM_SCGC_UART0_MASK                      0x100000u
+#define SIM_SCGC_UART0_SHIFT                     20
+#define SIM_SCGC_UART1_MASK                      0x200000u
+#define SIM_SCGC_UART1_SHIFT                     21
+#define SIM_SCGC_UART2_MASK                      0x400000u
+#define SIM_SCGC_UART2_SHIFT                     22
+#define SIM_SCGC_KBI0_MASK                       0x1000000u
+#define SIM_SCGC_KBI0_SHIFT                      24
+#define SIM_SCGC_KBI1_MASK                       0x2000000u
+#define SIM_SCGC_KBI1_SHIFT                      25
+#define SIM_SCGC_IRQ_MASK                        0x8000000u
+#define SIM_SCGC_IRQ_SHIFT                       27
+#define SIM_SCGC_ADC_MASK                        0x20000000u
+#define SIM_SCGC_ADC_SHIFT                       29
+#define SIM_SCGC_ACMP0_MASK                      0x40000000u
+#define SIM_SCGC_ACMP0_SHIFT                     30
+#define SIM_SCGC_ACMP1_MASK                      0x80000000u
+#define SIM_SCGC_ACMP1_SHIFT                     31
+/* UUIDL Bit Fields */
+#define SIM_UUIDL_ID_MASK                        0xFFFFFFFFu
+#define SIM_UUIDL_ID_SHIFT                       0
+#define SIM_UUIDL_ID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UUIDL_ID_SHIFT))&SIM_UUIDL_ID_MASK)
+/* UUIDH Bit Fields */
+#define SIM_UUIDM_ID_MASK                        0xFFFFFFFFu
+#define SIM_UUIDM_ID_SHIFT                       0
+#define SIM_UUIDM_ID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UUIDM_ID_SHIFT))&SIM_UUIDM_ID_MASK)
+/* UUIDM Bit Fields */
+#define SIM_UUIDH_ID_MASK                        0xFFFFFFFFu
+#define SIM_UUIDH_ID_SHIFT                       0
+#define SIM_UUIDH_ID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UUIDH_ID_SHIFT))&SIM_UUIDH_ID_MASK)
+/* BUSDIV Bit Fields */
+#define SIM_BUSDIV_BUSDIV_MASK                   0x1u
+#define SIM_BUSDIV_BUSDIV_SHIFT                  0
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40048000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASES                                { SIM }
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< SPI control register 1, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< SPI control register 2, offset: 0x1 */
+  __IO uint8_t BR;                                 /**< SPI baud rate register, offset: 0x2 */
+  __I  uint8_t S;                                  /**< SPI status register, offset: 0x3 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t D;                                  /**< SPI data register, offset: 0x5 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t M;                                  /**< SPI match register, offset: 0x7 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define SPI_C1_LSBFE_MASK                        0x1u
+#define SPI_C1_LSBFE_SHIFT                       0
+#define SPI_C1_SSOE_MASK                         0x2u
+#define SPI_C1_SSOE_SHIFT                        1
+#define SPI_C1_CPHA_MASK                         0x4u
+#define SPI_C1_CPHA_SHIFT                        2
+#define SPI_C1_CPOL_MASK                         0x8u
+#define SPI_C1_CPOL_SHIFT                        3
+#define SPI_C1_MSTR_MASK                         0x10u
+#define SPI_C1_MSTR_SHIFT                        4
+#define SPI_C1_SPTIE_MASK                        0x20u
+#define SPI_C1_SPTIE_SHIFT                       5
+#define SPI_C1_SPE_MASK                          0x40u
+#define SPI_C1_SPE_SHIFT                         6
+#define SPI_C1_SPIE_MASK                         0x80u
+#define SPI_C1_SPIE_SHIFT                        7
+/* C2 Bit Fields */
+#define SPI_C2_SPC0_MASK                         0x1u
+#define SPI_C2_SPC0_SHIFT                        0
+#define SPI_C2_SPISWAI_MASK                      0x2u
+#define SPI_C2_SPISWAI_SHIFT                     1
+#define SPI_C2_BIDIROE_MASK                      0x8u
+#define SPI_C2_BIDIROE_SHIFT                     3
+#define SPI_C2_MODFEN_MASK                       0x10u
+#define SPI_C2_MODFEN_SHIFT                      4
+#define SPI_C2_SPMIE_MASK                        0x80u
+#define SPI_C2_SPMIE_SHIFT                       7
+/* BR Bit Fields */
+#define SPI_BR_SPR_MASK                          0xFu
+#define SPI_BR_SPR_SHIFT                         0
+#define SPI_BR_SPR(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK                         0x70u
+#define SPI_BR_SPPR_SHIFT                        4
+#define SPI_BR_SPPR(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
+/* S Bit Fields */
+#define SPI_S_MODF_MASK                          0x10u
+#define SPI_S_MODF_SHIFT                         4
+#define SPI_S_SPTEF_MASK                         0x20u
+#define SPI_S_SPTEF_SHIFT                        5
+#define SPI_S_SPMF_MASK                          0x40u
+#define SPI_S_SPMF_SHIFT                         6
+#define SPI_S_SPRF_MASK                          0x80u
+#define SPI_S_SPRF_SHIFT                         7
+/* D Bit Fields */
+#define SPI_D_Bits_MASK                          0xFFu
+#define SPI_D_Bits_SHIFT                         0
+#define SPI_D_Bits(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
+/* M Bit Fields */
+#define SPI_M_Bits_MASK                          0xFFu
+#define SPI_M_Bits_SHIFT                         0
+#define SPI_M_Bits(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x40077000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASES                                { SPI0, SPI1 }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /**< UART Baud Rate Register: High, offset: 0x0 */
+  __IO uint8_t BDL;                                /**< UART Baud Rate Register: Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
+  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK                        0x1Fu
+#define UART_BDH_SBR_SHIFT                       0
+#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK                       0x20u
+#define UART_BDH_SBNS_SHIFT                      5
+#define UART_BDH_RXEDGIE_MASK                    0x40u
+#define UART_BDH_RXEDGIE_SHIFT                   6
+#define UART_BDH_LBKDIE_MASK                     0x80u
+#define UART_BDH_LBKDIE_SHIFT                    7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK                        0xFFu
+#define UART_BDL_SBR_SHIFT                       0
+#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK                          0x1u
+#define UART_C1_PT_SHIFT                         0
+#define UART_C1_PE_MASK                          0x2u
+#define UART_C1_PE_SHIFT                         1
+#define UART_C1_ILT_MASK                         0x4u
+#define UART_C1_ILT_SHIFT                        2
+#define UART_C1_WAKE_MASK                        0x8u
+#define UART_C1_WAKE_SHIFT                       3
+#define UART_C1_M_MASK                           0x10u
+#define UART_C1_M_SHIFT                          4
+#define UART_C1_RSRC_MASK                        0x20u
+#define UART_C1_RSRC_SHIFT                       5
+#define UART_C1_UARTSWAI_MASK                    0x40u
+#define UART_C1_UARTSWAI_SHIFT                   6
+#define UART_C1_LOOPS_MASK                       0x80u
+#define UART_C1_LOOPS_SHIFT                      7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK                         0x1u
+#define UART_C2_SBK_SHIFT                        0
+#define UART_C2_RWU_MASK                         0x2u
+#define UART_C2_RWU_SHIFT                        1
+#define UART_C2_RE_MASK                          0x4u
+#define UART_C2_RE_SHIFT                         2
+#define UART_C2_TE_MASK                          0x8u
+#define UART_C2_TE_SHIFT                         3
+#define UART_C2_ILIE_MASK                        0x10u
+#define UART_C2_ILIE_SHIFT                       4
+#define UART_C2_RIE_MASK                         0x20u
+#define UART_C2_RIE_SHIFT                        5
+#define UART_C2_TCIE_MASK                        0x40u
+#define UART_C2_TCIE_SHIFT                       6
+#define UART_C2_TIE_MASK                         0x80u
+#define UART_C2_TIE_SHIFT                        7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK                          0x1u
+#define UART_S1_PF_SHIFT                         0
+#define UART_S1_FE_MASK                          0x2u
+#define UART_S1_FE_SHIFT                         1
+#define UART_S1_NF_MASK                          0x4u
+#define UART_S1_NF_SHIFT                         2
+#define UART_S1_OR_MASK                          0x8u
+#define UART_S1_OR_SHIFT                         3
+#define UART_S1_IDLE_MASK                        0x10u
+#define UART_S1_IDLE_SHIFT                       4
+#define UART_S1_RDRF_MASK                        0x20u
+#define UART_S1_RDRF_SHIFT                       5
+#define UART_S1_TC_MASK                          0x40u
+#define UART_S1_TC_SHIFT                         6
+#define UART_S1_TDRE_MASK                        0x80u
+#define UART_S1_TDRE_SHIFT                       7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK                         0x1u
+#define UART_S2_RAF_SHIFT                        0
+#define UART_S2_LBKDE_MASK                       0x2u
+#define UART_S2_LBKDE_SHIFT                      1
+#define UART_S2_BRK13_MASK                       0x4u
+#define UART_S2_BRK13_SHIFT                      2
+#define UART_S2_RWUID_MASK                       0x8u
+#define UART_S2_RWUID_SHIFT                      3
+#define UART_S2_RXINV_MASK                       0x10u
+#define UART_S2_RXINV_SHIFT                      4
+#define UART_S2_RXEDGIF_MASK                     0x40u
+#define UART_S2_RXEDGIF_SHIFT                    6
+#define UART_S2_LBKDIF_MASK                      0x80u
+#define UART_S2_LBKDIF_SHIFT                     7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK                        0x1u
+#define UART_C3_PEIE_SHIFT                       0
+#define UART_C3_FEIE_MASK                        0x2u
+#define UART_C3_FEIE_SHIFT                       1
+#define UART_C3_NEIE_MASK                        0x4u
+#define UART_C3_NEIE_SHIFT                       2
+#define UART_C3_ORIE_MASK                        0x8u
+#define UART_C3_ORIE_SHIFT                       3
+#define UART_C3_TXINV_MASK                       0x10u
+#define UART_C3_TXINV_SHIFT                      4
+#define UART_C3_TXDIR_MASK                       0x20u
+#define UART_C3_TXDIR_SHIFT                      5
+#define UART_C3_T8_MASK                          0x40u
+#define UART_C3_T8_SHIFT                         6
+#define UART_C3_R8_MASK                          0x80u
+#define UART_C3_R8_SHIFT                         7
+/* D Bit Fields */
+#define UART_D_R0T0_MASK                         0x1u
+#define UART_D_R0T0_SHIFT                        0
+#define UART_D_R1T1_MASK                         0x2u
+#define UART_D_R1T1_SHIFT                        1
+#define UART_D_R2T2_MASK                         0x4u
+#define UART_D_R2T2_SHIFT                        2
+#define UART_D_R3T3_MASK                         0x8u
+#define UART_D_R3T3_SHIFT                        3
+#define UART_D_R4T4_MASK                         0x10u
+#define UART_D_R4T4_SHIFT                        4
+#define UART_D_R5T5_MASK                         0x20u
+#define UART_D_R5T5_SHIFT                        5
+#define UART_D_R6T6_MASK                         0x40u
+#define UART_D_R6T6_SHIFT                        6
+#define UART_D_R7T7_MASK                         0x80u
+#define UART_D_R7T7_SHIFT                        7
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE                               (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0                                    ((UART_Type *)UART0_BASE)
+/** Peripheral UART1 base address */
+#define UART1_BASE                               (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1                                    ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE                               (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2                                    ((UART_Type *)UART2_BASE)
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASES                               { UART0, UART1, UART2 }
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CS1;                                /**< Watchdog Control and Status Register 1, offset: 0x0 */
+  __IO uint8_t CS2;                                /**< Watchdog Control and Status Register 2, offset: 0x1 */
+  union {                                          /* offset: 0x2 */
+    __IO uint16_t CNT;                               /**< WDOG_CNT register., offset: 0x2 */
+    struct {                                         /* offset: 0x2 */
+      __I  uint8_t CNTH;                               /**< Watchdog Counter Register: High, offset: 0x2 */
+      __I  uint8_t CNTL;                               /**< Watchdog Counter Register: Low, offset: 0x3 */
+    } CNT8B;
+  };
+  union {                                          /* offset: 0x4 */
+    __IO uint16_t TOVAL;                             /**< WDOG_TOVAL register., offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t TOVALH;                             /**< Watchdog ETMeout Value Register: High, offset: 0x4 */
+      __IO uint8_t TOVALL;                             /**< Watchdog ETMeout Value Register: Low, offset: 0x5 */
+    } TOVAL8B;
+  };
+  union {                                          /* offset: 0x6 */
+    __IO uint16_t WIN;                               /**< WDOG_WIN register., offset: 0x6 */
+    struct {                                         /* offset: 0x6 */
+      __IO uint8_t WINH;                               /**< Watchdog Window Register: High, offset: 0x6 */
+      __IO uint8_t WINL;                               /**< Watchdog Window Register: Low, offset: 0x7 */
+    } WIN8B;
+  };
+} WDOG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* CS1 Bit Fields */
+#define WDOG_CS1_STOP_MASK                       0x1u
+#define WDOG_CS1_STOP_SHIFT                      0
+#define WDOG_CS1_WAIT_MASK                       0x2u
+#define WDOG_CS1_WAIT_SHIFT                      1
+#define WDOG_CS1_DBG_MASK                        0x4u
+#define WDOG_CS1_DBG_SHIFT                       2
+#define WDOG_CS1_TST_MASK                        0x18u
+#define WDOG_CS1_TST_SHIFT                       3
+#define WDOG_CS1_TST(x)                          (((uint8_t)(((uint8_t)(x))<<WDOG_CS1_TST_SHIFT))&WDOG_CS1_TST_MASK)
+#define WDOG_CS1_UPDATE_MASK                     0x20u
+#define WDOG_CS1_UPDATE_SHIFT                    5
+#define WDOG_CS1_INT_MASK                        0x40u
+#define WDOG_CS1_INT_SHIFT                       6
+#define WDOG_CS1_EN_MASK                         0x80u
+#define WDOG_CS1_EN_SHIFT                        7
+/* CS2 Bit Fields */
+#define WDOG_CS2_CLK_MASK                        0x3u
+#define WDOG_CS2_CLK_SHIFT                       0
+#define WDOG_CS2_CLK(x)                          (((uint8_t)(((uint8_t)(x))<<WDOG_CS2_CLK_SHIFT))&WDOG_CS2_CLK_MASK)
+#define WDOG_CS2_PRES_MASK                       0x10u
+#define WDOG_CS2_PRES_SHIFT                      4
+#define WDOG_CS2_FLG_MASK                        0x40u
+#define WDOG_CS2_FLG_SHIFT                       6
+#define WDOG_CS2_WIN_MASK                        0x80u
+#define WDOG_CS2_WIN_SHIFT                       7
+/* CNT Bit Fields */
+#define WDOG_CNT_CNT_MASK                        0xFFFFu
+#define WDOG_CNT_CNT_SHIFT                       0
+#define WDOG_CNT_CNT(x)                          (((uint16_t)(((uint16_t)(x))<<WDOG_CNT_CNT_SHIFT))&WDOG_CNT_CNT_MASK)
+/* CNTH Bit Fields */
+#define WDOG_CNTH_CNTHIGH_MASK                   0xFFu
+#define WDOG_CNTH_CNTHIGH_SHIFT                  0
+#define WDOG_CNTH_CNTHIGH(x)                     (((uint8_t)(((uint8_t)(x))<<WDOG_CNTH_CNTHIGH_SHIFT))&WDOG_CNTH_CNTHIGH_MASK)
+/* CNTL Bit Fields */
+#define WDOG_CNTL_CNTLOW_MASK                    0xFFu
+#define WDOG_CNTL_CNTLOW_SHIFT                   0
+#define WDOG_CNTL_CNTLOW(x)                      (((uint8_t)(((uint8_t)(x))<<WDOG_CNTL_CNTLOW_SHIFT))&WDOG_CNTL_CNTLOW_MASK)
+/* TOVAL Bit Fields */
+#define WDOG_TOVAL_TOVAL_MASK                    0xFFFFu
+#define WDOG_TOVAL_TOVAL_SHIFT                   0
+#define WDOG_TOVAL_TOVAL(x)                      (((uint16_t)(((uint16_t)(x))<<WDOG_TOVAL_TOVAL_SHIFT))&WDOG_TOVAL_TOVAL_MASK)
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK               0xFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT              0
+#define WDOG_TOVALH_TOVALHIGH(x)                 (((uint8_t)(((uint8_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK                0xFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT               0
+#define WDOG_TOVALL_TOVALLOW(x)                  (((uint8_t)(((uint8_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WIN Bit Fields */
+#define WDOG_WIN_WIN_MASK                        0xFFFFu
+#define WDOG_WIN_WIN_SHIFT                       0
+#define WDOG_WIN_WIN(x)                          (((uint16_t)(((uint16_t)(x))<<WDOG_WIN_WIN_SHIFT))&WDOG_WIN_WIN_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK                   0xFFu
+#define WDOG_WINH_WINHIGH_SHIFT                  0
+#define WDOG_WINH_WINHIGH(x)                     (((uint8_t)(((uint8_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK                    0xFFu
+#define WDOG_WINL_WINLOW_SHIFT                   0
+#define WDOG_WINL_WINLOW(x)                      (((uint8_t)(((uint8_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE                                (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG                                     ((WDOG_Type *)WDOG_BASE)
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASES                               { WDOG }
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Backward Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define NV_DFPROT_DPS_MASK                NV_EEPROT_DPS_MASK
+#define NV_DFPROT_DPS_SHIFT               NV_EEPROT_DPS_SHIFT
+#define NV_DFPROT_DPS(x)                  NV_EEPROT_DPS(x)
+#define NV_DFPROT_DPOPEN_MASK             NV_EEPROT_DPOPEN_MASK
+#define NV_DFPROT_DPOPEN_SHIFT            NV_EEPROT_DPOPEN_SHIFT
+#define NV_DFPROT_DPOPEN_SHIFT            NV_EEPROT_DPOPEN_SHIFT
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#endif  /* #if !defined(NV32_H_) */
+
+/* NV32.h, eof. */

bsp/nv32f100x/lib/inc/NV32_config.h

@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* NOTE:系统所使用的一些宏定义，以及时钟模式的选择。
+******************************************************************************/
+
+#ifndef _NVxx_CONFIG_H_
+#define _NVxx_CONFIG_H_
+
+
+#include <stdint.h>
+
+#define CPU_NV32
+#define TEST
+
+
+//#define TRIM_IRC                    /*!< 是否使用定义的TRIM值来校准内部IRC，若注释则使用出厂校准的TRIM值出厂校准至37.5K--48M */
+//#define SPI0_PINREMAP               /*!< SPI0的管脚映射定义 */
+//#define ENABLE_WDOG               /*!< 使能看门狗 */
+//#define DISABLE_NMI               /*!< 禁用NMI中断输入引脚 */
+
+/*! 定义是否打印系统信息 */      
+//#define PRINT_SYS_LOG           
+
+#if     !defined(BOOT_LOADER)
+#endif
+
+//#define OUTPUT_BUSCLK             /*!< 定义是否输出系统时钟，输出引脚为PH2 */
+#define ICS_TRIM_VALUE  0x2c   
+
+
+    /*! 定义时钟的时钟模式以及频率
+     */
+   //#define USE_FEE                         /*!< 使用外部时钟FEE模式 */
+   //#define USE_FEE_OSC                     /*!< 使用外部时钟输入OSC模式 */
+     #define USE_FEI                         /*!< 使用系统内部时钟IRC */
+  // #define USE_FBELP	
+   //#define USE_FBE_OSC
+
+   /*! 定义外部晶振频率. */
+   //#define EXT_CLK_FREQ_KHZ	32          /* in KHz */
+   //#define EXT_CLK_FREQ_KHZ	4000        /* in KHz */
+   //#define EXT_CLK_FREQ_KHZ	4000        /* in KHz */
+   //#define EXT_CLK_FREQ_KHZ	1000        /* in KHz */
+     #define EXT_CLK_FREQ_KHZ	10000       /* in KHz */
+    /*! 定义所使用的UART口 */
+    #define TERM_PORT   UART1               /*!< 定义使用UART1口，开发板上默认使用UART1口 */
+
+
+    /* 定义总线时钟主频 */
+    #if	defined(USE_FEI)
+        #define  BUS_CLK_HZ		40000000L
+
+    #elif  (EXT_CLK_FREQ_KHZ == 10000)
+        #define  BUS_CLK_HZ		50000000L
+    #elif  (EXT_CLK_FREQ_KHZ == 12000)
+        #define  BUS_CLK_HZ   30000000L
+    #elif  (EXT_CLK_FREQ_KHZ == 8000)
+        #define  BUS_CLK_HZ		24000000L
+    #elif  (EXT_CLK_FREQ_KHZ == 4000)
+        #define  BUS_CLK_HZ		40000000L
+    #elif  (EXT_CLK_FREQ_KHZ == 32)
+        #define  BUS_CLK_HZ		16777216L
+    #else   
+        #define  BUS_CLK_HZ		60000000L
+    #endif
+
+    /*! define UART baud rate */
+    #define UART_PRINT_BITRATE              115200      /*! UART波特率 */
+
+
+#endif /* NVxx_CONFIG_H_ */

bsp/nv32f100x/lib/inc/acmp.h

@@ -0,0 +1,568 @@
+/******************************************************************************
+* @brief header file for ACMP utilities. 
+*
+*******************************************************************************
+*
+* provide APIs for accessing ACMP
+******************************************************************************/
+#ifndef _MY_ACMP_H_
+#define _MY_ACMP_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/* DAC reference select */
+enum
+{
+    DAC_REF_BANDGAP = 0,
+    DAC_REF_VDDA
+};
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+
+/******************************************************************************
+ * ACMP module number definition                                               *
+ ******************************************************************************/
+#define     MAX_ACMP_NO             2
+
+/******************************************************************************
+* ACMP positive and negative pin select definition
+*
+*//*! @addtogroup acmp_pinsel_list
+* @{
+*******************************************************************************/
+#define     ACMP_INPUT_P_EXT0       (0<<4)  /*!< positive pin select external pin 0 */
+#define     ACMP_INPUT_P_EXT1       (1<<4)  /*!< positive pin select external pin 1 */
+#define     ACMP_INPUT_P_EXT2       (2<<4)  /*!< positive pin select external pin 2 */
+#define     ACMP_INPUT_P_DAC        (3<<4)  /*!< positive pin select internal DAC */
+
+#define     ACMP_INPUT_N_EXT0       0       /*!< positive pin select external pin 0 */
+#define     ACMP_INPUT_N_EXT1       1       /*!< positive pin select external pin 1 */
+#define     ACMP_INPUT_N_EXT2       2       /*!< positive pin select external pin 2 */
+#define     ACMP_INPUT_N_DAC        3       /*!< positive pin select internal DAC */
+/*! @} End of acmp_pinsel_list                                                */
+
+/******************************************************************************
+* ACMP interrupt sensitivity edge definition
+*
+*//*! @addtogroup acmp_intedgesel
+* @{
+*******************************************************************************/
+#define     ACMP_SENSITIVITYMODE_FALLING   0    /*!< interrupt on falling edge  */
+#define     ACMP_SENSITIVITYMODE_RISING    1    /*!< interrupt on rising edge  */
+#define     ACMP_SENSITIVITYMODE_ANY       3    /*!< interrupt on falling or rising edge */ 
+/*! @} End of acmp_intedgesel                                                 */
+
+
+/******************************************************************************
+* ACMP hysterisis selection definition
+*
+*//*! @addtogroup acmp_hyst
+* @{
+*******************************************************************************/
+#define     ACMP_HYST_20MV                 (0<<6)  /*!< 20mv hyst */
+#define     ACMP_HYST_30MV                 (1<<6)  /*!< 30mv hyst */
+/*! @} End of acmp_hyst                                                       */
+
+
+/******************************************************************************
+* ACMP internal DAC reference selection definition
+*
+*//*! @addtogroup acmp_dacref
+* @{
+*******************************************************************************/
+#define     ACMP_DAC_REFERENCE_BANDGAP     (0<<6)  /*!< select bandgap as refference */
+#define     ACMP_DAC_REFERENCE_VDDA        (1<<6)  /*!< select VDDA as refference */
+/*! @} End of acmp_dacref                                                     */
+
+
+/******************************************************************************
+* Types
+******************************************************************************/
+
+/*! @brief ACMP_CALLBACK function declaration                                  */
+typedef void (*ACMP_CallbackPtr)(void);
+/*! @} End of acmp_callback                                                    */
+
+/******************************************************************************
+* ACMP control status struct
+*
+*//*! @addtogroup acmp_ctrlstatusstruct
+* @{
+*******************************************************************************/
+/*!
+ * @brief ACMP control and status fields type.
+ *
+ */
+
+typedef union 
+{
+    uint8_t byte;    				 /*!< byte field of union type */
+    struct 
+    {
+        uint8_t bMod        : 2;     /*!< Sensitivity modes of the interrupt trigger */
+        uint8_t bOutEn      : 1;     /*!< Output can be placed onto an external pin */
+        uint8_t bOutState   : 1;     /*!< The current value of the analog comparator output */
+        uint8_t bIntEn      : 1;     /*!< ACMP interrupt enable */
+        uint8_t bIntFlag    : 1;     /*!< ACMP Interrupt Flag Bit */
+        uint8_t bHyst       : 1;     /*!< Selects ACMP hystersis */
+        uint8_t bEn         : 1;     /*!< Enables the ACMP module */
+    }bits;      				     /*!< bitfield of union type */
+}ACMP_CtrlStatusType, *ACMP_CtrlStatusPtr;  /*!< ACMP Control/Status reg structure */
+/*! @} End of acmp_ctrlstatusstruct                                           */
+
+/******************************************************************************
+* ACMP pin select struct
+*
+*//*! @addtogroup acmp_pinselectstruct
+* @{
+*******************************************************************************/
+/*!
+* @brief ACMP external pins control struct.
+*
+*/
+
+typedef union 
+{
+    uint8_t byte;    				 /*!< byte field of union type */
+    struct 
+    {
+        uint8_t bNegPin  : 2;        /*!< Negative pin select */
+        uint8_t          : 2;
+        uint8_t bPosPin  : 2;        /*!< Positive pin select */
+        uint8_t          : 2;
+    }bits;      				     /*!< bitfield of union type */  
+}ACMP_PinSelType, *ACMP_PinSelPtr; 	     /*!< ACMP Pin select structure */ 
+/*! @} End of acmp_pinselectstruct                                            */
+
+/******************************************************************************
+* ACMP DAC control struct
+*
+*//*! @addtogroup acmp_dacctrlstruct
+* @{
+*******************************************************************************/
+/*!
+* @brief ACMP internal ADC control struct.
+*
+*/
+typedef union 
+{
+    uint8_t byte;    				 /*!< byte field of union type */
+    struct 
+    {
+        uint8_t bVal  : 6;           /*!< 6 bit DAC value */
+        uint8_t bRef  : 1;           /*!< 6 bit DAC reference select */
+        uint8_t bEn   : 1;           /*!< 6 bit DAC enable bit */
+    }bits;      				     /*!< bitfield of union type */  
+}ACMP_DACType, *ACMP_DACPtr;	     /*!< ACMP DAC control structure */ 
+/*! @} End of acmp_dacctrlstruct                                              */
+
+/******************************************************************************
+* ACMP pin enable union
+*
+*//*! @addtogroup acmp_pinenunion
+* @{
+*******************************************************************************/
+/*!
+* @brief ACMP external input pin enable control struct.
+*
+*/
+typedef union 
+{
+    uint8_t byte;    				 /*!< byte field of union type */
+    struct 
+    {
+        uint8_t bEn   : 3;           /*!< ACMP external input pin enable */
+        uint8_t bRsvd : 5;
+    }bits;      				     /*!< bitfield of union type */  
+}ACMP_PinEnType, *ACMP_PinEnPtr;	 /*!< ACMP Pin enable structure */ 
+/*! @} End of acmp_pinenunion                                                 */
+
+/******************************************************************************
+* ACMP config struct
+*
+*//*! @addtogroup acmp_configstruct
+* @{
+*******************************************************************************/
+/*!
+* @brief ACMP module configuration struct.
+*
+*/
+
+typedef struct 
+{
+    ACMP_CtrlStatusType  sCtrlStatus;     /*!< ACMP control and status */
+    ACMP_PinSelType      sPinSelect;      /*!< ACMP pin select */
+    ACMP_DACType         sDacSet;         /*!< ACMP internal dac set */
+    ACMP_PinEnType       sPinEnable;      /*!< ACMP external pin control */
+}ACMP_ConfigType, *ACMP_ConfigPtr;
+/*! @} End of acmp_configstruct                                               */
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/*!
+ * inline functions
+ */
+/******************************************************************************
+* ACMP api list.
+*
+*//*! @addtogroup acmp_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+*
+* @brief  enable the acmp module.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_Disable.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_Enable(ACMP_Type *pACMPx)
+{
+    pACMPx->CS |= ACMP_CS_ACE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable the acmp module.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_Enable.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_Disable(ACMP_Type *pACMPx)
+{
+    pACMPx->CS &= ~ACMP_CS_ACE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  select sensitivity modes of the interrupt trigger.
+*        
+* @param[in]  pACMPx         pointer to an ACMP module.
+* @param[in]  u8EdgeSelect   falling or rising selction, 0~3. 
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_SelectIntMode(ACMP_Type *pACMPx, uint8_t u8EdgeSelect)
+{
+    pACMPx->CS &= ~ACMP_CS_ACMOD_MASK;
+    pACMPx->CS |= ACMP_CS_ACMOD(u8EdgeSelect & 0x3);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  enable the ACMP module analog comparator output.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_DisablePinOut.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_EnablePinOut(ACMP_Type *pACMPx)
+{
+    pACMPx->CS |= ACMP_CS_ACOPE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable the ACMP module analog comparator output.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_EnablePinOut.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_DisablePinOut(ACMP_Type *pACMPx)
+{
+    pACMPx->CS &= ~ACMP_CS_ACOPE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  select ACMP hystersis. 
+*        
+* @param[in]  pACMPx           pointer to an ACMP module.
+* @param[in]  u8HystSelect     ACMP_HYST_20MV or ACMP_HYST_30MV.   
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_SelectHyst(ACMP_Type *pACMPx, uint8_t u8HystSelect)
+{
+    pACMPx->CS &= ~ACMP_CS_HYST_MASK;
+    pACMPx->CS |= u8HystSelect;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  enable the acmp module interrupt.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_DisableInterrupt.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_EnableInterrupt(ACMP_Type *pACMPx)
+{
+    pACMPx->CS |= ACMP_CS_ACIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable the acmp module interrupt.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_EnableInterrupt.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_DisableInterrupt(ACMP_Type *pACMPx)
+{
+    pACMPx->CS &= ~ACMP_CS_ACIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  get the interrupt flag bit.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_ClrFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE uint8_t ACMP_GetFlag(ACMP_Type *pACMPx)
+{
+    return (pACMPx->CS & ACMP_CS_ACF_MASK);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  clear the interrupt flag bit.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_GetFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_ClrFlag(ACMP_Type *pACMPx)
+{
+    pACMPx->CS &= ~ACMP_CS_ACF_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  ACMP Positive Input Select.
+*        
+* @param[in]  pACMPx        pointer to an ACMP module.
+* @param[in]  u8PosPinSel   positive input select, ACMP_INPUT_P_EXT0~2 or ACMP_INPUT_P_DAC.     
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_NegativeInputSelect.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_PositiveInputSelect(ACMP_Type *pACMPx, uint8_t u8PosPinSel)
+{
+    pACMPx->C0 &= ~ACMP_C0_ACPSEL_MASK;
+    pACMPx->C0 |= u8PosPinSel;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  ACMP Negative Input Select.
+*        
+* @param[in]  pACMPx        pointer to an ACMP module.
+* @param[in]  u8NegPinSel   negative input select, ACMP_INPUT_N_EXT0~2 or ACMP_INPUT_N_DAC.  
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_PositiveInputSelect.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_NegativeInputSelect(ACMP_Type *pACMPx, uint8_t u8NegPinSel)
+{
+    pACMPx->C0 &= ~ACMP_C0_ACNSEL_MASK;
+    pACMPx->C0 |= u8NegPinSel;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  Enable 6 bit DAC in ACMP module.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_DacDisable.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_DacEnable(ACMP_Type *pACMPx)
+{
+    pACMPx->C1 |= ACMP_C1_DACEN_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  Disable 6 bit DAC in ACMP module.
+*        
+* @param[in]  pACMPx      pointer to an ACMP module.
+*              
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see    ACMP_DacEnable.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_DacDisable(ACMP_Type *pACMPx)
+{
+    pACMPx->C1 &= ~ACMP_C1_DACEN_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  ACMP 6 bit DAC Reference Select.
+*        
+* @param[in]  pACMPx        pointer to an ACMP module.
+* @param[in]  u8RefSelect   dac reference select:ACMP_DAC_REFERENCE_BANDGAP or ACMP_DAC_REFERENCE_VDDA.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_DacReferenceSelect(ACMP_Type *pACMPx, uint8_t u8RefSelect)
+{
+    pACMPx->C1 &= ~ACMP_C1_DACREF_MASK;
+    pACMPx->C1 |= u8RefSelect;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  ACMP 6 bit DAC Output Value Set.
+*        
+* @param[in]  pACMPx        pointer to an ACMP module.
+* @param[in]  u8DacValue    dac output set, Voutput= (Vin/64)x(DACVAL[5:0]+1).
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_DacOutputSet(ACMP_Type *pACMPx, uint8_t u8DacValue)
+{
+    ASSERT(!(u8DacValue & (~ACMP_C1_DACVAL_MASK)));
+    pACMPx->C1 &= ~ACMP_C1_DACVAL_MASK;
+    pACMPx->C1 |= ACMP_C1_DACVAL(u8DacValue);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  Enable ACMP input pin.
+*        
+* @param[in]  pACMPx        pointer to an ACMP module.
+* @param[in]  u8InputPin    ACMP external pin, 0~2.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_InputPinEnable(ACMP_Type *pACMPx, uint8_t u8InputPin)
+{
+    ASSERT(!(u8InputPin & (~ACMP_C2_ACIPE_MASK)));
+    pACMPx->C2 |= ACMP_C2_ACIPE(u8InputPin);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  Disable ACMP input pin.
+*        
+* @param[in]  pACMPx        pointer to an ACMP module.
+* @param[in]  u8InputPin    ACMP external pin, 0~2.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+__STATIC_INLINE void ACMP_InputPinDisable(ACMP_Type *pACMPx, uint8_t u8InputPin)
+{
+    ASSERT(!(u8InputPin & (~ACMP_C2_ACIPE_MASK)));
+    pACMPx->C2 &= ~ACMP_C2_ACIPE(u8InputPin);
+}
+
+/*! @} End of acmp_api_list                                                  */
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void ACMP_Init(ACMP_Type *pACMPx, ACMP_ConfigType *pConfig);
+void ACMP_DeInit(ACMP_Type *pACMPx); 
+void ACMP_ConfigDAC(ACMP_Type *pACMPx, ACMP_DACType *pDACConfig);
+void ACMP_SetCallback(ACMP_Type *pACMPx, ACMP_CallbackPtr pfnCallback);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _MY_ACMP_H_ */
+
+
+

bsp/nv32f100x/lib/inc/adc.h

@@ -0,0 +1,711 @@
+/******************************************************************************
+*
+* @brief header file for ADC module utilities (ADC). 
+*
+*******************************************************************************
+*
+* provide APIs for accessing ADC module (ADC)
+******************************************************************************/
+
+#ifndef ADC_H_
+#define ADC_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Macros
+******************************************************************************/
+/******************************************************************************
+*define ADC refernce voltage 
+*
+*//*! @addtogroup adc_ref_list
+* @{
+*******************************************************************************/
+
+#define ADC_VREF_VREFH                 0x00			/*!< ADC reference voltage is VREFH*/
+#define ADC_VREF_VDDA                  0x01			/*!< ADC reference voltage is VDDA*/
+
+/*! @} End of adc_ref_list                                                    						*/
+
+/******************************************************************************
+* define ADC clock source 
+*
+*//*! @addtogroup adc_clock_source_list
+* @{
+*******************************************************************************/
+
+#define CLOCK_SOURCE_BUS_CLOCK							0x00	/*!< ADC clock source is bus clock*/
+#define CLOCK_SOURCE_BUS_CLOCK_DIVIDE_2			        0x01	/*!< ADC clock source is bus clock devided by 2*/
+#define CLOCK_SOURCE_ALTCLK								0x02	/*!< ADC clock source is alternative clcok*/
+#define CLOCK_SOURCE_ADACK								0x03	/*!< ADC clock source is asynchronous clock*/
+/*! @} End of adc_clock_source_list                                          						*/
+
+
+/******************************************************************************
+* define ADC divider 
+*
+*//*! @addtogroup adc_clock_divider_list
+* @{
+*******************************************************************************/
+
+#define ADC_ADIV_DIVIDE_1								0x00		/*!< ADC clock divide by 1*/
+#define ADC_ADIV_DIVIDE_2								0x01		/*!< ADC clock divide by 2*/
+#define ADC_ADIV_DIVIDE_4								0x02		/*!< ADC clock divide by 4*/
+#define ADC_ADIV_DIVIDE_8								0x03		/*!< ADC clock divide by 8*/
+/*! @} End of adc_clock_divider_list                                          						*/
+
+/******************************************************************************
+* define ADC mode 
+*
+*//*! @addtogroup adc_mode_list
+* @{
+*******************************************************************************/
+
+#define ADC_MODE_8BIT									0x00		/*!< ADC 8bit mode*/
+#define ADC_MODE_10BIT									0x01		/*!< ADC 10bit mode*/
+#define ADC_MODE_12BIT									0x02		/*!< ADC 12bit mode */
+/*! @} End of adc_mode_list                                               						*/
+
+/******************************************************************************
+* define ADC channel
+*
+*//*! @addtogroup adc_channel_list
+* @{
+*******************************************************************************/
+
+#define ADC_CHANNEL_AD0                                 0x0 /*!< ADC input channel 0 */
+#define ADC_CHANNEL_AD1                                 0x1 /*!< ADC input channel 1 */
+#define ADC_CHANNEL_AD2                                 0x2 /*!< ADC input channel 2 */
+#define ADC_CHANNEL_AD3                                 0x3 /*!< ADC input channel 3 */
+#define ADC_CHANNEL_AD4                                 0x4 /*!< ADC input channel 4 */
+#define ADC_CHANNEL_AD5                                 0x5 /*!< ADC input channel 5 */
+#define ADC_CHANNEL_AD6                                 0x6 /*!< ADC input channel 6 */
+#define ADC_CHANNEL_AD7                                 0x7 /*!< ADC input channel 7 */
+#define ADC_CHANNEL_AD8                                 0x8 /*!< ADC input channel 8 */
+#define ADC_CHANNEL_AD9                                 0x9 /*!< ADC input channel 9 */
+#define ADC_CHANNEL_AD10                                 0xa /*!< ADC input channel 10 */
+#define ADC_CHANNEL_AD11                                 0xb /*!< ADC input channel 11 */
+#define ADC_CHANNEL_AD12                                 0xc /*!< ADC input channel 12 */
+#define ADC_CHANNEL_AD13                                 0xd /*!< ADC input channel 13 */
+#define ADC_CHANNEL_AD14                                 0xe /*!< ADC input channel 14 */
+#define ADC_CHANNEL_AD15                                 0xf /*!< ADC input channel 15 */
+#define ADC_CHANNEL_AD18_VSS                            0x12 /*!< ADC input channel VSS */ 
+#define ADC_CHANNEL_AD22_TEMPSENSOR                     0x16 /*!< ADC input channel internal temperature sensor */
+#define ADC_CHANNEL_AD23_BANDGAP                        0x17 /*!< ADC input channel bandgap */ 
+#define ADC_CHANNEL_AD29_VREFH                          0x1D /*!< ADC input channel Vrefh */ 
+#define ADC_CHANNEL_AD30_VREFL                          0x1E /*!< ADC input channel Vrefl */ 
+#define ADC_CHANNEL_DISABLE                             0x1F /*!< ADC disable */
+/*! @} End of adc_channel_list                                               						*/
+
+
+/******************************************************************************
+* define ADC FIFO_LEVEL
+*
+*//*! @addtogroup adc_fifo_level_list
+* @{
+*******************************************************************************/
+#define ADC_FIFO_DISABLE                                0 /*!< FIFO Level 0 */
+#define ADC_FIFO_LEVEL2                                 1 /*!< FIFO Level 1 */
+#define ADC_FIFO_LEVEL3                                 2 /*!< FIFO Level 2 */
+#define ADC_FIFO_LEVEL4                                 3 /*!< FIFO Level 3 */
+#define ADC_FIFO_LEVEL5                                 4 /*!< FIFO Level 4 */
+#define ADC_FIFO_LEVEL6                                 5 /*!< FIFO Level 5 */
+#define ADC_FIFO_LEVEL7                                 6 /*!< FIFO Level 6 */
+#define ADC_FIFO_LEVEL8                                 7	/*!< FIFO Level 7 */
+/*! @} End of adc_fifo_level_list                                               						*/
+
+
+/******************************************************************************
+* define ADC trigger source
+*
+*//*! @addtogroup adc_trigger_list
+* @{
+*******************************************************************************/
+#define ADC_HARDWARE_TRIGGER                            0x01  /*!< hardware trigger */
+#define ADC_SOFTWARE_TRIGGER                            0x00	/*!< software trigger */
+#define ADC_TRIGGER_RTC                                 0x00  /*!< RTC act as trigger source */          
+#define ADC_TRIGGER_PIT                                 0x01  /*!< PIT act as trigger source */ 
+#define ADC_TRIGGER_ETM2INIT                            0x10  /*!< ETM2 initialization act as trigger source */ 
+#define ADC_TRIGGER_ETM2MATCH                           0x11  /*!< ETM2 match interrupt act as trigger source */
+/*! @} End of adc_trigger_list                                               						*/
+
+
+#define ADC_COMPARE_LESS                                0x00
+#define ADC_COMPARE_GREATER                             0x01
+
+
+/******************************************************************************
+* define ADC call back
+*
+*//*! @addtogroup adc_callback
+* @{
+*******************************************************************************/
+typedef void (*ADC_CallbackType)(void);							/*!< ADC call back function */
+/*! @} End of adc_callback                                               						*/
+
+/******************************************************************************
+* 
+*
+*//*! @addtogroup adc_setting_type
+* @{
+*******************************************************************************/
+/*!
+ * @brief ADC setting type.
+ *
+ */
+typedef struct
+{
+    uint16_t bIntEn                 :1;     /*!< 1: Interrupt Enable, 0: Interrupt disable */
+    uint16_t bContinuousEn          :1;     /*!< 1: Continuous Conversion Enable, 0: Continuous Conversion disable */
+    uint16_t bHardwareTriggerEn     :1;     /*!< 1: hardware trigger, 0: software trigger */
+    uint16_t bCompareEn             :1;     /*!< 1: compare mode Enable, 0: compare mode disable */
+    uint16_t bCompareGreaterEn      :1;     /*!< 1: Compare greater mode, 0: compare less than mode */
+    uint16_t bLowPowerEn            :1;     /*!< 1: Low power mode, 0: high speed mode */
+    uint16_t bLongSampleEn          :1;     /*!< 1: long sample mode, 0: short sample mode */
+    uint16_t bFiFoScanModeEn        :1;     /*!< 1: FIFO scan mode enable, 0: FIFO scan mode disable */
+    uint16_t bCompareAndEn          :1;     /*!< 1: Compare and logic, 0: Compare and logic */
+#ifdef CPU_NV32 
+    uint16_t bReverse               :7;    
+#else
+    uint16_t bHTRGMEn               :1;     /*!< one hardware trigger pulse trigger multiple conversions in fifo mode */      
+    uint16_t bHTRGMASKEn            :1;		/*!< Hardware trigger mask enable. */
+    uint16_t bHTRGMASKSEL           :1;		/*!< This field selects hardware trigger mask mode. */
+    uint16_t Reserve                :4;
+#endif
+}ADC_SettingType;
+/*! @} End of adc_setting_type                                               						*/
+
+/******************************************************************************
+* 
+*
+*//*! @addtogroup adc_config_type
+* @{
+*******************************************************************************/
+/*!
+ * @brief ADC configure type.
+ *
+ */
+typedef struct
+{
+    ADC_SettingType sSetting;               /*!< ADC setting structure*/
+    uint16_t u16PinControl;                 /*!< pin control */
+    uint8_t u8ClockSource;                  /*!< clock source selection */
+    uint8_t u8ClockDiv;                     /*!< set clock divider */
+    uint8_t u8Mode;                         /*!< set clcok mode(8/10/12 bit mode) */
+    uint8_t u8FiFoLevel;                    /*!< set FIFO level */
+}ADC_ConfigType,*ADC_ConfigTypePtr;
+/*! @} End of adc_config_type                                               */
+
+/******************************************************************************
+* define ADC APIs
+*
+*//*! @addtogroup adc_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief enable ADC interrupt.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_IntEnable( ADC_Type *pADC )
+{
+    pADC->SC1 |= ADC_SC1_AIEN_MASK;   
+}
+/*****************************************************************************//*!
+   *
+   * @brief disable ADC interrupt.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_IntDisable( ADC_Type *pADC )
+{
+    pADC->SC1 &= ~ADC_SC1_AIEN_MASK;   
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable ADC continuous conversion.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_ContinuousConversion( ADC_Type *pADC )
+{
+    pADC->SC1 |= ADC_SC1_ADCO_MASK;   
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable ADC single conversion
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SingleConversion( ADC_Type *pADC )
+{
+    pADC->SC1 &= ~ADC_SC1_ADCO_MASK;   
+}
+/*****************************************************************************//*!
+   *
+   * @brief set the ADC to hardware trigger.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SetHardwareTrigger( ADC_Type *pADC )
+{
+    pADC->SC2 |= ADC_SC2_ADTRG_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief set the ADC to software trigger.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SetSoftwareTrigger( ADC_Type *pADC )
+{
+    pADC->SC2 &= ~ADC_SC2_ADTRG_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable ADC compare function.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_CompareEnable( ADC_Type *pADC )
+{
+    pADC->SC2 |= ADC_SC2_ACFE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief disable ADC compare function.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_CompareDisable( ADC_Type *pADC )
+{
+    pADC->SC2 &= ~ADC_SC2_ACFE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable ADC compare greater function.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_CompareGreaterFunction( ADC_Type *pADC )
+{
+    pADC->SC2 |= ADC_SC2_ACFGT_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable ADC compare less function.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_CompareLessFunction( ADC_Type *pADC )
+{
+    pADC->SC2 &= ~ADC_SC2_ACFGT_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief set ADC to low power configuration.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SetLowPower( ADC_Type *pADC )
+{
+    pADC->SC3 |= ADC_SC3_ADLPC_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief set ADC to high speed configuration.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SetHighSpeed( ADC_Type *pADC )
+{
+    pADC->SC3 &= ~ADC_SC3_ADLPC_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Long Sample ETMe Configuration.
+   *        
+   * @param[in]  pADC point to ADC module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SetLongSample( ADC_Type *pADC )
+{
+    pADC->SC3 |= ADC_SC3_ADLSMP_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Short Sample ETMe Configuration.
+   *        
+   * @param[in]  pADC point to ADC module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SetShortSample( ADC_Type *pADC )
+{
+    pADC->SC3 &= ~ADC_SC3_ADLSMP_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief FIFO scan mode enable.
+   *        
+   * @param[in]  pADC point to ADC module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+__STATIC_INLINE void ADC_FifoScanModeEnable( ADC_Type *pADC )
+{
+    pADC->SC4 |= ADC_SC4_ASCANE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief FIFO scan mode disable.
+   *        
+   * @param[in]  pADC point to ADC module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_FifoScanModeDisable( ADC_Type *pADC )
+{
+    pADC->SC4 &= ~ADC_SC4_ASCANE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief OR all of compare trigger.
+   *        
+   * @param[in]  pADC point to ADC module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_CompareFifoOr( ADC_Type *pADC )
+{
+    pADC->SC4 &= ~ADC_SC4_ACFSEL_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief And all of compare trigger.
+   *        
+   * @param[in]  pADC point to ADC module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_CompareFifoAnd( ADC_Type *pADC )
+{
+    pADC->SC4 |= ADC_SC4_ACFSEL_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief read ADC result register.
+   *        
+   * @param[in]  pADC point to ADC module type.
+   *
+   * @return ADC result value.
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE uint16_t ADC_ReadResultReg( ADC_Type *pADC )
+{
+    return (uint16_t)pADC->R;
+}
+/*****************************************************************************//*!
+   *
+   * @brief set ADC compare value.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u16Compare compare value. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_SetCompareValue( ADC_Type *pADC, uint16_t u16Compare )
+{
+    pADC->CV = u16Compare;
+}
+/*****************************************************************************//*!
+   *
+   * @brief ADC pin control enable.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u16PinNumber enable ADC function to specified pin number. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_PinControlEnable( ADC_Type *pADC, uint16_t u16PinNumber)
+{
+    ASSERT((u16PinNumber<16));
+    pADC->APCTL1 &= ~(0x01<<u16PinNumber);
+}
+/*****************************************************************************//*!
+   *
+   * @brief ADC pin control disable.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u16PinNumber  disable ADC function to specified pin number. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_PinControlDisable( ADC_Type *pADC, uint16_t u16PinNumber)
+{
+    ASSERT((u16PinNumber<16));
+    pADC->APCTL1 |= (0x01<<u16PinNumber);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check conversion active status
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return TRUE or FALSE
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE uint8_t ADC_IsConversionActiveFlag( ADC_Type *pADC )
+{
+    return(pADC->SC2 & ADC_SC2_ADACT_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check COCO flag
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return TRUE or FALSE
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE uint8_t ADC_IsCOCOFlag( ADC_Type *pADC )
+{
+    return(pADC->SC1 & ADC_SC1_COCO_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check Result FIFO empty
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return TRUE or FALSE
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE uint8_t ADC_IsFIFOEmptyFlag( ADC_Type *pADC )
+{
+    return(pADC->SC2 & ADC_SC2_FEMPTY_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check Result FIFO full
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return TRUE or FALSE
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE uint8_t ADC_IsFIFOFullFlag( ADC_Type *pADC )
+{
+    return(pADC->SC2 & ADC_SC2_FFULL_MASK);
+}
+#ifndef CPU_NV32
+/*****************************************************************************//*!
+   *
+   * @brief Hardware Trigger Multiple Conversion Enable
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_HardwareTriggerMultiple( ADC_Type *pADC )
+{
+    pADC->SC4 |= ADC_SC4_HTRGME_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Hardware Trigger Single Conversion
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_HardwareTriggerSingle( ADC_Type *pADC )
+{
+    pADC->SC4 &= ~ADC_SC4_HTRGME_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Hardware Trigger Mask Enable
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_HardwareTriggerMaskEnable( ADC_Type *pADC )
+{
+    pADC->SC5 |= ADC_SC5_HTRGMASKE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Hardware Trigger Mask Disable
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_HardwareTriggerMaskDisable( ADC_Type *pADC )
+{
+    pADC->SC5 &= ~ADC_SC5_HTRGMASKE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Hardware Trigger Mask Mode Select Automatic Mode
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_HardwareTriggerMaskAuto( ADC_Type *pADC )
+{
+    pADC->SC5 |= ADC_SC5_HTRGMASKSEL_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Hardware Trigger Mask Mode Select to be with HTRGMASKE
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+__STATIC_INLINE void ADC_HardwareTriggerMaskNonAuto( ADC_Type *pADC )
+{
+    pADC->SC5 &= ~ADC_SC5_HTRGMASKSEL_MASK;
+}
+#endif
+/******************************************************************************
+* Global function
+******************************************************************************/
+
+void ADC_SetChannel( ADC_Type *pADC, uint8_t u8Channel );
+void ADC_IntEnable( ADC_Type *pADC );
+void ADC_IntDisable( ADC_Type *pADC );
+void ADC_ContinuousConversion( ADC_Type *pADC );
+void ADC_SingleConversion( ADC_Type *pADC );
+void ADC_SetSoftwareTrigger( ADC_Type *pADC );
+void ADC_SetHardwareTrigger( ADC_Type *pADC );
+void ADC_VrefSelect( ADC_Type *pADC, uint8_t u8Vref );
+void ADC_CompareEnable( ADC_Type *pADC );
+void ADC_CompareDisable( ADC_Type *pADC );
+void ADC_CompareGreaterFunction( ADC_Type *pADC );
+void ADC_CompareLessFunction( ADC_Type *pADC );
+void ADC_SetLowPower( ADC_Type *pADC );
+void ADC_SetHighSpeed( ADC_Type *pADC );
+void ADC_SelectClockDivide( ADC_Type *pADC, uint8_t u8Div);
+void ADC_SetLongSample(ADC_Type *pADC);
+void ADC_SetShortSample(ADC_Type *pADC);
+void ADC_SetMode(ADC_Type *pADC, uint8_t u8Mode);
+void ADC_SelectClock(ADC_Type *pADC, uint8_t u8Clock);
+void ADC_FifoScanModeEnable(ADC_Type *pADC);
+void ADC_FifoScanModeDisable(ADC_Type *pADC);
+void ADC_CompareFifoOr(ADC_Type *pADC);
+void ADC_CompareFifoAnd(ADC_Type *pADC);
+void ADC_SetFifoLevel(ADC_Type *pADC, uint8_t u8FifoLevel);
+uint16_t ADC_ReadResultReg(ADC_Type *pADC );
+void ADC_SetCompareValue(ADC_Type *pADC, uint16_t u16Compare );
+void ADC_PinControlEnable(ADC_Type *pADC, uint16_t u16PinNumber);
+void ADC_PinControlDisable(ADC_Type *pADC, uint16_t u16PinNumber);
+uint8_t ADC_IsConversionActiveFlag(ADC_Type *pADC);
+uint8_t ADC_IsCOCOFlag(ADC_Type *pADC);
+uint8_t ADC_IsFIFOEmptyFlag(ADC_Type *pADC);
+uint8_t ADC_IsFIFOFullFlag(ADC_Type *pADC);
+void ADC_HardwareTriggerMaskNonAuto(ADC_Type *pADC);
+void ADC_HardwareTriggerMaskAuto(ADC_Type *pADC);
+void ADC_HardwareTriggerMaskDisable( ADC_Type *pADC );
+void ADC_HardwareTriggerMaskEnable( ADC_Type *pADC );
+void ADC_HardwareTriggerSingle( ADC_Type *pADC );
+void ADC_HardwareTriggerMultiple( ADC_Type *pADC );
+unsigned int ADC_PollRead( ADC_Type *pADC, uint8_t u8Channel);
+void ADC_SetCallBack(ADC_CallbackType pADC_CallBack);
+void ADC_DeInit(ADC_Type *pADC);
+void ADC_Init(ADC_Type *pADC, ADC_ConfigTypePtr pADC_Config);
+/*! @} End of adc_api_list                                               						*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ADC_H_ */

bsp/nv32f100x/lib/inc/arm_cm0.h

@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* @brief provide generic high-level routines for ARM Cortex M0/M0+ processors. 
+*
+*******************************************************************************/
+
+#ifndef _CPU_ARM_CM0_H
+#define _CPU_ARM_CM0_H
+
+/*ARM Cortex M0 implementation for interrupt priority shift*/
+#define ARM_INTERRUPT_LEVEL_BITS          2
+
+
+/***********************************************************************/
+  /*!< Macro to enable all interrupts. */
+#ifndef KEIL
+#define EnableInterrupts asm(" CPSIE i");
+#else
+#define EnableInterrupts  __enable_irq()
+#endif
+
+  /*!< Macro to disable all interrupts. */
+#ifndef KEIL
+#define DisableInterrupts asm(" CPSID i");
+#else
+#define DisableInterrupts __disable_irq()
+#endif
+
+#define disable_irq(irq)             NVIC_DisableIRQ(irq)
+#define enable_irq(irq)              NVIC_EnableIRQ(irq)
+#define set_irq_priority(irq, prio)  NVIC_SetPriority(irq, prio)
+/***********************************************************************/
+
+
+/*
+ * Misc. Defines
+ */
+#ifdef	FALSE
+#undef	FALSE
+#endif
+#define FALSE	(0)
+
+#ifdef	TRUE
+#undef	TRUE
+#endif
+#define	TRUE	(1)
+
+#ifdef	NULL
+#undef	NULL
+#endif
+#define NULL	(0)
+
+#ifdef  ON
+#undef  ON
+#endif
+#define ON      (1)
+
+#ifdef  OFF
+#undef  OFF
+#endif
+#define OFF     (0)
+
+#undef  ENABLE
+#define ENABLE  (1)
+
+#undef  DISABLE
+#define DISABLE  (0)
+
+
+/***********************************************************************/
+/*
+ * The basic data types
+ */
+typedef unsigned char		uint8;  /*  8 bits */
+typedef unsigned short int	uint16; /* 16 bits */
+typedef unsigned long int	uint32; /* 32 bits */
+
+typedef char			int8;   /*  8 bits */
+typedef short int	        int16;  /* 16 bits */
+typedef int		        int32;  /* 32 bits */
+
+typedef volatile int8		vint8;  /*  8 bits */
+typedef volatile int16		vint16; /* 16 bits */
+typedef volatile int32		vint32; /* 32 bits */
+
+typedef volatile uint8		vuint8;  /*  8 bits */
+typedef volatile uint16		vuint16; /* 16 bits */
+typedef volatile uint32		vuint32; /* 32 bits */
+
+// function prototype for main function
+int main(void);
+/***********************************************************************/
+// function prototypes for arm_cm0.c
+void stop (void);
+void wait (void);
+void write_vtor (int);
+
+/***********************************************************************/
+#endif	/* _CPU_ARM_CM4_H */
+

bsp/nv32f100x/lib/inc/common.h

@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* @brief provide header files to be included by all project files. 
+*
+*******************************************************************************/
+
+
+#ifndef _COMMON_H_
+#define _COMMON_H_
+
+#define swap_bytes(ptrWord)   *ptrWord = (*ptrWord >>8) | (*ptrWord<<8)
+typedef unsigned long   dword;
+typedef unsigned short  word;
+
+/********************************************************************/
+
+/*
+ * Debug prints ON (#define) or OFF (#undef)
+ */
+
+#define DEBUG
+#define DEBUG_PRINT
+
+/* 
+ * Include the generic CPU header file 
+ */
+#include "arm_cm0.h"
+
+/* 
+ * Include the platform specific header file 
+ */
+#if (defined(NV32))
+ #include  "NV32_config.h"
+#elif (defined(FRDM_NV32M3))
+ #include  "NV32M3_config.h"
+#elif (defined(FRDM_NV32M4))
+ #include  "NV32M4_config.h"
+#else
+  #error "No valid board defined"
+#endif
+
+/* 
+ * Include the cpu specific header file 
+*/
+#if (defined(CPU_NV32))
+ #include "NV32.h"
+#elif (defined(CPU_NV32M3))
+ #include "NV32M3.h"
+#elif (defined(CPU_NV32M4))
+ #include "NV32M4.h"
+#else
+  #error "No valid CPU defined"
+#endif
+
+
+/* 
+ * Include any toolchain specfic header files 
+ */
+#if (defined(__MWERKS__))
+  #include "mwerks.h"
+#elif (defined(__DCC__))
+  #include "build/wrs/diab.h"
+#elif (defined(__ghs__))
+  #include "build/ghs/ghs.h"
+#elif (defined(__GNUC__))
+  #if (defined(IAR))
+    #include "build/gnu/gnu.h"
+  #endif
+#elif (defined(IAR))
+  #include "iar.h"
+#elif (defined(KEIL))
+  
+#else
+#warning "No toolchain specific header included"
+#endif
+
+/* 
+ * Include common utilities
+ */
+
+#define ASSERT(x)
+
+#if (defined(IAR))
+#include "intrinsics.h"
+#endif
+/********************************************************************/
+
+#endif /* _COMMON_H_ */

bsp/nv32f100x/lib/inc/core_cm0plus.h

@@ -0,0 +1,822 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/nv32f100x/lib/inc/core_cmFunc.h

@@ -0,0 +1,637 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

bsp/nv32f100x/lib/inc/core_cmInstr.h

@@ -0,0 +1,880 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

bsp/nv32f100x/lib/inc/core_cmSimd.h

@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */

bsp/nv32f100x/lib/inc/crc.h

@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* @brief    Cyclic redundancy check (CRC) header file. 
+*
+******************************************************************************/
+#ifndef CRC_H_
+#define CRC_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+
+
+/******************************************************************************
+* CRC control bit definition
+*
+*//*! @addtogroup crc_controlbit
+* @{
+*******************************************************************************/
+
+/*!
+ * @brief CRC control register bit definition.
+ *
+ */
+
+#define CRC_WIDTH_16BIT                 0	/*!< select CRC16 protocol */   
+#define CRC_WIDTH_32BIT                 1	/*!< select CRC32 protocol */ 
+#define CRC_DATA_SEED                   1	/*!< Write CRC Data Register are seed */  
+#define CRC_DATA_DATA                   0	/*!< Write CRC Data Register are data */ 
+#define CRC_READ_COMPLETE               1	/*!< Invert or complement read CRC Data register */ 
+#define CRC_READ_NONE                   0	/*!< No XOR on reading */ 
+#define CRC_READ_TRANSPOSE_NONE         0	/*!< No transposition in read */ 
+#define CRC_READ_TRANSPOSE_BIT          1	/*!< only bits in bytes are transposed in read */
+#define CRC_READ_TRANSPOSE_ALL          2	/*!< both bits in bytes and bytes are transposed in read */
+#define CRC_READ_TRANSPOSE_BYTE         3	/*!< only bytes are transposed in read */
+#define CRC_WRITE_TRANSPOSE_NONE        0	/*!< No transposition write */
+#define CRC_WRITE_TRANSPOSE_BIT         1	/*!< only bits in bytes are transposed in write */ 
+#define CRC_WRITE_TRANSPOSE_ALL         2	/*!< both bits in bytes and bytes are transposed in write */
+#define CRC_WRITE_TRANSPOSE_BYTE        3	/*!< only bytes are transposed in write */
+
+/*! @} End of crc_controlbit                                                */
+
+     
+/******************************************************************************
+* Types
+******************************************************************************/
+/* CRC configuration structure 
+ */  
+/******************************************************************************
+* CRC Configuration Structure type.
+*
+*//*! @addtogroup crc_config_type
+* @{
+*******************************************************************************/ 
+/*!
+ * @brief CRC Configuration Structure.
+ *
+ */
+
+typedef struct
+{          
+    uint8_t bWidth                  : 1;    /*!< 1: 32-bit CRC protocol , 0: 16-bit CRC protocol */
+    uint8_t bDataType               : 1;    /*!< 1: write seed , 0: write data */
+    uint8_t bFinalXOR               : 1;    /*!< 1: Invert or complement read , 0: No XOR on reading */
+    uint8_t bRESERVED               : 1;    /*!< reserved bit */  
+    uint8_t bTransposeReadType      : 2;    /*!< type of transpose For read, see reference manual */
+    uint8_t bTransposeWriteType     : 2;    /*!< type of transpose For write, see reference manual */      
+    uint32_t u32PolyData               ;    /*!< 32bit or 16-biy poly data */           
+} CRC_ConfigType, *CRC_ConfigPtr  ; 
+/*! @} End of crc_config_type                                                */
+
+           
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* CRC API list
+*
+*//*! @addtogroup crc_api_list
+* @{
+*******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void        CRC_Init(CRC_ConfigType *pConfig);
+uint32_t    CRC_Cal16(uint32_t u32Seed, uint8_t *msg, uint32_t u32SizeBytes);
+uint32_t    CRC_Cal32(uint32_t u32Seed, uint8_t *msg, uint32_t u32SizeBytes);
+void        CRC_DeInit(void);
+/*! @} End of crc_api_list                                                   */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* CRC_H_ */
+
+
+

bsp/nv32f100x/lib/inc/eeprom.h

@@ -0,0 +1,28 @@
+#ifndef EEPROM_H_
+#define EEPROM_H_
+
+/******************************************************************************
+* Includes
+******************************************************************************/
+#include "common.h"
+
+#define EERPOM_SIZE	1024		// in bytes
+#define EEPROM_START_ADR 0x00401000
+#define EEPROM_ERR_SUCCESS 0x01
+#define EEPROM_ADR_OverFlow 0x02
+#define EEPROM_ERR_INVALID_PARAM 0x04
+#define EEPROM_BLANK 0xffffffff
+#define EEPROM_SECTOR_MASK 0x00401200
+#define EEPROM_ARRAY_ADR_MASK 0x1ff
+
+
+uint16_t Adress_Js(uint32_t adr);
+uint16_t EEPROM_Erase(uint32_t adr);
+uint32_t EEPROM_Read(uint32_t adr);
+uint8_t EEPROM_ReadByte(uint32_t adr);
+
+
+uint16_t EEPROM_Write(uint32_t adr, uint32_t Data);
+uint16_t EEPROM_WriteByte(uint32_t adr, uint8_t Data);
+uint16_t EERPOM_Writeup4byte(uint32_t adr, uint8_t *pData,uint32_t length);
+#endif

bsp/nv32f100x/lib/inc/etm.h

@@ -0,0 +1,1166 @@
+/******************************************************************************
+* @brief header file for ETM. 
+*
+*******************************************************************************
+*
+* provide APIs for accessing ETM
+******************************************************************************/
+#ifndef ETM_H_
+#define ETM_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+
+/******************************************************************************
+* ETM return status definition
+*
+*//*! @addtogroup ETM_returnstatus
+* @{
+*******************************************************************************/
+#define ETM_ERR_SUCCESS         0               /*!< return ok */
+#define ETM_ERR_INVALID_PARAM   1               /*!< return invalid parameter */
+/*! @} End of ETM_returnstatus                                                */
+
+
+/******************************************************************************
+* ETM channel number definition
+*
+*//*! @addtogroup ETM_channelnumber
+* @{
+*******************************************************************************/
+#define ETM_CHANNEL_CHANNEL0    0               /*!< channel 0 */
+#define ETM_CHANNEL_CHANNEL1    1               /*!< channel 1 */
+#define ETM_CHANNEL_CHANNEL2    2               /*!< channel 2 */
+#define ETM_CHANNEL_CHANNEL3    3               /*!< channel 3 */
+#define ETM_CHANNEL_CHANNEL4    4               /*!< channel 4 */
+#define ETM_CHANNEL_CHANNEL5    5               /*!< channel 5 */
+
+#define ETM_CHANNELPAIR0        0               /*!< channel pair 0:ch0 & ch1 */
+#define ETM_CHANNELPAIR1        2               /*!< channel pair 1:ch2 & ch3 */
+#define ETM_CHANNELPAIR2        4               /*!< channel pair 2:ch4 & ch5 */
+
+/*! @} End of ETM_channelnumber                                               */
+
+/******************************************************************************
+* ETM pwm mode definition
+*
+*//*! @addtogroup ETM_pwmmode
+* @{
+*******************************************************************************/
+#define ETM_PWMMODE_EDGEALLIGNED      1          /*!< EPWM */
+#define ETM_PWMMODE_CENTERALLIGNED    2          /*!< CPWM */
+#define ETM_PWMMODE_COMBINE           3          /*!< Combine PWM */
+/*! @} End of ETM_pwmmode                                                     */
+
+/******************************************************************************
+* ETM init value definition
+*
+*//*! @addtogroup ETM_initvalue
+* @{
+*******************************************************************************/
+#define ETM_MOD_INIT	(20000-1)                /*!< MOD inite value */
+#define ETM_C0V_INIT	1000                     /*!< C0V inite value */
+#define ETM_C1V_INIT	1000                     /*!< C1V inite value */
+#define ETM_C2V_INIT	1000                     /*!< C2V inite value */    
+#define ETM_C3V_INIT	1000                     /*!< C3V inite value */
+#define ETM_C4V_INIT	1000                     /*!< C4V inite value */
+#define ETM_C5V_INIT	1000                     /*!< C5V inite value */
+/*! @} End of ETM_initvalue                                                   */
+
+/******************************************************************************
+* ETM combine feature definition
+*
+*//*! @addtogroup ETM_combinefeature
+* @{
+*******************************************************************************/
+#define ETM_COMBINE_FAULTEN_MASK  0x40       /*!< fault enable */
+#define ETM_COMBINE_SYNCEN_MASK   0x20       /*!< sync enable */
+#define ETM_COMBINE_DTEN_MASK     0x10       /*!< dead ETMe insertion enable */
+#define ETM_COMBINE_DECAP_MASK    0x08       /*!< dual capture status */
+#define ETM_COMBINE_DECAPEN_MASK  0x04       /*!< dual capture enable */
+#define ETM_COMBINE_COMP_MASK     0x02       /*!< complementary enable */
+#define ETM_COMBINE_COMBINE_MASK  0x01       /*!< combine enable */
+/*! @} End of ETM_combinefeature                                              */
+
+/******************************************************************************
+* ETM clock sources definition
+*
+*//*! @addtogroup ETM_clocksource
+* @{
+*******************************************************************************/
+#define ETM_CLOCK_NOCLOCK             0                 /*!< No Clock */
+#define ETM_CLOCK_SYSTEMCLOCK         1                 /*!< System clock/2 */
+#define ETM_CLOCK_FIXEDFREQCLOCK      2                 /*!< Fixed Freq Clock */
+#define ETM_CLOCK_EXTERNALCLOCK       3                 /*!< External Clock */
+
+/* clock prescale */
+#define ETM_CLOCK_PS_DIV1             0                 /*!< DIV 1 */
+#define ETM_CLOCK_PS_DIV2             1                 /*!< DIV 2 */
+#define ETM_CLOCK_PS_DIV4             2                 /*!< DIV 4 */
+#define ETM_CLOCK_PS_DIV8             3                 /*!< DIV 8 */
+#define ETM_CLOCK_PS_DIV16            4                 /*!< DIV 16 */
+#define ETM_CLOCK_PS_DIV32            5                 /*!< DIV 32 */
+#define ETM_CLOCK_PS_DIV64            6                 /*!< DIV 64 */
+#define ETM_CLOCK_PS_DIV128           7                 /*!< DIV 128 */
+/*! @} End of ETM_clocksource                                                 */
+
+/******************************************************************************
+* ETM dead ETMe clock prescale definition
+*
+*//*! @addtogroup ETM_deadETMeprescale
+* @{
+*******************************************************************************/
+/*  */
+#define ETM_DEADETME_DTPS_DIV1        0                 /*!< DIV 1 */
+#define ETM_DEADETME_DTPS_DIV4        2                 /*!< DIV 4 */
+#define ETM_DEADETME_DTPS_DIV16       3                 /*!< DIV 16 */
+/*! @} End of ETM_deadETMeprescale                                            */
+
+/******************************************************************************
+* ETM output mode definition
+*
+*//*! @addtogroup ETM_outputmode
+* @{
+*******************************************************************************/
+/* output mode */
+#define ETM_OUTPUT_TOGGLE   1                    /*!< toggle output on match */
+#define ETM_OUTPUT_CLEAR    2                    /*!< clear output on match */
+#define ETM_OUTPUT_SET      3                    /*!< set output on match */
+/*! @} End of ETM_outputmode                                                  */
+
+/******************************************************************************
+* ETM input capture edge definition
+*
+*//*! @addtogroup ETM_inputcaptureedge
+* @{
+*******************************************************************************/
+/* mode edge select*/
+#define ETM_INPUTCAPTURE_RISINGEDGE           1     /*!< rising edge */
+#define ETM_INPUTCAPTURE_FALLINGEDGE          2     /*!< falling edge */
+#define ETM_INPUTCAPTURE_BOTHEDGE             3     /*!< both edge */
+
+#define ETM_INPUTCAPTURE_DUALEDGE_NOEDGE      0     /*!< none */
+#define ETM_INPUTCAPTURE_DUALEDGE_RISINGEDGE  1     /*!< rising edge*/
+#define ETM_INPUTCAPTURE_DUALEDGE_FALLInGEDGE 2     /*!< falling edge*/
+#define ETM_INPUTCAPTURE_DUALEDGE_BOTHEDGE    3     /*!< both edge */
+/*! @} End of ETM_inputcaptureedge                                            */
+
+/******************************************************************************
+* ETM dual edge capture mode definition
+*
+*//*! @addtogroup ETM_dualcapturemode
+* @{
+*******************************************************************************/
+#define ETM_INPUTCAPTURE_DUALEDGE_ONESHOT     4  /*!< dual edge one shot mode*/ 
+#define ETM_INPUTCAPTURE_DUALEDGE_CONTINUOUS  5  /*!< dual edge continuouse mode*/
+/*! @} End of ETM_dualcapturemode                                            */
+
+/******************************************************************************
+* ETM PWM edge definition
+*
+*//*! @addtogroup ETM_pwmedge
+* @{
+*******************************************************************************/
+#define ETM_PWM_HIGHTRUEPULSE        1            /*!< high true pulses */
+#define ETM_PWM_LOWTRUEPULSE         2            /*!< low true pulses */
+/*! @} End of ETM_pwmedge                                                     */
+
+/******************************************************************************
+* ETM sync trigger source definition
+*
+*//*! @addtogroup ETM_syncsource
+* @{
+*******************************************************************************/
+#define ETM_SYNC_TRIGGER_SOFTWARE    1        /*!< Software synchronization */
+#define ETM_SYNC_TRIGGER_TRIGGER2    2        /*!< Tigger2 synchronization, SIM_SOPT[ETMSYNC] */
+#define ETM_SYNC_TRIGGER_TRIGGER1    3        /*!< Tigger1 synchronization, ETM0CH0 */
+#define ETM_SYNC_TRIGGER_TRIGGER0    4        /*!< Tigger0 synchronization, ACMP0 */
+/*! @} End of ETM_syncsource                                                  */
+
+/******************************************************************************
+* ETM SW output control definition
+*
+*//*! @addtogroup ETM_swoutputcontrol
+* @{
+*******************************************************************************/ 
+#define ETM_SWOCTRL_HIGH    1                /*!< software output high */
+#define ETM_SWOCTRL_LOW     0                /*!< software output low */
+/*! @} End of ETM_swoutputcontrol                                             */
+
+/******************************************************************************
+* ETM  polarity definition
+*
+*//*! @addtogroup ETM_polarity
+* @{
+*******************************************************************************/
+#define ETM_POLARITY_HIGHACTIVE     0        /*!< active high */
+#define ETM_POLARITY_LOWACTIVE      1        /*!< active low */
+/*! @} End of ETM_polarity                                                    */
+
+
+/******************************************************************************
+* Types
+******************************************************************************/
+/*! @brief ETM_CALLBACK function declaration                                  */
+typedef void (*ETM_CallbackPtr)(void);
+/*! @} End of ETM_callback                                                    */
+
+/******************************************************************************
+* ETM configure struct.
+*
+*//*! @addtogroup ETM_configsturct
+* @{
+*******************************************************************************/
+/*!
+* @brief ETM configure struct.
+*
+*/
+
+typedef struct
+{
+  uint8_t   clk_source;       /*!< clock source */
+  uint8_t   prescaler;        /*!< clock prescaler */
+  uint8_t   sc;               /*!< status and control */
+  uint16_t  modulo;           /*!< counter mod */
+  uint16_t  cnt;              /*!< counter value */
+  uint16_t  cntin;            /*!< counter inite */
+  uint8_t   mode;             /*!< features mode selction */
+  uint8_t   sync;             /*!< synchronization */
+  uint8_t   outinit;          /*!< initial state for channels output  */
+  uint8_t   outmask;          /*!< output mask */
+  uint32_t  combine;          /*!< function for linked channels */
+  uint16_t  deadETMe;         /*!< dead ETMe insertion control */
+  uint8_t   exttrig;          /*!< external trigger */
+  uint8_t   pol;              /*!< channels polarity */
+  uint16_t  filter;           /*!< input filter control */
+  uint8_t   fms;              /*!< fault mode status */
+  uint16_t  fltctrl;          /*!< fault control */
+  uint8_t   fltpol;           /*!< fault input polarity */
+  uint16_t  conf;             /*!< ETM configuration */
+  uint32_t  synconf;          /*!< synchronization configuration*/
+  uint8_t   invctrl;          /*!< inverting control */
+  uint16_t  swoctrl;          /*!< software output control */
+  uint16_t  pwmload;          /*!< pwm load control */
+} ETM_ConfigType, *ETM_ConfigPtr;
+/*! @} End of ETM_configsturct                                                */
+
+/******************************************************************************
+* ETM channel configure struct.
+*
+*//*! @addtogroup ETM_chconfigsturct
+* @{
+*******************************************************************************/
+/*!
+* @brief ETM channel configure struct.
+*
+*/
+typedef struct
+{
+  uint8_t         u8CnSC;                  /*!< ETM channel status and control */
+  uint16_t        u16CnV;                  /*!< ETM channel value control */
+  union
+  {
+    uint32_t      u32dw;
+    struct 
+    {
+      uint32_t    bMode         : 3;        /*!< flexETMer mode: GPIO, INPUT_CAPTURE, OUTPUT_COMPARE, EDGE_ALIGNED_PWM, CENTER_ALIGNED_PWM,
+                                             * COMBINE_PWM, DUAL_EDGE_CAPTURE 
+                                             */
+      uint32_t    bEdge         : 2;        /*!< edge select */
+      uint32_t    bOutCmp       : 2;        /*!< toggle, clear, set */
+      uint32_t    bPWMPol       : 1;        /*!< high-true pulse, low-true pulses */
+      uint32_t    bDualCapMode  : 1;        /*!< dual edge capture mode: one-shot, continuous mode */
+      uint32_t    bCHIE         : 1;        /*!< enable channel interrupt */
+    }bits;
+  }ctrl;                                    /*!< ETM channel feature control */
+} ETM_ChParamsType;
+
+/*! @} End of ETM_chconfigsturct                                              */
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/*!
+ * inline functions
+ */
+/******************************************************************************
+* ETM inline functions
+*
+*//*! @addtogroup ETM_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+*
+* @brief  enable the over flow interrupt.
+*        
+* @param[in]    pETM          pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_DisableOverflowInt.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_EnableOverflowInt(ETM_Type *pETM)
+{
+    if(pETM->SC & ETM_SC_TOF_MASK)
+    {
+        pETM->SC &= ~ETM_SC_TOF_MASK;
+    }
+    pETM->SC |= ETM_SC_TOIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable the over flow interrupt.
+*        
+* @param[in]    pETM          pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see ETM_EnableOverflowInt.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_DisableOverflowInt(ETM_Type *pETM)
+{
+    pETM->SC &= ~ETM_SC_TOIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  enable the channel interrupt.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+* @param[in]    u8ETM_Channel  channel number.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_DisableChannelInt.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_EnableChannelInt(ETM_Type *pETM, uint8_t u8ETM_Channel)
+{
+    pETM->CONTROLS[u8ETM_Channel].CnSC |= ETM_CnSC_CHIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable the channel interrupt.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+* @param[in]    u8ETM_Channel  channel number.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_EnableChannelInt.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_DisableChannelInt(ETM_Type *pETM, uint8_t u8ETM_Channel)
+{
+    pETM->CONTROLS[u8ETM_Channel].CnSC &= ~ETM_CnSC_CHIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  get the over flow flag.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+*    
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_ClrOverFlowFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE uint8_t ETM_GetOverFlowFlag(ETM_Type *pETM)
+{
+    return (pETM->SC & ETM_SC_TOF_MASK);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  clear the over flow flag.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+*    
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_GetOverFlowFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_ClrOverFlowFlag(ETM_Type *pETM)
+{
+    if(pETM->SC & ETM_SC_TOF_MASK)
+    {
+         pETM->SC &= ~ETM_SC_TOF_MASK;
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  get the channel flag.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+* @param[in]    u8ETM_Channel  channel number.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_ClrChannelFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE uint8_t ETM_GetChannelFlag(ETM_Type *pETM, uint8_t u8ETM_Channel)
+{
+    return (pETM->CONTROLS[u8ETM_Channel].CnSC & ETM_CnSC_CHF_MASK);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  clear the channel flag.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+*    
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_GetChannelFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_ClrChannelFlag(ETM_Type *pETM, uint8_t u8ETM_Channel)
+{
+    pETM->CONTROLS[u8ETM_Channel].CnSC &= ~ETM_CnSC_CHF_MASK;
+}
+
+/*********************************************************************************//*!
+*
+* @brief enable the write protection function.Write protected bits cannot be written. 
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_WriteProtectionDisable.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_WriteProtectionEnable(ETM_Type *pETM)
+{
+    pETM->FMS |= ETM_FMS_WPEN_MASK;
+}
+
+/*********************************************************************************//*!
+*
+* @brief disable the write protection function.Write protected bits can be written. 
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_WriteProtectionDisable.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_WriteProtectionDisable(ETM_Type *pETM)
+{
+    if (pETM->FMS & ETM_FMS_WPEN_MASK)
+    {
+        pETM->MODE |= ETM_MODE_WPDIS_MASK;
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set ETMEN bit to enable ETM-specific register.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+*    
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetETMBasic.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_SetETMEnhanced(ETM_Type *pETM)
+{
+    if(pETM->MODE & ETM_MODE_WPDIS_MASK)   /* if not write protected */
+    {
+        pETM->MODE |= ETM_MODE_ETMEN_MASK;
+    }
+    else
+    {
+        ETM_WriteProtectionDisable(pETM);
+        pETM->MODE |= ETM_MODE_ETMEN_MASK;
+        ETM_WriteProtectionEnable(pETM);
+    }    
+}
+
+/*****************************************************************************//*!
+*
+* @brief  clear ETMEN bit to disable ETM-specific registers, only TPM-compatible
+*         registers can be used.
+*        
+* @param[in]    pETM           pointer to one of three ETM base register address.
+*    
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetETMEnhanced.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_SetETMBasic(ETM_Type *pETM)
+{
+    if(pETM->MODE & ETM_MODE_WPDIS_MASK)    /* if not write protected */
+    {
+        pETM->MODE &= ~ETM_MODE_ETMEN_MASK;
+    }
+    else
+    {
+        ETM_WriteProtectionDisable(pETM);
+        pETM->MODE &= ~ETM_MODE_ETMEN_MASK;
+        ETM_WriteProtectionEnable(pETM);
+    }  
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set the ETM mod value.
+*              
+* @param[in]    pETM           pointer to one of three ETM base register address.
+* @param[in]    u16ModValue    the mod value required to set.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetChannelValue.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_SetModValue(ETM_Type *pETM, uint16_t u16ModValue)
+{
+    pETM->CNT = 0;
+    pETM->MOD = u16ModValue;
+    if(ETM2 == pETM)
+    {
+        if(pETM->MODE & ETM_MODE_ETMEN_MASK)
+        {
+            pETM->PWMLOAD |= ETM_PWMLOAD_LDOK_MASK;
+        }
+        else
+        {
+        }
+    }
+    else
+    {
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set the ETM channel value.
+*                
+* @param[in]    pETM             pointer to one of three ETM base register address.
+* @param[in]    u16ChannelValue  the CnV value required to set.
+* @param[in]    u8ETM_Channel    ETM channel number.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetModValue.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_SetChannelValue(ETM_Type *pETM, uint8_t u8ETM_Channel, uint16_t u16ChannelValue)
+{
+    pETM->CONTROLS[u8ETM_Channel].CnV = u16ChannelValue;
+    if(ETM2 == pETM)
+    {
+        if(pETM->MODE & ETM_MODE_ETMEN_MASK)
+        {
+            if(u8ETM_Channel < 2)
+            {
+                pETM->COMBINE |= ETM_COMBINE_SYNCEN0_MASK;  /* enable the sync function */
+            }
+            else if (u8ETM_Channel < 4)
+            {
+                pETM->COMBINE |= ETM_COMBINE_SYNCEN1_MASK;
+            }
+            else
+            {
+                pETM->COMBINE |= ETM_COMBINE_SYNCEN2_MASK;
+            }
+            pETM->PWMLOAD |= ETM_PWMLOAD_LDOK_MASK;  
+        }
+        else
+        {
+        }
+    }
+    else
+    {
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set the ETM channel value.
+*               
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u16CounterValue   the CNTIN value required to set.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see ETM_SetModValue.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_SetCounterInitValue(ETM_Type *pETM, uint16_t u16CounterValue)
+{
+    pETM->CNTIN = u16CounterValue;
+    if(pETM->MODE & ETM_MODE_ETMEN_MASK)
+    {
+        pETM->PWMLOAD |= ETM_PWMLOAD_LDOK_MASK;
+    }
+    else
+    {
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set the channel output mask value, ETM2 used only.
+*               
+* @param[in]    pETM            pointer to one of three ETM base register address.
+* @param[in]    u16ChMask       the CNTIN value required to set.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see ETM_UnMaskChannels.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_MaskChannels(ETM_Type *pETM, uint16_t u16ChMask)
+{
+     pETM->OUTMASK |= u16ChMask;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  clear the channel output mask value, ETM2 used only.
+*               
+* @param[in]    pETM            pointer to one of three ETM base register address.
+* @param[in]    u16ChMask       the CNTIN value required to set.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see ETM_MaskChannels.
+*
+*****************************************************************************/
+__STATIC_INLINE void ETM_UnMaskChannels(ETM_Type *pETM, uint16_t u16ChMask)
+{
+     pETM->OUTMASK &= ~u16ChMask;
+}
+
+/*********************************************************************************//*!
+*
+* @brief set ETM channels polarity.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    u8ChsPolValue         the channels value need to be set.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_GetChannelsPolarity.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_SetChannelsPolarity(ETM_Type *pETM, uint8_t u8ChsPolValue)
+{
+    pETM->POL = u8ChsPolValue;
+}
+
+/*********************************************************************************//*!
+*
+* @brief get ETM channels polarity.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+*
+* @return uint8_t the channels polarity.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetChannelsPolarity.
+*
+*********************************************************************************/
+__STATIC_INLINE uint8_t ETM_GetChannelsPolarity(ETM_Type *pETM)
+{
+    return (pETM->POL);
+}
+
+/*********************************************************************************//*!
+*
+* @brief select the enhanced SYNC mode.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_DisableEnhancedSYNCMode.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_EnableEnhancedSYNCMode(ETM_Type *pETM)
+{
+    pETM->SYNCONF   |= ETM_SYNCONF_SYNCMODE_MASK;   /* recommend enhanced sync mode */
+}
+
+/*********************************************************************************//*!
+*
+* @brief select the legacy SYNC mode.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_EnableEnhancedSYNCMode.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_DisableEnhancedSYNCMode(ETM_Type *pETM)
+{
+    pETM->SYNCONF   &= ~ETM_SYNCONF_SYNCMODE_MASK;   /* recommend enhanced sync mode */
+}
+
+/*********************************************************************************//*!
+*
+* @brief set the external trigger source.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8TirggerSource   initial trigger or CHn(0~5)trigger
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_GetExternalTriggerFlag.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_SetExternalTrigger(ETM_Type *pETM, uint8_t u8TirggerSource)
+{
+    pETM->EXTTRIG   = u8TirggerSource;
+}
+
+/*********************************************************************************//*!
+*
+* @brief get the external trigger flag.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return ex trigger flag.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetExternalTrigger.
+*
+*********************************************************************************/
+__STATIC_INLINE uint8_t ETM_GetExternalTriggerFlag(ETM_Type *pETM)
+{
+    return (pETM->EXTTRIG & ETM_EXTTRIG_TRIGF_MASK);
+}
+
+/*********************************************************************************//*!
+*
+* @brief set LDOK bit.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetLoadMatchChannel.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_SetLoadEnable(ETM_Type *pETM)
+{
+    pETM->PWMLOAD |= ETM_PWMLOAD_LDOK_MASK;
+}
+
+/*********************************************************************************//*!
+*
+* @brief set the channel in the matching process.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8Matchchannel    the channel in the matching process.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_SetLoadEnable.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_SetLoadMatchChannel(ETM_Type *pETM, uint8_t u8Matchchannel)
+{
+    pETM->PWMLOAD |= u8Matchchannel;
+}
+
+/*********************************************************************************//*!
+*
+* @brief disable the channel input capture filter.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8ETM_Channel     the channel number: 0~3.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_InputCaptureFilterSet.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_InputCaptureFilterClr(ETM_Type *pETM, uint8_t u8ETM_Channel)
+{
+    pETM->FILTER &= ~(0x000F << (u8ETM_Channel << 2));
+}
+
+/*********************************************************************************//*!
+*
+* @brief set the channel input capture filter value.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8ETM_Channel     the channel number: 0~3.
+* @param[in]    u8FilterValue     fliter cycles:1~15, 0: disable channel filter.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_InputCaptureFilterClr.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_InputCaptureFilterSet(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8FilterValue)
+{
+    if (u8FilterValue)
+    {
+        pETM->FILTER |= (u8FilterValue << (u8ETM_Channel << 2));
+    }
+    else
+    {
+        ETM_InputCaptureFilterClr(pETM, u8ETM_Channel);
+    }
+}
+
+
+/*********************************************************************************//*!
+*
+* @brief enable the fault input pin.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8FaultPin        the fault input channel number: 0~3.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_FaultPinDisable.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_FaultPinEnable(ETM_Type *pETM, uint8_t u8FaultPin)
+{
+    if (pETM->MODE & ETM_MODE_WPDIS_MASK) /* if not protected */
+    {
+        pETM->FLTCTRL |= (1 << u8FaultPin);
+    }
+    else                                  /* if protected */ 
+    {
+        ETM_WriteProtectionDisable(pETM);
+        pETM->FLTCTRL |= (1 << u8FaultPin);
+        ETM_WriteProtectionEnable(pETM);
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief disable the fault input pin.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8FaultPin        the fault input channel number: 0~3.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_FaultPinEnable.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_FaultPinDisable(ETM_Type *pETM, uint8_t u8FaultPin)
+{
+    if (pETM->MODE & ETM_MODE_WPDIS_MASK) /* if not protected */
+    {
+        pETM->FLTCTRL &= ~(1 << u8FaultPin);
+    }
+    else                                  /* if protected */ 
+    {
+        ETM_WriteProtectionDisable(pETM);
+        pETM->FLTCTRL &= ~(1 << u8FaultPin);
+        ETM_WriteProtectionEnable(pETM);
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief enable the fault pin filter.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8FaultPin        the fault input channel number: 0~3.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_FaultPinFilterDisable.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_FaultPinFilterEnable(ETM_Type *pETM, uint8_t u8FaultPin)
+{
+    if (pETM->MODE & ETM_MODE_WPDIS_MASK) /* if not protected */
+    {
+        pETM->FLTCTRL |= (0x10 << u8FaultPin);
+    }
+    else                                  /* if protected */ 
+    {
+        ETM_WriteProtectionDisable(pETM);
+        pETM->FLTCTRL |= (0x10 << u8FaultPin);
+        ETM_WriteProtectionEnable(pETM);
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief disable the fault pin filter.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8FaultPin        the fault input channel number: 0~3.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_FaultPinFilterDisable.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_FaultPinFilterDisable(ETM_Type *pETM, uint8_t u8FaultPin)
+{
+    if (pETM->MODE & ETM_MODE_WPDIS_MASK) /* if not protected */
+    {
+        pETM->FLTCTRL &= ~(0x10 << u8FaultPin);
+    }
+    else                                  /* if protected */ 
+    {
+        ETM_WriteProtectionDisable(pETM);
+        pETM->FLTCTRL &= ~(0x10 << u8FaultPin);
+        ETM_WriteProtectionEnable(pETM);
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief disable all the fault pins filter together. 
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_FaultPinFilterSet.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_FaultPinFilterCDisableAll(ETM_Type *pETM)
+{
+    pETM->FLTCTRL &= ~ETM_FLTCTRL_FFVAL_MASK;
+}
+
+/*********************************************************************************//*!
+*
+* @brief set the fault filter value. All channels share the same filter value.
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8FilterValue     the fault input filter value: 1~15, 0 disable the filter.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_FaultPinFilterCDisableAll.
+*
+*********************************************************************************/
+__STATIC_INLINE void ETM_FaultPinFilterSet(ETM_Type *pETM, uint8_t u8FilterValue)
+{
+    if (u8FilterValue)
+    {
+        pETM->FLTCTRL |= ETM_FLTCTRL_FFVAL(u8FilterValue);
+    }
+    else
+    {
+        ETM_FaultPinFilterCDisableAll(pETM);
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief get the logic OR of all the fault detection flags
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_GetFaultDetectionFlag.
+*
+*********************************************************************************/
+__STATIC_INLINE uint8_t ETM_GetFaultDetectionLogicORFlag(ETM_Type *pETM)
+{
+    return (pETM->FMS & ETM_FMS_FAULTF_MASK);
+}
+
+/*********************************************************************************//*!
+*
+* @brief get the fault detection flag
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+* @param[in]    u8FaultPin        fault input pin number: 0~3.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see ETM_GetFaultDetectionLogicORFlag.
+*
+*********************************************************************************/
+__STATIC_INLINE uint8_t ETM_GetFaultDetectionFlag(ETM_Type *pETM, uint8_t u8FaultPin)
+{
+    return (pETM->FMS & (1 << u8FaultPin));
+}
+
+/*********************************************************************************//*!
+*
+* @brief get the logic OR value of the fault inputs
+*        
+* @param[in]    pETM              pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+__STATIC_INLINE uint8_t ETM_GetFaultInputsLogicORValue(ETM_Type *pETM)
+{
+    return (pETM->FMS & ETM_FMS_FAULTIN_MASK);
+}
+
+/*! @} End of ETM_api_list                                                    */
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+void ETM_ClockSet(ETM_Type *pETM, uint8_t u8ClockSource, uint8_t u8ClockPrescale);
+void ETM_PWMInit(ETM_Type *pETM, uint8_t u8PWMModeSelect, uint8_t u8PWMEdgeSelect);
+void ETM_InputCaptureInit(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8CaptureMode);
+void ETM_DualEdgeCaptureInit(ETM_Type *pETM, uint8_t u8ChannelPair, uint8_t u8CaptureMode, 
+                             uint8_t u8Channel_N_Edge, uint8_t u8Channel_Np1_Edge);
+void ETM_OutputCompareInit(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8CompareMode);
+void ETM_SoftwareSync(ETM_Type *pETM);
+void ETM_HardwareSync(ETM_Type *pETM, uint8_t u8TriggerN);
+void ETM_HardwareSyncCombine(ETM_Type *pETM, uint8_t u8TriggerMask);
+void ETM_GenerateTrig2(ETM_Type *pETM);
+void ETM_PWMDeadETMeSet(ETM_Type *pETM, uint8_t u8PrescalerValue, uint8_t u8DeadETMeValue);
+void ETM_OutputMaskSet(ETM_Type *pETM, uint8_t u8ETM_Channel);
+void ETM_SWOutputControlSet(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8ChannelValue);
+void ETM_SetDebugModeBehavior(ETM_Type *pETM, uint8_t u8DebugMode);
+void ETM_SetTOFFrequency(ETM_Type *pETM, uint8_t u8TOFNUM);
+void ETM_PolaritySet(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8ActiveValue);
+void ETM_InvertChannel(ETM_Type *pETM, uint8_t u8ChannelPair);
+void ETM_Init(ETM_Type *pETM, ETM_ConfigType *pConfig);
+void ETM_DeInit(ETM_Type *pETM);
+void ETM_ChannelInit(ETM_Type *pETM, uint8_t u8ETM_Channel, ETM_ChParamsType *pETM_ChParams);
+void ETM_SetDutyCycleCombine(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8DutyCycle);
+void ETM_SetCallback(ETM_Type *pETM, ETM_CallbackPtr pfnCallback);
+void  ETM_SyncConfigActivate(ETM_Type *pETM, uint32_t u32ConfigValue);
+void ETM_SyncConfigDeactivate(ETM_Type * pETM, uint32_t u32ConfigValue);
+uint8_t ETM_GetFaultDetectionLogicORFlag(ETM_Type *pETM);
+uint8_t ETM_GetFaultDetectionFlag(ETM_Type *pETM, uint8_t u8FaultPin);
+uint8_t ETM_GetFaultInputsLogicORValue(ETM_Type *pETM);
+void ETM_WriteProtectionEnable(ETM_Type *pETM);
+void ETM_WriteProtectionDisable(ETM_Type *pETM);
+void ETM_FaultPinFilterCDisableAll(ETM_Type *pETM);
+void ETM_FaultPinFilterSet(ETM_Type *pETM, uint8_t u8FilterValue);
+void ETM_FaultPinFilterDisable(ETM_Type *pETM, uint8_t u8FaultPin);
+void ETM_FaultPinFilterEnable(ETM_Type *pETM, uint8_t u8FaultPin);
+void ETM_FaultPinEnable(ETM_Type *pETM, uint8_t u8FaultPin);
+void ETM_FaultPinDisable(ETM_Type *pETM, uint8_t u8FaultPin);
+void ETM_InputCaptureFilterClr(ETM_Type *pETM, uint8_t u8ETM_Channel);
+void ETM_InputCaptureFilterSet(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8FilterValue);
+void ETM_SetLoadMatchChannel(ETM_Type *pETM, uint8_t u8Matchchannel);
+void ETM_SetLoadEnable(ETM_Type *pETM);
+uint8_t ETM_GetExternalTriggerFlag(ETM_Type *pETM);
+void ETM_DisableEnhancedSYNCMode(ETM_Type *pETM);
+void ETM_EnableEnhancedSYNCMode(ETM_Type *pETM);
+uint8_t ETM_GetChannelsPolarity(ETM_Type *pETM);
+void ETM_SetChannelsPolarity(ETM_Type *pETM, uint8_t u8ChsPolValue);
+void ETM_UnMaskChannels(ETM_Type *pETM, uint16_t u16ChMask);
+void ETM_MaskChannels(ETM_Type *pETM, uint16_t u16ChMask);
+void ETM_SetCounterInitValue(ETM_Type *pETM, uint16_t u16CounterValue);
+void ETM_SetChannelValue(ETM_Type *pETM, uint8_t u8ETM_Channel, uint16_t u16ChannelValue);
+void ETM_SetModValue(ETM_Type *pETM, uint16_t u16ModValue);
+void ETM_SetETMBasic(ETM_Type *pETM);
+void ETM_SetETMEnhanced(ETM_Type *pETM);
+void ETM_ClrChannelFlag(ETM_Type *pETM, uint8_t u8ETM_Channel);
+uint8_t ETM_GetChannelFlag(ETM_Type *pETM, uint8_t u8ETM_Channel);
+void ETM_ClrOverFlowFlag(ETM_Type *pETM);
+uint8_t ETM_GetOverFlowFlag(ETM_Type *pETM);
+void ETM_DisableChannelInt(ETM_Type *pETM, uint8_t u8ETM_Channel);
+void ETM_EnableChannelInt(ETM_Type *pETM, uint8_t u8ETM_Channel);
+void ETM_DisableOverflowInt(ETM_Type *pETM);
+void ETM_EnableOverflowInt(ETM_Type *pETM);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ETM_H_ */

bsp/nv32f100x/lib/inc/flash.h

@@ -0,0 +1,118 @@
+/******************************************************************************
+******************************************************************************
+*
+* @file flash.h
+*
+* @brief application entry point which performs application specific tasks. 
+*
+*******************************************************************************
+*
+* provide a demo for how to initialize the NV32, output messages via SCI, 
+* flash operations, etc.
+* NOTE:
+*	printf call may occupy a lot of memory (around 1924 bytes), so please
+*	consider your code size before using printf.
+******************************************************************************
+*
+* provide FLASH driver
+*
+******************************************************************************/
+
+
+
+#ifndef FLASH_H_
+#define FLASH_H_
+
+/******************************************************************************
+* Includes
+******************************************************************************/
+#include "common.h"
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+/* Uncomment the following line to support programming flash while running code from flash */
+// #define FLASH_ENABLE_STALLING_FLASH_CONTROLLER
+
+#define ETMRH_FSTAT_MGSTAT0_MASK  (1)
+#define ETMRH_FSTAT_MGSTAT1_MASK  (1<<1)
+
+#define FLASH_SECTOR_SIZE	512		// in bytes
+
+/* Flash driver errors */
+#define FLASH_ERR_BASE				0x3000
+#define FLASH_ERR_SUCCESS			0
+#define FLASH_ERR_INVALID_PARAM		(FLASH_ERR_BASE+1)	// invalid parameter error code
+#define EEPROM_ERR_SINGLE_BIT_FAULT	(FLASH_ERR_BASE+2)	// EEPROM single bit fault error code
+#define EEPROM_ERR_DOUBLE_BIT_FAULT	(FLASH_ERR_BASE+4)	// EEPROM double bits fault error code
+#define FLASH_ERR_ACCESS			(FLASH_ERR_BASE+8)	// flash access error code
+#define FLASH_ERR_PROTECTION		(FLASH_ERR_BASE+0x10)	// flash protection error code
+#define FLASH_ERR_MGSTAT0			(FLASH_ERR_BASE+0x11)	// flash verification error code
+#define FLASH_ERR_MGSTAT1			(FLASH_ERR_BASE+0x12)	// flash non-correctable error code
+#define FLASH_ERR_INIT_CCIF			(FLASH_ERR_BASE+0x14)	// flash driver init error with CCIF = 1
+#define FLASH_ERR_INIT_FDIV			(FLASH_ERR_BASE+0x18)	// flash driver init error with wrong FDIV 
+
+/* Flash and EEPROM commands */
+
+
+#define FLASH_CMD_PROGRAM			0x20000000
+#define FLASH_CMD_CLEAR       0x00005000
+#define FLASH_CMD_ERASE_ALL   0x41000000
+#define FLASH_CMD_ERASE_SECTOR		0x40000000
+#define FLASH_FACTORY_KEY 0x0065fe9a
+
+#define EFM_DONE_MASK    0x00006000
+#define EFM_STATUS_DONE  0x00006000
+#define EFM_STATUS_READY 0x00002000
+
+#define FLASH_ACCERR_MASK 0x10
+
+#define M8(adr)  (*((volatile unsigned char  *) (adr)))
+#define M16(adr) (*((volatile unsigned short *) (adr)))
+#define M32(adr) (*((volatile unsigned long  *) (adr)))
+
+
+
+/******************************************************************************
+* Types
+******************************************************************************/
+typedef  uint16_t (*TFlash_Fun1)(uint32_t wNVMTargetAddress, uint8_t *pbData, uint8_t bByteCount);
+typedef  uint16_t (*TFlash_Fun2)(uint32_t wNVMTargetAddress, uint32_t dwData0, uint32_t dwData1);
+typedef  uint16_t (*TFlash_Fun3)(uint32_t wNVMTargetAddress, uint32_t dwData);
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+uint16_t Flash_Program(uint32_t wNVMTargetAddress, uint8_t *pData, uint16_t sizeBytes);
+uint16_t Flash_Program1LongWord(uint32_t wNVMTargetAddress, uint32_t dwData);
+uint16_t Flash_Program2LongWords(uint32_t wNVMTargetAddress, uint32_t dwData0, uint32_t dwData1);
+
+uint16_t Flash_EraseSector(uint32_t wNVMTargetAddress);
+
+uint16_t Flash_VerifyBackdoorKey(void);
+
+uint16_t NVM_EraseAll(void);
+
+uint16_t NVM_Unsecure(void);
+
+uint16_t Flash_Init(void);
+
+#ifdef IAR
+void __ramfunc EFM_LaunchCMD(uint32_t EFM_CMD);
+#else
+void EFM_LaunchCMD(uint32_t EFM_CMD);
+#endif
+
+
+void	Flash_CopyInRAM(void);
+void	Flash_CopyRouinte2RAM(char *func, uint16_t sizeFunc);
+/********************************************************************/
+
+#endif /* FLASH_H_ */

bsp/nv32f100x/lib/inc/gpio.h

@@ -0,0 +1,278 @@
+/******************************************************************************
+*
+* @brief provide commond GPIO utilities. 
+*
+*******************************************************************************/
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "common.h"
+#include "stdint.h"
+
+/******************************************************************************
+*define gpio pin name
+*
+*//*! @addtogroup gpio_pin_name_list
+* @{
+*******************************************************************************/
+typedef enum
+{
+    /* in GPIOA register */
+    GPIO_PTA0 = 0,              /*!< GPIO Pin PTA0 */
+    GPIO_PTA1,                  /*!< GPIO Pin PTA1 */
+    GPIO_PTA2,                  /*!< GPIO Pin PTA2 */
+    GPIO_PTA3,                  /*!< GPIO Pin PTA3 */
+    GPIO_PTA4,                  /*!< GPIO Pin PTA4 */
+    GPIO_PTA5,                  /*!< GPIO Pin PTA5 */
+    GPIO_PTA6,                  /*!< GPIO Pin PTA6 */
+    GPIO_PTA7,                  /*!< GPIO Pin PTA7 */
+    GPIO_PTB0,                  /*!< GPIO Pin PTB0 */
+    GPIO_PTB1,                  /*!< GPIO Pin PTB1 */
+    GPIO_PTB2,                  /*!< GPIO Pin PTB2 */
+    GPIO_PTB3,                  /*!< GPIO Pin PTB3 */
+    GPIO_PTB4,                  /*!< GPIO Pin PTB4 */
+    GPIO_PTB5,                  /*!< GPIO Pin PTB5 */
+    GPIO_PTB6,                  /*!< GPIO Pin PTB6 */
+    GPIO_PTB7,                  /*!< GPIO Pin PTB7 */
+    GPIO_PTC0,                  /*!< GPIO Pin PTC0 */
+    GPIO_PTC1,                  /*!< GPIO Pin PTC1 */
+    GPIO_PTC2,                  /*!< GPIO Pin PTC2 */
+    GPIO_PTC3,                  /*!< GPIO Pin PTC3 */
+    GPIO_PTC4,                  /*!< GPIO Pin PTC4 */
+    GPIO_PTC5,                  /*!< GPIO Pin PTC5 */
+    GPIO_PTC6,                  /*!< GPIO Pin PTC6 */
+    GPIO_PTC7,                  /*!< GPIO Pin PTC7 */
+    GPIO_PTD0,                  /*!< GPIO Pin PTD0 */
+    GPIO_PTD1,                  /*!< GPIO Pin PTD1 */
+    GPIO_PTD2,                  /*!< GPIO Pin PTD2 */
+    GPIO_PTD3,                  /*!< GPIO Pin PTD3 */
+    GPIO_PTD4,                  /*!< GPIO Pin PTD4 */
+    GPIO_PTD5,                  /*!< GPIO Pin PTD5 */
+    GPIO_PTD6,                  /*!< GPIO Pin PTD6 */
+    GPIO_PTD7,                  /*!< GPIO Pin PTD7 */
+    /* in GPIOB register */
+    GPIO_PTE0,                  /*!< GPIO Pin PTE0 */
+    GPIO_PTE1,                  /*!< GPIO Pin PTE1 */
+    GPIO_PTE2,                  /*!< GPIO Pin PTE2 */
+    GPIO_PTE3,                  /*!< GPIO Pin PTE3 */
+    GPIO_PTE4,                  /*!< GPIO Pin PTE4 */
+    GPIO_PTE5,                  /*!< GPIO Pin PTE5 */
+    GPIO_PTE6,                  /*!< GPIO Pin PTE6 */
+    GPIO_PTE7,                  /*!< GPIO Pin PTE7 */
+    GPIO_PTF0,                  /*!< GPIO Pin PTF0 */
+    GPIO_PTF1,                  /*!< GPIO Pin PTF1 */
+    GPIO_PTF2,                  /*!< GPIO Pin PTF2 */
+    GPIO_PTF3,                  /*!< GPIO Pin PTF3 */
+    GPIO_PTF4,                  /*!< GPIO Pin PTF4 */
+    GPIO_PTF5,                  /*!< GPIO Pin PTF5 */
+    GPIO_PTF6,                  /*!< GPIO Pin PTF6 */
+    GPIO_PTF7,                  /*!< GPIO Pin PTF7 */
+    GPIO_PTG0,                  /*!< GPIO Pin PTG0 */
+    GPIO_PTG1,                  /*!< GPIO Pin PTG1 */
+    GPIO_PTG2,                  /*!< GPIO Pin PTG2 */
+    GPIO_PTG3,                  /*!< GPIO Pin PTG3 */
+    GPIO_PTG4,                  /*!< GPIO Pin PTG4 */
+    GPIO_PTG5,                  /*!< GPIO Pin PTG5 */
+    GPIO_PTG6,                  /*!< GPIO Pin PTG6 */
+    GPIO_PTG7,                  /*!< GPIO Pin PTG7 */
+    GPIO_PTH0,                  /*!< GPIO Pin PTH0 */
+    GPIO_PTH1,                  /*!< GPIO Pin PTH1 */
+    GPIO_PTH2,                  /*!< GPIO Pin PTH2 */
+    GPIO_PTH3,                  /*!< GPIO Pin PTH3 */
+    GPIO_PTH4,                  /*!< GPIO Pin PTH4 */
+    GPIO_PTH5,                  /*!< GPIO Pin PTH5 */
+    GPIO_PTH6,                  /*!< GPIO Pin PTH6 */
+    GPIO_PTH7,                  /*!< GPIO Pin PTH7 */
+    /* the following pins are not in NV322 */
+    GPIO_PTI0,                  /*!< GPIO Pin PTI0 */
+    GPIO_PTI1,                  /*!< GPIO Pin PTI1 */
+    GPIO_PTI2,                  /*!< GPIO Pin PTI2 */
+    GPIO_PTI3,                  /*!< GPIO Pin PTI3 */
+    GPIO_PTI4,                  /*!< GPIO Pin PTI4 */
+    GPIO_PTI5,                  /*!< GPIO Pin PTI5 */
+    GPIO_PTI6,                  /*!< GPIO Pin PTI6 */
+    GPIO_PTI7,                  /*!< GPIO Pin PTI7 */
+    GPIO_PIN_MAX,
+} GPIO_PinType;
+/*! @} End of gpio_pin_name_list    */
+
+/******************************************************************************
+*define gpio pin mask
+*
+*//*! @addtogroup gpio_pin_mask_list
+* @{
+*******************************************************************************/
+typedef enum
+{
+    /* in GPIOA register */
+    GPIO_PTA0_MASK = (1<<0),    /*!< GPIO Pin PTA0 bit mask */        
+    GPIO_PTA1_MASK = (1<<1),    /*!< GPIO Pin PTA1 bit mask */
+    GPIO_PTA2_MASK = (1<<2),    /*!< GPIO Pin PTA2 bit mask */
+    GPIO_PTA3_MASK = (1<<3),    /*!< GPIO Pin PTA3 bit mask */
+    GPIO_PTA4_MASK = (1<<4),    /*!< GPIO Pin PTA4 bit mask */
+    GPIO_PTA5_MASK = (1<<5),    /*!< GPIO Pin PTA5 bit mask */
+    GPIO_PTA6_MASK = (1<<6),    /*!< GPIO Pin PTA6 bit mask */
+    GPIO_PTA7_MASK = (1<<7),    /*!< GPIO Pin PTA7 bit mask */
+    GPIO_PTB0_MASK = (1<<8),    /*!< GPIO Pin PTB0 bit mask */
+    GPIO_PTB1_MASK = (1<<9),    /*!< GPIO Pin PTB1 bit mask */
+    GPIO_PTB2_MASK = (1<<10),   /*!< GPIO Pin PTB2 bit mask */
+    GPIO_PTB3_MASK = (1<<11),   /*!< GPIO Pin PTB3 bit mask */
+    GPIO_PTB4_MASK = (1<<12),   /*!< GPIO Pin PTB4 bit mask */
+    GPIO_PTB5_MASK = (1<<13),   /*!< GPIO Pin PTB5 bit mask */
+    GPIO_PTB6_MASK = (1<<14),   /*!< GPIO Pin PTB6 bit mask */
+    GPIO_PTB7_MASK = (1<<15),   /*!< GPIO Pin PTB7 bit mask */
+    GPIO_PTC0_MASK = (1<<16),   /*!< GPIO Pin PTC0 bit mask */
+    GPIO_PTC1_MASK = (1<<17),   /*!< GPIO Pin PTC1 bit mask */
+    GPIO_PTC2_MASK = (1<<18),   /*!< GPIO Pin PTC2 bit mask */
+    GPIO_PTC3_MASK = (1<<19),   /*!< GPIO Pin PTC3 bit mask */
+    GPIO_PTC4_MASK = (1<<20),   /*!< GPIO Pin PTC4 bit mask */
+    GPIO_PTC5_MASK = (1<<21),   /*!< GPIO Pin PTC5 bit mask */
+    GPIO_PTC6_MASK = (1<<22),   /*!< GPIO Pin PTC6 bit mask */
+    GPIO_PTC7_MASK = (1<<23),   /*!< GPIO Pin PTC7 bit mask */
+    GPIO_PTD0_MASK = (1<<24),   /*!< GPIO Pin PTD0 bit mask */
+    GPIO_PTD1_MASK = (1<<25),   /*!< GPIO Pin PTD1 bit mask */
+    GPIO_PTD2_MASK = (1<<26),   /*!< GPIO Pin PTD2 bit mask */
+    GPIO_PTD3_MASK = (1<<27),   /*!< GPIO Pin PTD3 bit mask */
+    GPIO_PTD4_MASK = (1<<28),   /*!< GPIO Pin PTD4 bit mask */
+    GPIO_PTD5_MASK = (1<<29),   /*!< GPIO Pin PTD5 bit mask */
+    GPIO_PTD6_MASK = (1<<30),   /*!< GPIO Pin PTD6 bit mask */
+    GPIO_PTD7_MASK = (1<<31),   /*!< GPIO Pin PTD7 bit mask */
+    /* in GPIOB register */
+    GPIO_PTE0_MASK = (1<<0),    /*!< GPIO Pin PTE0 bit mask */
+    GPIO_PTE1_MASK = (1<<1),    /*!< GPIO Pin PTE1 bit mask */
+    GPIO_PTE2_MASK = (1<<2),    /*!< GPIO Pin PTE2 bit mask */
+    GPIO_PTE3_MASK = (1<<3),    /*!< GPIO Pin PTE3 bit mask */
+    GPIO_PTE4_MASK = (1<<4),    /*!< GPIO Pin PTE4 bit mask */
+    GPIO_PTE5_MASK = (1<<5),    /*!< GPIO Pin PTE5 bit mask */
+    GPIO_PTE6_MASK = (1<<6),    /*!< GPIO Pin PTE6 bit mask */
+    GPIO_PTE7_MASK = (1<<7),    /*!< GPIO Pin PTE7 bit mask */
+    GPIO_PTF0_MASK = (1<<8),    /*!< GPIO Pin PTF0 bit mask */
+    GPIO_PTF1_MASK = (1<<9),    /*!< GPIO Pin PTF1 bit mask */
+    GPIO_PTF2_MASK = (1<<10),   /*!< GPIO Pin PTF2 bit mask */
+    GPIO_PTF3_MASK = (1<<11),   /*!< GPIO Pin PTF3 bit mask */
+    GPIO_PTF4_MASK = (1<<12),   /*!< GPIO Pin PTF4 bit mask */
+    GPIO_PTF5_MASK = (1<<13),   /*!< GPIO Pin PTF5 bit mask */
+    GPIO_PTF6_MASK = (1<<14),   /*!< GPIO Pin PTF6 bit mask */
+    GPIO_PTF7_MASK = (1<<15),   /*!< GPIO Pin PTF7 bit mask */
+    GPIO_PTG0_MASK = (1<<16),   /*!< GPIO Pin PTG0 bit mask */
+    GPIO_PTG1_MASK = (1<<17),   /*!< GPIO Pin PTG1 bit mask */
+    GPIO_PTG2_MASK = (1<<18),   /*!< GPIO Pin PTG2 bit mask */
+    GPIO_PTG3_MASK = (1<<19),   /*!< GPIO Pin PTG3 bit mask */
+    GPIO_PTG4_MASK = (1<<20),   /*!< GPIO Pin PTG4 bit mask */
+    GPIO_PTG5_MASK = (1<<21),   /*!< GPIO Pin PTG5 bit mask */
+    GPIO_PTG6_MASK = (1<<22),   /*!< GPIO Pin PTG6 bit mask */
+    GPIO_PTG7_MASK = (1<<23),   /*!< GPIO Pin PTG7 bit mask */
+    GPIO_PTH0_MASK = (1<<24),   /*!< GPIO Pin PTH0 bit mask */
+    GPIO_PTH1_MASK = (1<<25),   /*!< GPIO Pin PTH1 bit mask */
+    GPIO_PTH2_MASK = (1<<26),   /*!< GPIO Pin PTH2 bit mask */
+    GPIO_PTH3_MASK = (1<<27),   /*!< GPIO Pin PTH3 bit mask */
+    GPIO_PTH4_MASK = (1<<28),   /*!< GPIO Pin PTH4 bit mask */
+    GPIO_PTH5_MASK = (1<<29),   /*!< GPIO Pin PTH5 bit mask */
+    GPIO_PTH6_MASK = (1<<30),   /*!< GPIO Pin PTH6 bit mask */
+    GPIO_PTH7_MASK = (1<<31),   /*!< GPIO Pin PTH7 bit mask */
+    /* in GPIOC register */
+    GPIO_PTI0_MASK = (1<<0),    /*!< GPIO Pin PTI0 bit mask */
+    GPIO_PTI1_MASK = (1<<1),    /*!< GPIO Pin PTI1 bit mask */
+    GPIO_PTI2_MASK = (1<<2),    /*!< GPIO Pin PTI2 bit mask */
+    GPIO_PTI3_MASK = (1<<3),    /*!< GPIO Pin PTI3 bit mask */
+    GPIO_PTI4_MASK = (1<<4),    /*!< GPIO Pin PTI4 bit mask */
+    GPIO_PTI5_MASK = (1<<5),    /*!< GPIO Pin PTI5 bit mask */
+    GPIO_PTI6_MASK = (1<<6),    /*!< GPIO Pin PTI6 bit mask */
+    GPIO_PTI7_MASK = (1<<7),    /*!< GPIO Pin PTI7 bit mask */
+} GPIO_PinMaskType;
+/*! @} End of gpio_pin_mask_list    */
+
+
+/******************************************************************************
+*define gpio pin config type
+*
+*//*! @addtogroup gpio_pin_config_type_list
+* @{
+*******************************************************************************/
+/*
+*   . Internal pullup is disabled if the pin is configured as an output
+*   . High-current drive function is disabled, if the pin is configured as an input
+*       Only PTH1/0, PTE1/0, PTD1/0, PTB5/4 support Hight-current Drive.
+*/
+typedef enum
+{
+    GPIO_PinOutput = 0,                 /*!< set pin as outout */
+    GPIO_PinInput,                      /*!< set pin as input */
+    GPIO_PinInput_InternalPullup,       /*!< set internal pullup for input pin */
+    GPIO_PinOutput_HighCurrent,         /*!< set high drive for output pin */
+} GPIO_PinConfigType;
+/*! @} End of gpio_pin_config_type_list */
+
+/******************************************************************************
+* define GPIO APIs
+*
+*//*! @addtogroup gpio_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+* @brief    Toggle the pins which are specified by u32PinMask in single cycle.
+*        
+* @param[in] pGPIO       Pointer to GPIO module, can be FGPIOA/FGPIOB.
+* @param[in] u32PinMask  Specify GPIO pin need to be toggled
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void FGPIO_Toggle(FGPIO_Type *pFGPIO, uint32_t u32PinMask)
+{
+    pFGPIO->PTOR = u32PinMask;   /* Toggle the pins specified by u32PinMask */
+}
+
+/*****************************************************************************//*!
+* @brief Read input data from GPIO which is specified by pGPIO in single cycle.
+*        
+* @param[in] pGPIO       Pointer to GPIO module, can be FGPIOA/FGPIOB.
+*
+* @return   GPIO input value unsigned int 32-bit
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+ __STATIC_INLINE uint32_t FGPIO_Read(FGPIO_Type *pFGPIO)
+{
+    return (pFGPIO->PDIR);      /* Read Port Data Input Register */
+  
+}
+
+/*****************************************************************************//*!
+* @brief    Write output data to GPIO which is specified by pGPIO in single cycle.
+*        
+* @param[in] pGPIO       Pointer to GPIO module, can be FGPIOA/FGPIOB.
+* @param[in] u32Value    value to output
+*
+* @return   none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void FGPIO_Write(FGPIO_Type *pFGPIO, uint32_t u32Value)
+{    
+    pFGPIO->PDOR = u32Value;    /* Write Port Ouput Data Register */
+}
+
+void GPIO_DeInit(GPIO_Type *pGPIO);
+void GPIO_Init(GPIO_Type *pGPIO, uint32_t u32PinMask, GPIO_PinConfigType sGpioType);
+void GPIO_Toggle(GPIO_Type *pGPIO, uint32_t u32PinMask);
+uint32_t GPIO_Read(GPIO_Type *pGPIO);
+void GPIO_Write(GPIO_Type *pGPIO, uint32_t u32Value);
+void GPIO_PinInit(GPIO_PinType GPIO_Pin, GPIO_PinConfigType GPIO_PinConfig);
+void GPIO_PinToggle(GPIO_PinType GPIO_Pin);
+void GPIO_PinSet(GPIO_PinType GPIO_Pin);
+void GPIO_PinClear(GPIO_PinType GPIO_Pin);
+uint8_t GPIO_BitRead(GPIO_PinType GPIO_Pin);
+    
+/*! @} End of gpio_api_list */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* #ifndef _GPIO_H_ */

bsp/nv32f100x/lib/inc/i2c.h

@@ -0,0 +1,524 @@
+/******************************************************************************
+* @brief header file for I2C module utilities (I2C). 
+*
+*******************************************************************************
+*
+* provide APIs for accessing I2C module (I2C)
+******************************************************************************/
+#ifndef _I2C_H__
+#define _I2C_H__
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+/******************************************************************************
+* define I2C work read or write 
+*
+*//*! @addtogroup i2c_read_write_list
+* @{
+*******************************************************************************/
+#define I2C_READ                        0x01				/*!< I2C read */
+#define I2C_WRITE                       0x0  				/*!< I2C write */
+/*! @} End of i2c_read_write_list                                             */
+
+#define I2C_SEND_ACK                    0						/*!< I2C send ACK */
+#define I2C_SEND_NACK                   1						/*!< I2C send NACK */
+
+#define I2C_WAIT_STATUS_ETMEOUT         200000
+
+/******************************************************************************
+* define I2C error state
+*
+*//*! @addtogroup i2c_error_state_list
+* @{
+*******************************************************************************/
+#define I2C_ERROR_NULL                  0x00			/*!< I2C sucess*/
+#define I2C_ERROR_NO_WAIT_TCF_FLAG      0x01			/*!< I2C wait TCF overETMe*/
+#define I2C_ERROR_NO_WAIT_IICIF_FLAG    0x02			/*!< I2C wait IICIF overETMe */
+#define I2C_ERROR_NO_GET_ACK            0x04			/*!< I2C no get ACK */
+#define I2C_ERROR_START_NO_BUSY_FLAG    0x10			/*!< I2C fail to send start signals */
+#define I2C_ERROR_STOP_BUSY_FLAG        0x20			/*!< I2C fail to send stop signal */
+#define I2C_ERROR_BUS_BUSY              0x80			/*!< I2C bus busy error */
+/*! @} End of i2c_error_state_list                                            */
+
+/******************************************************************************
+* define I2C bus state
+*
+*//*! @addtogroup i2c_bus_state_list
+* @{
+*******************************************************************************/
+#define I2C_BUS_NORMAL				0x00								/*!< I2C bus normal */
+#define I2C_BUS_SLTF					0x01								/*!< I2C bus SLTF flag */
+#define I2C_BUS_SHTF2					0x02								/*!< I2C bus SHTF2 flag */
+/*! @} End of i2c_bus_state_list                                             */
+
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+#define I2C_MODE_MASTER             1
+#define I2C_MODE_SLAVE              0
+#define I2C_ADDRESS_7BIT            0
+#define I2C_ADDRESS_10BIT           1
+#define I2C_ETMEOUT_BUS_CLOCK_DIV64 0
+#define I2C_ETMEOUT_BUS_CLOCK       1
+
+/******************************************************************************
+*
+*//*! @addtogroup i2c_setting_type
+* @{
+*******************************************************************************/
+/*!
+ * @brief I2C setting type.
+ *
+ */
+typedef struct
+{
+	uint16_t bI2CEn         :1;     			/*!< enable I2C module */
+	uint16_t bIntEn         :1;    			 	/*!< enable I2C enable */
+	uint16_t bWakeUpEn      :1;     			/*!< I2C wake up enable */
+	uint16_t bGCAEn         :1;     			/*!< I2C General call address enable */
+	uint16_t bAddressExt    :1;     			/*!< I2C extertion address selection */
+	uint16_t bRangeAddEn    :1;     			/*!< enable range address */
+	uint16_t bFackEn        :1;     			/*!< enable fast ack */
+	uint16_t bSMB_AlertEn   :1;     			/*!< SMB Alert enable */
+	uint16_t bSecondAddressEn:1;    			/*!< enable the second address */
+	uint16_t bETMeoutCountClockSelect:1;  /*!< ETMeoutCountClockSelect */
+    uint16_t bSHTF2IntEn    :1;					/*!< SHTF2 interrupt enable */
+    uint16_t Reserve        :5;
+}I2C_SettingType;
+/*! @} End of i2c_setting_type                                       						*/
+
+/******************************************************************************
+*
+*//*! @addtogroup i2c_config_type
+* @{
+*******************************************************************************/
+/*!
+ * @brief I2C configure type.
+ *
+ */
+typedef struct
+{
+    I2C_SettingType sSetting;
+    uint16_t u16F;              /*!< setting the band rate for I2C */
+    uint16_t u16OwnA1;          /*!< slave address */
+    uint16_t u16OwnA2;          /*!< the second slave address */
+    uint16_t u16RangeA;         /*!< range address */
+    uint16_t u16Filt;           /*!< Filter for I2C   */
+    uint16_t u16Slt;            /*!< SCL Low ETMeout register low */
+    
+}I2C_ConfigType, *I2C_ConfigPtr;
+/*! @} End of i2c_config_type                                             				*/
+
+/******************************************************************************
+*
+*//*! @addtogroup i2c_callback
+* @{
+*******************************************************************************/
+typedef void (*I2C_CallbackType)(void);		/*!< I2C call back function */
+/*! @} End of i2c_callback                                             						*/
+
+/******************************************************************************
+* inline functions
+******************************************************************************/
+/******************************************************************************
+*
+*//*! @addtogroup i2c_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief enable I2C to transmit data.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_TxEnable(I2C_Type *pI2Cx)
+{
+    pI2Cx->C1 |= I2C_C1_TX_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable I2C to receive data.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE void I2C_RxEnable(I2C_Type *pI2Cx)
+{
+    pI2Cx->C1 &= ~I2C_C1_TX_MASK;
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief set IIC band rate. 
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_SetBaudRate(I2C_Type *pI2Cx,uint32_t u32Bps)
+{
+    pI2Cx->F = (uint8_t)u32Bps;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable general call.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE void I2C_GeneralCallEnable(I2C_Type *pI2Cx)
+{
+     pI2Cx->C2 |= I2C_C2_GCAEN_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SMBus Alert Response Address Enable. 
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_SMBusAlertEnable(I2C_Type *pI2Cx)
+{
+     pI2Cx->SMB|= I2C_SMB_ALERTEN_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Range Address Matching Enable.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_RangeAddressEnable(I2C_Type *pI2Cx)
+{
+     pI2Cx->C2 |= I2C_C2_RMEN_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SHTF2 Interrupt Enable.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_SHTF2IntEnable(I2C_Type *pI2Cx)
+{
+     pI2Cx->SMB |= I2C_SMB_SHTF2IE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief ETMeout Counter Clock Select.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_ETMeoutCounterClockSelect(I2C_Type *pI2Cx, uint8_t u8Clock)
+{
+    if( u8Clock )
+    {
+        pI2Cx->SMB |= I2C_SMB_TCKSEL_MASK;
+    }
+    else
+    {
+        pI2Cx->SMB &= ~I2C_SMB_TCKSEL_MASK;
+    }
+}
+/*****************************************************************************//*!
+   *
+   * @brief get I2C status.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return I2C status
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_GetStatus(I2C_Type *pI2Cx)
+{
+    return pI2Cx->S;
+}
+/*****************************************************************************//*!
+   *
+   * @brief clear specified status.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_ClearStatus(I2C_Type *pI2Cx, uint8_t u8ClearFlag)
+{
+    pI2Cx->S |= u8ClearFlag;
+}
+/*****************************************************************************//*!
+   *
+   * @brief write data to data register.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_WriteDataReg(I2C_Type *pI2Cx, uint8_t u8DataBuff)
+{
+    pI2Cx->D = u8DataBuff;
+}
+/*****************************************************************************//*!
+   *
+   * @brief read data from data register.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return I2C data register value
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_ReadDataReg(I2C_Type *pI2Cx )
+{
+    return pI2Cx->D;
+}
+/*****************************************************************************//*!
+   *
+   * @brief check if is Tx mode.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return result  TRUE or FALSE
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_IsTxMode(I2C_Type *pI2Cx )
+{
+    return(pI2Cx->C1 & I2C_C1_TX_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check I2C if busy.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return result  TRUE or FALSE
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_IsBusy(I2C_Type *pI2Cx )
+{
+    return (pI2Cx->S & I2C_S_BUSY_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check I2C receive ack or nack.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return result    TRUE or FALSE
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_IsReceivedAck(I2C_Type *pI2Cx )
+{
+    return (pI2Cx->S & I2C_S_RXAK_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check I2C if is master mode.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return result    TRUE or FALSE.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_IsMasterMode(I2C_Type *pI2Cx )
+{
+    return(pI2Cx->C1 & I2C_C1_MST_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check SCL Low ETMeout Flag.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return result    TRUE or FALSE.
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_IsSMB_SLTF(I2C_Type *pI2Cx )
+{
+    return (pI2Cx->SMB & I2C_SMB_SLTF_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check SCL High ETMeout Flag is set or clear.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return result    TRUE or FALSE.
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t I2C_IsSMB_SHTF2(I2C_Type *pI2Cx )
+{
+    return(pI2Cx->SMB & I2C_SMB_SHTF2_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief clear SLTF flag.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE void I2C_ClearSLTF(I2C_Type *pI2Cx )
+{
+    pI2Cx->SMB |= I2C_SMB_SLTF_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief clear SHTF2 flag.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void I2C_ClearSHTF2(I2C_Type *pI2Cx )
+{
+    pI2Cx->SMB |= I2C_SMB_SHTF2_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief send out ACK.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE void I2C_SendAck(I2C_Type *pI2Cx )
+{
+    pI2Cx->C1 &= ~I2C_C1_TXAK_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief send out NACK.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE void I2C_SendNack(I2C_Type *pI2Cx )
+{
+    pI2Cx->C1 |= I2C_C1_TXAK_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Second I2C Address Enable.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+__STATIC_INLINE void I2C_SecondAddressEnable(I2C_Type *pI2Cx)
+{
+     pI2Cx->SMB |= I2C_SMB_SIICAEN_MASK;
+}
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void I2C_Init(I2C_Type *pI2Cx,I2C_ConfigPtr pI2CConfig);
+uint8_t I2C_Start(I2C_Type *pI2Cx);
+uint8_t I2C_Stop(I2C_Type *pI2Cx);
+uint8_t I2C_RepeatStart(I2C_Type *pI2Cx);
+uint8_t I2C_IsTxMode(I2C_Type *pI2Cx );
+uint8_t I2C_IsBusy(I2C_Type *pI2Cx );
+uint8_t I2C_IsReceivedAck(I2C_Type *pI2Cx );
+uint8_t I2C_IsMasterMode(I2C_Type *pI2Cx );
+void I2C_ClearSHTF2(I2C_Type *pI2Cx );
+void I2C_ClearSLTF(I2C_Type *pI2Cx );
+uint8_t I2C_IsSMB_SHTF2(I2C_Type *pI2Cx );
+uint8_t I2C_IsSMB_SLTF(I2C_Type *pI2Cx );
+void I2C_TxEnable(I2C_Type *pI2Cx);
+void I2C_RxEnable(I2C_Type *pI2Cx);
+void I2C_IntEnable(I2C_Type *pI2Cx);
+void I2C_IntDisable(I2C_Type *pI2Cx);
+void I2C_SetBaudRate(I2C_Type *pI2Cx,uint32_t u32Bps);
+void I2C_SetSlaveAddress(I2C_Type *pI2Cx,uint16_t u16SlaveAddress);
+void I2C_GeneralCallEnable(I2C_Type *pI2Cx);
+void I2C_SMBusAlertEnable(I2C_Type *pI2Cx);
+void I2C_RangeAddressEnable(I2C_Type *pI2Cx);
+void I2C_SHTF2IntEnable(I2C_Type *pI2Cx);
+void I2C_ETMeoutCounterClockSelect(I2C_Type *pI2Cx, uint8_t u8Clock);
+void I2C_SetSCLLowETMeout(I2C_Type *pI2Cx, uint16_t u16ETMeout);
+uint8_t I2C_GetStatus(I2C_Type *pI2Cx);
+void I2C_ClearStatus(I2C_Type *pI2Cx, uint8_t u8ClearFlag);
+void I2C_SendAck(I2C_Type *pI2Cx );
+void I2C_SendNack(I2C_Type *pI2Cx );
+void I2C_SecondAddressEnable(I2C_Type *pI2Cx);
+void I2C_ClearStatus(I2C_Type *pI2Cx, uint8_t u8ClearFlag);
+void I2C_WriteDataReg(I2C_Type *pI2Cx, uint8_t u8DataBuff);
+uint8_t I2C_ReadDataReg(I2C_Type *pI2Cx );
+void I2C_Deinit(I2C_Type *pI2Cx);
+uint8_t I2C_WriteOneByte(I2C_Type *pI2Cx, uint8_t u8WrBuff);
+uint8_t I2C_ReadOneByte(I2C_Type *pI2Cx, uint8_t *pRdBuff, uint8_t u8Ack);
+uint8_t I2C_MasterSendWait(I2C_Type *pI2Cx,uint16_t u16SlaveAddress,uint8_t *pWrBuff,uint32_t u32Length);
+uint8_t I2C_MasterReadWait(I2C_Type *pI2Cx,uint16_t u16SlaveAddress,uint8_t *pRdBuff,uint32_t u32Length);
+void I2C0_SetCallBack( I2C_CallbackType pCallBack );
+void I2C1_SetCallBack( I2C_CallbackType pCallBack );
+
+/*! @} End of i2c_bus_state_list                                             						*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif //
+
+

bsp/nv32f100x/lib/inc/ics.h

@@ -0,0 +1,347 @@
+/******************************************************************************
+*
+* @brief  ICS 驱动头文件.  
+*
+******************************************************************************/
+#ifndef ICS_H_
+#define ICS_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "common.h"
+/****************************************************************************!
+ * @brief 时钟模式常量定义
+ *
+ ***************************************************************************/
+enum
+{
+    ICS_CLK_MODE_FEI = 1,       /*!< FEI 模式 */
+    ICS_CLK_MODE_FEE,           /*!< FEE 模式 */
+    ICS_CLK_MODE_FEE_OSC,       /*!< FEE 模式 OSC输出时钟源选择来自EXTAL引脚的外部时钟源 */    
+    ICS_CLK_MODE_FBE,           /*!< FBE 模式 */
+    ICS_CLK_MODE_FBE_OSC,       /*!< FBE 模式 OSC输出时钟源选择来自EXTAL引脚的外部时钟源  */    
+    ICS_CLK_MODE_FBI,           /*!< FBI 模式 */
+    ICS_CLK_MODE_FBILP,         /*!< FBILP 模式 */    
+    ICS_CLK_MODE_FBELP,         /*!< FBELP 模式 */        
+};			
+  
+/*****************************************************************************//*!
+   *
+   * @brief 将时钟模式从当前模式切换到另一个时钟模式.
+   *
+   *  时钟模式宏观定义如下:
+   *      FEI, FBI, FEE, FBE, FBILP, FBELP, FEE_OSC, FBE_OSC
+   *   注：FEE_OSC, FBE_OSC 不能用作当前时钟模式. 当前时钟模式和要切换到的时钟模式组合如下： 
+   *    < 当前时钟模式，要切换到的时钟模式>     
+   *    <FEI,FEE>, <FEI,FBI>, <FEI,FBE>, <FEI,FBE_OSC>, <FEI,FEE_OSC>, <FEE,FEI>,
+   *    <FEE,FBI>, <FEE,FBE>, <FBI,FBE>, <FBI,FEE>, <FBI,FBILP>, <FBI,FEI>,
+   *    <FBE,FBI>, <FBE,FEE>, <FBE,FEI>, <FBE,FBELP>, <FBELP,FBE>, <FBILP,FBI>.
+   *    
+   * @param[in] CurMode   当前时钟模式
+   * @param[in] NewMode   要切换到的时钟模式
+   * @param[in] clkFreq     参考时钟频率
+   *       
+   * @return none
+   * @warning   FEE_OSC, FBE_OSC 不能用作当前时钟模式. 
+   *
+   *****************************************************************************/
+
+#define ICS_SwitchMode(CurMode, NewMode, clkFreq)   CurMode##_to_##NewMode(clkFreq)
+       
+ 
+/******************************************************************************
+* 定义 OSC 配置结构体
+*
+*******************************************************************************/
+typedef struct
+{
+	uint8_t bRange      : 1;        /*!< 1: 高频范围, 0: 低频范围 */
+	uint8_t bGain       : 1;        /*!< 1: 高增益, 0:低增益 */
+	uint8_t bEnable     : 1;        /*!< 1: 使能OSC, 0: 禁用OSC */
+	uint8_t bStopEnable : 1;        /*!< 1: 停止模式下OSC使能, 0: 停止模式下OSC禁用 */
+	uint8_t bIsCryst    : 1;        /*!< 1: OSC输出选择振荡器时钟, 0: OSC输出选择来自extal引脚的外部时钟 */
+	uint8_t bWaitInit   : 1;        /*!< 1: 等待振荡器初始化完成, 0: 不等待 */
+} OSC_ConfigType, *OSC_ConfigPtr;
+
+
+
+/******************************************************************************
+* 
+* ICS配置结构体
+*
+*******************************************************************************/
+typedef struct
+{
+   uint8_t    u8ClkMode;        /*!< 选择时钟模式*/
+   uint8_t    bLPEnable;        /*!< 低功耗模式下使能 */
+   uint32_t   u32ClkFreq;       /*!< 参考时钟频率 */  
+   OSC_ConfigType  oscConfig;   /*!< OSC 配置 */
+} ICS_ConfigType ;
+
+/*****************************************************************************//*!
+*
+* @brief 使能中断.
+*        
+* @param   none
+*
+* @return none
+* 
+* @see    ICS_DisableInt
+*****************************************************************************/
+__STATIC_INLINE void ICS_EnableInt(void)
+{
+    ICS->C4 |= (ICS_C4_LOLIE_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 禁用中断
+*        
+* @param   none
+*
+* @return none
+*
+* @see    ICS_EnableInt
+*****************************************************************************/
+__STATIC_INLINE void ICS_DisableInt(void)
+{
+    ICS->C4 &= ~(ICS_C4_LOLIE_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 使能时钟监控
+*        
+* @param   none
+*
+* @return none
+*
+* @see    ICS_DisableClockMonitor
+*****************************************************************************/
+__STATIC_INLINE void ICS_EnableClockMonitor(void)
+{
+    ICS->C4 |= (ICS_C4_CME_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 禁用时钟监控
+*        
+* @param   none
+*
+* @return none
+*
+* @see    ICS_EnableClockMonitor
+*****************************************************************************/
+__STATIC_INLINE void ICS_DisableClockMonitor(void)
+{
+    ICS->C4 &= ~(ICS_C4_CME_MASK);    
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief 设置ICS输出时钟源分频
+   *        
+   * @param[in] busDivide   -- 分频值
+   *
+   * @return  depends on commands
+   *****************************************************************************/
+__STATIC_INLINE void ICS_SetBusDivider(uint8_t u8BusDivide)
+{
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(u8BusDivide);
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief 使能OSC
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_Enable(void)
+{
+    OSC->CR |= (OSC_CR_OSCEN_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 禁用OSC
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_Disable(void)
+{
+    OSC->CR &= ~(OSC_CR_OSCEN_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 设置OSC模块的频率范围为低频范围
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_SetLowRange(void)
+{
+    OSC->CR &= ~(OSC_CR_RANGE_MASK);    
+}
+
+/*!***************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+*
+* @brief 设置OSC模块的频率范围为高频范围
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_SetHighRange(void)
+{
+    OSC->CR |= (OSC_CR_RANGE_MASK);    
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief 设置OSC的工作模式为高增益模式
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_SetHighGain(void)
+{
+    OSC->CR |= (OSC_CR_HGO_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 设置OSC的工作模式为低功耗模式
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_SetLowGain(void)
+{
+    OSC->CR &= ~(OSC_CR_HGO_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 选择OSC模块的输出时钟源为振荡器时钟源
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_SelectCrystal(void)
+{
+    OSC->CR |= (OSC_CR_OSCOS_MASK);    
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief OSC输出选择来自extal引脚的外部时钟 
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_SelectClock(void)
+{
+    OSC->CR &= ~(OSC_CR_OSCOS_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 在停止模式下OSC模块使能
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_ActiveInStop(void)
+{
+    OSC->CR |= (OSC_CR_OSCSTEN_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief 在停止模式下OSC模块禁用
+*        
+* @param   none
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void OSC_InactiveInStop(void)
+{
+    OSC->CR &= ~(OSC_CR_OSCSTEN_MASK);    
+}
+
+/******************************************************************************/
+
+void ICS_Init(ICS_ConfigType *pConfig);
+void ICS_DeInit(void);
+void ICS_SetClkDivider(uint32_t u32ClkFreqKHz);
+void ICS_Trim(uint16 u16TrimValue);
+void OSC_Init(OSC_ConfigType *pConfig);
+void OSC_DeInit(void);
+
+/************** 内联函数 ******************/
+void ICS_DisableClockMonitor(void);
+void ICS_DisableInt(void);
+void ICS_EnableClockMonitor(void);
+void ICS_EnableInt(void);
+void ICS_SetBusDivider(uint8_t u8BusDivide);
+void OSC_ActiveInStop(void);
+void OSC_Enable(void);
+void OSC_Disable(void);
+void OSC_InactiveInStop(void);
+void OSC_SelectClock(void);
+void OSC_SelectCrystal(void);
+void OSC_SetHighGain(void);
+void OSC_SetHighRange(void);
+void OSC_SetLowGain(void);
+void OSC_SetLowRange(void);
+
+/* do not touch the following functions */
+void FEI_to_FEE(ICS_ConfigType *pConfig);
+void FEI_to_FBI(ICS_ConfigType *pConfig);
+void FEI_to_FBE(ICS_ConfigType *pConfig);
+void FEE_to_FBI(ICS_ConfigType *pConfig);
+void FEE_to_FEI(ICS_ConfigType *pConfig);
+void FEE_to_FBE(ICS_ConfigType *pConfig);
+void FBE_to_FEE(ICS_ConfigType *pConfig);
+void FBE_to_FEI(ICS_ConfigType *pConfig);
+void FBE_to_FBI(ICS_ConfigType *pConfig);
+void FBE_to_FBELP(ICS_ConfigType *pConfig);
+void FBI_to_FEI(ICS_ConfigType *pConfig);
+void FBI_to_FBE(ICS_ConfigType *pConfig);
+void FBI_to_FEE(ICS_ConfigType *pConfig);
+void FBI_to_FBILP(ICS_ConfigType *pConfig);
+void FBILP_to_FBI(ICS_ConfigType *pConfig);
+void FBELP_to_FBE(ICS_ConfigType *pConfig);
+void FEI_to_FBE_OSC(ICS_ConfigType *pConfig);
+void FEI_to_FEE_OSC(ICS_ConfigType *pConfig);
+#ifdef __cplusplus
+}
+#endif
+#endif 

bsp/nv32f100x/lib/inc/kbi.h

@@ -0,0 +1,428 @@
+/******************************************************************************
+**
+* @brief header file for KBI. 
+*
+*******************************************************************************
+*
+* provide APIs for accessing KBI
+******************************************************************************/
+#ifndef _KBI_H_
+#define _KBI_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/*!
+* @brief KBI MODE select enum.
+*
+*/
+typedef enum
+{
+    KBI_MODE_EDGE_ONLY = 0,             /*!< select  edge only mode  */         
+    KBI_MODE_EDGE_LEVEL                 /*!< select  both edge and level  mode */
+}KBI_ModeType;
+
+
+ /*!
+ * @brief KBI Edge select enum.
+ *
+ */
+typedef enum
+{
+    KBI_FALLING_EDGE_LOW_LEVEL = 0,     /*!< select falling edge and/or low level  */
+    KBI_RISING_EDGE_HIGH_LEVEL          /*!< select rising edge and/or high level  */
+}KBI_EdgeType;
+
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+
+/******************************************************************************
+* KBI module max number and port pins definition
+*
+*//*! @addtogroup kbi_macro
+* @{
+*******************************************************************************/
+#define KBI_MAX_NO              2                  /*!< max number of modules */
+
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+   #define KBI_MAX_PINS_PER_PORT   8                  /*!< max number of pins */
+#elif defined(CPU_NV32M4)
+   #define KBI_MAX_PINS_PER_PORT   32                  /*!< max number of pins */
+#endif
+/*! @} End of kbi_macro                                                    */
+
+
+/******************************************************************************
+* Types
+******************************************************************************/
+
+/*! @brief KBI_CALLBACK function declaration                                  */
+typedef void (*KBI_CallbackType)(void);                     
+/*! @} End of kbi_callback                                                    */
+
+
+
+/******************************************************************************
+* KBI pin config struct
+*
+*//*! @addtogroup kbi_pinconfigstruct
+* @{
+*******************************************************************************/
+/*!
+* @brief KBI pin enable and edge select struct.
+*
+*/
+
+typedef struct
+{
+    uint8_t     bEdge   : 1;                                /*!< edge/level select bit */
+    uint8_t     bEn     : 1;                                /*!< pin enable bit */
+    uint8_t     bRsvd   : 6;                                /*!< reserved */
+} KBI_PinConfigType;
+/*! @} End of kbi_pinconfigstruct                                             */
+
+
+/******************************************************************************
+* KBI config struct
+*
+*//*! @addtogroup kbi_configstruct
+* @{
+*******************************************************************************/
+/*!
+ * @brief KBI status and control struct.
+ *
+ */
+
+typedef struct
+{
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+    struct
+    {
+        uint8_t     bMode   : 1;                            /*!< KBI detection mode select */
+        uint8_t     bIntEn  : 1;                            /*!< KBI interrupt enable bit */
+        uint8_t     bRsvd   : 6;                            /*!< reserved */
+    } sBits;
+#elif  defined(CPU_NV32M4)
+    struct
+    {
+        uint32_t     bMode   : 1;                            /*!< KBI detection mode select */
+        uint32_t     bIntEn  : 1;                            /*!< KBI interrupt enable bit */
+        uint32_t     bRsvd2  : 2;                           /*!< reserved */
+        uint32_t     bKbspEn : 1;							  /*!<Real KBI_SP register enable*/
+		uint32_t     bRstKbsp: 1;                            /*!<Reset KBI_SP register*/
+        uint32_t     bRsvd26 : 26;                           /*!< reserved */
+    } sBits;
+#endif
+    KBI_PinConfigType   sPin[KBI_MAX_PINS_PER_PORT];
+} KBI_ConfigType, *KBI_ConfigTypePtr;
+/*! @} End of kbi_configstruct                                                */
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+/*!
+ * inline functions
+ */
+/******************************************************************************
+* KBI api list
+*
+*//*! @addtogroup kbi_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+*
+* @brief set detect falling edge only.
+*        
+* @param[in]   pKBI          pointer to KBI module.
+* @param[in]   PinMasks      indicate pin numbers.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_DetectRisingEdge.
+*
+*****************************************************************************/
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+__STATIC_INLINE  void KBI_DetectFallingEdge(KBI_Type *pKBI, uint8_t PinMasks)
+#elif defined(CPU_NV32M4)
+__STATIC_INLINE  void KBI_DetectFallingEdge(KBI_Type *pKBI, uint32_t PinMasks)
+#endif
+{
+    pKBI->SC &= ~KBI_SC_KBMOD_MASK;
+    pKBI->ES &= ~(PinMasks);
+}
+
+/*****************************************************************************//*!
+*
+* @brief set detect falling edge only.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+* @param[in]   PinMasks     indicate pin numbers.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_DetectFallingEdge.
+*
+*****************************************************************************/
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+__STATIC_INLINE  void KBI_DetectRisingEdge(KBI_Type *pKBI, uint8_t PinMasks)
+#elif defined(CPU_NV32M4)
+__STATIC_INLINE  void KBI_DetectRisingEdge(KBI_Type *pKBI, uint32_t PinMasks)
+#endif
+{
+    pKBI->SC &= ~KBI_SC_KBMOD_MASK;
+    pKBI->ES |= (PinMasks);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief set detect falling edge only.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+* @param[in]   PinMasks     indicate pin number/mask.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_DetectFallingEdgeLowLevel.
+*
+*****************************************************************************/
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+__STATIC_INLINE  void KBI_DetectRisingEdgeHighLevel(KBI_Type *pKBI, uint8_t PinMasks)
+#elif defined(CPU_NV32M4)
+__STATIC_INLINE  void KBI_DetectRisingEdgeHighLevel(KBI_Type *pKBI, uint32_t PinMasks)
+#endif
+{
+    pKBI->SC |= KBI_SC_KBMOD_MASK;
+    pKBI->ES |= (PinMasks);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief set detect falling edge only.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+* @param[in]   PinMasks     indicate pin number/mask.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_DetectRisingEdgeHighLevel.
+*
+*****************************************************************************/
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+__STATIC_INLINE  void KBI_DetectFallingEdgeLowLevel(KBI_Type *pKBI, uint8_t PinMasks)
+#elif defined(CPU_NV32M4)
+__STATIC_INLINE  void KBI_DetectFallingEdgeLowLevel(KBI_Type *pKBI, uint32_t PinMasks)
+#endif
+{
+    pKBI->SC |= KBI_SC_KBMOD_MASK;
+    pKBI->ES &= ~(PinMasks);        
+}
+
+/*****************************************************************************//*!
+*
+* @brief enable the pin specified.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+* @param[in]   PinMasks     indicate pin number/mask.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_Disable.
+*
+*****************************************************************************/
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+__STATIC_INLINE  void KBI_Enable(KBI_Type *pKBI, uint8_t PinMasks)
+#elif defined(CPU_NV32M4)
+__STATIC_INLINE  void KBI_Enable(KBI_Type *pKBI, uint32_t PinMasks)
+#endif
+{
+    pKBI->PE |= (PinMasks);        
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable the pin specified.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+* @param[in]   PinMasks     indicate pin number/mask.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_Enable.
+*
+*****************************************************************************/
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+__STATIC_INLINE  void KBI_Disable(KBI_Type *pKBI, uint8_t PinMasks)
+#elif defined(CPU_NV32M4)
+__STATIC_INLINE  void KBI_Disable(KBI_Type *pKBI, uint32_t PinMasks)
+#endif
+{
+    pKBI->PE &= ~(PinMasks);        
+}
+
+/*****************************************************************************//*!
+*
+* @brief enable the corresponding interrupt.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+*          
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_DisableInt.
+*
+*****************************************************************************/
+__STATIC_INLINE  void KBI_EnableInt(KBI_Type *pKBI)
+{
+    pKBI->SC |= KBI_SC_KBIE_MASK;        
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief disable the corresponding interrupt.
+*        
+* @param[in]  pKBI         pointer to KBI module.
+*          
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see KBI_EnableInt.
+*
+*****************************************************************************/
+__STATIC_INLINE  void KBI_DisableInt(KBI_Type *pKBI)
+{
+    pKBI->SC &= ~KBI_SC_KBIE_MASK;        
+}
+
+/*****************************************************************************//*!
+*
+* @brief Get the corresponding status flag bits.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+*          
+* @return uint8_t.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_ClrFlags.
+*
+*****************************************************************************/
+#if defined(CPU_NV32)|| defined(CPU_NV32M3)
+__STATIC_INLINE  uint8_t KBI_GetFlags(KBI_Type *pKBI)
+#elif defined(CPU_NV32M4)
+__STATIC_INLINE  uint32_t KBI_GetFlags(KBI_Type *pKBI)
+#endif
+{
+    return (pKBI->SC & KBI_SC_KBF_MASK);        
+}
+
+/*****************************************************************************//*!
+*
+* @brief clear the corresponding status flag bits.
+*        
+* @param[in]   pKBI         pointer to KBI module
+*          
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see KBI_GetFlags.
+*
+*****************************************************************************/
+__STATIC_INLINE  void KBI_ClrFlags(KBI_Type *pKBI)
+{
+    pKBI->SC |= KBI_SC_KBACK_MASK;        
+}
+
+#if defined(CPU_NV32M4)
+/*****************************************************************************//*!
+*
+* @brief Real KBI_SP register enable.
+*        
+* @param[in]   pKBI         pointer to KBI module
+*          
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see The real ETMe value of Keyboard source pin to be read.
+*
+*****************************************************************************/
+__STATIC_INLINE  void KBI_SPEnable(KBI_Type *pKBI)
+{
+    pKBI->SC |= KBI_SC_KBSPEN_MASK;        
+}
+
+/*****************************************************************************//*!
+*
+* @brief Get KBI source pin register fields.
+*        
+* @param[in]   pKBI         pointer to KBI module.
+*          
+* @return uint32_t.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_GetSP.
+*
+*****************************************************************************/
+__STATIC_INLINE  uint32_t KBI_GetSP(KBI_Type *pKBI)
+{
+    return (pKBI->SP & KBI_SP_SP_MASK);        
+}
+
+/*****************************************************************************//*!
+*
+* @brief Reset KBI_SP register.
+*        
+* @param[in]   pKBI         pointer to KBI module
+*          
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see KBI_RstSP.
+*
+*****************************************************************************/
+__STATIC_INLINE  void KBI_RstSP(KBI_Type *pKBI)
+{
+    pKBI->SC |= KBI_SC_RSTKBSP_MASK;        
+}
+#endif
+
+/*! @} End of kbi_api_list                                                  */
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+void KBI_Init(KBI_Type *pKBI, KBI_ConfigType *pConfig);
+void KBI_SetCallback(KBI_Type *pKBI, KBI_CallbackType pfnCallback);
+
+#ifdef __cplusplus
+}
+#endif
+#endif 

bsp/nv32f100x/lib/inc/pit.h

@@ -0,0 +1,317 @@
+/******************************************************************************
+* @brief    Periodic Interrupt ETMer (PIT) driver head file. 
+*
+******************************************************************************/
+#ifndef PIT_H_
+#define PIT_H_
+#include"common.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* PIT channel number list
+*
+*//*! @addtogroup pit_channelnumber
+* @{
+*******************************************************************************/
+enum
+{
+    PIT_CHANNEL0 = 0,       /*!< PIT channel 0 */
+    PIT_CHANNEL1            /*!< PIT channel 1 */
+};
+
+/*! @} End of pit_channelnumber                                               */
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+
+/******************************************************************************
+* Types
+******************************************************************************/
+
+/*
+ * Callback type
+ */
+
+/******************************************************************************
+* PIT callback function declaration
+*
+*//*! @addtogroup pit_callback
+* @{
+*******************************************************************************/
+typedef void (*PIT_CallbackType)(void);             /*!< PIT callback type */
+
+/*! @} End of pit_callback                                                    */
+
+/* PIT configuration structure 
+ */  
+/*!
+ * @brief PIT configuration type.
+ *
+ */
+typedef struct
+{   
+    uint8_t bFreeze         : 1;    /*!< 1: stop in debug mode, 0: run in debug mode */
+    uint8_t bModuleDis      : 1;    /*!< 1: PIT module is disable, 0: PIT module is enable */    
+    uint8_t bReserved0      : 1;    /*!< reserved bit */ 
+    uint8_t bReserved1      : 5;    /*!< reserved bit */ 
+    uint8_t bETMerEn        : 1;    /*!< 1: channel ETMer is enable, 0: channel ETMer is disable */ 
+    uint8_t bInterruptEn    : 1;    /*!< 1: channel ETMer interrupt is enable, 0: channel ETMer interrupt is disable */ 
+    uint8_t bChainMode      : 1;    /*!< 1: chain mode is enable, 0: chain mode is disable */ 
+    uint8_t bReserved2      : 5;    /*!< reserved bit */ 
+    uint8_t bFlag           : 1;    /*!< 1: flag is set,and write 1 to clear flag, 0: no flag is set */
+    uint8_t bReserved3      : 7;    /*!< reserved bit */   
+    uint32_t u32LoadValue      ;    /*!< 32-bit channel load value */  
+} PIT_ConfigType, *PIT_ConfigPtr; 
+
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+
+/*!
+ * inline functions
+ */
+
+/******************************************************************************
+* PIT API list
+*
+*//*! @addtogroup pit_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief enable pit module.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_Enable(void)
+{
+
+    PIT->MCR &= ~PIT_MCR_MDIS_MASK; 
+    
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief disable pit module.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_Disable(void)
+{
+
+    PIT->MCR |= PIT_MCR_MDIS_MASK; 
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief pit ETMers are stopped in debug mode.
+*        
+* @param  none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_SetDebugFreeze(void)
+{
+
+    PIT->MCR |= PIT_MCR_FRZ_MASK;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief pit ETMers are running in debug mode.
+*        
+* @param  none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_SetDebugOn(void)
+{
+
+    PIT->MCR &= ~PIT_MCR_FRZ_MASK;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief enable pit channel ETMer.
+*        
+* @param[in]   u8Channel.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_ChannelEnable(uint8_t u8Channel)
+
+{
+
+    PIT->CHANNEL[u8Channel].TCTRL |= PIT_TCTRL_TEN_MASK; 
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief disable pit channel ETMer.
+*        
+* @param[in]   u8Channel.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_ChannelDisable(uint8_t u8Channel)
+{
+
+    PIT->CHANNEL[u8Channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; 
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief enable pit channel ETMer interrupt.
+*        
+* @param[in]  u8Channel.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_ChannelEnableInt(uint8_t u8Channel)
+
+{
+
+    PIT->CHANNEL[u8Channel].TCTRL |= PIT_TCTRL_TIE_MASK; 
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief disable pit channel ETMer interrupt .
+*        
+* @param[in]   u8Channel.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_ChannelDisableInt(uint8_t u8Channel)
+
+{
+
+    PIT->CHANNEL[u8Channel].TCTRL &= ~PIT_TCTRL_TIE_MASK; 
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief  enable pit channel ETMer chain mode.
+*        
+* @param[in]   u8Channel.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_ChannelEnableChain(uint8_t u8Channel)
+{
+    PIT->CHANNEL[u8Channel].TCTRL |= PIT_TCTRL_CHN_MASK;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief  disable pit channel ETMer chain mode.
+*        
+* @param[in]   u8Channel.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_ChannelDisableChain(uint8_t u8Channel)
+
+{
+    PIT->CHANNEL[u8Channel].TCTRL &= ~PIT_TCTRL_CHN_MASK;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief get pit channel ETMer interrrupt flag.
+*        
+* @param[in]   u8Channel.
+*
+* @return bflag.
+*
+* @ Pass/ Fail criteria: none
+
+*****************************************************************************/
+__STATIC_INLINE uint8_t PIT_ChannelGetFlags(uint8_t u8Channel)
+
+{
+    uint8_t bflag;  
+    
+    bflag = (PIT->CHANNEL[u8Channel].TFLG & PIT_TFLG_TIF_MASK);    
+    
+    return bflag;
+    
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief clear pit channel ETMer interrrupt flag.
+*        
+* @param[in] u8Channel
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void PIT_ChannelClrFlags(uint8_t u8Channel)
+{
+    PIT->CHANNEL[u8Channel].TFLG |= PIT_TFLG_TIF_MASK;       
+}
+
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void PIT_Init(uint8_t u8Channel_No, PIT_ConfigType *pConfig);
+void PIT_SetLoadVal(uint8_t u8Channel, uint32_t u32loadvalue);
+void PIT_SetCallback(uint8_t u8Channel_No, PIT_CallbackType pfnCallback);
+void PIT_DeInit(void);
+/*! @} End of pit_api_list                                                   */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* PIT_H_ */

bsp/nv32f100x/lib/inc/pmc.h

@@ -0,0 +1,373 @@
+/******************************************************************************
+*
+* @brief header file for PMC. 
+*
+*******************************************************************************
+*
+* provide APIs for accessing PMC
+******************************************************************************/
+#ifndef PMC_H_
+#define PMC_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+/******************************************************************************
+* PMC system mode definition
+*
+*//*! @addtogroup pmc_sysmode
+* @{
+*******************************************************************************/
+#define PmcModeRun     0                     /*!< run mode */
+#define PmcModeWait    1                     /*!< wait mode */
+#define PmcModeStop4   2                     /*!< stop4 mode */
+#define PmcModeStop3   3                     /*!< stop3 mode */
+/*! @} End of pmc_sysmode                                                     */
+
+/******************************************************************************
+* PMC LVD and LVW voltage definition
+*
+*//*! @addtogroup pmc_voltageselect
+* @{
+*******************************************************************************/
+#define PmcLVDTrip_Low   0                    /*!< LVD low trip point */
+#define PmcLVDTrip_High  1                     /*!< LVD high trip point  */
+
+#define PmcLVWTrip_Low   0                     /*!< LVW low trip point */
+#define PmcLVWTrip_Mid1  1                     /*!< LVW mid1 trip point */
+#define PmcLVWTrip_Mid2  2                     /*!< LVW mid2 trip point */
+#define PmcLVWTrip_High  3                     /*!< LVW high trip point */
+/*! @} End of pmc_voltageselect                                               */
+
+
+/******************************************************************************
+* Types
+******************************************************************************/
+
+/******************************************************************************
+* PMC control  struct
+*
+*//*! @addtogroup pmc_ctrlstruct
+* @{
+*******************************************************************************/
+/*!
+ * @brief PMC Control Structure Type.
+ *
+ */
+
+typedef union 
+{
+   uint8_t byte;						  /*!< byte field of union type */
+   struct 
+   {     
+       uint8_t bBandgapEn        :1;      /*!< bandgap enable */
+       uint8_t bBandgapDrv       :1;      /*!< bandgap drive select */
+       uint8_t bLvdEn            :1;      /*!< LVD enable */
+       uint8_t bLvdStopEn        :1;      /*!< LVD enable in stop mode */
+       uint8_t bLvdRstEn         :1;      /*!< reset enable when VLD evvent */
+       uint8_t bLvwIrqEn         :1;      /*!< LVW int enable */
+       uint8_t bLvwAck           :1;      /*!< LVW acknowledge */
+       uint8_t bLvwFlag          :1;      /*!< LVW flag */
+   }bits; 								  /*!< bitfield of union type */
+}PMC_Ctrl1Type, *PMC_Ctrl1Ptr;		  /*!< PMC control1 reg structure */
+/*! @} End of pmc_ctrlstruct                                                  */
+
+/******************************************************************************
+* PMC control-- voltage select type.
+*
+*//*! @addtogroup pmc_voltselectstruct
+* @{
+*******************************************************************************/
+/*!
+ * @brief PMC control-- voltage select type.
+ *
+ */
+typedef union 
+{
+   uint8_t byte;						   /*!< byte field of union type */
+   struct 
+   {     
+       uint8_t           :4;               /*!< none */  
+       uint8_t bLVWV     :2;               /*!< LVW voltage select */  
+       uint8_t bLVDV     :1;               /*!< LVD voltage select */  
+       uint8_t           :1;               /*!< none */                 
+   }bits;  								   /*!< bitfield of union type */
+}PMC_Ctrl2Type, *PMC_Ctrl2Ptr;		   /*!< PMC control2 reg structure */
+/*! @} End of pmc_voltselectstruct                                            */
+
+/******************************************************************************
+* PMC configrue type.
+*
+*//*! @addtogroup pmc_configstruct
+* @{
+*******************************************************************************/
+/*!
+ * @brief PMC configrue type.
+ *
+ */
+
+typedef struct 
+{
+    PMC_Ctrl1Type    sCtrlstatus;          /*!< PMC control and status */  
+    PMC_Ctrl2Type    sDetectVoltSelect;    /*!< LVW and LVW voltage select */  
+}PMC_ConfigType, *PMC_ConfigPtr;		   /*!< PMC configuration structure */
+/*! @} End of pmc_configstruct                                            */  
+
+
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/*!
+ * inline functions
+ */
+/******************************************************************************
+* PMC api list.
+*
+*//*! @addtogroup pmc_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+*
+* @brief  enable LVD events during stop mode.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_DisableLVDInStopMode.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_EnableLVDInStopMode(PMC_Type *pPMC)
+{
+    pPMC->SPMSC1 |= PMC_SPMSC1_LVDSE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable LVD events during stop mode.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_EnableLVDInStopMode.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_DisableLVDInStopMode(PMC_Type *pPMC)
+{
+    pPMC->SPMSC1 &= ~PMC_SPMSC1_LVDSE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  enable LVD events to generate a hardware reset,  note: write once.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_DisableLVDRst.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_EnableLVDRst(PMC_Type *pPMC)
+{
+    pPMC->SPMSC1 |= PMC_SPMSC1_LVDRE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable LVD events to generate a hardware reset,  note: write once.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_EnableLVDRst.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_DisableLVDRst(PMC_Type *pPMC)
+{
+    pPMC->SPMSC1 &= ~PMC_SPMSC1_LVDRE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  enable low-voltage detect logic,  note: write once.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_DisableLVD.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_EnableLVD(PMC_Type *pPMC)
+{
+    pPMC->SPMSC1 |= PMC_SPMSC1_LVDE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  disable low-voltage detect logic,  note: write once
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+* @see PMC_EnableLVD.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_DisableLVD(PMC_Type *pPMC)
+{
+    pPMC->SPMSC1 &= ~PMC_SPMSC1_LVDE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set the low-voltage detect trip point voltage, note: write once.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+* @param[in]  Trippoint         LVD trip point voltage,0~1.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_SetLVWTripVolt.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_SetLVDTripVolt(PMC_Type *pPMC, uint8_t Trippoint)
+{
+    if(Trippoint)
+        pPMC->SPMSC2 |= PMC_SPMSC2_LVDV_MASK;
+    else
+        pPMC->SPMSC2 &= ~PMC_SPMSC2_LVDV_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set the low-voltage warning (LVW) trip point voltage.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+* @param[in]  Trippoint         LVW trip point voltage,0~3.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_SetLVDTripVolt.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_SetLVWTripVolt(PMC_Type *pPMC, uint8_t Trippoint)
+{
+    pPMC->SPMSC2 &= ~PMC_SPMSC2_LVWV_MASK;
+    pPMC->SPMSC2 |= PMC_SPMSC2_LVWV(Trippoint);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  Enable hardware interrupt requests for LVWF.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_DisableLVWInterrupt.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_EnableLVWInterrupt(PMC_Type *pPMC)
+{
+   pPMC->SPMSC1 |= PMC_SPMSC1_LVWIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  Disable hardware interrupt requests for LVWF.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_EnableLVWInterrupt.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_DisableLVWInterrupt(PMC_Type *pPMC)
+{
+   pPMC->SPMSC1 &= ~PMC_SPMSC1_LVWIE_MASK;
+}
+
+/*****************************************************************************//*!
+*
+* @brief  get the lvw warning flag.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return uint8_t lvw warning flag.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_ClrLVWFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE uint8_t PMC_GetLVWFlag(PMC_Type *pPMC)
+{
+   return (pPMC->SPMSC1 & PMC_SPMSC1_LVWF_MASK);
+}
+
+/*****************************************************************************//*!
+*
+* @brief  clear the lvw warning flag.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_GetLVWFlag.
+*
+*****************************************************************************/
+__STATIC_INLINE void PMC_ClrLVWFlag(PMC_Type *pPMC)
+{
+   pPMC->SPMSC1 |= PMC_SPMSC1_LVWACK_MASK;
+}
+
+/*! @} End of pmc_api_list                                                    */
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+void PMC_Init(PMC_Type *pPMC, PMC_ConfigType *pPMC_Config);
+void PMC_DeInit(PMC_Type *pPMC);
+void PMC_SetMode(PMC_Type *pPMC,uint8_t u8PmcMode);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* PMC_H_ */

bsp/nv32f100x/lib/inc/rtc.h

@@ -0,0 +1,224 @@
+/******************************************************************************
+*
+* @brief    Real-ETMe counter (RTC) driver head file.  
+*
+******************************************************************************/
+#ifndef RTC_H_
+#define RTC_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+
+/******************************************************************************
+* RTC control bit definition
+*
+*//*! @addtogroup rtc_controlbit
+* @{
+*******************************************************************************/
+
+#define RTC_OUTPUT_ENABLE           1	/*!< enable RTCO pin  */ 
+#define RTC_INTERRUPT_ENABLE        1	/*!< enable RTC interrupt  */ 
+#define RTC_CLKSRC_EXTERNAL         0	/*!< select external clock as RTC clock source  */
+#define RTC_CLKSRC_1KHZ             1	/*!< select LPO as RTC clock source  */
+#define RTC_CLKSRC_IREF             2	/*!< select internal reference clock as RTC clock source  */
+#define RTC_CLKSRC_BUS              3	/*!< select bus clock as RTC clock source  */
+#define RTC_CLK_PRESCALER_128       1	/*!< presalcer is 1 or 128 according to RTCLKS bits */
+#define RTC_CLK_PRESCALER_256       2	/*!< presalcer is 2 or 256 according to RTCLKS bits */
+#define RTC_CLK_PRESCALER_512       3	/*!< presalcer is 4 or 512 according to RTCLKS bits */
+#define RTC_CLK_PRESCALER_1024      4	/*!< presalcer is 8 or 1024 according to RTCLKS bits */
+#define RTC_CLK_PRESCALER_2048      5	/*!< presalcer is 16 or 2048 according to RTCLKS bits */
+#define RTC_CLK_PRESCALER_100       6	/*!< presalcer is 32 or 100 according to RTCLKS bits */
+#define RTC_CLK_PRESCALER_1000      7	/*!< presalcer is 64 or 1000 according to RTCLKS bits */
+
+
+/*! @} End of rtc_controlbit                                                  */
+
+/******************************************************************************
+* Types
+******************************************************************************/
+
+/*
+ * Callback type
+ */
+
+/******************************************************************************
+* RTC callback function declaration
+*
+*//*! @addtogroup rtc_callback
+* @{
+*******************************************************************************/
+
+/*!
+ * @brief RTC Callback type.
+ *
+ */
+
+typedef void (*RTC_CallbackType)(void);
+
+/*! @} End of rtc_callback                                                    */
+
+
+/* RTC configuration structure 
+ */  
+/*!
+ * @brief RTC configuration type.
+ *
+ */
+typedef struct
+{   
+    uint16_t bReserved                  : 4;    /*!< reserved */     
+    uint16_t bRTCOut                    : 1;    /*!< 1: RTCO pin is enable, 0: RTCO pin is disable */
+    uint16_t bReserved1                 : 1;    /*!< reserved */ 
+    uint16_t bInterruptEn               : 1;    /*!< 1: RTC interrupt is enable, 0: RTC interrupt is disable */
+    uint16_t bFlag                      : 1;    /*!< 1: RTC flag is set, 0: RTC flag is not set */   
+    uint16_t bClockPresaler             : 3;    /*!< 1: RTC presclaer, from 0x0 to 0x7 */    
+    uint16_t bReserved2                 : 3;    /*!< reserved */ 
+    uint16_t bClockSource               : 2;    /*!< RTC clock source selection from 0x0 to 0x3 */
+    uint16_t u16ModuloValue                ;    /*!< 16-bit rtc modulo value */
+} RTC_ConfigType, *RTC_ConfigPtr; 
+
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/*!
+ * inline functions
+ */
+
+/******************************************************************************
+* RTC API list
+*
+*//*! @addtogroup rtc_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief enable rtc interrupt.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void RTC_EnableInt(void)
+{
+    RTC->SC |= RTC_SC_RTIE_MASK;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief disable rtc interrupt.
+*        
+* @param   none
+*
+* @return non
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void RTC_DisableInt(void)
+{
+    RTC->SC &= ~RTC_SC_RTIE_MASK;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief set rtc modulo value.
+*        
+* @param[in]   u16Mod_Value
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void RTC_SetModulo(uint16_t u16Mod_Value)
+{
+ 
+    RTC->MOD = u16Mod_Value;
+}
+
+/*****************************************************************************//*!
+*
+* @brief set rtc clock source and presalcer.
+*        
+* @param[in]   u16Clock_Number clock source number
+* @param[in]   u16Presalcer prescaler value
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void RTC_SetClock(uint16_t u16Clock_Number, uint16_t u16Presalcer)
+{
+    uint32_t u32rtc_sc;
+        
+    u32rtc_sc  = RTC->SC; 
+    u32rtc_sc &= ~(RTC_SC_RTCLKS_MASK | RTC_SC_RTCPS_MASK);
+    u32rtc_sc |= RTC_SC_RTCLKS(u16Clock_Number) | RTC_SC_RTCPS(u16Presalcer); 
+    RTC->SC   = u32rtc_sc;
+}
+
+/*****************************************************************************//*!
+*
+* @brief get rtc flag bit.
+*        
+* @param  none 
+*
+* @return bflag.
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t RTC_GetFlags(void)
+{
+  uint8_t bflag;
+  
+  bflag = RTC->SC & RTC_SC_RTIF_MASK; 
+  
+  return bflag;  
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief clear rtc flag bit.
+*        
+* @param  none 
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void RTC_ClrFlags(void)
+{
+    RTC->SC |= RTC_SC_RTIF_MASK; 
+}
+
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void RTC_Init(RTC_ConfigType *pConfig);
+void RTC_SetCallback(RTC_CallbackType pfnCallback);
+void RTC_DeInit(void);
+
+/*! @} End of rtc_api_list                                                   */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* RTC_H_ */

bsp/nv32f100x/lib/inc/sim.h

@@ -0,0 +1,2507 @@
+/******************************************************************************
+*
+* @brief header file for SIM utilities. 
+*
+*******************************************************************************
+*
+* provide APIs for accessing SIM
+******************************************************************************/
+
+#ifndef SIM_H_
+#define SIM_H_
+
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* define SIM device ID types
+*
+*//*! @addtogroup sim_id_types
+* @{
+*******************************************************************************/
+
+typedef enum {
+    ID_TYPE_FAMID,                  /*!< device Family ID */
+    ID_TYPE_SUBFAMID,               /*!< device Subfamily ID */ 
+    ID_TYPE_REVID,                  /*!< device Revision ID */
+    ID_TYPE_PINID                   /*!< device Pin ID (Pin count) */
+} IDType;
+/*! @} End of sim_id_types                                                    					*/
+
+/******************************************************************************
+* Macros
+******************************************************************************/ 
+
+/******************************************************************************
+* Types
+******************************************************************************/
+    
+/* SIM configuration structure 
+ */ 
+ 
+/******************************************************************************
+* define SIM configuration structure
+*
+*//*! @addtogroup sim_config_type
+* @{
+*******************************************************************************/
+
+/*!
+ * @brief SIM configuration structure.
+ *
+ */
+#if defined(CPU_NV32)
+typedef struct{
+    struct{
+        uint32_t bEnableCLKOUT  : 1;        /*!< 1: enable , 0: disable */
+        uint32_t bTXDME         : 1;        /*!< 1: enable TXDME, 0: disable */
+        uint32_t bETMSYNC       : 1;        /*!< 1: enable ETM SYNC, 0: no sync */
+        uint32_t bRXDFE         : 1;        /*!< 1: enable RXD filter, 0: no filter */
+        uint32_t bRXDCE         : 1;        /*!< 1: enable RXD capture, 0: no capture */
+        uint32_t bACIC          : 1;        /*!< 1: ACMP0 to ETM1 channel0 connection, 0: no connection */
+        uint32_t bRTCC          : 1;        /*!< 1: RTC overflow connected to ETM1 channel1, 0: no connection */
+        uint32_t u8ADHWT        : 2;        /*!< ADC h/w trigger source selection */
+        uint32_t bDisableSWD    : 1;        /*!< 1: disable SWD, 0: enable */
+        uint32_t bDisableRESET  : 1;        /*!< 1: disable RESET pin, 0: enable */
+        uint32_t bDisableNMI    : 1;        /*!< 1: disable NMI pin, 0: enable */
+        uint32_t bBusDiv        : 1;        /*!< bus divider BUSDIV value */
+    } sBits;
+    uint8_t     u8Delay;                /*!< delay value */
+    uint8_t     u8BusRef;               /*!< bus reference */
+    uint32_t    u32PinSel;              /*!< pin select reg value */
+    uint32_t    u32SCGC;                /*!< clock gating value register */   
+} SIM_ConfigType, *SIM_ConfigPtr; /*!< sim configuration structure type */
+#elif defined(CPU_NV32M3)
+typedef struct{
+    struct{
+        uint32_t bEnableCLKOUT  : 1;        /*!< 1: enable , 0: disable */
+        uint32_t bTXDME         : 1;        /*!< 1: enable TXDME, 0: disable */
+        uint32_t bETMSYNC       : 1;        /*!< 1: enable ETM SYNC, 0: no sync */
+        uint32_t bRXDCE         : 1;        /*!< 1: enable RXD capture, 0: no capture */
+        uint32_t bRXDFE         : 2;        /*!< 1: enable RXD filter, 0: no filter */
+        uint32_t u8ADHWT        : 3;        /*!< ADC h/w trigger source selection */
+        uint32_t bETMIC         : 2;        /*!< ETM0CH0 input capture source selection */
+        uint32_t bACTRG         : 1;        /*!< ACMP Trigger ETM2 selection*/
+        uint32_t bDisableSWD    : 1;        /*!< 1: disable SWD, 0: enable */
+        uint32_t bDisableRESET  : 1;        /*!< 1: disable RESET pin, 0: enable */
+        uint32_t bDisableNMI    : 1;        /*!< 1: disable NMI pin, 0: enable */
+    } sBits;
+    uint8_t     u8Delay;                /*!< delay value */
+    uint8_t     u8BusRef;               /*!< bus reference */
+    uint32_t    u32PinSel;              /*!< pin select reg value */
+    uint32_t    u32SCGC;                /*!< clock gating value register */ 
+    uint32_t    u32CLKDIV;              /*!< clock divider CLKDIV value */   
+} SIM_ConfigType, *SIM_ConfigPtr; /*!< sim configuration structure type */
+#elif defined(CPU_NV32M4)
+typedef struct{
+    struct{
+        uint32_t bEnableCLKOUT  : 1;        /*!< 1: enable , 0: disable */
+        uint32_t bTXDME         : 1;        /*!< 1: enable TXDME, 0: disable */
+        uint32_t bETMSYNC       : 1;        /*!< 1: enable ETM SYNC, 0: no sync */
+        uint32_t bRXDCE         : 1;        /*!< 1: enable RXD capture, 0: no capture */
+        uint32_t bRXDFE         : 2;        /*!< 1: enable RXD filter, 0: no filter */
+        uint32_t u8ADHWT        : 3;        /*!< ADC h/w trigger source selection */
+        uint32_t bACTRG         : 1;        /*!< ACMP Trigger ETM2 selection*/
+        uint32_t bDisableSWD    : 1;        /*!< 1: disable SWD, 0: enable */
+        uint32_t bDisableRESET  : 1;        /*!< 1: disable RESET pin, 0: enable */
+        uint32_t bDisableNMI    : 1;        /*!< 1: disable NMI pin, 0: enable */
+    } sBits;
+    uint8_t     u8Delay;                /*!< delay value */
+    uint8_t     u8BusRef;               /*!< bus reference */
+    uint32_t    u32PinSel;              /*!< pin select reg value */
+    uint32_t    u32SCGC;                /*!< clock gating value register */ 
+    uint32_t    u32CLKDIV;              /*!< clock divider CLKDIV value */   
+} SIM_ConfigType, *SIM_ConfigPtr; /*!< sim configuration structure type */
+#endif
+/*! @} End of sim_config_type                                                    					*/
+  
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+/******************************************************************************
+* define SIM API list
+*
+*//*! @addtogroup sim_api_list
+* @{
+*******************************************************************************/
+#if defined(CPU_NV32)
+/*****************************************************************************//*!
+*
+* @brief delay ETM2 triggering ADC for u8Delay bus clock output divide. 
+*        
+* @param[in]   u8Delay     delay value of Bus clock output divide.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DelayETM2Trig2ADC(uint8_t u8Delay)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_DELAY_MASK)) | SIM_SOPT_DELAY(u8Delay);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable clock output.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see  SIM_DisableClockOutput
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableClockOutput(void)
+{
+    SIM->SOPT |= (SIM_SOPT_CLKOE_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable clock output.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see  SIM_EnableClockOutput
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableClockOutput(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_CLKOE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief set bus clock output divide. 
+*        
+* @param[in]  u8Divide     divide (3-bits)
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClockOutputDivide(uint8_t u8Divide)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_BUSREF_MASK)) | SIM_SOPT_BUSREF(u8Divide & 0x07);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable UART0 RXD connect with UART0 module  and ETM0 channel 1.. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0RXDConnectETMOCH1(void)
+{
+    SIM->SOPT |= (SIM_SOPT_RXDCE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable UART0 TX modulation. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0Modulation(void)
+{
+    SIM->SOPT |= (SIM_SOPT_TXDME_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable UART0 TX modulation. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableUART0Modulation(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_TXDME_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief generate a softare sync trigger to ETM2 module (trigger).
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_GenerateSoftwareTrig2ETM2(void)
+{
+    SIM->SOPT |= (SIM_SOPT_ETMSYNC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH3 pin from default to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH3Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM2PS3_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH2 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH2Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM2PS2_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH1 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH1Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM0PS1_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM0PS0_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_UART0PS_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap SPI0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapSPI0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_SPI0PS_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap I2C pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapI2CPin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_IICPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief enable UART0 RX filter. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0Filter(void)
+{
+    SIM->SOPT |= (SIM_SOPT_RXDFE_MASK);    
+}
+/******************************************************************************!
+
+* @function name: SIM_DisableUART0Filter
+*
+* @brief disable UART0 RX filter. 
+*        
+* @param         
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableUART0Filter(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_RXDFE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to RTC overflow. 
+*        
+* @param  none        
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByRTC(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_ADHWT_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to PIT . 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByPIT(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ETM2 init trigger with 8-bit programmable delay. 
+*        
+* @param  none      
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByETM2Init(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(2);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ETM2 match trigger with 8-bit programmable delay. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByETM2Match(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(3);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable RTC capture to ETM1 input channel1. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableRTCCapture(void)
+{
+    SIM->SOPT |= (SIM_SOPT_RTCC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief disable RTC capture to ETM1 input channel1. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableRTCCapture(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_RTCC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable ACMP0 input capture to ETM1 input channel0. 
+*        
+* @param  none      
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableACMP0InputCapture(void)
+{
+    SIM->SOPT |= (SIM_SOPT_ACIC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief disable ACMP0 input capture to ETM1 input channel0. 
+*        
+* @param  none      
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableACMP0InputCapture(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_ACIC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap RTC pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapRTCPin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_RTCPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief set bus divide BUSDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetBusDivide(uint8_t u8Divide)
+{
+    SIM->BUSDIV = u8Divide;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH1 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH1Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM2PS1_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM2PS0_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap ETM1CH1 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM1CH1Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM1PS1_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap ETM1CH0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM1CH0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM1PS0_MASK;    
+}
+#elif defined(CPU_NV32M3)
+/*****************************************************************************//*!
+*
+* @brief delay ETM2 triggering ADC for u8Delay bus clock output divide. 
+*        
+* @param[in]   u8Delay     delay value of Bus clock output divide.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DelayETM2Trig2ADC(uint8_t u8Delay)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_DELAY_MASK)) | SIM_SOPT_DELAY(u8Delay);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable clock output.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see  SIM_DisableClockOutput
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableClockOutput(void)
+{
+    SIM->SOPT |= (SIM_SOPT_CLKOE_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable clock output.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see  SIM_EnableClockOutput
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableClockOutput(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_CLKOE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief set bus clock output divide. 
+*        
+* @param[in]  u8Divide     divide (3-bits)
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClockOutputDivide(uint8_t u8Divide)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_BUSREF_MASK)) | SIM_SOPT_BUSREF(u8Divide & 0x07);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable UART0 RXD connect with UART0 module  and ETM0 channel 1.. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0RXDConnectETMOCH1(void)
+{
+    SIM->SOPT |= (SIM_SOPT_RXDCE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable UART0 TX modulation. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0Modulation(void)
+{
+    SIM->SOPT |= (SIM_SOPT_TXDME_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable UART0 TX modulation. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableUART0Modulation(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_TXDME_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief generate a softare sync trigger to ETM2 module (trigger).
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_GenerateSoftwareTrig2ETM2(void)
+{
+    SIM->SOPT |= (SIM_SOPT_ETMSYNC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH3 pin from default to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH3Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM2PS3_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH2 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH2Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM2PS2_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH1 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH1Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM0PS1_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM0PS0_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_UART0PS_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap SPI0 pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapSPI0Pin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_SPI0PS_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief remap I2C pin from default  to the other. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapI2CPin(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_IICPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief UART0 RXD input signal is connected to UART0 module directly. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0Filter(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_RXDFE_MASK);   
+}
+/*****************************************************************************//*!
+*
+* @brief UART0 RXD input signal is filtered by ACMP0, then injected to UART0. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0FilterByACMP0(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_RXDFE_MASK)) | SIM_SOPT_RXDFE(1);  
+}
+/*****************************************************************************//*!
+*
+* @brief UART0 RXD input signal is filtered by ACMP1, then injected to UART0. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0FilterByACMP1(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_RXDFE_MASK)) | SIM_SOPT_RXDFE(2);  
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to RTC overflow. 
+*        
+* @param  none        
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByRTC(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_ADHWT_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ETM0 init trigger . 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByPIT(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ETM2 init trigger with 8-bit programmable delay. 
+*        
+* @param  none      
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByETM2Init(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(2);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ETM2 match trigger with 8-bit programmable delay. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByETM2Match(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(3);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to PIT channel0 overflow. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByPITCH0Overflow(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(4);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to PIT channel1 overflow. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByPITChannel1Overflow(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(5);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ACMP0 out. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByACMP0Out(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(6);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ACMP1 out. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByACMP1Out(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ADHWT_MASK)) | SIM_SOPT_ADHWT(7);    
+}
+/*****************************************************************************//*!
+*
+* @brief Select ETM0CH0 as ETM0CH0 Input Capture Source. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelETM0CH0AsETM0CH0ICS(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_ETMIC_MASK);   
+}
+/*****************************************************************************//*!
+*
+* @brief Select ACMP0 OUT as ETM0CH0 Input Capture Source. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelACMP0AsETM0CH0ICS(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ETMIC_MASK)) | SIM_SOPT_ETMIC(1);  
+}
+/*****************************************************************************//*!
+*
+* @brief Select ACMP1 OUT as ETM0CH0 Input Capture Source. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelACMP1AsETM0CH0ICS(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ETMIC_MASK)) | SIM_SOPT_ETMIC(2);  
+}
+/*****************************************************************************//*!
+*
+* @brief Select RTC overflow as ETM0CH0 Input Capture Source. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelRTCOverflowAsETM0CH0ICS(void)
+{
+    SIM->SOPT = (SIM->SOPT & ~(SIM_SOPT_ETMIC_MASK)) | SIM_SOPT_ETMIC(3);  
+}
+/*****************************************************************************//*!
+*
+* @brief Select ACMP0 output as the trigger0 input of ETM2. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelACMP0AsETM2Trigger0(void)
+{
+    SIM->SOPT &= ~(SIM_SOPT_ACTRG_MASK);  
+}
+/*****************************************************************************//*!
+*
+* @brief Select ACMP1 output as the trigger0 input of ETM2. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelACMP1AsETM2Trigger0(void)
+{
+    SIM->SOPT |= (SIM_SOPT_ACTRG_MASK);  
+}
+/*****************************************************************************//*!
+*
+* @brief set clock3 divide CLKDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClock3Divide(void)
+{
+    SIM->CLKDIV |= SIM_CLKDIV_OUTDIV3_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief set clock2 divide CLKDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClock2Divide(void)
+{
+    SIM->CLKDIV |= SIM_CLKDIV_OUTDIV2_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief set clock1 divide CLKDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClock1Divide(uint8_t u8divide)
+{
+    SIM->CLKDIV |= SIM_CLKDIV_OUTDIV1(u8divide);    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK2 for PWT module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK2ForPWT(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_PWTCLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK1 for PWT module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK1ForPWT(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_PWTCLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK2 for ETM2 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK2ForETM2(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM2CLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK1 for ETM2 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK1ForETM2(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM2CLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK2 for ETM0 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK2ForETM0(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM0CLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK1 for ETM0 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK1ForETM0(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM0CLKPS_MASK;    
+}
+#elif defined(CPU_NV32M4)
+/*****************************************************************************//*!
+*
+* @brief delay ETM2 triggering ADC for u8Delay bus clock output divide. 
+*        
+* @param[in]   u8Delay     delay value of Bus clock output divide.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DelayETM2Trig2ADC(uint8_t u8Delay)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_DELAY_MASK)) | SIM_SOPT0_DELAY(u8Delay);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable clock output.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see  SIM_DisableClockOutput
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableClockOutput(void)
+{
+    SIM->SOPT0 |= (SIM_SOPT0_CLKOE_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable clock output.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see  SIM_EnableClockOutput
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableClockOutput(void)
+{
+    SIM->SOPT0 &= ~(SIM_SOPT0_CLKOE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief set bus clock output divide. 
+*        
+* @param[in]  u8Divide     divide (3-bits)
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClockOutputDivide(uint8_t u8Divide)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_BUSREF_MASK)) | SIM_SOPT0_BUSREF(u8Divide & 0x07);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable UART0 RXD connect with UART0 module  and ETM0 channel 1.. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0RXDConnectETMOCH1(void)
+{
+    SIM->SOPT0 |= (SIM_SOPT0_RXDCE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable UART0 TX modulation. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0Modulation(void)
+{
+    SIM->SOPT0 |= (SIM_SOPT0_TXDME_MASK);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable UART0 TX modulation. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableUART0Modulation(void)
+{
+    SIM->SOPT0 &= ~(SIM_SOPT0_TXDME_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief generate a softare sync trigger to ETM2 module (trigger).
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_GenerateSoftwareTrig2ETM2(void)
+{
+    SIM->SOPT0 |= (SIM_SOPT0_ETMSYNC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief select PWTIN3 input signal from UART0RX.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+__STATIC_INLINE void SIM_SetPWTIN3InputFromUART0Rx(void)
+{
+    SIM->SOPT1 = (SIM->SOPT1 & (~SIM_SOPT1_UARTPWTS_MASK)) | SIM_SOPT1_UARTPWTS(0);    
+}
+/*****************************************************************************//*!
+*
+* @brief select PWTIN3 input signal from UART1RX.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+__STATIC_INLINE void SIM_SetPWTIN3InputFromUART1Rx(void)
+{
+    SIM->SOPT1 = (SIM->SOPT1 & (~SIM_SOPT1_UARTPWTS_MASK)) | SIM_SOPT1_UARTPWTS(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief select PWTIN3 input signal from UART2RX.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+__STATIC_INLINE void SIM_SetPWTIN3InputFromUART2Rx(void)
+{
+    SIM->SOPT1 = (SIM->SOPT1 & (~SIM_SOPT1_UARTPWTS_MASK)) | SIM_SOPT1_UARTPWTS(2);    
+}
+/*****************************************************************************//*!
+*
+* @brief select PWTIN2 input signal from ACMP0_OUT.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetPWTIN2InputFromACMP0(void)
+{
+    SIM->SOPT1 &= (~SIM_SOPT1_ACPWTS_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief select PWTIN2 input signal from ACMP1_OUT.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetPWTIN2InputFromACMP1(void)
+{
+    SIM->SOPT1 |= SIM_SOPT1_ACPWTS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief enable invertion of the I2C output.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableI2C0OuputInvertion(void)
+{
+    SIM->SOPT1 |= SIM_SOPT1_I2C0OINV_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief disable invertion of the I2C output.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_DisableI2C0OuputInvertion(void)
+{
+    SIM->SOPT1 &= ~SIM_SOPT1_I2C0OINV_MASK;    
+}
+
+/*****************************************************************************//*!
+*
+* @brief enable 4-wire I2C.
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_Enable4WireI2C0(void)
+{
+    SIM->SOPT1 |= SIM_SOPT1_I2C04WEN_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief  disable 4-wire I2C..
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_Disable4WireI2C0(void)
+{
+    SIM->SOPT1 &= ~SIM_SOPT1_I2C04WEN_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief UART0 RXD input signal is connected to UART0 module directly. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0Filter(void)
+{
+    SIM->SOPT0 &= ~(SIM_SOPT0_RXDFE_MASK);   
+}
+/*****************************************************************************//*!
+*
+* @brief UART0 RXD input signal is filtered by ACMP0, then injected to UART0. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0FilterByACMP0(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_RXDFE_MASK)) | SIM_SOPT0_RXDFE(1);  
+}
+/*****************************************************************************//*!
+*
+* @brief UART0 RXD input signal is filtered by ACMP1, then injected to UART0. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableUART0FilterByACMP1(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_RXDFE_MASK)) | SIM_SOPT0_RXDFE(2);  
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to RTC overflow. 
+*        
+* @param  none        
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByRTC(void)
+{
+    SIM->SOPT0 &= ~(SIM_SOPT0_ADHWT_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to PIT . 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByPIT(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_ADHWT_MASK)) | SIM_SOPT0_ADHWT(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ETM2 init trigger with 8-bit programmable delay. 
+*        
+* @param  none      
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByETM2Init(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_ADHWT_MASK)) | SIM_SOPT0_ADHWT(2);    
+}
+
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ETM2 match trigger with 8-bit programmable delay. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByETM2Match(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_ADHWT_MASK)) | SIM_SOPT0_ADHWT(3);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to PIT channel0 overflow. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByPITCH0Overflow(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_ADHWT_MASK)) | SIM_SOPT0_ADHWT(4);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to PIT channel1 overflow. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByPITChannel1Overflow(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_ADHWT_MASK)) | SIM_SOPT0_ADHWT(5);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ACMP0 out. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByACMP0Out(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_ADHWT_MASK)) | SIM_SOPT0_ADHWT(6);    
+}
+/*****************************************************************************//*!
+*
+* @brief set ADC hardware trigger source to ACMP1 out. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_TriggerADCByACMP1Out(void)
+{
+    SIM->SOPT0 = (SIM->SOPT0 & ~(SIM_SOPT0_ADHWT_MASK)) | SIM_SOPT0_ADHWT(7);    
+}
+/*****************************************************************************//*!
+*
+* @brief Select ACMP0 output as the trigger0 input of ETM2. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelACMP0AsETM2Trigger0(void)
+{
+    SIM->SOPT0 &= ~(SIM_SOPT0_ACTRG_MASK);  
+}
+/*****************************************************************************//*!
+*
+* @brief Select ACMP1 output as the trigger0 input of ETM2. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelACMP1AsETM2Trigger0(void)
+{
+    SIM->SOPT0 |= (SIM_SOPT0_ACTRG_MASK);  
+}
+/*****************************************************************************//*!
+*
+* @brief enable RTC capture to ETM1 input channel1. 
+*        
+* @param  none       
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableRTCCapture(void)
+{
+    SIM->SOPT0 |= (SIM_SOPT0_RTCC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief enable ACMP0 input capture to ETM1 input channel0. 
+*        
+* @param  none      
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_EnableACMP0InputCapture(void)
+{
+    SIM->SOPT0 |= (SIM_SOPT0_ACIC_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK0 for PWT module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK0ForPWT(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_PWTCLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK1 for PWT module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK1ForPWT(void)
+{
+    SIM->PINSEL = (SIM->PINSEL&(~SIM_PINSEL_PWTCLKPS_MASK)) | SIM_PINSEL_PWTCLKPS(1) ;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK2 for PWT module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK2ForPWT(void)
+{
+    SIM->PINSEL = (SIM->PINSEL&(~SIM_PINSEL_PWTCLKPS_MASK)) | SIM_PINSEL_PWTCLKPS(2) ;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK0 for ETM2 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK0ForETM2(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM2CLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK1 for ETM2 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK1ForETM2(void)
+{
+    SIM->PINSEL = (SIM->PINSEL & (~SIM_PINSEL_ETM2CLKPS_MASK)) | (((uint32_t)0x1)<<SIM_PINSEL_ETM2CLKPS_SHIFT);    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK2 for ETM2 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK2ForETM2(void)
+{
+    SIM->PINSEL =(SIM->PINSEL & (~SIM_PINSEL_ETM2CLKPS_MASK)) | (((uint32_t)0x2)<<SIM_PINSEL_ETM2CLKPS_SHIFT);    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK0 for ETM1 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK0ForETM1(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM1CLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK1 for ETM1 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK1ForETM1(void)
+{
+    SIM->PINSEL = (SIM->PINSEL & (~SIM_PINSEL_ETM1CLKPS_MASK)) | (((uint32_t)0x1)<<SIM_PINSEL_ETM1CLKPS_SHIFT);    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK2 for ETM1 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK2ForETM1(void)
+{
+    SIM->PINSEL = (SIM->PINSEL & (~SIM_PINSEL_ETM1CLKPS_MASK)) | (((uint32_t)0x2)<<SIM_PINSEL_ETM1CLKPS_SHIFT);    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK0 for ETM0 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK0ForETM0(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM0CLKPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK1 for ETM0 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK1ForETM0(void)
+{
+    SIM->PINSEL = (SIM->PINSEL &(~SIM_PINSEL_ETM0CLKPS_MASK)) | (((uint32_t)0x1)<<SIM_PINSEL_ETM0CLKPS_SHIFT);    
+}
+/*****************************************************************************//*!
+*
+* @brief select TCLK2 for ETM0 module. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SelectTCLK2ForETM0(void)
+{
+    SIM->PINSEL = (SIM->PINSEL &(~SIM_PINSEL_ETM0CLKPS_MASK)) | (((uint32_t)0x2)<<SIM_PINSEL_ETM0CLKPS_SHIFT);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM1CH1 to pin PTC5 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM1CH1ToPTC5(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM1PS1_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM1CH1 to pin PTE7. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM1CH1ToPTE7(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM1PS1_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM1CH0 to pin PTC4 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM1CH0ToPTC4(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM1PS0_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM1CH0 to pin PTH2. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM1CH0ToPTH2(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM1PS0_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH1 to pin PTA1 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH1ToPTA1(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM0PS1_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH1 to pin PTB3. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH1ToPTB3(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM0PS1_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH0 to pin PTA0 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH0ToPTA1(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_ETM0PS0_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM0CH0 to pin PTB2. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM0CH0ToPTB3(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_ETM0PS0_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART0 to pin PTB0/1 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART0ToPTB_0_1(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_UART0PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART0 to pin PTA2/3. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART0ToPTA_2_3(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_UART0PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap SPI0 to pin PTB2/3/4/5 (default).  
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapSPI0ToPTB_2_3_4_5(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_SPI0PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap SPI0 to pin PTE01/2/3.  
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapSPI0ToPTE_0_12_3(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_SPI0PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap I2C to pin PTA2/3 (default).  
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapI2CToPTA_2_3(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_I2C0PS_MASK;    
+}   
+/*****************************************************************************//*!
+*
+* @brief remap I2C to pin PTB6/7 (default).  
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapI2CToPTB_6_7(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_I2C0PS_MASK;    
+} 
+/*****************************************************************************//*!
+*
+* @brief remap RTC to pin PTC4 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapRTCToPTC4(void)
+{
+    SIM->PINSEL &= ~SIM_PINSEL_RTCPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap RTC to pin PTC5. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapRTCToPTC5(void)
+{
+    SIM->PINSEL |= SIM_PINSEL_RTCPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap MSCAN to pin PTC6/7 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapMSCANToPTC_6_7(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_MSCANPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap MSCAN to pin PTH2/7. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapMSCANToPTH_2_7(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_MSCANPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap PWTIN1 to pin PTB0 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapPWTIN1ToPTB0(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_MSCANPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap PWTIN1 to pin PTH7. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapPWTIN1ToPTH7(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_MSCANPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap PWTIN0 to pin PTD5 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapPWTIN0ToPTD5(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_MSCANPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap PWTIN0 to pin PTE2. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapPWTIN0ToPTE2(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_MSCANPS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART2 to pin PTD6/7 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART2ToPTD_6_7(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_UART2PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART2 to pin PTI0/1. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART2ToPTI_0_1(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_UART2PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART1 to pin PTC6/7 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART1ToPTC_6_7(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_UART1PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap UART1 to pin PTF2/3. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapUART1ToPTF_2_3(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_UART1PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap SPI1 to pin PTD0/1/2/3 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapSPI1ToPTD_0_1_2_3(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_SPI1PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap SPI1 to pin PTG4/5/6/7. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapSPI1ToPTG_4_5_6_7(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_SPI1PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap I2C1 to pin PTE0/1 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapI2C1ToPTE_0_1(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_I2C1PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap I2C1 to pin PTH3/4. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapI2C1ToPTH_3_4(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_I2C1PS_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH5 to pin PTB5 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH5ToPTB5(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_ETM2PS5_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH5 to pin PTG7. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH5ToPTG7(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_ETM2PS5_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH4 to pin PTB4 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH4ToPTB4(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_ETM2PS4_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH4 to pin PTG6. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH4ToPTG6(void)
+{
+    SIM->PINSEL1 |= SIM_PINSEL1_ETM2PS4_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH3 to pin PTC3 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH3ToPTC3(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_ETM2PS3_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH3 to pin PTD1. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH3ToPTD1(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 & (~SIM_PINSEL1_ETM2PS3_MASK)) | SIM_PINSEL1_ETM2PS3(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH3 to pin PTG5. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH3ToPTG5(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 & (~SIM_PINSEL1_ETM2PS3_MASK)) | SIM_PINSEL1_ETM2PS3(2);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH2 to pin PTC2 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH2ToPTC2(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_ETM2PS2_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH2 to pin PTD0. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH2ToPTD0(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 & (~SIM_PINSEL1_ETM2PS2_MASK)) | SIM_PINSEL1_ETM2PS2(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH2 to pin PTG4. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH2ToPTG4(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 & (~SIM_PINSEL1_ETM2PS2_MASK)) | SIM_PINSEL1_ETM2PS2(2);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH1 to pin PTC1 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH1ToPTC1(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_ETM2PS1_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH1 to pin PTH1. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH1ToPTH1(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 & (~SIM_PINSEL1_ETM2PS1_MASK)) | SIM_PINSEL1_ETM2PS1(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH1 to pin PTF1. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH1ToPTF1(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 & (~SIM_PINSEL1_ETM2PS1_MASK)) | SIM_PINSEL1_ETM2PS1(2);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH0 to pin PTC0 (default). 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH0ToPTC0(void)
+{
+    SIM->PINSEL1 &= ~SIM_PINSEL1_ETM2PS0_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH0 to pin PTH0. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH0ToPTH0(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 & (~SIM_PINSEL1_ETM2PS0_MASK)) | SIM_PINSEL1_ETM2PS0(1);    
+}
+/*****************************************************************************//*!
+*
+* @brief remap ETM2CH0 to pin PTF0. 
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_RemapETM2CH0ToPTF0(void)
+{
+    SIM->PINSEL1 = (SIM->PINSEL1 &(~SIM_PINSEL1_ETM2PS0_MASK)) | SIM_PINSEL1_ETM2PS0(2);    
+}
+/*****************************************************************************//*!
+*
+* @brief set clock3 divide CLKDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClock3Divide(void)
+{
+    SIM->CLKDIV |= SIM_CLKDIV_OUTDIV3_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief set clock2 divide CLKDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClock2Divide(void)
+{
+    SIM->CLKDIV |= SIM_CLKDIV_OUTDIV2_MASK;    
+}
+/*****************************************************************************//*!
+*
+* @brief set clock1 divide CLKDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetClock1Divide(uint8_t u8divide)
+{
+    SIM->CLKDIV |= SIM_CLKDIV_OUTDIV1(u8divide);    
+}
+/*****************************************************************************//*!
+*
+* @brief set bus divide BUSDIV.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE void SIM_SetBusDivide(uint8_t u8Divide)
+{
+    SIM->CLKDIV = u8Divide;    
+}
+
+#endif
+
+
+/*! @} End of sim_api_list                                                   */
+
+void SIM_Init(SIM_ConfigType *pConfig);
+void SIM_SetClockGating(uint32_t u32PeripheralMask, uint8_t u8GateOn);
+uint32_t SIM_GetStatus(uint32_t u32StatusMask);
+uint8_t SIM_ReadID(IDType sID);
+
+#endif /* SIM_H_ */
+
+

bsp/nv32f100x/lib/inc/spi.h

@@ -0,0 +1,634 @@
+/******************************************************************************
+*
+* @brief header file for SPI module utilities (SPI). 
+*
+*******************************************************************************
+*
+* provide APIs for accessing SPI module (SPI)
+******************************************************************************/
+
+#ifndef SPI_H_
+#define SPI_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+/******************************************************************************
+* Includes
+******************************************************************************/
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+/* maximum number of SPIs */
+#define     MAX_SPI_NO              2
+
+
+
+/******************************************************************************
+* define SPI register default value
+*
+*//*! @addtogroup spi_default_value
+* @{
+*******************************************************************************/
+
+#define SPI_C1_DEFAULT          0x04						/*!< SPI C1 register */
+#define SPI_C2_DEFAULT          0x00						/*!< SPI C2 register */
+#define SPI_BR_DEFAULT          0x00						/*!< SPI BR register */
+#define SPI_S_DEFAULT           0x20						/*!< SPI S register */
+#define SPI_M_DEFAULT           0x00						/*!< SPI M register */
+/*! @} End of spi_default_value                                                    					*/
+
+/******************************************************************************
+* define SPI error status
+*
+*//*! @addtogroup spi_error_list
+* @{
+*******************************************************************************/
+
+#define     SPI_ERR_SUCCESS            0                                /*!< success */
+#define     SPI_ERR_CODE_BASE         ((uint32)SPI0 - 0x40000000L)      /*!< error code base for SPI */
+#define     SPI_ERR_TXBUF_NOT_EMPTY   (SPI_ERR_CODE_BASE+1)             /*!< failure due to SPTEF (empty) not set */
+#define     SPI_ERR_RXBUF_NOT_FULL    (SPI_ERR_CODE_BASE+2)             /*!< failure due to SPRF (full) not set */
+/*! @} End of spi_error_list                                            */
+        
+/******************************************************************************
+* Types
+******************************************************************************/
+
+typedef uint8_t   SPI_WidthType;  /* SPI width type */
+typedef uint32_t  ResultType;     /* SPI routine Result code */
+
+/******************************************************************************
+* define SPI call back funtion
+*
+*//*! @addtogroup spi_callback
+* @{
+*******************************************************************************/
+typedef void (*SPI_CallbackType)(void);  /*!< SPI call back function */
+/*! @} End of spi_callback                                            */
+
+/******************************************************************************
+*
+*//*! @addtogroup spi_setting_type
+* @{
+*******************************************************************************/
+/*!
+ * @brief SPI setting type.
+ *
+ */
+typedef struct
+{
+    uint32_t bIntEn                               : 1; /*!< 1: Interrupt Enable, 0: Interrupt disable */
+    uint32_t bModuleEn                            : 1; /*!< 1: SPI module Enable, 0: SPI module disable */
+    uint32_t bTxIntEn                             : 1; /*!< 1: Tx Interrupt Enable, 0: Tx Interrupt disable */
+    uint32_t bMasterMode                          : 1; /*!< 1: Master mode, 0: Slave mode */
+    uint32_t bClkPolarityLow                      : 1; /*!< 1: Active-low SPI clock, 0: Active-HIgh SPI clock */
+    uint32_t bClkPhase1                           : 1; /*!< Set clock phase */
+    uint32_t bMasterAutoDriveSS                   : 1; /*!< Slave select output enable */
+    uint32_t bShiftLSBFirst                       : 1; /*!< 1: LSB first, 0: MSB first */
+    uint32_t bMatchIntEn                          : 1; /*!< 1: Match interrupt Enable, 0: Match interrupt disable */
+    uint32_t bModeFaultEn                         : 1; /*!< Master mode-fault function enable */
+    uint32_t bBidirectionModeEn                   : 1; /*!< Bidirectional mode output enable */
+    uint32_t bPinAsOuput                          : 1; /*!< enables bidirectional pin configurations */
+    uint32_t bStopInWaitMode                      : 1; /*!< SPI stop in wait mode */
+    uint32_t bRsvd                                : 19;
+} SPI_SettingType;
+/*! @} End of spi_setting_type                                            */
+
+/******************************************************************************
+*
+*//*! @addtogroup spi_config_type
+* @{
+*******************************************************************************/
+/*!
+ * @brief SPI configuration type.
+ *
+ */
+typedef struct 
+{
+    SPI_SettingType     sSettings;              /*!< SPI settings */
+    uint32_t              u32BitRate;             /*!< set baud rate */
+    uint32_t              u32BusClkHz;            /*!< input bus clock */
+} SPI_ConfigType;                              /*!< SPI configuration structure */
+/*! @} End of spi_config_type                                            */
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* inline function
+******************************************************************************/
+/******************************************************************************
+*
+*//*! @addtogroup spi_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief LSB first (shifter direction).
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+
+ __STATIC_INLINE void SPI_SetLSBFirst(SPI_Type *pSPI)
+{
+	pSPI->C1 |= SPI_C1_LSBFE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief MSB first (shifter direction).
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+
+ __STATIC_INLINE void SPI_SetMSBFirst(SPI_Type *pSPI)
+{
+	pSPI->C1 &= ~SPI_C1_LSBFE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief set SPI clock polarity.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   * @param[in]  u8PolLow   set clock polarity, 1 - Active-low SPI clock (idles high).  
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+
+ __STATIC_INLINE void SPI_SetClockPol(SPI_Type *pSPI,uint8_t u8PolLow)
+{
+	if( u8PolLow )
+	{
+		pSPI->C1 |= SPI_C1_CPOL_MASK;	
+	}
+	else
+	{
+		pSPI->C1 &= ~SPI_C1_CPOL_MASK;	
+	}
+}
+/*****************************************************************************//*!
+   *
+   * @brief set SPI clock phase.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   * @param[in]  u8Phase   set clock phase, 1 - First edge on SPSCK occurs at the start of the first cycle of a data transfer. 
+   * 
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+
+ __STATIC_INLINE void SPI_SetClockPhase(SPI_Type *pSPI,uint8_t u8Phase)
+{
+	if( u8Phase )
+	{
+		pSPI->C1 |= SPI_C1_CPHA_MASK;	
+	}
+	else
+	{
+		pSPI->C1 &= ~SPI_C1_CPHA_MASK;	
+	}
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable SPI module.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+
+ __STATIC_INLINE void SPI_Enable(SPI_Type *pSPI)
+{
+	pSPI->C1 |= SPI_C1_SPE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief disable SPI module.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *  
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+
+ __STATIC_INLINE void SPI_Disable(SPI_Type *pSPI)
+{
+	pSPI->C1 &= ~SPI_C1_SPE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable SPI interrupt.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+
+ __STATIC_INLINE void SPI_IntEnable(SPI_Type *pSPI)
+{
+	pSPI->C1 |= SPI_C1_SPIE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief disable SPI interrupt.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_IntDisable(SPI_Type *pSPI)
+{
+	pSPI->C1 &= ~SPI_C1_SPIE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief set SPI to master mode.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_SetMasterMode(SPI_Type *pSPI)
+{
+	pSPI->C1 |= SPI_C1_MSTR_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief set SPI to slave mode.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_SetSlaveMode(SPI_Type *pSPI)
+{
+	pSPI->C1 &= ~SPI_C1_MSTR_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SPI transmit interrupt enable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_TxIntEnable(SPI_Type *pSPI)
+{
+	pSPI->C1 |= SPI_C1_SPTIE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SPI transmit interrupt disable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_TxIntDisable(SPI_Type *pSPI)
+{
+	pSPI->C1 &= ~SPI_C1_SPTIE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Slave select output enable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_SSOutputEnable(SPI_Type *pSPI )
+{
+	pSPI->C1 |= SPI_C1_SSOE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Slave select output disable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_SSOutputDisable(SPI_Type *pSPI )
+{
+	pSPI->C1 &= ~SPI_C1_SSOE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SPI match interrupt enable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   * 
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_MatchIntEnable(SPI_Type *pSPI )
+{
+	pSPI->C2 |= SPI_C2_SPMIE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SPI match interrupt disable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_MatchIntDisable(SPI_Type *pSPI )
+{
+	pSPI->C2 &= ~SPI_C2_SPMIE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Master mode-fault function disable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_ModfDisable(SPI_Type *pSPI )
+{
+	pSPI->C2 &= ~SPI_C2_MODFEN_MASK;
+}
+/*****************************************************************************//*!
+
+   *
+   * @brief Master mode-fault function enable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_ModfEnable(SPI_Type *pSPI )
+{
+	pSPI->C2 |= SPI_C2_MODFEN_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Bidirectional mode output enable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_BidirOutEnable(SPI_Type *pSPI )
+{
+	pSPI->C2 |= SPI_C2_BIDIROE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief Bidirectional mode output disable.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_BidirOutDisable(SPI_Type *pSPI )
+{
+	pSPI->C2 &= ~SPI_C2_BIDIROE_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SPI stop in wait mode
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   * 
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_ClockStopDisable(SPI_Type *pSPI )
+{
+	pSPI->C2 &= ~SPI_C2_SPISWAI_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief SPI stop in wait mode.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *  
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_ClockStopEnable(SPI_Type *pSPI )
+{
+	pSPI->C2 |= SPI_C2_SPISWAI_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enables bidirectional pin configurations.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *   
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_BidirPinEnable(SPI_Type *pSPI)
+{
+	pSPI->C2 |= SPI_C2_SPC0_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief enables bidirectional pin configurations.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *   
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_BidirPinDisable(SPI_Type *pSPI)
+{
+	pSPI->C2 &= ~SPI_C2_SPC0_MASK;
+}
+/*****************************************************************************//*!
+   *
+   * @brief check SPI read buffer full flag.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *    
+   * @return  TRUE or FALSE.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE uint8_t SPI_IsSPRF(SPI_Type *pSPI )
+{
+	return(pSPI->S & SPI_S_SPRF_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check SPI match flag.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *    
+   * @return  TRUE or FALSE.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ __STATIC_INLINE uint8_t SPI_IsSPMF(SPI_Type *pSPI )
+{
+	return(pSPI->S & SPI_S_SPMF_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check SPI transmit buffer empty flag.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *    
+   * @return  TRUE or FALSE.
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE uint8_t SPI_IsSPTEF(SPI_Type *pSPI )
+{
+	return(pSPI->S & SPI_S_SPTEF_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief check master mode fault flag.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *    
+   * @return  TRUE or FALSE.
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE uint8_t SPI_IsMODF(SPI_Type *pSPI )
+{
+	return(pSPI->S & SPI_S_MODF_MASK);
+}
+/*****************************************************************************//*!
+   *
+   * @brief read SPI data register.
+   *        
+   * @param[in]  pSPI   point to SPI module type.  
+   *    
+   * @return data register value
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE uint8_t SPI_ReadDataReg(SPI_Type *pSPI )
+{
+	return pSPI->D;
+}
+/*****************************************************************************//*!
+   *
+   * @brief write SPI data register.
+   *        
+   * @param[in]  pSPI   point to SPI module type. 
+   * @param[in]  u8WrBuff   data buffer write to spi data register. 
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_WriteDataReg(SPI_Type *pSPI, uint8_t u8WrBuff )
+{
+	pSPI->D = u8WrBuff;
+}
+/*****************************************************************************//*!
+   *
+   * @brief write SPI match  register.
+   *        
+   * @param[in]  pSPI   point to SPI module type. 
+   * @param[in]  u8WrBuff   the data buffer write to match register. 
+   *
+   * @return  none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+ __STATIC_INLINE void SPI_WriteMatchValue(SPI_Type *pSPI, uint8_t u8WrBuff )
+{
+	pSPI->M = u8WrBuff;
+}
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void SPI_Enable(SPI_Type *pSPI);
+void SPI_Disable(SPI_Type *pSPI);
+void SPI_SetLSBFirst(SPI_Type *pSPI);
+void SPI_SetMSBFirst(SPI_Type *pSPI);
+void SPI_IntEnable(SPI_Type *pSPI);
+void SPI_IntDisable(SPI_Type *pSPI);
+void SPI_SetMasterMode(SPI_Type *pSPI);
+void SPI_SetSlaveMode(SPI_Type *pSPI);
+void SPI_TxIntEnable(SPI_Type *pSPI);
+void SPI_TxIntDisable(SPI_Type *pSPI);
+void SPI_SSOutputEnable(SPI_Type *pSPI );
+void SPI_SSOutputDisable(SPI_Type *pSPI );
+void SPI_MatchIntEnable(SPI_Type *pSPI );
+void SPI_MatchIntDisable(SPI_Type *pSPI );
+void SPI_ModfDisable(SPI_Type *pSPI );
+void SPI_ModfEnable(SPI_Type *pSPI );
+void SPI_BidirOutEnable(SPI_Type *pSPI );
+void SPI_BidirOutDisable(SPI_Type *pSPI );
+void SPI_ClockStopDisable(SPI_Type *pSPI );
+void SPI_ClockStopEnable(SPI_Type *pSPI );
+void SPI_BidirPinEnable(SPI_Type *pSPI );
+void SPI_BidirPinDisable(SPI_Type *pSPI );
+void SPI_SetClockPol(SPI_Type *pSPI,uint8_t u8PolLow);
+void SPI_SetClockPhase(SPI_Type *pSPI,uint8_t u8Phase);
+void SPI_SetBaudRate(SPI_Type *pSPI,uint32_t u32BusClock,uint32_t u32Bps );
+uint8_t SPI_IsSPRF(SPI_Type *pSPI );
+uint8_t SPI_IsSPMF(SPI_Type *pSPI );
+uint8_t SPI_IsSPTEF(SPI_Type *pSPI );
+uint8_t SPI_IsMODF(SPI_Type *pSPI );
+uint8_t SPI_ReadDataReg(SPI_Type *pSPI );
+void SPI_WriteDataReg(SPI_Type *pSPI, uint8_t u8WrBuff );
+void SPI_WriteMatchValue(SPI_Type *pSPI, uint8_t u8WrBuff );
+void SPI_Init(SPI_Type *pSPI, SPI_ConfigType *pConfig);
+void SPI_DeInit(SPI_Type *pSPI);
+ResultType SPI_TransferWait(SPI_Type *pSPI, SPI_WidthType* pRdBuff, SPI_WidthType *pWrBuff,uint32 uiLength);
+void SPI_SetCallback(SPI_Type *pSPI,SPI_CallbackType pfnCallback);
+
+/*! @} End of spi_api_list                                            */
+#ifdef __cplusplus
+}
+#endif
+#endif /* SPI_H_ */

bsp/nv32f100x/lib/inc/uart.h

@@ -0,0 +1,496 @@
+/******************************************************************************
+*
+* @brief provide commond UART utilities. 
+*
+*******************************************************************************/
+#ifndef _UART_H_
+#define _UART_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+* Includes
+******************************************************************************/
+#include "common.h"
+#include "wdog.h"
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+#define MAX_UART_NO             3
+
+/******************************************************************************
+* Types
+******************************************************************************/
+
+/******************************************************************************
+*define uart setting type
+*
+*//*! @addtogroup uart_setting_type
+* @{
+*******************************************************************************/  
+
+/*!
+* @brief UART setting type.
+*
+*/ 
+
+typedef struct
+{
+    uint32_t bEnable      : 1;                /*!< 1: enable, 0: disable */
+    uint32_t resvd        : 31;               /*!< 1: reserved bit field */
+} UART_SettingType;
+/*! @} End of uart_setting_type */
+
+/******************************************************************************
+*define uart config type
+*
+*//*! @addtogroup uart_config_type
+* @{
+******************************************************************************/
+ /*!
+ * @brief UART Configuration structure.
+ *
+ */   
+typedef struct 
+{
+    UART_SettingType    sSettings;              /*!< UART settings */
+    uint32_t    u32SysClkHz;        /*!< system clock */
+    uint32_t    u32Baudrate;        /*!< UART baudrate */
+} UART_ConfigType;
+/*! @} End of uart_config_type  */
+
+/******************************************************************************
+*define uart config baudrate type
+*
+*//*! @addtogroup uart_config_baudrate_type
+* @{
+******************************************************************************/
+ /*!
+ * @brief UART baudrate type structure.
+ *
+ */   
+typedef struct
+{
+    uint32_t    u32SysClkHz;        /*!< system clock */
+    uint32_t    u32Baudrate;        /*!< UART baudrate */
+} UART_ConfigBaudrateType;
+/*! @} End of uart_config_baudrate_type */
+
+/******************************************************************************
+*define uart config mode type list
+*
+*//*! @addtogroup uart_mode_type_list
+* @{
+******************************************************************************/
+typedef enum
+{
+    UART_Mode8Bit,                  /*!< 8 bit mode */
+    UART_Mode9Bit,                  /*!< 9 bit mode */
+    UART_ModeEnableLoopback,        /*!< enable looback mode */
+    UART_ModeDisableLoopback,       /*!< disable loopback mode*/
+    UART_ModeEnableSingleWire,      /*!< enable single wire mode */
+    UART_ModeDisableSingleWire,     /*!< disable single wire mode */
+} UART_ModeType;
+/*! @} End of uart_mode_type_list   */
+
+/******************************************************************************
+*define uart interrupt type list
+*
+*//*! @addtogroup uart_interrupt_type_list
+* @{
+******************************************************************************/
+
+typedef enum
+{
+    UART_TxBuffEmptyInt,            /*!< transmit buffer empty interrupt */
+    UART_TxCompleteInt,             /*!< transmit complete interrupt */
+    UART_RxBuffFullInt,             /*!< receive buffer full interrupt */
+
+    UART_IdleLineInt,               /*!< idle line interrupt */
+
+    UART_RxOverrunInt,              /*!< receive overrun interrupt */
+    UART_NoiseErrorInt,             /*!< noise error interrupt */
+    UART_FramingErrorInt,           /*!< framing error interrupt */
+    UART_ParityErrorInt,            /*!< parity error interrupt */
+} UART_InterruptType;
+/*! @} End of uart_interrupt_type_list  */
+
+/******************************************************************************
+*define uart flag type list
+*
+*//*! @addtogroup uart_flag_type_list
+* @{
+******************************************************************************/
+typedef enum
+{
+    UART_FlagPF = 0,        /*!< Parity error flag */
+    UART_FlagFE,            /*!< Framing error flag */
+    UART_FlagNF,            /*!< Noise flag */
+    UART_FlagOR,            /*!< Receive overrun */
+    UART_FlagIDLE,          /*!< Idle line flag */
+    UART_FlagRDRF,          /*!< Receive data register full flag */
+    UART_FlagTC,            /*!< Transmission complete flag */
+    UART_FlagTDRE,          /*!< Transmit data register flag */
+
+    UART_FlagRAF,           /*!< Receiver active flag */
+    UART_FlagLBKDE,         /*!< LIN break detection enable */
+    UART_FlagBRK13,         /*!< Break character generation length */ 
+    UART_FlagRWUID,         /*!< Receive wake up idle detect */
+    UART_FlagRXINV,         /*!< Receive data inversion */
+    UART_FlagRev1,          /*!< Reserved */
+    UART_FlagRXEDGIF,       /*!< RxD pin active edge interrupt flag */
+    UART_FlagLBKDIF,        /*!< LIN break detect interrupt flag */
+} UART_FlagType;
+/*! @} End of uart_flag_type_list   */
+
+/* callback types */
+typedef void (*UART_CallbackType)(UART_Type *pUART);
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Inline functions
+******************************************************************************/
+
+/******************************************************************************
+* define UART APIs
+*
+*//*! @addtogroup uart_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief read receive buffer
+*        
+* @param[in] pUART       base of UART port
+*
+* @return unsign char received char
+*
+*****************************************************************************/
+__STATIC_INLINE uint8_t UART_ReadDataReg(UART_Type *pUART)
+{
+    /* Return the 8-bit data from the receiver */
+    return pUART->D;
+}
+/*****************************************************************************//*!
+*
+* @brief write transmit buffer
+*        
+* @param[in] pUART       base of UART port
+* @param[in] u8Char      char to send
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_WriteDataReg(UART_Type *pUART, uint8_t u8Char)
+{
+    /* Send the character */
+    pUART->D = (uint8_t)u8Char;
+}
+
+/*****************************************************************************//*!
+*
+* @brief check if a character has been received
+*
+* @param[in] pUART  base of UART port
+*
+* @return 0, No character received; no-zero, Character has been received
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE uint8_t UART_CharPresent(UART_Type *pUART)
+{  
+    return (pUART->S1 & UART_S1_RDRF_MASK);
+}
+/*****************************************************************************//*!
+*
+* @brief enable transmit
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_EnableTx(UART_Type *pUART)
+{
+    
+    pUART->C2 |= UART_C2_TE_MASK;
+}
+/*****************************************************************************//*!
+*
+* @brief disable transmit
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_DisableTx(UART_Type *pUART)
+{    
+    pUART->C2 &= (~UART_C2_TE_MASK);
+}
+/*****************************************************************************//*!
+*
+* @brief enable receive
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_EnableRx(UART_Type *pUART)
+{    
+    pUART->C2 |= UART_C2_RE_MASK;
+}
+/*****************************************************************************//*!
+*
+* @brief disable receive
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_DisableRx(UART_Type *pUART)
+{    
+    pUART->C2 &= (~UART_C2_RE_MASK);
+}
+/*****************************************************************************//*!
+*
+* @brief Enable loopback mode
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_EnableLoopback(UART_Type *pUART)
+{
+    pUART->C1 |= UART_C1_LOOPS_MASK;
+    pUART->C1 &= (~UART_C1_RSRC_MASK);
+}
+/*****************************************************************************//*!
+*
+* @brief enable single wire mode
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_EnableSingleWire(UART_Type *pUART)
+{
+    pUART->C1 |= UART_C1_LOOPS_MASK;
+    pUART->C1 |= UART_C1_RSRC_MASK;
+}
+/*****************************************************************************//*!
+*
+* @brief set 8-bit mode
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_Set8BitMode(UART_Type *pUART)
+{
+    pUART->C1 &= (~UART_C1_M_MASK);
+}
+/*****************************************************************************//*!
+*
+* @brief set 9-bit mode
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+*****************************************************************************/
+__STATIC_INLINE void UART_Set9BitMode(UART_Type *pUART)
+{
+    pUART->C1 |= UART_C1_M_MASK;
+}
+/*****************************************************************************//*!
+*
+* @brief enable transmit buffer empty interrupt
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE void UART_EnableTxBuffEmptyInt(UART_Type *pUART)
+{
+    pUART->C2 |= UART_C2_TIE_MASK;
+}
+/*****************************************************************************//*!
+*
+* @brief enable transmit complete interrupt
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE void UART_EnableTxCompleteInt(UART_Type *pUART)
+{
+    pUART->C2 |= UART_C2_TCIE_MASK;
+}
+/*****************************************************************************//*!
+*
+* @brief enable receive buffer full interrupt
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE void UART_EnableRxBuffFullInt(UART_Type *pUART)
+{
+    pUART->C2 |= UART_C2_RIE_MASK;
+}
+/*****************************************************************************//*!
+*
+* @brief disable transmit buffer empty interrupt
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE void UART_DisableTxBuffEmptyInt(UART_Type *pUART)
+{
+        pUART->C2 &= (~UART_C2_TIE_MASK);    
+}
+/*****************************************************************************//*!
+*
+* @brief disable transmit complete interrupt
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE void UART_DisableTxCompleteInt(UART_Type *pUART)
+{
+    pUART->C2 &= (~UART_C2_TCIE_MASK);   
+}
+/*****************************************************************************//*!
+*
+* @brief disable receive buffer full interrupt
+*        
+* @param[in] pUART       base of UART port
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE void UART_DisableRxBuffFullInt(UART_Type *pUART)
+{
+    pUART->C2 &= (~UART_C2_RIE_MASK);  
+}
+/*****************************************************************************//*!
+*
+* @brief print out break character
+*        
+* @param[in] pUART  base of UART port
+*
+* @return       none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+__STATIC_INLINE void UART_PutBreak(UART_Type *pUART)
+{
+    /* Write 1 then write 0 to UART_C2[SBK] bit, will put break character */
+    pUART->C2 |= UART_C2_SBK_MASK; 
+    pUART->C2 &= (~UART_C2_SBK_MASK);
+}
+
+/*****************************************************************************//*!
+*
+* @brief check whether tx is complete,i.e. data has been sent out.
+*        
+* @param[in] pUART  base of UART port
+*
+* @return       
+*               1, Tx complete flag is set
+*               0, Tx complete flag is clear
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t UART_IsTxComplete(UART_Type *pUART)
+{
+    return (pUART->S1 & UART_S1_TC_MASK);
+}
+/*****************************************************************************//*!
+*
+* @brief check whether Tx buffer is empty
+*        
+* @param[in] pUART  base of UART port
+*
+* @return       
+*               1, Tx buffer is empty
+*               0, Tx buffer is not empty
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t UART_IsTxBuffEmpty(UART_Type *pUART)
+{
+    return (pUART->S1 & UART_S1_TDRE_MASK);
+}
+/*****************************************************************************//*!
+*
+* @brief check whether Rx buffer is full, i.e. receive a character
+*        
+* @param[in] pUART  base of UART port
+*
+* @return       
+*               1, Rx buffer is full
+*               0, Rx buffer is not full
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+__STATIC_INLINE uint8_t UART_IsRxBuffFull(UART_Type *pUART)
+{
+    return (pUART->S1 & UART_S1_RDRF_MASK);
+}
+/*! @} End of uart_api_list */
+
+
+/******************************************************************************
+* Global functions declaration
+******************************************************************************/
+void UART_Init(UART_Type *pUART, UART_ConfigType *pConfig);
+uint8_t UART_GetChar(UART_Type *pUART);
+void UART_PutChar(UART_Type *pUART, uint8_t u8Char);
+void UART_SetBaudrate(UART_Type *pUART, UART_ConfigBaudrateType *pConfig);
+void UART_EnableInterrupt(UART_Type *pUART, UART_InterruptType InterruptType);
+void UART_DisableInterrupt(UART_Type *pUART, UART_InterruptType InterruptType);
+uint16_t UART_GetFlags(UART_Type *pUART);
+uint8_t UART_CheckFlag(UART_Type *pUART, UART_FlagType FlagType);
+void UART_SendWait(UART_Type *pUART, uint8_t *pSendBuff, uint32_t u32Length);
+void UART_ReceiveWait(UART_Type *pUART, uint8_t *pReceiveBuff, uint32_t u32Length);
+void UART_WaitTxComplete(UART_Type *pUART);
+void UART_SetCallback(UART_CallbackType pfnCallback);
+void UART0_Isr(void);
+void UART1_Isr(void);
+void UART2_Isr(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* #ifndef _UART_H_ */

bsp/nv32f100x/lib/inc/wdog.h

@@ -0,0 +1,203 @@
+
+/******************************************************************************
+* @brief provide commond watch dog utilities. 
+*
+*******************************************************************************
+*
+* provide APIs for accessing watch dog
+******************************************************************************/
+
+#ifndef __WDOG_H__
+#define __WDOG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/******************************************************************************
+* Includes
+******************************************************************************/
+#include "sim.h"
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+
+/******************************************************************************
+* Macros
+******************************************************************************/
+/* wdog_unlock sequence must be performed within 16 bus clock cycles without
+ * any interrupt 
+ */
+
+   
+/* WDOG clock sources option */
+/******************************************************************************
+* define watchdog clock source selection
+*
+*//*! @addtogroup wdog_clock_sources
+* @{
+*******************************************************************************/
+
+#define WDOG_CLK_BUS                    0   /*!< clock source is bus clock */
+#define WDOG_CLK_INTERNAL_32KHZ         2   /*!< clock source is internal oscillator 32 kHz (ICSIRCLK) */
+#define WDOG_CLK_INTERNAL_1KHZ	        1   /*!< clock source is internal LPO 1 KHz */
+#define WDOG_CLK_EXTERNAL               3   /*!< clock source is external clock */
+/*! @} End of wdog_clock_sources                                                    					*/
+
+/* WDOG clock source selection */
+#define WDOG_CLK  (WDOG_CLK_INTERNAL_1KHZ)
+    
+/* WDOG default values */
+#define WDOG_CS1_DEFAULT_VALUE      0x80
+#define WDOG_CS2_DEFAULT_VALUE      0x01
+#define WDOG_TOVAL_DEFAULT_VALUE    0x0400
+#define WDOG_WIN_DEFAULT_VALUE      0x0000
+     
+/* WDOG utilities */  
+
+/******************************************************************************
+* define watchdog API list
+*
+*//*! @addtogroup wdog_api_list
+* @{
+*******************************************************************************/
+/*! 
+ * @brief watchdog unlock routine.
+ */
+#define WDOG_Unlock()        WDOG->CNT = 0x20C5; WDOG->CNT = 0x28D9        
+//#define WDOG_Unlock()       DisableInterrupts; WDOG->CNT = 0x20C5; WDOG->CNT = 0x28D9; EnableInterrupts        
+/*! @} End of wdog_api_list                                                    					*/
+
+/******************************************************************************
+* Types
+******************************************************************************/
+
+/******************************************************************************
+* define watchdog configuration structure
+*
+*//*! @addtogroup wdog_config_type
+* @{
+*******************************************************************************/
+
+/*!
+ * @brief watchdog configuration structure.
+ *
+ */
+typedef struct {	
+    struct {
+	uint16_t    bIntEnable      : 1;    /*!< watchdog interrupt enable */
+	uint16_t    bDisable        : 1;    /*!< disable watchdog */
+	uint16_t    bWaitEnable     : 1;    /*!< enable watchdog in wait mode */
+	uint16_t    bStopEnable     : 1;    /*!< enable watchdog in stop mode */
+	uint16_t    bDbgEnable      : 1;    /*!< enable watchdog in debug mode */
+	uint16_t    bWinEnable      : 1;    /*!< enable watchdog window mode */
+	uint16_t    bUpdateEnable   : 1;    /*!< enable update of watchdog control */
+	uint16_t    bClkSrc         : 2;    /*!< watchdog clock source selection */  
+	uint16_t    bPrescaler      : 1;    /*!< prescaler */  
+    }sBits;                             /*!< bitfield structure  */
+    uint16_t    u16ETMeOut;             /*!< watchdog ETMeout value */
+    uint16_t    u16WinETMe;             /*!< watchdog window value */
+} WDOG_ConfigType, *WDOG_ConfigPtr;  /*!< watchdog configuration structure type */
+/*! @} End of wdog_config_type                                                    					*/
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define watchdog API list
+*
+*//*! @addtogroup wdog_api_list
+* @{
+*******************************************************************************/
+
+
+/*****************************************************************************//*!
+*
+* @brief set ETMe out value for WDOG.
+*        
+* @param[in]   u16ETMeOut  ETMeout value to TOVAL register.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*
+*****************************************************************************/
+
+__STATIC_INLINE void WDOG_SetETMeOut(uint16_t u16ETMeOut)
+{
+    WDOG->CNT = 0x20C5; 
+    WDOG->CNT = 0x28D9;
+    WDOG->TOVAL8B.TOVALL  = u16ETMeOut;
+    WDOG->TOVAL8B.TOVALH  = u16ETMeOut >> 8;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief set window value for WDOG.
+*        
+* @param[in]   u16WinETMe  window value to WIN register.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*
+*****************************************************************************/
+
+__STATIC_INLINE void WDOG_SetWindow(uint16_t u16WinETMe)
+{
+    WDOG->CNT = 0x20C5; 
+    WDOG->CNT = 0x28D9;
+    WDOG->WIN8B.WINL  = u16WinETMe;
+    WDOG->WIN8B.WINH  = u16WinETMe >> 8;
+}
+
+/*****************************************************************************//*!
+*
+* @brief check if watchdog reset occurs.
+*        
+* @param    none.
+*
+* @return   TRUE if watchdog reset occurs, FALSE otherwise.
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+__STATIC_INLINE uint8_t WDOG_IsReset(void)
+{
+    if(SIM_GetStatus(SIM_SRSID_WDOG_MASK))
+    {
+        return (TRUE);
+    }
+    return (FALSE);
+}
+
+/*! @} End of wdog_api_list                                                    					*/
+
+
+void WDOG_Init(WDOG_ConfigPtr pConfig);
+void WDOG_DeInit(void);
+void WDOG_Disable(void);
+void WDOG_DisableWDOGEnableUpdate(void);
+void WDOG_Enable(void);
+void WDOG_Feed(void);
+void WDOG_SetETMeOut(uint16_t u16ETMeOut);
+void WDOG_SetWindow(uint16_t u16WinETMe);
+void WDOG_EnableUpdate(void);
+void WDOG_DisableUpdate(void);
+uint8_t WDOG_IsReset(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+/********************************************************************/
+#endif /* __WDOG_H__ */
+

bsp/nv32f100x/lib/src/acmp.c

@@ -0,0 +1,215 @@
+
+/******************************************************************************
+*
+* @brief providing APIs for configuring ACMP. 
+*
+*******************************************************************************
+*
+* provide APIs for configuring ACMP
+******************************************************************************/
+#include "common.h"
+#include "acmp.h"
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+ACMP_CallbackPtr ACMP_Callback[2] = {(ACMP_CallbackPtr)NULL};
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+/******************************************************************************
+* Global functions
+******************************************************************************/
+void ACMP0_Isr(void);
+void ACMP1_Isr(void);
+
+/******************************************************************************
+* ACMP api list.
+*
+*//*! @addtogroup acmp_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief initialize ACMP as per control field.
+*        
+* @param   pACMPx         pointer to an ACMP register base.
+* @param   pConfig        control parameters.  
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see   ACMP_DeInit.  
+*
+*****************************************************************************/
+void ACMP_Init(ACMP_Type *pACMPx, ACMP_ConfigType *pConfig) 
+{
+    if(ACMP0 == pACMPx)
+    {    
+        /* enable clock to ACMP */
+        SIM->SCGC |= SIM_SCGC_ACMP0_MASK;
+ 
+        /* enable ACMP interrupt */
+        if(pConfig->sCtrlStatus.bits.bIntEn)
+            NVIC_EnableIRQ(ACMP0_IRQn);
+    }
+    else
+    {
+        SIM->SCGC |= SIM_SCGC_ACMP1_MASK;
+        if(pConfig->sCtrlStatus.bits.bIntEn)
+            NVIC_EnableIRQ(ACMP1_IRQn);            
+    }
+    /* neg and pos pin are not equal */
+    pACMPx->C0 = pConfig->sPinSelect.byte;
+    ACMP_ConfigDAC(pACMPx, &pConfig->sDacSet );
+    //pACMPx->C1 = pConfig->sDacSet.byte;
+    pACMPx->C2 = pConfig->sPinEnable.byte;
+    pACMPx->CS = pConfig->sCtrlStatus.byte;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief write ACMP register bits.
+*        
+* @param   pACMPx      pointer to an ACMP register base.
+* @param   pDACConfig   pointer to an ACMP DAC control structure.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+void ACMP_ConfigDAC(ACMP_Type *pACMPx, ACMP_DACType *pDACConfig) 
+{
+    pACMPx->C1 = pDACConfig->byte;  
+}
+
+/*****************************************************************************//*!
+*
+* @brief deinit ACMP module.
+*        
+* @param   pACMPx      pointer to an ACMP register base.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see   ACMP_Init.  
+*
+*****************************************************************************/
+void ACMP_DeInit(ACMP_Type *pACMPx) 
+{
+    if(ACMP0 == pACMPx)
+    {    
+        if(pACMPx->CS & ACMP_CS_ACIE_MASK)
+            NVIC_DisableIRQ(ACMP0_IRQn);
+    }
+    else
+    {
+        if(pACMPx->CS & ACMP_CS_ACIE_MASK)
+            NVIC_DisableIRQ(ACMP1_IRQn);            
+    }
+    
+    pACMPx->CS = 0;
+    pACMPx->C0 = 0;
+    pACMPx->C1 = 0;
+    pACMPx->C2 = 0;
+    
+    if(ACMP0 == pACMPx)
+    {    
+        SIM->SCGC &= ~SIM_SCGC_ACMP0_MASK;
+    }
+    else
+    {
+        SIM->SCGC &= ~SIM_SCGC_ACMP1_MASK;           
+    } 
+}
+
+/*****************************************************************************//*!
+*
+* @brief  set up ACMP callback routines to be called by interrupt service routine.
+*        
+* @param  pACMPx       pointer to an ACMP register base. 
+* @param   pfnCallback  callback routine.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+void ACMP_SetCallback(ACMP_Type *pACMPx, ACMP_CallbackPtr pfnCallback)
+{
+    if(ACMP0 == pACMPx)
+    {
+        ACMP_Callback[0] = pfnCallback;
+    }
+    else
+    {
+        ACMP_Callback[1] = pfnCallback;
+    }
+}
+
+/*! @} End of acmp_api_list                                                  */
+
+
+/*****************************************************************************//*!
+*
+* @brief  ACMP0 interrupt service routine.
+*        
+* @param  none. 
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+void ACMP0_Isr(void)
+{
+
+    if(ACMP_Callback[0])
+    {
+        ACMP_Callback[0]();             /* call callback routine */
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  ACMP1 interrupt service routine.
+*        
+* @param  none. 
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+void ACMP1_Isr(void)
+{
+
+    if(ACMP_Callback[1])
+    {
+        ACMP_Callback[1]();             /* call callback routine */
+    }
+}
+
+

bsp/nv32f100x/lib/src/adc.c

@@ -0,0 +1,336 @@
+/******************************************************************************
+* @brief providing APIs for configuring ADC module (ADC). 
+*
+*******************************************************************************
+*
+* provide APIs for configuring ADC module (ADC)
+******************************************************************************/
+#include "common.h"
+#include "adc.h"
+/******************************************************************************
+* Local function
+******************************************************************************/
+ADC_CallbackType ADC_Callback[1] = {NULL};
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* define ADC APIs
+*
+*//*! @addtogroup adc_api_list
+* @{
+*******************************************************************************/
+
+
+/*****************************************************************************//**
+   *
+   * @brief initialize ADC module.
+   *
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  pADC_Config point to ADC configuration structure. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+void ADC_Init(ADC_Type *pADC, ADC_ConfigTypePtr pADC_Config)
+{
+    if( pADC == ADC)
+    {
+        SIM->SCGC |= SIM_SCGC_ADC_MASK;
+    }
+
+    /* set clock cource for ADC */
+    ADC_SelectClock(pADC,pADC_Config->u8ClockSource);
+
+    /* set clock divide */
+    ADC_SelectClockDivide(pADC,pADC_Config->u8ClockDiv);
+
+    /* set ADC mode */
+    ADC_SetMode(pADC,pADC_Config->u8Mode);
+
+    /* set FIFO level */
+    ADC_SetFifoLevel(pADC,pADC_Config->u8FiFoLevel);
+
+    /* set pin control */
+    pADC->APCTL1 = pADC_Config->u16PinControl;
+
+    if( pADC_Config->sSetting.bCompareEn )
+    {
+        ADC_CompareEnable(pADC);
+    }
+    
+    if( pADC_Config->sSetting.bCompareGreaterEn )
+    {
+        ADC_CompareGreaterFunction(pADC);
+    }
+        
+    if( pADC_Config->sSetting.bContinuousEn )
+    {
+        ADC_ContinuousConversion(pADC);
+    }
+        
+    if( pADC_Config->sSetting.bCompareAndEn ) 
+    {
+        ADC_CompareFifoAnd(pADC);
+    }
+    
+    if( pADC_Config->sSetting.bFiFoScanModeEn )
+    {
+        ADC_FifoScanModeEnable(pADC);
+    }
+    
+    if( pADC_Config->sSetting.bHardwareTriggerEn )
+    {
+        ADC_SetHardwareTrigger(pADC);
+    }
+
+    if( pADC_Config->sSetting.bIntEn )
+    {
+        ADC_IntEnable(pADC);
+        NVIC_EnableIRQ( ADC0_IRQn );
+    } 
+
+    if( pADC_Config->sSetting.bLongSampleEn )
+    {
+        ADC_SetLongSample(pADC);
+    } 
+
+    if( pADC_Config->sSetting.bLowPowerEn )
+    {
+        ADC_SetLowPower(pADC);
+    }
+
+#if !defined(CPU_NV32)
+
+    if( pADC_Config->sSetting.bHTRGMEn )
+    {
+        ADC_HardwareTriggerMultiple(pADC);
+    }
+    else
+    {
+		ADC_HardwareTriggerSingle(pADC);
+    }
+    if( pADC_Config->sSetting.bHTRGMASKEn )
+    {
+        ADC_HardwareTriggerMaskEnable(pADC);
+    }
+    else
+    {
+		ADC_HardwareTriggerMaskDisable(pADC);
+    }
+    if( pADC_Config->sSetting.bHTRGMASKSEL )
+    {
+        ADC_HardwareTriggerMaskAuto(pADC);
+    }
+    else
+    {
+		ADC_HardwareTriggerMaskNonAuto(pADC);
+    }
+#endif
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief disable ADC module.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+void ADC_DeInit( ADC_Type *pADC )
+{
+    ADC_SetChannel(pADC,ADC_CHANNEL_DISABLE);
+
+    SIM->SCGC &= ~SIM_SCGC_ADC_MASK;
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief start a conversion and get conversion result
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u8Channel adc channel to conversion. 
+   *
+   * @return ADC conversion result.
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+unsigned int ADC_PollRead( ADC_Type *pADC, uint8_t u8Channel )
+{
+		ADC_SetChannel(pADC,u8Channel);
+		while( !ADC_IsCOCOFlag(pADC) );
+		return ADC_ReadResultReg(pADC);
+}
+
+
+/*****************************************************************************//*!
+   *
+   * @brief install ADC call back function.
+   *        
+   * @param[in]	 pADC_CallBack point to address of  adc call back function.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+void ADC_SetCallBack(ADC_CallbackType pADC_CallBack)
+{
+    ADC_Callback[0] = pADC_CallBack;
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief set ADC channel.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u8Channel adc channel to conversion. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+void ADC_SetChannel( ADC_Type *pADC, uint8_t u8Channel )
+{
+    uint32_t u32temp;    
+    u32temp = pADC->SC1; 
+    u32temp &= ~ADC_SC1_ADCH_MASK;
+    pADC->SC1 = u32temp|ADC_SC1_ADCH(u8Channel);   
+}
+/*****************************************************************************//*!
+   *
+   * @brief Voltage Reference Selection.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u8Vref adc reference voltage selection. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+void ADC_VrefSelect( ADC_Type *pADC, uint8_t u8Vref )
+{
+    uint32_t u32Temp;
+    u32Temp = pADC->SC2;
+    u32Temp &= ~ADC_SC2_REFSEL_MASK;
+    pADC->SC2 = u32Temp|ADC_SC2_REFSEL(u8Vref);
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief select clock divide
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u8Div Clock Divide Select. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+void ADC_SelectClockDivide( ADC_Type *pADC, uint8_t u8Div )
+{
+    uint32_t u32Temp;
+    u32Temp = pADC->SC3;
+    u32Temp &= ~ADC_SC3_ADIV_MASK;
+    pADC->SC3 = u32Temp|ADC_SC3_ADIV(u8Div);
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief set ADC mode.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u8Mode Conversion Mode Selection. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+void ADC_SetMode( ADC_Type *pADC, uint8_t u8Mode )
+{
+    uint32_t u32Temp;
+    u32Temp = pADC->SC3;
+    u32Temp &= ~ADC_SC3_MODE_MASK;
+    pADC->SC3 = u32Temp|ADC_SC3_MODE(u8Mode);
+}
+/*****************************************************************************//*!
+   *
+   * @brief Input Clock Select.
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u8Clock Input Clock Select. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+void ADC_SelectClock( ADC_Type *pADC, uint8_t u8Clock )
+{
+    uint32_t u32Temp;
+    u32Temp = pADC->SC3;
+    u32Temp &= ~ADC_SC3_ADICLK_MASK;
+    pADC->SC3 = u32Temp|ADC_SC3_ADICLK(u8Clock);
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief FIFO Depth enables
+   *        
+   * @param[in]  pADC point to ADC module type. 
+   * @param[in]  u8FifoLevel set FIFO level. 
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+void ADC_SetFifoLevel( ADC_Type *pADC, uint8_t u8FifoLevel )
+{
+    uint32_t u32Temp;
+    u32Temp = pADC->SC4;
+    u32Temp &= ~ADC_SC4_AFDEP_MASK;
+    pADC->SC4 = u32Temp|ADC_SC4_AFDEP(u8FifoLevel);
+}
+
+/*! @} End of adc_api_list                                               						*/
+
+
+/*****************************************************************************//*!
+   *
+   * @brief ADC interrupt service routine.
+   *        
+   * @param  none. 
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+void ADC_Isr(void)
+{ 
+//	printf("input any character to start a new conversion!\n");
+    if( ADC_Callback[0] )
+    {
+        ADC_Callback[0]();
+    }
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

bsp/nv32f100x/lib/src/arm_cm0.c

@@ -0,0 +1,77 @@
+/******************************************************************************
+* @brief provide generic high-level routines for ARM Cortex M0/M0+ processors. 
+*
+*******************************************************************************/
+
+#include "common.h"
+
+/***********************************************************************/
+/*
+ * Configures the ARM system control register for STOP (deep sleep) mode
+ * and then executes the WFI instruction to enter the mode.
+ *
+ * Parameters:
+ * none
+ *
+ * Note: Might want to change this later to allow for passing in a parameter
+ *       to optionally set the sleep on exit bit.
+ */
+
+void stop (void)
+{
+	/* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */
+	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;	
+
+	/* WFI instruction will start entry into STOP mode */
+#ifndef KEIL
+        // If not using KEIL's uVision use the standard assembly command
+	asm("WFI");
+#else
+        // If using KEIL's uVision, use the CMSIS intrinsic
+	__wfi();
+#endif
+}
+/***********************************************************************/
+/*
+ * Configures the ARM system control register for WAIT (sleep) mode
+ * and then executes the WFI instruction to enter the mode.
+ *
+ * Parameters:
+ * none
+ *
+ * Note: Might want to change this later to allow for passing in a parameter
+ *       to optionally set the sleep on exit bit.
+ */
+
+void wait (void)
+{
+	/* Clear the SLEEPDEEP bit to make sure we go into WAIT (sleep) mode instead
+	 * of deep sleep.
+	 */
+	SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;	
+
+	/* WFI instruction will start entry into WAIT mode */
+#ifndef KEIL
+        // If not using KEIL's uVision use the standard assembly command
+	asm("WFI");
+#else
+        // If using KEIL's uVision, use the CMSIS intrinsic
+    __wfi();
+#endif
+}
+/***********************************************************************/
+/*
+ * Change the value of the vector table offset register to the specified value.
+ *
+ * Parameters:
+ * vtor     new value to write to the VTOR
+ */
+
+void write_vtor (int vtor)
+{
+        /* Write the VTOR with the new value */
+        SCB->VTOR = vtor;	
+}
+
+/***********************************************************************/
+

bsp/nv32f100x/lib/src/crc.c

@@ -0,0 +1,256 @@
+/******************************************************************************
+* @brief    Cyclic redundancy check (CRC) source code. 
+*
+******************************************************************************/
+#include "common.h"
+#include "crc.h"
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define CRC APIs
+*
+*//*! @addtogroup crc_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief initialize CRC with poly per control parameters
+*        
+* @param[in]  pConfig point to configuration. 
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void CRC_Init(CRC_ConfigType *pConfig)
+{       
+    uint32_t     u32Sc ;
+    
+    u32Sc      = 0;
+    
+    SIM->SCGC |= SIM_SCGC_CRC_MASK;  
+    
+    u32Sc     |= ((pConfig->bWidth & 0x01)<<24);    
+    u32Sc     |= CRC_CTRL_TOTR(pConfig->bTransposeReadType & 0x03); 
+    u32Sc     |= CRC_CTRL_TOT(pConfig->bTransposeWriteType & 0x03);
+    
+    if (pConfig->bFinalXOR)
+    {
+        u32Sc |= CRC_CTRL_FXOR_MASK;        
+    }
+    
+    CRC0->CTRL  = u32Sc;
+
+    if ( pConfig->bWidth )      
+    {
+        CRC0->GPOLY = pConfig->u32PolyData;
+    }
+    else 
+    {
+        CRC0->GPOLY_ACCESS16BIT.GPOLYL = pConfig->u32PolyData;  /*!< only 16-bit write allowed */             
+    }  
+    
+}     
+
+
+/*****************************************************************************//*!
+*
+* @brief crc module 16-bit mode calculation.
+*        
+* @param[in]  seed  
+* @param[in]  msg  poiont to message buffer
+* @param[in]  sizeBytes  size of message
+*
+* @return data_out convertion result
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint32_t CRC_Cal16(uint32_t seed, uint8_t *msg, uint32_t sizeBytes)
+{
+  uint32_t ctrl_reg,data_out,data_in;
+  uint8_t  *pCRCBytes;
+  uint32_t sizeWords;
+  uint32_t i,j;  
+  
+  /* Input seed, Set WaS=1 */
+  ctrl_reg  = CRC0->CTRL;
+  CRC0->CTRL  = ctrl_reg | CRC_CTRL_WAS_MASK;
+  CRC0->ACCESS16BIT.DATAL = seed;
+  
+  /*Input data, Set WaS=0*/
+  CRC0->CTRL  = ctrl_reg & 0xFD000000;
+
+  /*Wait for calculation completion*/
+  sizeWords = sizeBytes>>1;
+  j = 0;
+  for(i=0;i<sizeWords;i++){ 
+      data_in = (msg[j] << 8) | (msg[j+1]);
+      j += 2;
+      CRC0->ACCESS16BIT.DATAL =data_in; 
+  }
+  if (j<sizeBytes)
+  { 
+     pCRCBytes = (uint8_t*)&CRC0->ACCESS8BIT.DATALL;
+     *pCRCBytes++ = msg[j];
+  }
+    data_out=CRC0->ACCESS16BIT.DATAL;
+  
+  return(data_out);
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief crc module 32-bit mode calculation.
+*        
+* @param[in]  seed 
+* @param[in]  msg  poiont to message buffer
+* @param[in]  sizeBytes  size of message
+*
+* @return data_out convertion result 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint32_t CRC_Cal32(uint32_t seed, uint8_t *msg, uint32_t sizeBytes)
+{  
+  uint32_t ctrl_reg,data_out,data_in;
+  uint32_t sizeDwords;
+  uint8_t  *pCRCBytes;
+  uint32_t i,j;
+  
+  /*Input seed, Set WaS=1*/
+  ctrl_reg = CRC0->CTRL;
+  CRC0->CTRL = ctrl_reg | 0x02000000;
+  CRC0->DATA = seed;
+ 
+  /*Input data, Set WaS=0*/
+  CRC0->CTRL = ctrl_reg & 0xFD000000;
+  
+  /*Wait for calculation completion*/
+  sizeDwords = sizeBytes>>2;
+  j = 0;
+  for(i=0;i<sizeDwords;i++)
+  { 
+      data_in = ((msg[j] << 24) | (msg[j+1] << 16) | (msg[j+2] << 8) | msg[j+3]);
+      j += 4;
+      CRC0->DATA = data_in; 
+  }
+  if (j<sizeBytes)
+  {
+    pCRCBytes = (uint8_t*)&CRC0->ACCESS8BIT.DATALL;
+
+#if  defined(BYTE_ENABLES_1_2_4_8)    
+    
+    /*write single byte*/  
+    for(;j<sizeBytes;j++)
+    {     
+       *pCRCBytes++ = msg[j];
+    }
+#elif  defined(BYTE_ENABLES_3_6_C)
+    
+    /*write two bytes*/ 
+    data_in = 0;
+    i = 0;
+    for(;j<sizeBytes;j++)
+    {     
+      data_in = (data_in <<8) | msg[j];
+      i++;
+      if (i==2)
+      {
+        i = 0;
+        CRC0->ACCESS16BIT.DATAL = data_in;
+      }
+    }
+    if (i==1)
+    {
+       CRC0->ACCESS8BIT.DATALL = data_in;                /*!< write last byte */
+    }
+#elif  defined(BYTE_ENABLES_7_E)                         
+    /*!< write three bytes */
+    data_in = 0;
+    i = 0;
+    for(;j<sizeBytes;j++)
+    {     
+      data_in = (data_in <<8) | msg[j];
+      i++;
+      if (i==3)
+      {
+        i = 0;
+        /*write first  char*/
+        CRC0->ACCESS8BIT.DATAHL  = (data_in>>16) & 0xff; /*!< write low byte of high word */
+        /*write last two chars*/
+        CRC0->ACCESS16BIT.DATAL = data_in & 0x00ffff;    /*!< write low word */
+       }
+    }
+    if ( i == 2)
+    {
+       CRC0->ACCESS16BIT.DATAL = (data_in);              /*!< write last 2 bytes */
+    }
+    else if (i == 1)
+    {
+       CRC0->ACCESS8BIT.DATALL = data_in;                /*!< write last byte */      
+    }
+#else                                                    /*!< write low byte only */
+    for(;j<sizeBytes;j++)
+    {     
+       *pCRCBytes = msg[j];
+    }
+#endif            
+  }
+  data_out=CRC0->DATA;
+
+  return(data_out);
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief de-initialize crc module, reset crc register.
+*        
+* @param none 
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void CRC_DeInit(void)
+{  
+   CRC0->CTRL  = 0x3000000; /*!< prepare for write 32-bit seed*/ 
+   CRC0->DATA  = 0xFFFFFFFF;/*!< write 32-bit seed to data register*/ 
+   while(!(CRC0->DATA == 0xFFFFFFFF));
+   CRC0->GPOLY = 0x00001021; 
+   CRC0->CTRL  = 0;         /*!< reset ctrl register*/  
+   SIM->SCGC &= ~SIM_SCGC_CRC_MASK;
+}
+
+/*! @} End of crc_api_list                                                   */
+
+

bsp/nv32f100x/lib/src/eeprom.c

@@ -0,0 +1,345 @@
+#include "flash.h"
+#include "eeprom.h"
+#include <string.h>
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+
+
+/******************************************************************************
+*
+* EEPROM 擦除命令，擦掉eeprom
+*输入参数：地址，函数将会擦除adr所在的512bytes eeprom
+*
+******************************************************************************/
+uint16_t Adress_Js(uint32_t adr)
+{
+    uint16_t err = EEPROM_ERR_SUCCESS;
+
+  
+    if(adr & 0x03)
+    {
+        err = EEPROM_ERR_INVALID_PARAM;
+	return (err);
+	}
+  
+    if(adr >1024)
+    {
+        err=EEPROM_ADR_OverFlow;
+      return(err);
+    }
+    return(err);
+}
+
+/******************************************************************************
+*
+* EEPROM 擦除命令，擦掉eeprom
+*输入参数：地址，函数将会擦除adr所在的512bytes eeprom
+*
+******************************************************************************/
+
+
+uint16_t EEPROM_Erase(uint32_t adr)
+{
+    uint16_t err = EEPROM_ERR_SUCCESS;
+    uint32_t e_adr;
+
+     if(adr & 0x03)
+    {
+        err = EEPROM_ERR_INVALID_PARAM;
+	return (err);
+	}
+  
+    if(adr >1024)
+    {
+        err=EEPROM_ADR_OverFlow;
+    
+      return(err);
+    }
+    
+    e_adr=adr+EEPROM_START_ADR;
+    err = Flash_EraseSector(e_adr);  
+    return(err);
+}
+
+/******************************************************************************
+*
+* EEPROM 读取函数，读取地址所在的eeprom
+*输入参数：地址
+*
+******************************************************************************/
+uint32_t EEPROM_Read(uint32_t adr)
+{
+    uint16_t err = EEPROM_ERR_SUCCESS;
+    uint32_t e_adr;
+    uint32_t data;
+    
+    if(adr & 0x03)
+    {
+        err = EEPROM_ERR_INVALID_PARAM;
+	return (err);
+	}
+  
+    if(adr >1024)
+    {
+        err=EEPROM_ADR_OverFlow;
+      return(err);
+    }
+    
+    e_adr=adr+EEPROM_START_ADR;
+    data = M32(e_adr);
+    return(data);
+    
+}
+/******************************************************************************
+*
+* EEPROM 写函数，写地址所在的eeprom
+*写之前读取出来，判断eeprom是否为空，如果为空，则直接写
+*如果非空，则先把整个512bytes sector读取到sram，修改要写的位置
+*然后再写入到flash，模拟一个eeprom的写过程
+*输入参数：地址
+*
+******************************************************************************/
+uint16_t EEPROM_Write(uint32_t adr, uint32_t Data)
+{
+  
+    uint32_t err = EEPROM_ERR_SUCCESS;
+    uint32_t e_adr;
+    uint32_t r_data;
+    uint16_t i;
+    uint32_t start_adr;
+ //   uint32_t modify_adr;
+    uint32_t EEPROM_DATA[128];
+
+    if(adr & 0x03)
+    {
+        err = EEPROM_ERR_INVALID_PARAM;
+	return (err);
+	}
+  
+    if(adr >1024)
+    {
+        err=EEPROM_ADR_OverFlow;
+      return(err);
+    }
+
+    
+    r_data = EEPROM_Read(adr);
+    
+    e_adr=adr+EEPROM_START_ADR;
+
+    if(r_data== EEPROM_BLANK) //如果要写的位置是空的，则直接写
+    {
+      err= Flash_Program1LongWord(e_adr,Data);
+    }
+   else if((r_data&Data) == Data)//如果要写的位置对应的bit，和要写的数据一致，或者是1，也是可以直接写
+     {
+      err= Flash_Program1LongWord(e_adr,Data);
+    }
+    else if(r_data == Data) //如果要写的数据和现有的数据一致，就不进行任何操作，直接返回
+    {
+      return(err);
+    }
+    else
+    {
+        start_adr = e_adr & EEPROM_SECTOR_MASK; //计算出sector的头地址    
+        
+        for( i=0;i<128;i++ ) //如果要写的位置不为空，则先把flash内容读取出来，放在sram中，修改
+        {
+          EEPROM_DATA[i] = M32(start_adr + 4*i);
+        }
+            
+        EEPROM_DATA[(adr&EEPROM_ARRAY_ADR_MASK)>>2] = Data; //修改SRAM 中的数据
+        
+        err=EEPROM_Erase(adr);
+     
+        err=Flash_Program(start_adr,(uint8_t*)EEPROM_DATA,512);//然后写入flash
+    }
+    return(err);
+    
+}
+
+/******************************************************************************
+*
+*Byte 写函数
+*
+******************************************************************************/
+uint16_t EEPROM_WriteByte(uint32_t adr, uint8_t Data)
+{
+    uint32_t err = EEPROM_ERR_SUCCESS;
+    uint32_t data_mask;
+    uint32_t r_data;
+    uint32_t data_m0;
+    uint32_t data_m1;
+    uint32_t word_adr = adr &0x3fc;
+    uint32_t  b_sit= adr & 0x3;
+    
+
+ //先让高位为FF
+    data_m0 = Data << b_sit*8;   
+    data_mask = 0xFFFFFFFF<<(b_sit+1)*8;    
+//   printf("datam0:=0x%x \n",data_m0);    
+//然后让低位为FF    
+     data_m1 = 0xFFFFFFFF >> (32-b_sit*8);
+     data_m1 = data_m1 | data_m0 | data_mask ;
+     
+//    printf("datam1:=0x%x \n",data_m1);  
+    
+    r_data = EEPROM_Read(word_adr);
+//    printf("r_data:=0x%x \n",r_data);        
+//或上原来的数据    
+    data_m1 = data_m1 & r_data;
+		
+    
+//    printf("data_m1:=0x%x \n",data_m1);     ;           
+    err = EEPROM_Write(word_adr , data_m1);
+    
+    return(err);
+
+}
+
+/******************************************************************************
+*
+*Byte 读函数
+*
+******************************************************************************/
+uint8_t EEPROM_ReadByte(uint32_t adr)
+{
+   uint32_t r_data;
+   uint32_t word_adr = adr &0x3fc;
+   uint32_t b_sit= adr & 0x3;
+   uint8_t  data;
+   
+    r_data = EEPROM_Read(word_adr);
+    data = (r_data>>b_sit*8)& 0xff;
+    return(data);
+   
+   
+}
+
+
+/******************************************************************************
+*
+*写函数，写一个长度为bytesize，到eeprom
+*先把1k的eeprom读取放入sram，然后修改要写的位置，
+*这个函数是还可以再优化的
+*这样更改后，没有考虑2K eeprom 。超过2K 也是完全可以的。
+******************************************************************************/
+uint16_t EERPOM_Writeup4byte(uint32_t adr,uint8_t *pData,uint32_t length)
+{
+	uint8_t buf[512];
+	uint8_t *pbuf;
+	uint32_t e_adr;
+	uint32_t e_sec;
+	uint32_t e_offset;
+	uint32_t a;
+	uint32_t err = EEPROM_ERR_SUCCESS;
+	
+   #ifdef IAR
+    if(adr & 0x03)
+    {
+        err = EEPROM_ERR_INVALID_PARAM;
+	      return (err);
+	   }
+    #endif
+  
+    if((adr + length )>1024)
+    {
+        err=EEPROM_ADR_OverFlow;
+      return(err);
+    }
+    
+	e_adr=adr+EEPROM_START_ADR;
+	e_sec=e_adr & EEPROM_SECTOR_MASK;
+	e_offset=e_adr & 0x1ff;
+
+	
+	while (length>0){
+          //如果起始地址不等于0，或者长度小于512 都进入这个循环
+		if (e_offset||(length<512)){
+			pbuf=buf;
+			a=512-e_offset;
+			a=(length>a?a:length);
+			
+			memcpy(buf,(uint8_t*)e_sec,512);
+			memcpy(&buf[e_offset],pData,a);
+			pData+=a;
+			length-=a;
+			e_offset=0;
+
+		}else{ //如果起始地址等于0且长度大于512 则简单了
+			pbuf=pData;
+			pData+=512;
+			length-=512;
+		}
+		err=Flash_EraseSector(e_sec);
+		err=Flash_Program(e_sec,(uint8_t*)pbuf,512);//然后写入flash
+		e_sec+=0x200;
+	}
+	return err;
+}
+
+
+/*
+uint16_t EERPOM_Writeup4byte(uint32_t adr,uint8_t *pData,uint32_t bytesize)
+{
+    uint32_t err = EEPROM_ERR_SUCCESS;
+    uint32_t e_adr;
+    uint16_t i;
+    uint32_t start_adr;
+    uint32_t EEPROM_DATA[256];
+    uint32_t longword = bytesize >>2;
+    uint32_t *pwData = (uint32_t*)pData ;
+    
+    err=Adress_Js(adr);
+    
+    if(adr+bytesize >1024) //如果写入的地址,加上要写的数据的个数大于1024，则报错
+    {
+      err = EEPROM_ADR_OverFlow;
+      return(err);
+    }
+    
+    e_adr=adr+EEPROM_START_ADR;
+    
+    start_adr = e_adr & EEPROM_SECTOR_MASK; //计算出sector 头地址
+
+    for( i=0;i<256;i++ ) //先把数据读取到sram
+      {
+        EEPROM_DATA[i] = M32(start_adr + 4*i);
+        }
+    for( i=0 ;i<longword ;i++) //然后修改要写的地址
+      {
+        EEPROM_DATA[(adr>>2)+i] = *pwData++;
+      }
+     //先erase掉2个eeprom secoter     
+     err=EEPROM_Erase(0x000);
+     err=EEPROM_Erase(0x200);   
+      
+    err=Flash_Program(start_adr,(uint8_t*)EEPROM_DATA,1024);//然后写入flash
+    
+    return(err);
+}
+*/
+

bsp/nv32f100x/lib/src/etm.c

@@ -0,0 +1,1207 @@
+
+/******************************************************************************
+* @brief providing APIs for configuring ETM. 
+*
+*******************************************************************************
+*
+* provide APIs for configuring ETM
+******************************************************************************/
+#include "common.h"
+#include "ETM.h"
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+ETM_CallbackPtr ETM_Callback[3] = {(ETM_CallbackPtr)NULL};
+
+
+/******************************************************************************
+* ETM api lists
+*
+*//*! @addtogroup ETM_api_list
+* @{
+*******************************************************************************/
+/*******************************************************************************//*!
+*
+* @brief set the ETM moule clock source and prescale.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    ClockSource           ETM clock source.
+* @param[in]    ClockPrescale         prescale factor.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*******************************************************************************//*!
+*
+* @设置时钟资源及分频系数    
+* @输入     pETM                 指向三个ETM定时器其中一个的基址
+* @输入     ClockSource          ETM 时钟资源
+* @输入     ClockPrescale        分频系数 
+*
+* @无返回
+*
+*********************************************************************************/
+void ETM_ClockSet(ETM_Type *pETM, uint8_t u8ClockSource, uint8_t u8ClockPrescale)
+{
+    uint8_t   u8Temp;
+	//pETM指向的SC寄存器低5位清0，即未选择时钟，时钟输入采取1分频
+    u8Temp  = (pETM->SC & 0xE0);
+	//时钟选择，及预分频因子选择
+    u8Temp |= (ETM_SC_CLKS(u8ClockSource & 0x3) | ETM_SC_PS(u8ClockPrescale & 0x7));
+	//配置该ETM的状态与控制寄存器ETMx_SC
+    pETM->SC = u8Temp;
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM_No to high ture EPWM mode, clock soure is the 
+*        system clock, MOD, CnV are the initial value.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    PWMModeSelect         select CPWM , EPWM  or combine pwm mode.
+* @param[in]    PWMEdgeSelect         select high true or low true pulse.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/******************************************************************************************
+*
+* @ETM中PWM的初始化函数      
+* @输入        pETM                 指向三个ETM定时器其中一个的基址
+* @输入        PWMModeSelect        居中对齐CPWM（10）、边沿对齐EPWM（01）以及级联模式PWM（11）
+* @输入        PWMEdgeSelect        高真脉冲（01）、低真脉冲（10）
+*
+* @无返回
+*
+******************************************************************************************/
+void ETM_PWMInit(ETM_Type *pETM, uint8_t u8PWMModeSelect, uint8_t u8PWMEdgeSelect)
+{
+    uint8_t   channels, i;
+    
+    ASSERT((ETM0== pETM) || (ETM1== pETM) || (ETM2== pETM));//断言检测通道合法性
+    
+    /* open the clock gate */  
+	//使能ETM的时钟
+	if (ETM0 == pETM)
+    {
+        channels = 2;
+        SIM->SCGC |= SIM_SCGC_ETM0_MASK;
+    }
+    else if(ETM1 == pETM)
+    {
+        channels = 2;
+#if !defined(CPU_NV32M3)
+        SIM->SCGC |= SIM_SCGC_ETM1_MASK;
+#endif
+    }        
+    else
+    {
+        channels = 6;
+        SIM->SCGC  |= SIM_SCGC_ETM2_MASK;
+    }
+    
+    pETM->SC  = 0x0;     //关闭计数器          /* disable counter */  
+	pETM->MOD = ETM_MOD_INIT; 
+    
+    if(ETM_PWMMODE_CENTERALLIGNED == u8PWMModeSelect) //使能CPWM   /* enable CPWM */
+    {
+        pETM->SC |= ETM_SC_CPWMS_MASK; 
+    }
+    else if(ETM_PWMMODE_COMBINE == u8PWMModeSelect) // 打开级联PWM模式    /* enable combine pwm mode */
+    {
+        ASSERT(ETM2 == pETM);
+        pETM->MODE    |= ETM_MODE_WPDIS_MASK | ETM_MODE_ETMEN_MASK;
+        pETM->COMBINE = ETM_COMBINE_COMBINE0_MASK | ETM_COMBINE_COMP0_MASK | ETM_COMBINE_SYNCEN0_MASK | ETM_COMBINE_DTEN0_MASK |
+                        ETM_COMBINE_COMBINE1_MASK | ETM_COMBINE_COMP1_MASK | ETM_COMBINE_SYNCEN1_MASK | ETM_COMBINE_DTEN1_MASK |
+                        ETM_COMBINE_COMBINE2_MASK | ETM_COMBINE_COMP2_MASK | ETM_COMBINE_SYNCEN2_MASK | ETM_COMBINE_DTEN2_MASK 
+                        ;     
+        pETM->SC &= ~ETM_SC_CPWMS_MASK; 
+    }
+    if(ETM_PWM_HIGHTRUEPULSE == u8PWMEdgeSelect)
+    {
+        /* Configure ETMers PWM High True Pulses */
+		/* 配置通道寄存器，设置通道状态及通道计数值 */
+        for(i=0; i<channels; i++)
+        {
+            pETM->CONTROLS[i].CnSC = ETM_CnSC_MSB_MASK | ETM_CnSC_ELSB_MASK;  
+            pETM->CONTROLS[i].CnV  = ETM_C0V_INIT + i*100; 
+        }
+    }
+    else if(ETM_PWM_LOWTRUEPULSE == u8PWMEdgeSelect)
+    {
+        /* Configure ETMers for PWM Low True Pulses */
+        for(i=0; i<channels; i++) 
+        {
+            pETM->CONTROLS[i].CnSC = ETM_CnSC_MSB_MASK | ETM_CnSC_ELSA_MASK; 
+            pETM->CONTROLS[i].CnV  = ETM_C0V_INIT + i*100 ; 
+        }
+    }  
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM_No to input capture mode, enable interrupt.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    Channel               channel number to be configured.
+* @param[in]    CaptureMode           select capture edge: rising, falling or both.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************
+*
+* @输入捕捉初始化函数
+*        
+* @输入        pETM                  指向三个ETM定时器其中一个的基址
+* @输入        Channel               配置通道号
+* @输入        CaptureMode           选择捕捉方式:上升沿, 下降沿或跳变沿.
+*
+* @无返回
+*
+*********************************************************************************/
+void ETM_InputCaptureInit(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8CaptureMode)
+{ 
+    ASSERT(((ETM0 == pETM) && (u8ETM_Channel < 2))   || 
+           ((ETM1 == pETM) && (u8ETM_Channel < 2))   || 
+           ((ETM2 == pETM) && (u8ETM_Channel < 6))
+           );
+
+    
+    /* open the clock gate */
+	 /* 使能ETM的时钟 */
+	if ((ETM0 == pETM) && (u8ETM_Channel < 2))
+    {
+        SIM->SCGC |= SIM_SCGC_ETM0_MASK;
+        NVIC_EnableIRQ(ETM0_IRQn);
+    }
+    else if((ETM1 == pETM)  && (u8ETM_Channel < 2))
+    {
+#if !defined(CPU_NV32M3)
+        SIM->SCGC |= SIM_SCGC_ETM1_MASK;
+        NVIC_EnableIRQ(ETM1_IRQn);
+#endif
+    }        
+    else 
+    {
+        SIM->SCGC |= SIM_SCGC_ETM2_MASK;
+        NVIC_EnableIRQ(ETM2_IRQn);
+    }
+    
+    pETM->SC  = 0x0;    //关闭计数器     /* diable counter */ 
+    pETM->MOD = 0xFFFF;  /* free running */
+    
+    if(ETM_INPUTCAPTURE_RISINGEDGE == u8CaptureMode) //使能中断，在上升沿捕捉       /* enable interrupt, Capture on rising edge */
+    {
+        pETM->CONTROLS[u8ETM_Channel].CnSC = ETM_CnSC_CHIE_MASK | ETM_CnSC_ELSA_MASK;
+    }
+    else if(ETM_INPUTCAPTURE_FALLINGEDGE == u8CaptureMode) //在下降沿捕捉      /* Capture on falling edge */
+    {
+        pETM->CONTROLS[u8ETM_Channel].CnSC = ETM_CnSC_CHIE_MASK | ETM_CnSC_ELSB_MASK;
+    }
+    else if(ETM_INPUTCAPTURE_BOTHEDGE == u8CaptureMode) //在上升沿或下降沿捕捉     /* Capture on rising or falling edge */
+    {
+        pETM->CONTROLS[u8ETM_Channel].CnSC = ETM_CnSC_CHIE_MASK | ETM_CnSC_ELSA_MASK | ETM_CnSC_ELSB_MASK;       
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM_No to Dual Edge Capture mode to measure the
+*        width or the period  of a pulse.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    ChannelPair           ChannelPair number to be configured: 0, 2, 4.
+* @param[in]    CaptureMode           select capture edge: one shot and continuous mode.
+* @param[in]    Channel_N_Edge        channel N detect edge. 
+* @param[in]    Channel_Np1_Edge      channel N+1 detect edge.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @对ETM配置双边捕获模式来测量一个脉冲的宽度或周期
+*        
+* @输入        pETM                  指向三个ETM定时器其中一个的基址
+* @输入        ChannelPair           频道配对数的配置为: 0, 2, 4.
+* @输入        CaptureMode           选择单周期捕捉，和连续捕捉方式
+* @输入        Channel_N_Edge        频道N边沿检测 
+* @输入        Channel_Np1_Edge      频道N+1边沿检测.
+*
+* @无返回
+*
+*********************************************************************************/
+void ETM_DualEdgeCaptureInit(ETM_Type *pETM, uint8_t u8ChannelPair, uint8_t u8CaptureMode, 
+                                 uint8_t u8Channel_N_Edge, uint8_t u8Channel_Np1_Edge)
+{ 
+    ASSERT((ETM2 == pETM)  && (u8ChannelPair < 6) && !(u8ChannelPair & 1) );
+    
+    SIM->SCGC |= SIM_SCGC_ETM2_MASK;
+    if((0 == u8ChannelPair) || (2== u8ChannelPair))
+    {
+                                  //通道滤波      /* channel filter is active */
+    }
+       
+    pETM->SC    = 0x0;         //关闭计数器         /* diable counter */ 
+    pETM->MOD   = 0xFFFF;
+    pETM->MODE |= ETM_MODE_ETMEN_MASK;  /* ETMEN = 1 */  
+    /* DECAPEN = 1,  ChannelPair/2 * 8 */
+    pETM->COMBINE |=  ((ETM_COMBINE_DECAPEN0_MASK) << (u8ChannelPair * 4)); 
+    
+    pETM->CONTROLS[u8ChannelPair].CnSC &= ~ETM_CnSC_CHF_MASK;  //清除相关位     /* CH(n)F and CH(n+1)F bits must be cleared first */
+    pETM->CONTROLS[u8ChannelPair + 1].CnSC &= ~ETM_CnSC_CHF_MASK;
+    
+    if(ETM_INPUTCAPTURE_DUALEDGE_ONESHOT == u8CaptureMode)   //单周期模式     /* oneshot mode */
+    {
+        pETM->CONTROLS[u8ChannelPair].CnSC &= ~ETM_CnSC_MSA_MASK;
+        pETM->CONTROLS[u8ChannelPair+1].CnSC &= ~ETM_CnSC_MSA_MASK;
+    }
+    else if(ETM_INPUTCAPTURE_DUALEDGE_CONTINUOUS == u8CaptureMode) //连续模式   /* continuouse mode */
+    {
+        pETM->CONTROLS[u8ChannelPair].CnSC |= ETM_CnSC_MSA_MASK;
+        pETM->CONTROLS[u8ChannelPair+1].CnSC |= ETM_CnSC_MSA_MASK;
+    }
+    
+    pETM->CONTROLS[u8ChannelPair].CnSC |= (u8Channel_N_Edge << 2); //选择检测边沿  /* select detec edge */
+    pETM->CONTROLS[u8ChannelPair + 1].CnSC |= (u8Channel_Np1_Edge << 2);   
+    
+    pETM->COMBINE |=  (ETM_COMBINE_DECAP0_MASK << (u8ChannelPair * 4)); 
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM_No to input capture mode.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    Channel               channel number to be configured.
+* @param[in]    CompareMode           select compare edge: toggle, set and clear.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @输出对比初始化
+* 
+* @输入     pETM                   指向三个ETM定时器其中一个的基址
+* @输入     Channel                必须完成配置通道即通道号
+* @输入     CompareMode            选择模式：翻转（01）、置位（11）、清0（10）
+*
+* @无返回
+*
+*********************************************************************************/
+void ETM_OutputCompareInit(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8CompareMode)
+{
+    ASSERT(((ETM0 == pETM) && (u8ETM_Channel < 2))   || 
+           ((ETM1 == pETM) && (u8ETM_Channel < 2))   || 
+           ((ETM2 == pETM) && (u8ETM_Channel < 6))
+           );
+    
+    /* open the clock gate */
+	 /* 使能ETM的时钟 */
+	if(ETM0 == pETM)
+    {
+        SIM->SCGC |= SIM_SCGC_ETM0_MASK;
+    }
+    else if(ETM1 == pETM)
+    {
+#if !defined(CPU_NV32M3)
+        SIM->SCGC |= SIM_SCGC_ETM1_MASK;
+#endif
+    }        
+    else
+    {
+        SIM->SCGC |= SIM_SCGC_ETM2_MASK;
+    }
+    
+    pETM->SC  = 0x0;                                                 //关闭计数器                  /* diable counter */
+    pETM->MOD = ETM_MOD_INIT; 
+    pETM->CONTROLS[u8ETM_Channel].CnSC = (ETM_CnSC_MSA_MASK | (u8CompareMode << 2)); //选择检测边沿   /* select detec edge */
+    pETM->CONTROLS[u8ETM_Channel].CnV  = ETM_C0V_INIT;
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM2 to start software synchronization.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @运用ETM2来实现软件同步
+*        
+* @输入       pETM                   指向三个ETM定时器其中一个的基址
+*
+* @无返回
+*
+*********************************************************************************/
+void ETM_SoftwareSync(ETM_Type *pETM)
+{
+    ASSERT(ETM2 == pETM);
+
+    pETM->SYNCONF   |= ETM_SYNCONF_SYNCMODE_MASK;   // 选择增强PWM同步  /* recommend enhanced sync mode */
+    pETM->SYNC      |= ETM_SYNC_SWSYNC_MASK;
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM to enable hardware synchronization.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    u8TriggerN            select the hardware trigger source.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/********************************************************************
+* @ETM中配置ETMx_SYNC 寄存器来保证软件同步        
+* 
+* @输入       pETM                    指向三个ETM定时器其中一个的基址
+* @输入       u8TriggerN              选择硬件触发资源
+*
+* @无返回
+*
+*********************************************************************************/
+void ETM_HardwareSync(ETM_Type *pETM, uint8_t u8TriggerN)
+{
+    ASSERT(ETM2 == pETM);
+    
+    pETM->SYNCONF   |= ETM_SYNCONF_SYNCMODE_MASK; //选择增强PWM同步 /* recommend enhanced sync mode */
+    
+    switch(u8TriggerN)
+    {
+        case ETM_SYNC_TRIGGER_TRIGGER2: 
+                pETM->SYNC |= ETM_SYNC_TRIG2_MASK;
+                break;  
+        case ETM_SYNC_TRIGGER_TRIGGER1: 
+                pETM->SYNC |= ETM_SYNC_TRIG1_MASK;
+                break;   //首先配置ETM0CH0  /* need configure ETM0CH0 first */
+        case ETM_SYNC_TRIGGER_TRIGGER0:
+                pETM->SYNC |= ETM_SYNC_TRIG0_MASK; 
+                break;   //首先配置CMP0  /* need configure CMP0 first */
+        default: 
+                break;
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM to enable hardware synchronization, more then 1 trigger.
+*        
+* @param[in]    pETM               pointer to one of three ETM base register address.
+* @param[in]    u8TriggerMask      select the hardware trigger source. combine TRIG0~TREG2.(x000xxxx~x111xxxx)
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @通过配置ETM保证硬件同步，产生触发
+*        
+* @输入   pETM              指向三个ETM定时器其中一个的基址
+* @输入   u8TriggerMask     选择硬件触发资源. 
+*
+* @无返回.
+*
+*********************************************************************************/
+void ETM_HardwareSyncCombine(ETM_Type *pETM, uint8_t u8TriggerMask)
+{
+    ASSERT(ETM2 == pETM);
+    
+    pETM->SYNCONF   |= ETM_SYNCONF_SYNCMODE_MASK;  //选择增强PWM同步 /* recommend enhanced sync mode */
+    pETM->SYNC      &= 0x8F;
+    pETM->SYNC      |= (u8TriggerMask & 0x70);
+}
+
+/*********************************************************************************//*!
+*
+* @brief generate ETM2 hardware trigger 2,Note: please call ETM_HardwareSyncCombine first.
+*        
+* @param[in]    pETM               pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @产生ETM2硬件触发
+*        
+* @输入        pETM              指向三个ETM定时器其中一个的基址
+*
+* @无返回
+*
+*********************************************************************************/
+void ETM_GenerateTrig2(ETM_Type *pETM)
+{
+    ASSERT(ETM2 == pETM);
+    
+    if(pETM->SYNC & ETM_SYNC_TRIG2_MASK)
+    {
+#if defined(CPU_NV32)
+        SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;
+#elif defined(CPU_NV32M3)
+        SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;
+#elif defined(CPU_NV32M4)
+        SIM->SOPT0  |= SIM_SOPT0_ETMSYNC_MASK;
+#endif
+    }
+}
+
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM_No to start software synchronization.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    PrescalerValue        system clock divide value, 0 to 3.
+* @param[in]    DeadETMeValue         n count clock is inserted, 0 to 63.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @ETM死区时间插入设置.
+*        
+* @输入         pETM                  指向三个ETM定时器其中一个的基址
+* @输入         PrescalerValue        系统时钟分频值
+* @输入         DeadETMeValue         死去插入时间值，0-63可选
+*
+* @无返回
+*
+*********************************************************************************/
+void ETM_PWMDeadETMeSet(ETM_Type *pETM, uint8_t u8PrescalerValue, uint8_t u8DeadETMeValue)
+{
+    ASSERT(ETM2 == pETM);
+    
+    pETM->COMBINE |= 0x101010;     //使能死区时间插入    /* enable dead ETMe insertion */
+
+    if(!(pETM->MODE & ETM_MODE_WPDIS_MASK)) //如果开启了写保护/* if write protection is enabled */
+    {
+        pETM->MODE |= ETM_MODE_WPDIS_MASK; //禁用写保护 /* disable the write protection */
+        pETM->DEADETME = (ETM_DEADETME_DTVAL(u8DeadETMeValue & 0x3F) | ETM_DEADETME_DTPS(u8PrescalerValue & 0x3));
+        pETM->MODE &= ~ETM_MODE_WPDIS_MASK;//使能写保护 /* enable the write protection */       
+    }
+    else 
+    {
+        //如果没有开启写保护     /* if no protection */
+        pETM->DEADETME = (ETM_DEADETME_DTVAL(u8DeadETMeValue & 0x3F) | ETM_DEADETME_DTPS(u8PrescalerValue & 0x3));
+    }
+    pETM->SYNC |= ETM_SYNC_SWSYNC_MASK;    //软件同步 /* software sync */
+}    
+
+/*********************************************************************************//*!
+*
+* @brief set output mask.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    Channel               pwm channel needed to be masked.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @设置输出标志位
+*        
+* @输入           pETM                  指向三个ETM定时器其中一个的基址
+* @输入           Channel               PWM通道位需要被置标志
+*
+* @无返回
+*
+*********************************************************************************/
+void ETM_OutputMaskSet(ETM_Type *pETM, uint8_t u8ETM_Channel)
+{
+    ASSERT((ETM2 == pETM) && (u8ETM_Channel < 6));
+
+    pETM->OUTMASK |= (1 << u8ETM_Channel);
+    
+    if(pETM->SYNC & ETM_SYNC_SYNCHOM_MASK)           //如果需要PWM同步更新   /* if PWM sync is needed */
+    {
+        pETM->SYNCONF |= ETM_SYNCONF_SYNCMODE_MASK;   //选择增强PWM同步  /* recommend enhanced sync mode */
+        if(pETM->SYNCONF & ETM_SYNCONF_SWOM_MASK)    //如果需要软件同步   /* if software sync is needed*/
+        {
+            pETM->SYNC |= ETM_SYNC_SWSYNC_MASK;
+        }
+        else if(pETM->SYNCONF & ETM_SYNCONF_HWOM_MASK)//如果需要硬件同步 /* if hardware sync is needed*/
+        {
+            pETM->SYNC |= ETM_SYNC_TRIG2_MASK;
+            
+#if defined(CPU_NV32)
+            SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;      //硬件同步   /* hardware sync */ 
+#elif defined(CPU_NV32M3)
+            SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;         /* hardware sync */ 
+#elif defined(CPU_NV32M4)
+            SIM->SOPT0  |= SIM_SOPT0_ETMSYNC_MASK;         /* hardware sync */ 
+#endif
+        }
+        else
+        {
+        }
+    }
+    else  /* no need to sync, update on the next rising edge of system clock  */
+    {
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief general configuration to ETM_No to start software synchronization.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    Channel               pwm channel needed to be controlled by software.
+* @param[in]    ChannelValue          the value to be set,  0 or 1.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @配置软件输出控制SWOCTRL寄存器的同步是否由软件触发
+*        
+* @输入        pETM                  指向三个ETM定时器其中一个的基址
+* @输入        Channel               PWM波的通道选择
+* @输入        ChannelValue          0或1,0不触发;1触发
+*
+* @无返回
+*
+*********************************************************************************/
+void ETM_SWOutputControlSet(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8ChannelValue)
+{
+    ASSERT((ETM2 == pETM) && (u8ETM_Channel < 6));
+    
+    if(ETM_SWOCTRL_HIGH == u8ChannelValue)
+    {
+        pETM->SWOCTRL |= (0x0101 << u8ETM_Channel);
+    }
+    else if(ETM_SWOCTRL_LOW == u8ChannelValue)
+    {
+        pETM->SWOCTRL |= (1 << u8ETM_Channel);
+        pETM->SWOCTRL &= ~(0x100 << u8ETM_Channel);
+    }
+    if(pETM->SYNCONF & ETM_SYNCONF_SWOC_MASK)               /* if PWM sync is needed */
+    {
+        pETM->SYNCONF |= ETM_SYNCONF_SYNCMODE_MASK;         /* recommend enhanced sync mode */
+        if(pETM->SYNCONF & ETM_SYNCONF_SWSOC_MASK)          /* if software sync is needed*/
+        {
+            pETM->SYNC |= ETM_SYNC_SWSYNC_MASK;             /* software sync */ 
+        }
+        else if(pETM->SYNCONF & ETM_SYNCONF_HWSOC_MASK)     /* if hardware sync is needed*/
+        {
+            pETM->SYNC |= ETM_SYNC_TRIG2_MASK;
+
+#if defined(CPU_NV32)
+            SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;             /* hardware sync */ 
+#elif defined(CPU_NV32M3)
+            SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;             /* hardware sync */ 
+#elif defined(CPU_NV32M4)
+            SIM->SOPT0  |= SIM_SOPT0_ETMSYNC_MASK;             /* hardware sync */ 
+#endif
+        }
+    }
+    else  /* no need to sync, update on the next rising edge of system clock  */
+    {
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief set PWM polarity.
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    Channel               pwm channel needed to be controlled by software.
+* @param[in]    ActiveValue           the value to be set,  0 or 1.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************
+*
+* @设置通道输出极性的功能函数
+*        
+* @输入     pETM                 指向三个ETM定时器其中一个的基址
+* @输入     Channel              PWM波的通道选择
+* @输入     ActiveValue          极性的选择，0为高电平，1为低电平
+*
+* @无返回
+*
+*********************************************************************************/
+void ETM_PolaritySet(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8ActiveValue)
+{
+    ASSERT((ETM2 == pETM) && (u8ETM_Channel < 6));
+    
+    if(ETM_POLARITY_HIGHACTIVE == u8ActiveValue)
+    {
+        pETM->POL &=  ~(1 << u8ETM_Channel);
+    }
+    else if(ETM_POLARITY_LOWACTIVE == u8ActiveValue)
+    {
+        pETM->POL |=  (1 << u8ETM_Channel);
+    }
+}
+
+/*********************************************************************************//*!
+*
+* @brief set ETM behavior in debug mode.
+*        
+* @param[in]    pETM             pointer to one of three ETM base register address.
+* @param[in]    u8DebugMode      debug mode select from 00 to 11.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************
+*
+* @选择BDM模式下的ETM行为
+*        
+* @输入   pETM             指向三个ETM定时器其中一个的基址
+* @输入   u8DebugMode      debug 的模式从00-11之间选择
+*
+* @无返回
+*
+*********************************************************************************/
+void ETM_SetDebugModeBehavior(ETM_Type *pETM, uint8_t u8DebugMode)
+{
+    ASSERT((ETM2 == pETM));
+    pETM->CONF &= ~ETM_CONF_BDMMODE_MASK;
+    pETM->CONF |= ETM_CONF_BDMMODE(u8DebugMode);
+}
+
+/*********************************************************************************//*!
+*
+* @brief Selects the ratio between the number of counter overflows to the number of ETMes the TOF bit is set.
+*        
+* @param[in]    pETM             pointer to one of three ETM base register address.
+* @param[in]    u8TOFNUM         TOF numbers before setting TOF bit, 0~31.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************//*!
+*
+* @ETM中TOF频率大小的设置功能函数
+*        
+* @输入    pETM              指向三个ETM定时器其中一个的基址
+* @输入    u8TOFNUM          TOF频率数，大小0和31之间
+* 
+* @无返回
+*
+*********************************************************************************/
+void ETM_SetTOFFrequency(ETM_Type *pETM, uint8_t u8TOFNUM)
+{
+    ASSERT((ETM2 == pETM));
+    pETM->CONF &= ~ETM_CONF_NUMTOF_MASK;
+    pETM->CONF |= ETM_CONF_NUMTOF(u8TOFNUM);
+}
+
+/*********************************************************************************//*!
+*
+* @brief swap the output of CH(n) and CH(n+1).
+*        
+* @param[in]    pETM                  pointer to one of three ETM base register address.
+* @param[in]    ChannelPair           the pair to be swapped, 0,1,2.
+*    
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*********************************************************************************/
+/*********************************************************************************
+*
+* @交换通道CH（n）和通道CH（n+1）的输出结果   
+*    
+* @输入  pETM                   其中一个ETM定时器的基址
+* @输入  ChannelPair            要被交换的通道数号，即n可为0,1,2,
+*
+*********************************************************************************/
+void ETM_InvertChannel(ETM_Type *pETM, uint8_t u8ChannelPair)
+{
+    ASSERT((ETM2 == pETM)  && u8ChannelPair <= 2);
+
+    pETM->INVCTRL |= 1<<u8ChannelPair;
+    if(pETM->SYNCONF & ETM_SYNCONF_INVC_MASK)     //如果需要PWM同步  /* if PWM sync is needed */
+    {
+        pETM->SYNCONF |= ETM_SYNCONF_SYNCMODE_MASK; //选择增强PWM同步 /* recommend enhanced sync mode */
+        if(pETM->SYNCONF & ETM_SYNCONF_SWINVC_MASK)//如果需要软件同步 /* if software sync is needed*/
+        {
+            pETM->SYNC |= ETM_SYNC_SWSYNC_MASK; //开启软件同步   /* software sync */ 
+        }
+        else if(pETM->SYNCONF & ETM_SYNCONF_HWINVC_MASK)   //如果需要硬件同步 /* if hardware sync is needed*/
+        {
+            pETM->SYNC |= ETM_SYNC_TRIG2_MASK;
+
+#if defined(CPU_NV32)
+            SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;       //硬件同步      /* hardware sync */ 
+#elif defined(CPU_NV32M3)
+            SIM->SOPT  |= SIM_SOPT_ETMSYNC_MASK;             /* hardware sync */ 
+#elif defined(CPU_NV32M4)
+            SIM->SOPT0  |= SIM_SOPT0_ETMSYNC_MASK;             /* hardware sync */ 
+#endif
+        }
+    }
+    else  
+    {
+    }
+}  
+
+/*****************************************************************************//*!
+*
+* @brief configure the ETM as specified control parameters, CnSC and CnV not 
+*        included.
+*        
+* @param[in]    pETM          pointer to one of three ETM base register address.
+* @param[in]    pConfig     pointer to ETM general parameters.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*****************************************************************************//*!
+*
+* @ETM初始化函数
+*        
+* @输入        pETM           指向三个ETM定时器其中一个的基址
+* @输入        pConfig        指向ETM的一些基本参数
+* @无返回值
+*
+*****************************************************************************/
+void ETM_Init(ETM_Type *pETM, ETM_ConfigType *pConfig)
+{
+    ASSERT((ETM0 == pETM) || (ETM1 == pETM) || (ETM2 == pETM));
+    if(ETM0 == pETM)
+    {
+        SIM->SCGC |= SIM_SCGC_ETM0_MASK;
+    }
+#if !defined(CPU_NV32M3)
+    else if(ETM1 == pETM)
+    {
+        SIM->SCGC |= SIM_SCGC_ETM1_MASK;
+    }
+#endif
+    else
+    {
+        SIM->SCGC |= SIM_SCGC_ETM2_MASK;
+    }
+        
+    /* diable counter */
+    pETM->SC = 0; 
+ 	pETM->MODE = pConfig->mode;       
+	pETM->MOD = pConfig->modulo;
+	pETM->CNT = pConfig->cnt;
+        
+    if( pETM->MODE & ETM_MODE_ETMEN_MASK  ) 
+    {
+        /* when ETMEN = 1, all other registers can be written */
+		 /* 当 ETMEN = 1, 所有寄存器都可以被写入 */
+        pETM->COMBINE   = pConfig->combine;      
+        pETM->CNTIN     = pConfig->cntin;      
+        pETM->SYNC      = pConfig->sync;      
+        pETM->OUTINIT   = pConfig->outinit;      
+        pETM->OUTMASK   = pConfig->outmask;      
+        pETM->DEADETME  = pConfig->deadETMe;      
+        pETM->EXTTRIG   = pConfig->exttrig;      
+        pETM->POL       = pConfig->pol;      
+        pETM->FMS       = pConfig->fms;      
+        pETM->FILTER    = pConfig->filter;      
+        pETM->FLTCTRL   = pConfig->fltctrl;    /* fault control */ 
+        pETM->FLTPOL    = pConfig->fltpol;      
+        pETM->CONF      = pConfig->conf;      
+        pETM->SYNCONF   = pConfig->synconf;      
+        pETM->SWOCTRL   = pConfig->swoctrl;      
+        pETM->PWMLOAD   = pConfig->pwmload;      
+    }
+    /* write SC to enable clock */
+    /*通过写入状态控制寄存器SC来使能ETM时钟 */
+    pETM->SC = pConfig->sc;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief  close the ETM moudle.
+*        
+* @param[in]    pETM          pointer to one of three ETM base register address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*****************************************************************************
+*
+*关闭相应的ETM功能组件函数     
+*
+*****************************************************************************/
+void ETM_DeInit(ETM_Type *pETM)
+{
+    ASSERT((ETM0 == pETM) || (ETM1 == pETM) || (ETM2 == pETM));
+    pETM->SC = 0;       
+	pETM->MOD = 0;
+	pETM->CNT = 0;
+    if(ETM2 == pETM) 
+    {
+          pETM->MODE = 0x4; 
+          pETM->COMBINE = 0;      
+          pETM->CNTIN = 0;      
+          pETM->SYNC = 0;      
+          pETM->OUTINIT = 0;      
+          pETM->OUTMASK = 0;      
+          pETM->DEADETME = 0;      
+          pETM->EXTTRIG = 0;      
+          pETM->POL = 0;      
+          pETM->FMS = 0;      
+          pETM->FILTER = 0;      
+          pETM->FLTCTRL = 0;  
+          pETM->FLTPOL = 0;      
+          pETM->CONF = 0;      
+          pETM->SYNCONF = 0;      
+          pETM->SWOCTRL = 0;      
+          pETM->PWMLOAD = 0;      
+    }
+    /* close the clock gate */
+	/* 禁用时钟 */
+	if (ETM0 == pETM)
+    {
+        SIM->SCGC &= ~SIM_SCGC_ETM0_MASK;
+        NVIC_DisableIRQ(ETM0_IRQn);
+    }
+#if !defined(CPU_NV32M3)    
+    else if(ETM1 == pETM)
+    {
+        SIM->SCGC &= ~SIM_SCGC_ETM1_MASK;
+        NVIC_DisableIRQ(ETM1_IRQn);
+    } 
+#endif
+    else if (ETM2 == pETM)
+    {
+        SIM->SCGC &= ~SIM_SCGC_ETM2_MASK;
+        NVIC_DisableIRQ(ETM2_IRQn);
+    }
+}
+    
+/*****************************************************************************//*!
+*
+* @brief configure the ETM  channels, CnSC and CnV are included.
+*        
+* @param[in]    pETM               pointer to one of three ETM base register address.
+* @param[in]    ETM_Channel        ETM channel number.
+* @param[in]    pTETMCH_Params     pointer to ETM channel general parameters.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*****************************************************************************//*!
+*
+* @本函数用来配置ETM通道, 包括通道状态及控制寄存器CnSC和通道计数值寄存器CnV      
+* @输入     pETM                 指向三个ETM定时器其中一个的基址
+* @输入     ETM_Channel          ETM的通道号
+* @输入     pTETMCH_Params      指向ETM通道一般参数的指针
+*
+* @无返回值
+*
+*****************************************************************************/
+void ETM_ChannelInit(ETM_Type *pETM, uint8_t u8ETM_Channel, ETM_ChParamsType *pTETMCH_Params)
+{
+    ASSERT((ETM0 == pETM) || (ETM1 == pETM) || (ETM2 == pETM));  
+    
+	if (ETM0 == pETM)
+    {
+        ASSERT(u8ETM_Channel < 2);
+        SIM->SCGC |= SIM_SCGC_ETM0_MASK;
+    }
+ #if !defined(CPU_NV32M3)
+    else if(ETM1 == pETM)
+    {
+        ASSERT(u8ETM_Channel < 2);
+        SIM->SCGC |= SIM_SCGC_ETM1_MASK;
+    }        
+#endif
+    else
+    {
+        ASSERT(u8ETM_Channel < 6);
+        SIM->SCGC |= SIM_SCGC_ETM2_MASK;
+    }
+    
+    pETM->CONTROLS[u8ETM_Channel].CnSC = pTETMCH_Params->u8CnSC;
+    pETM->CONTROLS[u8ETM_Channel].CnV = pTETMCH_Params->u16CnV; 
+    
+    return;
+}
+
+/*****************************************************************************//*!
+*
+* @brief set the ETM channel value register per duty cycle and modulo for combine mode
+*        odd channel no must be provided and even channel value register is not changed.
+*
+* @param[in]    pETM            pointer to one of three ETM base register address.
+* @param[in]    ETM_Channel     odd channel no:1,3,5.
+* @param[in]    dutyCycle       duty cycle in percentage. e.g. 10, means 10%.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*****************************************************************************//*!
+*
+* 必须设置奇数通道数，且偶数通道的值不变
+*
+* @输入        pETM            指向三个ETM定时器其中一个的基址
+* @输入        ETM_Channel     奇通道数：1、3、5
+* @输入        dutyCycle       设置占空比，若DutyCycle为10,那么占空比就为10%
+*
+* @return none.
+*
+*****************************************************************************/
+void  ETM_SetDutyCycleCombine(ETM_Type *pETM, uint8_t u8ETM_Channel, uint8_t u8DutyCycle)
+{
+    uint16_t   cnv = pETM->CONTROLS[u8ETM_Channel-1].CnV;
+    uint16_t   modulo = pETM->MOD; 
+    
+    ASSERT((1 == u8ETM_Channel) || (3 == u8ETM_Channel) || (5 == u8ETM_Channel));
+    
+    cnv += (u8DutyCycle * (modulo+1))  / 100;
+    if(cnv > modulo)
+    {
+        cnv = modulo - 1;
+    }
+    pETM->CONTROLS[u8ETM_Channel].CnV = cnv ;    
+    
+    pETM->PWMLOAD |= ETM_PWMLOAD_LDOK_MASK | (1<<u8ETM_Channel);     
+}
+
+/*****************************************************************************//*!
+*
+* @brief configure the ETMx_SYNCONF register including SW and HW Sync selection.
+*
+* @param[in]    pETM             pointer to one of three ETM base register address.
+* @param[in]    u32ConfigValue   ETMx_SYNCONF register config value.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*****************************************************************************
+*
+* @配置寄存器 ETMx_SYNCONF,其中里面包含了软件输出的控制是否由硬件触发HW或是否有软件出发SW
+*
+* @输入     pETM               指向三个ETM定时器其中一个的基址
+* @输入     u32ConfigValue     ETMx_SYNCONF这个寄存器的值 
+*
+* @无返回
+*
+*****************************************************************************/
+void  ETM_SyncConfigActivate(ETM_Type *pETM, uint32_t u32ConfigValue)
+{
+    ASSERT((ETM2 == pETM));
+    pETM->SYNCONF |= u32ConfigValue;   
+}
+
+/*****************************************************************************//*!
+
+*
+* @brief configure the ETMx_SYNCONF register including SW and HW Sync selection.
+*
+* @param[in]    pETM             pointer to one of three ETM base register address.
+* @param[in]    u32ConfigValue   ETMx_SYNCONF register config value.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*****************************************************************************
+*
+* @恢复配置寄存器 ETMx_SYNCONF,其中里面包含了软件输出的控制是否由硬件触发HW或是否有软件出发SW
+*
+* @输入     pETM               指向三个ETM定时器其中一个的基址
+* @输入     u32ConfigValue     ETMx_SYNCONF这个寄存器的值 
+*
+* @无返回
+*
+*****************************************************************************/
+void  ETM_SyncConfigDeactivate(ETM_Type *pETM, uint32_t u32ConfigValue)
+{
+    ASSERT((ETM2 == pETM));
+    pETM->SYNCONF &= ~u32ConfigValue;   
+}
+
+/*****************************************************************************//*!
+*
+* @brief This function sets the callback function.
+*
+* @param[in]    pETM          pointer to one of three ETM base register address.
+* @param[in]    pfnCallback     functon address.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none
+*
+*****************************************************************************/
+/*****************************************************************************//*!
+*
+* @设置中断回调函数入口
+*
+* @输入       pETM            指向三个ETM中其中一个的基址
+* @输入       pfnCallback     功能函数的地址
+*
+* @无返回.
+*
+*****************************************************************************/
+void  ETM_SetCallback(ETM_Type *pETM, ETM_CallbackPtr pfnCallback)
+{
+   ETM_Callback[((uint32_t)pETM - (uint32_t)ETM0_BASE)>>12] = pfnCallback;
+}
+
+/*! @} End of ETM_api_list                                                    */
+
+
+/*****************************************************************************//*!
+*
+* @brief  ETM0_Isr interrupt service routine.
+*        
+* @param  none.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*********************************************************************************//*!
+*
+* @ETM0中断服务函数
+* 
+* @无输入
+*
+* @无返回
+*
+*********************************************************************************/
+void ETM0_Isr(void)
+{
+    if(ETM_Callback[0])
+    {
+        ETM_Callback[0]();
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  ETM1_Isr interrupt service routine.
+*        
+* @param  none. 
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*********************************************************************************//*!
+*
+* @ETM1中断服务函数
+* 
+* @无输入
+*
+* @无返回
+*
+*********************************************************************************/
+void ETM1_Isr(void)
+{
+    if(ETM_Callback[1])
+    {
+        ETM_Callback[1]();
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief  ETM2_Isr interrupt service routine.
+*        
+* @param  none. 
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+/*********************************************************************************//*!
+*
+* @ETM2中断服务函数
+* 
+* @无输入
+*
+* @无返回
+*
+*********************************************************************************/
+void ETM2_Isr(void)
+{
+    if(ETM_Callback[2])
+    {
+        ETM_Callback[2]();
+    }
+}
+
+
+

bsp/nv32f100x/lib/src/flash.c

@@ -0,0 +1,351 @@
+/******************************************************************************
+******************************************************************************
+*
+* @file flash.c
+*
+* @brief application entry point which performs application specific tasks. 
+*
+*******************************************************************************
+*
+* provide a demo for how to initialize the NV32, output messages via SCI, 
+* flash operations, etc.
+* NOTE:
+*	printf call may occupy a lot of memory (around 1924 bytes), so please
+*	consider your code size before using printf.
+******************************************************************************
+*
+* provide FLASH driver
+*
+******************************************************************************/
+
+#include "flash.h"
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+/*****************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+* @function name: Flash_CopyInRAM
+*
+* @brief This section of the code is the one that copies the routine into RAM. 
+* It is following the steps  documented in Technical Note 228
+*        
+* @param  
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+#define FLASH_ENABLE_STALLING_FLASH_CONTROLLER
+
+
+/*****************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+* @function name: Flash_Init
+*
+* @brief initialize flash driver
+*        
+* @param  
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+uint16_t Flash_Init(void)
+{
+	uint16_t err   = FLASH_ERR_SUCCESS;
+	uint32_t clkDIV = BUS_CLK_HZ/1000000L - 1;
+	uint32_t Tpgs  =(285 *(BUS_CLK_HZ/100))/1000000L;  //update 2016.8.4 by ¹â½Å°å¤ÎGG
+	uint32_t Tprog =(675*(BUS_CLK_HZ/100))/1000000L;   //by ¹â½Å°å¤ÎGG
+//        printf("Tpgs= %x \n" , Tpgs);
+//        printf("Tprog= %x \n" , Tprog);   
+        
+	EFMCR=(clkDIV<<24) + 0x00001103; //divide to 1M hz 
+	EFMETM0=(Tpgs<<16)  + 0x00001194;  //0x00281194; //
+	EFMETM1=(Tprog<<16) + 0x000088B8; //
+//        printf("EFMCR= %x \n" , EFMCR); 
+//        printf("EFMETM0= %x \n" , EFMETM0);         
+//        printf("EFMETM1= %x \n" , EFMETM1); 
+  return(err);
+}
+
+/*****************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+* @function name: FlashProgram
+*
+* @brief program flash routine, each program operation supports up to 2 longwords
+* 		 programming
+*        
+* @param  
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+uint16_t Flash_Program(uint32_t wNVMTargetAddress, uint8_t *pData, uint16_t sizeBytes)
+{
+	uint16_t err = FLASH_ERR_SUCCESS;
+	uint16_t w2LongWordCount = sizeBytes>>3;
+	uint8_t  wLeftBytes = (sizeBytes & 0x07);
+	uint16_t wLeftLongWords = wLeftBytes>>2;
+	uint32_t wTargetAddress = wNVMTargetAddress;
+	uint32_t dwData0,dwData1;
+	uint32_t *pdwData = (uint32_t*)pData;
+	int  i;
+ //printf("\n adr : 0x%x ,data = 0x%x\n",w2LongWordCount,wLeftLongWords );
+	// Check address to see if it is aligned to 4 bytes
+	// Global address [1:0] must be 00.
+	if(wNVMTargetAddress & 0x03)
+	{
+		err = FLASH_ERR_INVALID_PARAM;
+		return (err);
+	}
+	// Loop for the two longwords (8 bytes) programming
+	for(i = 0; i < w2LongWordCount; i++)
+	{
+		dwData0 = *pdwData++;
+		dwData1 = *pdwData++;
+		err = Flash_Program2LongWords(wTargetAddress, dwData0, dwData1);
+		if(err)
+		{
+			goto EndP;
+			//break;
+		}
+		wTargetAddress += 8;
+	}
+	// Loop for the single longword (4 bytes) programming
+	for(i = 0; i < wLeftLongWords; i++)
+	{
+		dwData0 = *pdwData++;
+		//printf("\n adr : 0x%x ,data = 0x%x\n",i,dwData0 );
+		err = Flash_Program1LongWord(wTargetAddress, dwData0);
+    //printf("\n adr : 0x%x ,data = 0x%x\n",i,dwData0 );
+		if(err)
+		{			
+			goto EndP;
+			//break;
+		}
+		wTargetAddress += 4;
+	}
+	wLeftBytes = (wLeftBytes-(wLeftLongWords<<2));	// calculate the # of bytes that are not programmed
+	if(!wLeftBytes){
+		return (err);
+	}
+        
+#if     defined(BIG_ENDIAN)                
+	dwData0 = 0;
+	pData = (uint8_t*)pdwData;	// pointer to the left bytes
+	for(i = wLeftBytes; i >0; i--)
+	{
+		dwData0 <<= 8;
+		dwData0 |= *pData++;	// MSB byte first
+	}
+	// Calculate how many bytes need to be filled with 0xFFs
+	// in order to form a single longword for the left bytes of data
+	wLeftBytes = 4 - wLeftBytes;	
+	//  
+	for(i = wLeftBytes; i >0; i--)
+	{
+		dwData0 <<= 8;
+		dwData0 |= 0xFF;	// MSB byte first
+	}
+#else
+	dwData0 = 0xFFFFFFFFL;        
+	pData = (uint8_t*)pdwData+wLeftBytes-1;	// pointer to the left bytes
+	for(i = wLeftBytes; i >0; i--)
+	{
+		dwData0 <<= 8;
+		dwData0 |= *pData--;	// MSB byte first
+	}
+#endif	
+	// Now program the last longword
+	err = Flash_Program1LongWord(wTargetAddress, dwData0);	
+EndP:	
+	return (err);
+}
+
+uint16_t Flash_Program1LongWord(uint32_t wNVMTargetAddress, uint32_t dwData)
+{
+	uint16_t err = FLASH_ERR_SUCCESS;
+	
+	// Check address to see if it is aligned to 4 bytes
+	// Global address [1:0] must be 00.
+	if(wNVMTargetAddress & 0x03)
+	{
+		err = FLASH_ERR_INVALID_PARAM;
+		return (err);
+	}
+	// Clear error flags
+	EFMCMD = FLASH_CMD_CLEAR;
+	// Write index to specify the command code to be loaded
+	M32(wNVMTargetAddress) = dwData;
+	// Write command code and memory address bits[23:16]	
+        EFM_LaunchCMD(FLASH_CMD_PROGRAM);
+	return (err);
+}
+
+
+uint16_t Flash_Program2LongWords(uint32_t wNVMTargetAddress, uint32_t dwData0, uint32_t dwData1)
+{
+	uint16_t err = FLASH_ERR_SUCCESS;
+
+	
+	// Check address to see if it is aligned to 4 bytes
+	// Global address [1:0] must be 00.
+	if(wNVMTargetAddress & 0x03)
+	{
+		err = FLASH_ERR_INVALID_PARAM;
+		return (err);
+	}
+	// Clear error flags
+
+	EFMCMD = FLASH_CMD_CLEAR;
+
+//	printf("\n write data  adr : 0x%x ,data = 0x%x\n",dwData0,dwData1 );
+	// Write index to specify the command code to be loaded
+	M32(wNVMTargetAddress) = dwData0;
+	// Write command code and memory address bits[23:16]	
+  EFM_LaunchCMD(FLASH_CMD_PROGRAM);
+	wNVMTargetAddress = wNVMTargetAddress +4;
+	
+	//	printf("\n write data  adr : 0x%x ,data = 0x%x\n",wNVMTargetAddress,dwData1 );
+	// Clear error flags
+		EFMCMD = FLASH_CMD_CLEAR;
+	// Write index to specify the command code to be loaded
+	M32(wNVMTargetAddress) = dwData1;
+	// Write command code and memory address bits[23:16]	
+  EFM_LaunchCMD(FLASH_CMD_PROGRAM);
+//	printf("\n write data  adr : 0x%x ,data = 0x%x\n",wNVMTargetAddress,dwData1 );
+	return (err);
+}
+
+
+
+
+
+/*****************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+* @function name: Flash_EraseSector
+*
+* @brief erase flash sector, each flash sector is of 512 bytes long,
+* global address [1:0] = 00.
+*        
+* @param  
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint16_t  Flash_EraseSector(uint32_t wNVMTargetAddress)
+{
+	uint16_t err = FLASH_ERR_SUCCESS;
+	// Check address to see if it is aligned to 4 bytes
+	// Global address [1:0] must be 00.
+	if(wNVMTargetAddress & 0x03)
+	{
+		err = FLASH_ERR_INVALID_PARAM;
+		return (err);
+	}
+	// Clear error flags
+		EFMCMD = FLASH_CMD_CLEAR;
+	  M32(wNVMTargetAddress) = 0xffffffff;
+	  EFM_LaunchCMD(FLASH_CMD_ERASE_SECTOR);
+	return (err);
+}
+
+uint16_t Flash_VerifyBackdoorKey()
+{
+	uint16_t err = FLASH_ERR_SUCCESS;
+//        int i;
+        
+	// Clear error flags
+		EFMCMD = FLASH_CMD_CLEAR;
+	// Write index to specify the command code to be loaded
+	 Custombkd = FLASH_FACTORY_KEY;
+	return (err);
+}
+
+/*****************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+* @function name: NVM_EraseAll
+*
+* @brief erase all block,both flash and EEPROM
+*        
+* @param  
+*	
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint16_t NVM_EraseAll(void)
+{
+	uint16_t err = FLASH_ERR_SUCCESS;
+		EFMCMD = FLASH_CMD_CLEAR;
+	  EFM_LaunchCMD(FLASH_CMD_ERASE_ALL);
+	// Clear error flags
+    return err;
+}
+
+/*****************************************************************************//*!
++FUNCTION----------------------------------------------------------------
+* @function name: NVM_Unsecure
+*
+* @brief unsecure 
+*        
+* @param  
+*	
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint16_t NVM_Unsecure(void)
+{
+	uint16_t err = FLASH_ERR_SUCCESS;
+
+    return err;
+}
+
+#ifdef IAR
+void __ramfunc EFM_LaunchCMD(uint32_t EFM_CMD)
+#else
+void EFM_LaunchCMD(uint32_t EFM_CMD)
+#endif
+{
+  DisableInterrupts;
+		if((EFMCMD&EFM_DONE_MASK)== EFM_STATUS_READY)
+		{
+	  EFMCMD = EFM_CMD;
+		}
+	while(1)
+	{
+		if((EFMCMD&EFM_DONE_MASK) == EFM_STATUS_DONE) break;
+	}
+ EnableInterrupts;
+}

bsp/nv32f100x/lib/src/gpio.c

@@ -0,0 +1,688 @@
+/******************************************************************************
+* @brief providing common gpio API. 
+*
+******************************************************************************/
+#include "gpio.h"
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+*****************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define GPIO APIs
+*
+*//*! @addtogroup gpio_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+* @brief    Initialize the GPIO registers to the default reset values.
+*        
+* @param[in] pGPIO      Pointer to GPIO module, can be GPIOA/GPIOB.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_DeInit(GPIO_Type *pGPIO)
+{
+    /* Sanity check */
+#if defined(CPU_NV32)
+     ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB));
+#endif
+#if defined(CPU_NV32M3)
+    ASSERT(pGPIO == GPIOA);
+#endif
+#if defined(CPU_NV32M4)
+      ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB) || (pGPIO == GPIOC));
+#endif
+
+    pGPIO->PCOR = 0x00000000;   /* Port Clear Output Register */
+    pGPIO->PDDR = 0x00000000;   /* Port Data Direction */
+    //pGPIO->PDIR = 0x00000000;   /* Port Data Input Register */
+    pGPIO->PDOR = 0x00000000;   /* Port Data Output Register */
+    pGPIO->PIDR = 0xFFFFFFFF;   /* Port Input Disable Register */
+    pGPIO->PSOR = 0x00000000;   /* Port Set Output Register */
+    pGPIO->PTOR = 0x00000000;   /* Port Toggle Output Register */
+}
+
+/*****************************************************************************//*!
+* @brief    Initialize GPIO pins which are specified by u32PinMask
+*        
+* @param[in] pGPIO      Pointer to GPIO module, can be GPIOA/GPIOB.
+* @param[in] u32PinMask GPIO pin mask need to be set
+* @param[in] sGpioType  pin attribute 
+*
+* @return   none
+*
+* @Note
+*   . High-current drive function is disabled, if the pin is configured as an input
+*   . Internal pullup is disabled if the pin is configured as an output
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_Init(GPIO_Type *pGPIO, uint32_t u32PinMask, GPIO_PinConfigType sGpioType)
+{
+    /* Sanity check */
+#if defined(CPU_NV32)
+     ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB));
+#endif
+#if defined(CPU_NV32M3)
+    ASSERT(pGPIO == GPIOA);
+#endif
+#if defined(CPU_NV32M4)
+      ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB) || (pGPIO == GPIOC));
+#endif
+    
+    /* Config GPIO for Input or Output */
+    if ((sGpioType == GPIO_PinOutput) || (sGpioType == GPIO_PinOutput_HighCurrent))
+    {
+        pGPIO->PDDR |= u32PinMask;      /* Enable Port Data Direction Register */
+        pGPIO->PIDR |= u32PinMask;      /* Set Port Input Disable Register */   
+    }
+    else if ((sGpioType == GPIO_PinInput) || (sGpioType == GPIO_PinInput_InternalPullup))
+    {
+        pGPIO->PDDR &= ~u32PinMask;   /* Disable Port Data Direction Register */
+        pGPIO->PIDR &= ~u32PinMask;   /* Clear Port Input Disable Register */
+    }
+    /* Config PORT Pull select for GPIO */
+#if defined(CPU_NV32)
+    switch((uint32_t)pGPIO)
+    {
+        case GPIOA_BASE:
+            (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUEL |= u32PinMask):(PORT->PUEL &= ~u32PinMask);
+            break;
+        case GPIOB_BASE:
+            (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUEH |= u32PinMask):(PORT->PUEH &= ~u32PinMask);
+            break;
+        default:
+            break;
+     }
+#endif
+    
+#if defined(CPU_NV32M3)
+    switch((uint32_t)pGPIO)
+    {
+        case GPIOA_BASE:
+            (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUEL |= u32PinMask):(PORT->PUEL &= ~u32PinMask);
+            break;
+        default:
+            break;
+     }
+#endif
+    
+#if defined(CPU_NV32M4)
+    switch((uint32_t)pGPIO)
+    {
+        case GPIOA_BASE:
+            (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUE0 |= u32PinMask):(PORT->PUE0 &= ~u32PinMask);
+            break;
+        case GPIOB_BASE:
+            (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUE1 |= u32PinMask):(PORT->PUE1 &= ~u32PinMask);
+            break;
+        case GPIOC_BASE:
+            (sGpioType == GPIO_PinInput_InternalPullup)?(PORT->PUE2 |= u32PinMask):(PORT->PUE2 &= ~u32PinMask);
+            break;
+        default:
+            break;
+     }
+#endif   
+    
+    /* Config PORT GPIO_PinOutput_HighCurrent for GPIO */
+#if defined(CPU_NV32M3)
+    if (u32PinMask & GPIO_PTC5_MASK)
+    {   
+        PORT->HDRVE |= PORT_HDRVE_PTC5_MASK;
+    }   
+    if (u32PinMask & GPIO_PTC1_MASK)
+    {   
+        PORT->HDRVE |= PORT_HDRVE_PTC1_MASK;
+    }   
+    if (u32PinMask & GPIO_PTB5_MASK)
+    {   
+        PORT->HDRVE |= PORT_HDRVE_PTB5_MASK;
+    }   
+#endif
+    
+#if defined(CPU_NV32) | defined(CPU_NV32M4)
+    if (pGPIO == GPIOA)
+    {
+        if (u32PinMask & GPIO_PTB4_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTB4_MASK;
+        }   
+        if (u32PinMask & GPIO_PTB5_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTB5_MASK;
+        }   
+        if (u32PinMask & GPIO_PTD0_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTD0_MASK;
+        }   
+        if (u32PinMask & GPIO_PTD1_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTD1_MASK;
+        }   
+    }
+    if (pGPIO == GPIOB)
+    {
+        if (u32PinMask & GPIO_PTE0_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTE0_MASK;
+        }   
+        if (u32PinMask & GPIO_PTE1_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTE1_MASK;
+        }   
+        if (u32PinMask & GPIO_PTH0_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTH0_MASK;
+        }   
+        if (u32PinMask & GPIO_PTH1_MASK)
+        {   
+            PORT->HDRVE |= PORT_HDRVE_PTH1_MASK;
+        }   
+    }
+
+#endif
+    
+}
+
+
+
+/*****************************************************************************//*!
+* @brief    Toggle the pins which are specified by u32PinMask
+*        
+* @param[in] pGPIO       Pointer to GPIO module, can be GPIOA/GPIOB.
+* @param[in] u32PinMask  Specify GPIO pin need to be toggled
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_Toggle(GPIO_Type *pGPIO, uint32_t u32PinMask)
+{
+    /* Sanity check */
+#if defined(CPU_NV32)
+     ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB));
+#endif
+#if defined(CPU_NV32M3)
+    ASSERT(pGPIO == GPIOA);
+#endif
+#if defined(CPU_NV32M4)
+      ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB) || (pGPIO == GPIOC));
+#endif
+
+    pGPIO->PTOR = u32PinMask;   /* Toggle the pins specified by u32PinMask */
+}
+
+/*****************************************************************************//*!
+* @brief Read input data from GPIO which is specified by pGPIO
+*        
+* @param[in] pGPIO       Pointer to GPIO module, can be GPIOA/GPIOB.
+*
+* @return   GPIO input value unsigned int 32-bit
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint32_t GPIO_Read(GPIO_Type *pGPIO)
+{
+    /* Sanity check */
+#if defined(CPU_NV32)
+     ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB));
+#endif
+#if defined(CPU_NV32M3)
+    ASSERT(pGPIO == GPIOA);
+#endif
+#if defined(CPU_NV32M4)
+      ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB) || (pGPIO == GPIOC));
+#endif
+
+    return (pGPIO->PDIR);   /* Read Port Data Input Register */
+  
+}
+
+/*****************************************************************************//*!
+* @brief Read input data from Bit GPIO which is specified by pGPIO
+*        
+* @param[in] pGPIO       Pointer to GPIO module, can be GPIOA/GPIOB.
+*
+* @return   Bit GPIO input value 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint8_t GPIO_BitRead(GPIO_PinType GPIO_Pin)
+{
+  uint8_t data;  
+  /* Sanity check */
+    ASSERT(GPIO_Pin <= GPIO_PTI7);
+    
+      
+    /* Config GPIO and pull select*/
+
+      if (GPIO_Pin < GPIO_PTE0)
+      {
+            if(((1<<GPIO_Pin) & GPIOA->PDIR) > 0)       /* Read Bit GPIO input value */
+                data = 0x1;                             /* return value */
+            else 
+                data = 0x0;
+          
+      }
+      
+      else if (GPIO_Pin < GPIO_PTI0)
+      {
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - 32);
+        
+            if(((1<<GPIO_Pin) & GPIOB->PDIR) > 0)       /* Read Bit GPIO input value */
+                data = 0x1;                             /* return value */
+            else 
+	       data = 0x0;
+          
+      }
+
+     return data;
+		    
+}
+
+
+/*****************************************************************************//*!
+* @brief    Write output data to GPIO which is specified by pGPIO
+*        
+* @param[in] pGPIO       Pointer to GPIO module, can be GPIOA/GPIOB.
+* @param[in] u32Value    value to output
+*
+* @return   none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_Write(GPIO_Type *pGPIO, uint32_t u32Value)
+{
+    /* Sanity check */
+#if defined(CPU_NV32)
+     ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB));
+#endif
+#if defined(CPU_NV32M3)
+    ASSERT(pGPIO == GPIOA);
+#endif
+#if defined(CPU_NV32M4)
+      ASSERT((pGPIO == GPIOA) || (pGPIO == GPIOB) || (pGPIO == GPIOC));
+#endif
+    
+    pGPIO->PDOR = u32Value;    /* Write Port Ouput Data Register */
+  
+}
+
+/*****************************************************************************//*!
+* @brief    Initialize GPIO single pin which is specified by GPIO_Pin
+*        
+* @param[in] GPIO_Pin        GPIO pin name, can be GPIO_PTA0,1 ...
+* @param[in] GPIO_PinConfig  Config output or input
+*
+* @return   none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_PinInit(GPIO_PinType GPIO_Pin, GPIO_PinConfigType GPIO_PinConfig)
+{
+    /* Sanity check */
+    ASSERT(GPIO_Pin <= GPIO_PTI7);
+      
+    /* Config GPIO and pull select*/
+#if defined(CPU_NV32)
+      if (GPIO_Pin < GPIO_PTE0)
+      {
+        switch (GPIO_PinConfig)
+        {
+        case GPIO_PinOutput:
+            GPIOA->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOA->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUEL &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput:
+            GPIOA->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOA->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUEL &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput_InternalPullup:
+            GPIOA->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOA->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUEL |= (1<<GPIO_Pin);    /* Enable Pullup */
+          break;
+        case GPIO_PinOutput_HighCurrent:
+            GPIOA->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOA->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUEL &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        }
+      }
+      else if (GPIO_Pin < GPIO_PTI0)
+      {
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - 32);
+        switch (GPIO_PinConfig)
+        {
+        case GPIO_PinOutput:
+            GPIOB->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOB->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUEH &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput:
+            GPIOB->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOB->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUEH &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput_InternalPullup:
+            GPIOB->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOB->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUEH |= (1<<GPIO_Pin);    /* Enable Pullup */
+          break;
+        case GPIO_PinOutput_HighCurrent:
+            GPIOB->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOB->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUEH &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        }
+      }
+#endif
+      
+#if defined(CPU_NV32M3)
+      if (GPIO_Pin < GPIO_PTE0)
+      {
+        switch (GPIO_PinConfig)
+        {
+        case GPIO_PinOutput:
+            GPIOA->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOA->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUEL &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput:
+            GPIOA->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOA->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUEL &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput_InternalPullup:
+            GPIOA->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOA->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUEL |= (1<<GPIO_Pin);    /* Enable Pullup */
+          break;
+        case GPIO_PinOutput_HighCurrent:
+            GPIOA->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOA->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUEL &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        }
+      }
+#endif
+    
+    
+#if defined(CPU_NV32M4)
+      if (GPIO_Pin < GPIO_PTE0)
+      {
+        switch (GPIO_PinConfig)
+        {
+        case GPIO_PinOutput:
+            GPIOA->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOA->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUE0 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput:
+            GPIOA->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOA->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUE0 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput_InternalPullup:
+            GPIOA->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOA->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUE0 |= (1<<GPIO_Pin);    /* Enable Pullup */
+          break;
+        case GPIO_PinOutput_HighCurrent:
+            GPIOA->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOA->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUE0 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        }
+      }
+      else if (GPIO_Pin < GPIO_PTI0)
+      {
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - 32);
+        switch (GPIO_PinConfig)
+        {
+        case GPIO_PinOutput:
+            GPIOB->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOB->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUE1 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput:
+            GPIOB->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOB->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUE1 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput_InternalPullup:
+            GPIOB->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOB->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUE1 |= (1<<GPIO_Pin);    /* Enable Pullup */
+          break;
+        case GPIO_PinOutput_HighCurrent:
+            GPIOB->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOB->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUE1 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        }
+      }
+      else
+      {
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - 64);
+        switch (GPIO_PinConfig)
+        {
+        case GPIO_PinOutput:
+            GPIOC->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOC->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUE2 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput:
+            GPIOC->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOC->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUE2 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        case GPIO_PinInput_InternalPullup:
+            GPIOC->PDDR &= ~(1<<GPIO_Pin);     /* Disable Port Data Direction Register */
+            GPIOC->PIDR &= ~(1<<GPIO_Pin);     /* Clear Port Input Disable Register */
+            PORT->PUE2 |= (1<<GPIO_Pin);    /* Enable Pullup */
+          break;
+        case GPIO_PinOutput_HighCurrent:
+            GPIOC->PDDR |= (1<<GPIO_Pin);      /* Enable Port Data Direction Register */
+            GPIOC->PIDR |= (1<<GPIO_Pin);      /* Set Port Input Disable Register */
+            PORT->PUE2 &= ~(1<<GPIO_Pin);    /* Disable Pullup */
+          break;
+        }
+      }
+#endif
+      
+    /* Config GPIO HDRV */
+    if(GPIO_PinConfig == GPIO_PinOutput_HighCurrent)
+    {
+#if defined(CPU_NV32M3)
+        switch (GPIO_Pin)
+        {
+            case GPIO_PTB5:
+                PORT->HDRVE |= PORT_HDRVE_PTB5_MASK;
+                break;
+            case GPIO_PTC1:
+                PORT->HDRVE |= PORT_HDRVE_PTC1_MASK;
+                break;
+            case GPIO_PTC5:
+                PORT->HDRVE |= PORT_HDRVE_PTC5_MASK;
+                break;
+            default:
+                break;
+        }
+#endif
+    
+#if defined(CPU_NV32M4) | defined(CPU_NV32)
+        switch (GPIO_Pin)
+        {
+            case GPIO_PTB4:
+                PORT->HDRVE |= PORT_HDRVE_PTB4_MASK;
+                break;
+            case GPIO_PTB5:
+                PORT->HDRVE |= PORT_HDRVE_PTB5_MASK;
+                break;
+            case GPIO_PTD0:
+                PORT->HDRVE |= PORT_HDRVE_PTD0_MASK;
+                break;
+            case GPIO_PTD1:
+                PORT->HDRVE |= PORT_HDRVE_PTD1_MASK;
+                break;
+            case GPIO_PTE0:
+                PORT->HDRVE |= PORT_HDRVE_PTE0_MASK;
+                break;
+            case GPIO_PTE1:
+                PORT->HDRVE |= PORT_HDRVE_PTE1_MASK;
+                break;
+            case GPIO_PTH0:
+                PORT->HDRVE |= PORT_HDRVE_PTH0_MASK;
+                break;
+            case GPIO_PTH1:
+                PORT->HDRVE |= PORT_HDRVE_PTH1_MASK;
+                break;
+            default:
+                break; 
+        }
+#endif
+    }
+}
+
+/*****************************************************************************//*!
+* @brief    Toggle GPIO single pin which is specified by GPIO_Pin
+*        
+* @param[in] GPIO_Pin        GPIO pin name, can be GPIO_PTA0,1 ...
+*
+* @return   none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_PinToggle(GPIO_PinType GPIO_Pin)
+{
+    /* Sanity check */
+    ASSERT(GPIO_Pin <= GPIO_PTI7);
+
+    if (GPIO_Pin < GPIO_PTE0)
+    {
+        /* PTA0-7, PTB0-7, PTC0-7, PTD0-7 */
+        GPIOA->PTOR = (1<<GPIO_Pin);
+    }
+
+#if (defined(CPU_NV32) | defined(CPU_NV32M4))
+
+    else if (GPIO_Pin < GPIO_PTI0)
+    {
+        /* PTE0-7, PTF0-7, PTH0-7, PTI0-7 */
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTE0);
+        GPIOB->PTOR = (1<<GPIO_Pin);
+    }
+#endif
+
+#if defined(CPU_NV32M4)  
+    else if(GPIO_Pin < GPIO_PIN_MAX)
+    {
+        /* PTI0-7 */
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTI0);
+        GPIOC->PTOR = (1<<GPIO_Pin);
+    }
+#endif
+}
+
+/*****************************************************************************//*!
+* @brief    Set GPIO single pin which is specified by GPIO_Pin
+*        
+* @param[in] GPIO_Pin        GPIO pin name, can be GPIO_PTA0,1 ...
+*
+* @return   none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_PinSet(GPIO_PinType GPIO_Pin)
+{
+    /* Sanity check */
+    ASSERT(GPIO_Pin <= GPIO_PTI7);
+    
+    if (GPIO_Pin < GPIO_PTE0)
+    {
+        /* PTA0-7, PTB0-7, PTC0-7, PTD0-7 */
+        GPIOA->PSOR = (1<<GPIO_Pin);
+    }
+
+#if (defined(CPU_NV32) | defined(CPU_NV32M4))
+
+    else if (GPIO_Pin < GPIO_PTI0)
+    {
+        /* PTE0-7, PTF0-7, PTH0-7, PTI0-7 */
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTE0);
+        GPIOB->PSOR = (1<<GPIO_Pin);
+    }
+#endif
+
+#if defined(CPU_NV32M4) 
+    else if(GPIO_Pin < GPIO_PIN_MAX)
+    {
+        /* PTI0-7 */
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTI0);
+        GPIOC->PSOR = (1<<GPIO_Pin);
+    }
+#endif
+}
+
+/*****************************************************************************//*!
+* @brief    Clear GPIO single pin which is specified by GPIO_Pin
+*        
+* @param[in] GPIO_Pin        GPIO pin name, can be GPIO_PTA0,1 ...
+*
+* @return   none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void GPIO_PinClear(GPIO_PinType GPIO_Pin)
+{
+    /* Sanity check */
+    ASSERT(GPIO_Pin <= GPIO_PTI7);
+    
+    if (GPIO_Pin < GPIO_PTE0)
+    {
+        /* PTA0-7, PTB0-7, PTC0-7, PTD0-7 */
+        GPIOA->PCOR = (1<<GPIO_Pin);
+    }
+
+#if (defined(CPU_NV32) | defined(CPU_NV32M4))
+
+    else if (GPIO_Pin < GPIO_PTI0)
+    {
+        /* PTE0-7, PTF0-7, PTH0-7, PTI0-7 */
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTE0);
+        GPIOB->PCOR = (1<<GPIO_Pin);
+    }
+#endif
+
+#if defined(CPU_NV32M4)
+    else if(GPIO_Pin < GPIO_PIN_MAX)
+    {
+        /* PTI0-7 */
+        GPIO_Pin = (GPIO_PinType)(GPIO_Pin - GPIO_PTI0);
+        GPIOC->PCOR = (1<<GPIO_Pin);
+    }
+#endif
+}
+
+/*! @} End of gpio_api_list */
+

bsp/nv32f100x/lib/src/i2c.c

@@ -0,0 +1,656 @@
+/******************************************************************************
+*
+* @brief providing APIs for configuring I2C module (I2C). 
+*
+*******************************************************************************
+*
+* provide APIs for configuring I2C module (I2C).
+******************************************************************************/
+#include "common.h"
+#include "i2c.h"
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+static I2C_CallbackType I2C_Callback[2] = {(I2C_CallbackType)NULL};
+/******************************************************************************
+* Local functions
+******************************************************************************/
+void I2C0_Isr( void );
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+
+/******************************************************************************
+* define I2C APIs
+*
+*//*! @addtogroup i2c_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief Initialize I2C module.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+ 	 * @param[in] pI2CConfig point to I2C configure structure.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+void I2C_Init(I2C_Type *pI2Cx,I2C_ConfigPtr pI2CConfig)
+{
+    uint8_t u8Temp;
+
+#if defined(CPU_NV32)
+    SIM->SCGC |= SIM_SCGC_IIC_MASK;
+#elif defined(CPU_NV32M3)
+    SIM->SCGC |= SIM_SCGC_IIC_MASK;
+#elif defined(CPU_NV32M4)
+    if(pI2Cx == I2C0)
+    {
+        SIM->SCGC |= SIM_SCGC_I2C0_MASK;
+    }
+    else
+    {
+        SIM->SCGC |= SIM_SCGC_I2C1_MASK;
+    }
+#endif
+
+	I2C_SetBaudRate(pI2Cx,pI2CConfig->u16F);
+    I2C_SetSlaveAddress(pI2Cx,pI2CConfig->u16OwnA1);
+    pI2Cx->FLT = (uint8_t)pI2CConfig->u16Filt;
+    pI2Cx->RA = (uint8_t)pI2CConfig->u16RangeA & 0xfe;
+    I2C_SetSCLLowETMeout(pI2Cx,pI2CConfig->u16Slt);
+
+    /* configure C2 control register */
+    u8Temp = 0;
+    if( pI2CConfig->sSetting.bGCAEn )
+    {
+        u8Temp |= I2C_C2_GCAEN_MASK;
+    }
+    if( pI2CConfig->sSetting.bAddressExt )
+    {
+        u8Temp |= I2C_C2_ADEXT_MASK;
+    }
+    if( pI2CConfig->sSetting.bRangeAddEn )
+    {
+        u8Temp |= I2C_C2_RMEN_MASK;
+    }
+    pI2Cx->C2 |= u8Temp;
+
+    /* configure SMB rehister */
+    u8Temp = 0;
+    if( pI2CConfig->sSetting.bFackEn )
+    {
+        u8Temp |= I2C_SMB_FACK_MASK;
+    }
+    if( pI2CConfig->sSetting.bSMB_AlertEn )
+    {
+        u8Temp |= I2C_SMB_ALERTEN_MASK;
+    }
+    if( pI2CConfig->sSetting.bSecondAddressEn )
+    {
+        u8Temp |= I2C_SMB_SIICAEN_MASK;
+    }
+    if( pI2CConfig->sSetting.bSHTF2IntEn )
+    {
+        u8Temp |= I2C_SMB_SHTF2IE_MASK;
+    }
+    pI2Cx->SMB = u8Temp;
+    
+    /* configure C1 rehister */
+    u8Temp = 0;
+    if( pI2CConfig->sSetting.bIntEn )
+    {
+        u8Temp |= I2C_C1_IICIE_MASK;
+        if(pI2Cx == I2C0)
+        {
+            NVIC_EnableIRQ(I2C0_IRQn);
+        }
+    #if defined(CPU_NV32M4)     
+        else if(pI2Cx == I2C1)
+        {
+            NVIC_EnableIRQ(I2C1_IRQn);
+        }
+    #endif    
+        else
+        {
+            //
+        }
+    }
+    if( pI2CConfig->sSetting.bWakeUpEn )
+    {
+        u8Temp |= I2C_C1_WUEN_MASK;
+    }
+    if( pI2CConfig->sSetting.bI2CEn )
+    {
+        u8Temp |= I2C_C1_IICEN_MASK;
+    }
+    pI2Cx->C1 = u8Temp;
+
+
+}
+/*****************************************************************************//*!
+   *
+   * @brief send out start signals.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return error status
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint8_t I2C_Start(I2C_Type *pI2Cx)
+{
+    uint32_t u32ETMeout;
+    uint8_t u8ErrorStatus;
+    
+    u32ETMeout = 0; 
+    u8ErrorStatus = 0x00;
+
+    I2C_TxEnable(pI2Cx);
+    pI2Cx->C1 |= I2C_C1_MST_MASK;
+
+    while( (!I2C_IsBusy(pI2Cx)) && ( u32ETMeout < I2C_WAIT_STATUS_ETMEOUT))
+     {
+        u32ETMeout ++;
+     }
+
+     if( u32ETMeout == I2C_WAIT_STATUS_ETMEOUT )
+     {
+        u8ErrorStatus |= I2C_ERROR_START_NO_BUSY_FLAG;
+     }
+
+     return u8ErrorStatus;
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief send out stop signals.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return error status
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint8_t I2C_Stop(I2C_Type *pI2Cx)
+{
+    uint32_t u32ETMeout;
+    uint8_t u8ErrorStatus;
+    
+    u32ETMeout = 0; 
+    u8ErrorStatus = 0x00;
+    
+    pI2Cx->C1 &= ~I2C_C1_MST_MASK;
+
+    while( (I2C_IsBusy(pI2Cx) ) && ( u32ETMeout < I2C_WAIT_STATUS_ETMEOUT))
+     {
+        u32ETMeout ++;
+     }
+
+     if( u32ETMeout == I2C_WAIT_STATUS_ETMEOUT )
+     {
+        u8ErrorStatus |= I2C_ERROR_STOP_BUSY_FLAG;
+     }
+
+     return u8ErrorStatus;
+}
+
+
+/*****************************************************************************//*!
+   *
+   * @brief send out repeat start signals.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return error status.
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint8_t I2C_RepeatStart(I2C_Type *pI2Cx)
+{
+    uint32_t u32ETMeout;
+    uint8_t u8ErrorStatus;
+    
+    u32ETMeout = 0; 
+    u8ErrorStatus = 0x00;
+    
+    pI2Cx->C1 |= I2C_C1_RSTA_MASK;
+
+    while( (!I2C_IsBusy(I2C0) ) && ( u32ETMeout < I2C_WAIT_STATUS_ETMEOUT))
+     {
+        u32ETMeout ++;
+     }
+
+     if( u32ETMeout == I2C_WAIT_STATUS_ETMEOUT )
+     {
+        u8ErrorStatus |= I2C_ERROR_START_NO_BUSY_FLAG;
+     }
+
+     return u8ErrorStatus;
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief set slave address.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+void I2C_SetSlaveAddress(I2C_Type *pI2Cx,uint16_t u16SlaveAddress)
+{
+    /* write low 8bit address */
+    pI2Cx->A1 = (uint8_t)u16SlaveAddress;
+
+    /* write high 3bit address if it support 10bit slave address */
+    pI2Cx->C2 &= ~I2C_C2_AD_MASK;
+    pI2Cx->C2 |= (uint8_t)(u16SlaveAddress>>8)&0x03;
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief disable IICIF interrupt.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+void I2C_IntDisable(I2C_Type *pI2Cx)
+{
+    pI2Cx->C1 &= ~I2C_C1_IICIE_MASK;
+    if(pI2Cx == I2C0)
+    {
+        NVIC_DisableIRQ(I2C0_IRQn);
+    }
+    #if defined(CPU_NV32M4)
+    else if(pI2Cx == I2C1)
+    {
+        NVIC_DisableIRQ(I2C1_IRQn);
+    }
+    #endif
+    else
+    {
+        
+    }
+}
+/*****************************************************************************//*!
+   *
+   * @brief enable IICIF interrupt.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+void I2C_IntEnable(I2C_Type *pI2Cx)
+{
+    pI2Cx->C1 |= I2C_C1_IICIE_MASK;
+    if(pI2Cx == I2C0)
+    {
+        NVIC_EnableIRQ(I2C0_IRQn);
+    }
+    #if defined(CPU_NV32M4)
+    else if(pI2Cx == I2C1)
+    {
+        NVIC_EnableIRQ(I2C1_IRQn);
+    }
+    #endif
+    else
+    {
+        
+    }
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief SCL low ETMeout value that determines the ETMeout period of SCL low.
+   *        
+   * @param[in] pI2Cx      point to I2C module type.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+void I2C_SetSCLLowETMeout(I2C_Type *pI2Cx, uint16_t u16ETMeout)
+{
+    pI2Cx->SLTL = (uint8_t)u16ETMeout;
+    pI2Cx->SLTH = (uint8_t)(u16ETMeout>>8);
+}
+/*****************************************************************************//*!
+   *
+   * @brief deinit I2C module.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+void I2C_Deinit(I2C_Type *pI2Cx)
+{
+     pI2Cx->C1 &= ~I2C_C1_IICEN_MASK;
+#if defined(CPU_NV32)
+    SIM->SCGC &= ~SIM_SCGC_IIC_MASK;
+#elif defined(CPU_NV32M3)
+    SIM->SCGC &= ~SIM_SCGC_IIC_MASK;
+#elif defined(CPU_NV32M4)
+    if(pI2Cx == I2C0)
+    {
+        SIM->SCGC &= ~SIM_SCGC_I2C0_MASK;
+    }
+    else
+    {
+        SIM->SCGC &= ~SIM_SCGC_I2C1_MASK;
+    }
+#endif
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief write a byte to I2C module.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   * @param[in] u8WrBuff  data buffer for writing. 
+   *
+   * @return error status
+   *
+   * @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+uint8_t I2C_WriteOneByte(I2C_Type *pI2Cx, uint8_t u8WrBuff)
+{
+    uint32_t u32ETMeout;
+    uint8_t u8ErrorStatus;
+    
+    u32ETMeout = 0; 
+    u8ErrorStatus = 0x00;
+    while (((I2C_GetStatus(pI2Cx)&I2C_S_TCF_MASK) !=  I2C_S_TCF_MASK)
+            && (u32ETMeout<I2C_WAIT_STATUS_ETMEOUT))
+    {
+        u32ETMeout ++;
+    }
+    if (u32ETMeout >= I2C_WAIT_STATUS_ETMEOUT)
+    {
+        u8ErrorStatus |= I2C_ERROR_NO_WAIT_TCF_FLAG; 
+        return u8ErrorStatus;
+    }
+    
+    I2C_TxEnable(pI2Cx);
+    I2C_WriteDataReg(pI2Cx,u8WrBuff);
+
+    u32ETMeout = 0;
+    while (((I2C_GetStatus(pI2Cx)&I2C_S_IICIF_MASK) !=  I2C_S_IICIF_MASK)
+            && (u32ETMeout<I2C_WAIT_STATUS_ETMEOUT))
+    {
+        u32ETMeout ++;
+    }
+    if (u32ETMeout >= I2C_WAIT_STATUS_ETMEOUT)
+    {
+        u8ErrorStatus |= I2C_ERROR_NO_WAIT_IICIF_FLAG; 
+        return u8ErrorStatus;
+    }
+
+    /* clear IICIF flag */
+    I2C_ClearStatus(pI2Cx,I2C_S_IICIF_MASK);
+    if (I2C_GetStatus(pI2Cx) & I2C_S_RXAK_MASK) 
+    {
+        u8ErrorStatus |= I2C_ERROR_NO_GET_ACK;
+    }
+    return u8ErrorStatus;
+}
+/*****************************************************************************//*!
+   *
+   * @brief read a byte from slave I2C.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   * @param[out] pRdBuff point to the data read from slave I2C.
+   * @param[out] u8Ack   send out ack or nack.
+   *
+   * @return error status
+   *
+   * @ Pass/ Fail criteria:  none
+*****************************************************************************/
+
+uint8_t I2C_ReadOneByte(I2C_Type *pI2Cx, uint8_t *pRdBuff, uint8_t u8Ack)
+{
+    uint32_t u32ETMeout;
+    uint8_t u8ErrorStatus;
+    
+    u32ETMeout = 0; 
+    u8ErrorStatus = 0x00;
+    while (((I2C_GetStatus(pI2Cx)&I2C_S_TCF_MASK) !=  I2C_S_TCF_MASK)
+            && (u32ETMeout<I2C_WAIT_STATUS_ETMEOUT))
+    {
+        u32ETMeout ++;
+    }
+    if (u32ETMeout >= I2C_WAIT_STATUS_ETMEOUT)
+    {
+        u8ErrorStatus |= I2C_ERROR_NO_WAIT_TCF_FLAG; 
+        return u8ErrorStatus;
+    }
+    
+    I2C_RxEnable(pI2Cx);
+
+    if( u8Ack )
+    {
+        /* send out nack */
+        I2C_SendNack(pI2Cx);
+       
+    }
+    else
+    {
+         /* send out ack */
+        I2C_SendAck(pI2Cx);
+    }
+    *pRdBuff = I2C_ReadDataReg(pI2Cx);
+
+    u32ETMeout = 0;
+    while (((I2C_GetStatus(pI2Cx)&I2C_S_IICIF_MASK) !=  I2C_S_IICIF_MASK)
+            && (u32ETMeout<I2C_WAIT_STATUS_ETMEOUT))
+    {
+        u32ETMeout ++;
+    }
+    if (u32ETMeout >= I2C_WAIT_STATUS_ETMEOUT)
+    {
+        u8ErrorStatus |= I2C_ERROR_NO_WAIT_IICIF_FLAG; 
+        return u8ErrorStatus;
+    }
+
+    /* clear IICIF flag */
+    I2C_ClearStatus(pI2Cx,I2C_S_IICIF_MASK);
+
+    return u8ErrorStatus;
+}
+/*****************************************************************************//*!
+   *
+   * @brief send data to I2C, and wait to complete transfering.
+   *   
+   * @param[in]  pI2Cx    point to I2C module type.
+   * @param[in]  u16SlaveAddress slave address. 
+   * @param[in]  pWrBuff point the first address of transfering data buffer. 
+   * @param[in]  the length of transfering data.
+   *
+   * @return error status
+   *
+   * @ Pass/ Fail criteria:  none
+*****************************************************************************/
+
+uint8_t I2C_MasterSendWait(I2C_Type *pI2Cx,uint16_t u16SlaveAddress,uint8_t *pWrBuff,uint32_t u32Length)
+{
+    uint32_t i;
+    uint8_t u8ErrorStatus;
+
+    /* send start signals to bus */
+    u8ErrorStatus = I2C_Start(pI2Cx);
+
+    /* send device address to slave */
+    u8ErrorStatus = I2C_WriteOneByte(pI2Cx,((uint8_t)u16SlaveAddress<<1) | I2C_WRITE);
+
+    /* if no error occur, received the correct ack from slave
+            continue to send data to slave
+        */
+    if( u8ErrorStatus == I2C_ERROR_NULL )
+    {
+        for(i=0;i<u32Length;i++)
+        {
+            u8ErrorStatus = I2C_WriteOneByte(pI2Cx,pWrBuff[i]);
+            if( u8ErrorStatus != I2C_ERROR_NULL )
+            {
+                return u8ErrorStatus;
+            }
+        }
+     }
+
+     /* send stop signals to bus */
+     u8ErrorStatus = I2C_Stop(pI2Cx);
+
+     return u8ErrorStatus;
+            
+}
+/*****************************************************************************//*!
+   *
+   * @brief read data from I2C,and wait to complete transferring.
+   *        
+   * @param[in] pI2Cx    point to I2C module type.
+   * @param[in]  u16SlaveAddress slave address. 
+   * @param[in]  pRdBuff point the first address of reading data buffer. 
+   * @param[in]  the length of transfering data.
+   *
+   * @return error status
+   *
+   * @ Pass/ Fail criteria:  none
+*****************************************************************************/
+
+uint8_t I2C_MasterReadWait(I2C_Type *pI2Cx,uint16_t u16SlaveAddress,uint8_t *pRdBuff,uint32_t u32Length)
+{
+    uint32_t i;
+    uint8_t u8ErrorStatus;
+
+    /* send start signals to bus */
+    u8ErrorStatus = I2C_Start(pI2Cx);
+
+    /* send device address to slave */
+    u8ErrorStatus = I2C_WriteOneByte(pI2Cx,((uint8_t)u16SlaveAddress<<1) | I2C_READ);
+
+    /* if no error occur, received the correct ack from slave
+            continue to send data to slave
+        */
+    /* dummy read one byte to switch to Rx mode */
+    I2C_ReadOneByte(pI2Cx,&pRdBuff[0],I2C_SEND_ACK);
+    
+    if( u8ErrorStatus == I2C_ERROR_NULL )
+    {
+        for(i=0;i<u32Length-1;i++)
+        {
+            u8ErrorStatus = I2C_ReadOneByte(pI2Cx,&pRdBuff[i],I2C_SEND_ACK);
+            if( u8ErrorStatus != I2C_ERROR_NULL )
+            {
+                return u8ErrorStatus;
+            }
+        }
+        u8ErrorStatus = I2C_ReadOneByte(pI2Cx,&pRdBuff[i],I2C_SEND_NACK);
+     }
+     /* send stop signals to bus */
+     u8ErrorStatus = I2C_Stop(pI2Cx);
+     
+     return u8ErrorStatus;
+            
+}
+/*****************************************************************************//*!
+   *
+   * @brief set call back function for I2C1 module.
+   *        
+   * @param[in] pCallBack point to address of I2C1 call back function.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria:  none.
+*****************************************************************************/
+
+void I2C1_SetCallBack( I2C_CallbackType pCallBack )
+{
+    I2C_Callback[1] = pCallBack;
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief set call back function for I2C0 module.
+   *        
+   * @param[in] pCallBack point to address of I2C0 call back function.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria:  none.
+*****************************************************************************/
+
+void I2C0_SetCallBack( I2C_CallbackType pCallBack )
+{
+    I2C_Callback[0] = pCallBack;
+}
+/*! @} End of i2c_api_list                                               						*/
+
+
+/*****************************************************************************//*!
+   *
+   * @brief I2C0 interrupt service routine.
+   *        
+   * @param  
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria:  none
+*****************************************************************************/
+void I2C0_Isr( void )
+{
+    if( I2C_Callback[0] )
+    {
+        I2C_Callback[0]();
+    }
+}
+/*****************************************************************************//*!
+   *
+   * @brief I2C1 interrupt service routine.
+   *        
+   * @param  
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria:  none
+*****************************************************************************/
+void I2C1_Isr( void )
+{
+    if( I2C_Callback[1] )
+    {
+        I2C_Callback[1]();
+    }
+}
+
+
+

bsp/nv32f100x/lib/src/ics.c

@@ -0,0 +1,1109 @@
+/*************************************************************!     
+ *     技术讨论：QQ群  123763203
+ *     官网    ：www.navota.com
+ *
+ * @file       ics.c
+ * @brief      时钟模块（ICS)函数库
+ * @author     Navota
+ * @date       2017-1-1
+ ****************************************************************/
+#include "common.h"
+#include "ics.h"
+
+/* 复位后ICS和OSC模块寄存器的默认值 */
+#define ICS_C1_DEFAULT  0x04
+#define ICS_C2_DEFAULT  0x20
+#define ICS_C3_DEFAULT  0x54
+#define ICS_C4_DEFAULT  0x00
+#define ICS_S_DEFAULT   0x50
+#define OSC_CR_DEFAULT  0
+
+
+/*****************************************************************************//*!
+   * 
+   * @ 概要  ICS的工作模式由当前的FEI模式切换为FEE模式，对选中的时钟源做1分频
+   *         OSC模块的输出时钟选择振荡器时钟源
+   * 
+   * @ 参数【输入】 pConfig  指向ICS配置结构体
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   *****************************************************************************/
+void FEI_to_FEE(ICS_ConfigType *pConfig)
+{
+	/*
+	 * 使能OSC模块
+	 */
+	OSC_Init(&pConfig->oscConfig); /*OSC模块初始化 */
+	
+	/* 
+     * 对外部参考时钟进行分频，可将外部时钟分频到31.25k~39.0625k之间
+	 */
+ 
+    ICS_SetClkDivider(pConfig->u32ClkFreq);
+
+        /*将FLL的参考时钟选择为外部时钟*/
+	ICS->C1 =  ICS->C1 & ~ICS_C1_IREFS_MASK;
+         
+        /*等待FLL参考时钟变为外部时钟*/
+
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop 
+};        
+#endif        
+	while(ICS->S & ICS_S_IREFST_MASK);
+	
+        /* 等待FLL时钟成为ICS输出时钟源*/
+	while(!(ICS->S & ICS_S_LOCK_MASK));
+		
+	/*
+     *现在FLL输出时钟变时钟频率等于FLL参考时钟分频结果乘以FLL的倍频系数
+	 * FLL的倍频系数请参考参考手册
+	 */
+#if defined(CPU_NV32)
+  /*对选中的ICS输出时钟源做1分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) == 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+	}
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+	
+	/*
+	 * 完成对选中的时钟源做1分频，系统/总线时钟时频率为设置的目标频率
+	 */
+    /*LOLS清0*/
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要  ICS的工作模式由当前的FEI模式转变成FBI模式，对选中的ICS输出时钟源
+   *         进行2分频
+   *        
+   * @ 参数  pConfig    指向ICS配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FEI_to_FBI(ICS_ConfigType *pConfig)
+{
+
+        /*ICS输出时钟源选择内部参考时钟*/
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(1);   
+	ICS->C2 = ICS->C2 & ~(ICS_C2_LP_MASK); 
+        /*等待内部时钟成为ICS输出时钟源*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif        
+	while(((ICS->S & ICS_S_CLKST_MASK) >> ICS_S_CLKST_SHIFT) !=1);
+			
+	/*
+	 * 现在内部参考时钟为ICS输出时钟源
+	 */
+#if defined(BUS_CLK_EQU_CORE_DIVIDE_BY_2)||defined(CPU_NV32) 
+         /*对选中的ICS输出时钟源做2分频*/       
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+
+#else
+	ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK));     
+#endif        
+	
+     /*LOLS清零*/
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要  ICS的工作模式由当前的FEI模式转换成FBE模式，对选中的ICS输出时钟源做2分频
+   *         OSC模块的输出时钟选择振荡器时钟源
+   *
+   * @ 参数  pConfig   指向ICS的配置结构体 . 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+
+void FEI_to_FBE(ICS_ConfigType *pConfig)
+{
+	OSC_Init(&pConfig->oscConfig); /*初始化OSC 模块 */
+
+         /*设置FLL的参考时钟为外部时钟*/
+
+    ICS->C1 =  ICS->C1 & ~(ICS_C1_IREFS_MASK);
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(2);   
+	ICS->C2 = ICS->C2 & ~(ICS_C2_LP_MASK); 
+       
+        /*等在参考时钟发生改变*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif        
+
+	while(((ICS->S & ICS_S_CLKST_MASK) >> ICS_S_CLKST_SHIFT) !=2);  /*外部时钟成为ICS时钟输出源*/
+        while(ICS->S & ICS_S_IREFST_MASK);  /*FLL参考时钟成为外部时钟*/
+			
+	/* 
+	 * 现在外部时钟成为ICS输出时钟源
+	 */
+#if defined(CPU_NV32)
+        /*对选中的ICS输出时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+	/* 
+	 * 现在ICS输出时钟频率为选中的输出时钟源的2分频
+	 */
+        /* LOLS清零 */
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+
+/*****************************************************************************//*!
+   *
+   * @ 概要  ICS的工作模式由当前的FEI模式转换成FBE模式，对选中的输出时钟源做2分频 
+   *         OSC输出时钟选择EXTAL引脚的外部时钟源 
+   *
+   * @ 参数 pConfig  指向配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FEI_to_FBE_OSC(ICS_ConfigType *pConfig)
+{
+    
+	OSC_Init(&pConfig->oscConfig); /* 初始化OSC */
+
+	/* 
+	 * 设置外部参考时钟的分频系数，将参考时钟的分频结果设定在FLL可以锁定的31.25k~39.0625k范围内，
+	 */
+    ICS_SetClkDivider(pConfig->u32ClkFreq);
+    
+        /*改变参考时钟源，将FLL的参考时钟设置为而外部时钟*/
+        ICS->C1 =  ICS->C1 & ~(ICS_C1_IREFS_MASK);/*将FLL的参考时钟设置为而外部时钟*/
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(2);  /*输出时钟源选择外部时钟*/ 
+	ICS->C2 = ICS->C2 & ~(ICS_C2_LP_MASK); 
+        
+        /* 等待参考时钟发生改变*/
+
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(((ICS->S & ICS_S_CLKST_MASK) >> ICS_S_CLKST_SHIFT) !=2);/*外部时钟成为ICS时钟输出时钟源*/
+        while(ICS->S & ICS_S_IREFST_MASK);   /*外部时钟成为FLL参考时钟*/
+			
+	/* 
+	 * 现在外部时钟成为FLL参考时钟和ICS输出时钟源
+	 */
+#if defined(CPU_NV32)
+             /*对选中的ICS输出时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+	/* 
+	 * 现在ICS的输出时钟频率，为外部参考时钟的2分频
+	 */
+        /*LOLS 清零*/
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要  ICS的工作模式由当前的FEI模式转换FEE模式，对选中的ICS输出时钟源做2分频 
+   *         OSC输出时钟选择EXTAL引脚的外部时钟源
+   *
+   * @ 参数  pConfig    指向配置结构体
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+
+void FEI_to_FEE_OSC(ICS_ConfigType *pConfig)
+{
+
+	OSC_Init(&pConfig->oscConfig); /* 初始化OSC */
+
+	/* 
+	 * 设置外部参考时钟的分频系数，将参考时钟的分频结果设定在FLL可以锁定的31.25k~39.0625k范围内
+	 */
+    ICS_SetClkDivider(pConfig->u32ClkFreq);
+
+        /* 将FLL的参考时钟设置为外部时钟 */
+        
+    ICS->C1 =  ICS->C1 & ~(ICS_C1_IREFS_MASK);
+
+        /*等待参考时钟变化*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(ICS->S & ICS_S_IREFST_MASK); /*FLL参考时钟变为外部时钟*/
+	
+        /*等待FLL成为ICS输出时钟源 */
+	while(!(ICS->S & ICS_S_LOCK_MASK));
+#if defined(CPU_NV32)	
+       /*对选中的时钟源做2分频*/	
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+	/* 
+	 * 现在ICS输出时钟频率，成为要设置的目标频率
+	 */
+
+     /* LOLS清零 */
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FEE模式转换成FEI模式.
+   *        
+   * @ 参数  pConfig  指向配置结构体 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FEE_to_FEI(ICS_ConfigType *pConfig)
+{
+       /*选择内部时钟作为FLL的参考时钟*/ 
+    ICS->C1 =  ICS->C1 | (ICS_C1_IREFS_MASK);
+	
+        /*等待参考时钟发生改变*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(!(ICS->S & ICS_S_IREFST_MASK)); /*FLL参考时钟成为内部时钟*/
+	
+        /*FLL时钟成为ICS输出时钟源 */
+	while(!(ICS->S & ICS_S_LOCK_MASK));
+         /*LOLS清零*/
+	ICS->S |= ICS_S_LOLS_MASK;
+
+	/* 
+	 * 现在FLL输出成为ICS输出时钟源
+	 */
+#if defined(CPU_NV32)
+        /*对选中的ICS输出时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+	/* 
+	 * 现在系统/总线时钟大约为 16MHz
+	 */
+	    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+      OSC_Disable();            /* 禁用 OSC模块 */
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FEE模式转换成FBI模式.
+   *        
+   * @ 参数 pConfig    指向配置结构体
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FEE_to_FBI(ICS_ConfigType *pConfig)
+{
+        /*LOLS清零*/
+	ICS->S |= ICS_S_LOLS_MASK;
+	
+  /* 选择内部时钟作为ICS输出时钟源 */
+	/* 选择内部时钟作为FLL参考时钟 */ 
+	/* LP = 0 在bypass模式FLL不会被禁止*/
+        
+    ICS->C1 =  ICS->C1 | (ICS_C1_IREFS_MASK);
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(1);   
+	ICS->C2 = ICS->C2 & ~(ICS_C2_LP_MASK); 
+
+        /* 等待参考时钟发生改变 */
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(!(ICS->S & ICS_S_IREFST_MASK));  /*FLL参考时钟成为内部时钟*/
+	while(((ICS->S & ICS_S_CLKST_MASK) >> ICS_S_CLKST_SHIFT) !=1);  /*内部时成为ICS输出时钟源*/
+	
+#if defined(BUS_CLK_EQU_CORE_DIVIDE_BY_2)||defined(CPU_NV32)  
+         /*对所选中的ICS输出时钟源做2分频*/      
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+
+#else
+	ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK));
+       
+#endif    
+        OSC_Disable();            
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要  将ICS的工作模式由当前的FEE模式转变成FBE模式
+   *        
+   * @ 参数  pConfig  指向配置结构体
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+
+void FEE_to_FBE(ICS_ConfigType *pConfig)
+{
+        /*LOLS清零*/
+	ICS->S |= ICS_S_LOLS_MASK;
+	
+	
+        /* LP = 0 */
+        /*选择外部时钟作为ICS输出时钟源*/
+        /* LP = 0 在bypass模式FLL不会被禁止*/
+
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(2);   
+	ICS->C2 = ICS->C2 & ~(ICS_C2_LP_MASK); 
+
+        /*等待输出时钟源发生改变*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(((ICS->S & ICS_S_CLKST_MASK) >> ICS_S_CLKST_SHIFT) !=2);
+	
+   /* 现在ICS输出时钟源选择外部时钟源
+	 * 注释: 确保外部时钟频率在20MHz以内
+	 */
+#if defined(CPU_NV32)
+        /*对选择的ICS输出时钟源做2分频*/	 
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}	
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBI模式转换成FBE模式
+   *        
+   * @ 参数  pConfig   指向配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBI_to_FBE(ICS_ConfigType *pConfig)
+{
+	OSC_Init(&pConfig->oscConfig); /*初始化OSC*/
+    
+	/* 选择外部时钟做为FLL的参考时钟 */
+	/*选择外部时钟作为输出时钟源*/
+
+       ICS->C1 =  ICS->C1 & ~(ICS_C1_IREFS_MASK);
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(2);   
+
+
+	/* 等待输出时钟源发生改变 */
+
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(((ICS->S & ICS_S_CLKST_MASK) >> ICS_S_CLKST_SHIFT) !=2); /*外部时钟成为ICS输出时钟源*/
+	while((ICS->S & ICS_S_IREFST_MASK));/*外部时钟成为FLL的参考时钟*/
+
+        /* 现在系统时钟源是外部参考时钟
+	 * 注释:确保外部时钟源的频率在20MHz内
+	 */
+#if defined(CPU_NV32)
+         /*对选中的时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}	
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+}
+
+/*****************************************************************************//**
+   *
+   * @ 概要 将ICS的工作模式由当前的FBI模式转换成FEE模式
+   *        
+   * @ 参数  pConfig    指向配置结构体 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBI_to_FEE(ICS_ConfigType *pConfig)
+{
+	OSC_Init(&pConfig->oscConfig); /*初始化OSC*/
+ 
+	/* 选择外部时钟作为FLL的参考时钟 */
+	/* 选择FLL输出作为做为ICS输出时钟源*/
+
+    ICS->C1 =  ICS->C1 & ~(ICS_C1_IREFS_MASK);
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK));   
+
+        /*等待时钟源改变*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+
+	while((ICS->S & ICS_S_CLKST_MASK));   /*FLL时钟成为ICS输出时钟源*/
+	while((ICS->S & ICS_S_IREFST_MASK));  /*外部时钟成为FLL参考时钟*/
+	
+     /* 现在系统时钟源为外部时钟
+	 * 注释: 确保外部时钟源的频率在20MHz内
+	 */
+#if defined(CPU_NV32)
+        /*对选中的时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+       /*LOLS清零*/
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBI模式转换成FBIP模式 
+   * 
+   * @ 参数  pConfig   输出指向配置结构体 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 警告 必须运行在调试接口没有没有接线的状态下
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBI_to_FBILP(ICS_ConfigType *pConfig)
+{
+	/*
+	 * 假设外部晶振时8MHz或者4MHz
+	 */
+	ICS->C2 |= ICS_C2_LP_MASK;	/*进入低功耗模式 */
+}
+
+
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBI模式转变为FEI模式
+   * 
+   * @ 参数 pConfig  指向配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBI_to_FEI(ICS_ConfigType *pConfig)
+{
+     /* 选择内部时钟为FLL的参考时钟 */
+	/*选择FLL输出作为ICS输出时钟源*/
+    ICS->C1 =  ICS->C1 | (ICS_C1_IREFS_MASK);
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK));   
+	
+        /*等待时钟源发生改变*/
+
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while((ICS->S & ICS_S_CLKST_MASK));    /*FLL输出成为ICS输出时钟源*/
+	while(!(ICS->S & ICS_S_IREFST_MASK));  /*FLL的参考时钟选择为外部时钟*/
+
+        
+	/* 
+	 * 现在ICS输出时钟源为FLL输出
+	 */
+#if defined(CPU_NV32)
+         /*对选中的时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}	
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+
+        /*LOLS清零 */
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要  将ICS的工作模式由当前的FBE模式转换成FBI模式
+   *        
+   * @ 参数  pConfig   指向配置结构体 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBE_to_FBI(ICS_ConfigType *pConfig)
+{
+        /*选择内部时钟作为FLL的参考时钟*/
+	/*选择内部时钟作为ICS输出时钟源*/
+    ICS->C1 =  ICS->C1 | (ICS_C1_IREFS_MASK);
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK)) | ICS_C1_CLKS(1);   
+	
+        /*等待时钟源发生改变*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(((ICS->S & ICS_S_CLKST_MASK) >> ICS_S_CLKST_SHIFT) != 1);/*内部时钟成为ICS输出时钟源*/
+	while(!(ICS->S & ICS_S_IREFST_MASK)); /*内部时钟成为FLL的参考时钟*/
+	
+	/* 
+	 * 现在ICS输出时钟源为内部时钟
+	 */
+	 
+#if defined(CPU_NV32)
+        /*对选中的时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}	
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif
+        
+    /* 
+     * 禁用OSC模块
+     */
+    OSC_Disable();
+}
+
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBE模式转换成FEE模式
+   *        
+   * @ 参数 pConfig   指向配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBE_to_FEE(ICS_ConfigType *pConfig)
+{
+	
+        /*选择FLL输出作为输出时钟源*/
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK));   
+	
+        /*等待ICS输出时钟源发生改变*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while(ICS->S & ICS_S_CLKST_MASK);
+
+	
+	/* 
+    * 现在ICS输出时钟源为FLL输出
+	 * 注释: 外部时钟频率 <= 20MHz
+	 */
+#if defined(CPU_NV32)
+         /*对选中的ICS输出时钟源做2分频*/
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}	
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif	
+         /* LOLS清零 */
+	ICS->S |= ICS_S_LOLS_MASK;	
+}
+
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBE模式转变成FEI模式
+   *        
+   * @ 参数 pConfig    指向配置结构体 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBE_to_FEI(ICS_ConfigType *pConfig)
+{
+    /* 选择内部时钟作为FLL的参考时钟*/
+	/*选择FLL输出做为ICS输出时钟源*/
+
+    ICS->C1 =  ICS->C1 | (ICS_C1_IREFS_MASK);
+	ICS->C1 = (ICS->C1 & ~(ICS_C1_CLKS_MASK));   
+	
+        /*等待时钟源改变*/
+#if defined(IAR)        
+	asm(
+		"nop \n"
+		"nop \n"
+	);
+#elif defined(__MWERKS__)
+	asm{
+		nop 
+		nop
+        };        
+#endif     
+	while((ICS->S & ICS_S_CLKST_MASK));   /*FLL输出成为ICS输出时钟源*/
+	while(!(ICS->S & ICS_S_IREFST_MASK)); /*内部时钟中成为FLL参考时钟*/
+
+  /* 
+   * 现在FLL输出成为ICS输出时钟源
+   */
+
+#if defined(CPU_NV32)
+
+       /*对选中的时钟源做2分频*/	
+	if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) != 1)
+	{
+		ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(1);
+	}
+#else
+    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+#endif	
+         /*LOLS清零*/
+	ICS->S |= ICS_S_LOLS_MASK;	
+        
+    /*
+     *禁用OSC模块
+     */
+    OSC_Disable();
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBE模式转变为FBELP模式
+   *
+   * @ 参数  pConfig   指向配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBE_to_FBELP(ICS_ConfigType *pConfig)
+{
+	/* enter low power mode */
+        /*进入低功耗模式*/
+ 	ICS->C2 = ICS->C2 | (ICS_C2_LP_MASK); 
+}
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBELP模式转换成FBE模式
+   * 
+   * @ 参数  pConfig     指向配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBELP_to_FBE(ICS_ConfigType *pConfig)
+{
+	/* enter low power mode */
+        /*禁用低功耗模式*/
+ 	ICS->C2 = ICS->C2 & ~(ICS_C2_LP_MASK); 
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 将ICS的工作模式由当前的FBILP转换到FBI模式 
+   * 
+   * @ 参数  pConfig  指向配置结构体. 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+void FBILP_to_FBI(ICS_ConfigType *pConfig)
+{
+	/* enter low power mode */
+        /*禁用低功耗模式*/
+	ICS->C2 = ICS->C2 & ~(ICS_C2_LP_MASK); 
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 调整内部内部时钟 (IRC). 
+   * 
+   * @ 参数  u16TrimValue   调整值 
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   *****************************************************************************/
+
+void ICS_Trim(uint16_t u16TrimValue)
+{
+   ICS->C3 =  (uint8_t) u16TrimValue;  /*将调整值写入寄存器*/
+   ICS->C4 = (ICS->C4 & ~(ICS_C4_SCFTRIM_MASK)) | ((u16TrimValue>>8) & 0x01);
+   while(!(ICS->S & ICS_S_LOCK_MASK));    
+}
+/*****************************************************************************//*!
+   *
+   * @ 概要 对外部参考时钟进行分频，使得分频结果在FLL可以锁定的31.25k~39.0625k内
+   *
+   * @ 参数 u32ClkFreqKHz    参考时钟频率.
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   *****************************************************************************/
+
+void ICS_SetClkDivider(uint32_t u32ClkFreqKHz)
+{
+    
+    switch(u32ClkFreqKHz)
+    {
+        case 8000L:
+        case 10000L:
+            /* 8MHz or 10MHz*/
+            ICS->C1 = (ICS->C1 & ~(ICS_C1_RDIV_MASK)) | ICS_C1_RDIV(3);	
+                                                                         /*8MHz分频结果是 8000/256 = 31.25K */ 
+                                                                        /*10MHz分频结果是 8000/256 = 31.25K*/ 
+            break;
+        case 4000L:
+            /* 4MHz */
+            ICS->C1 = (ICS->C1 & ~(ICS_C1_RDIV_MASK)) | ICS_C1_RDIV(2);	
+                                                                        /*4MHz分频结果是 4000/128 = 31.25K*/
+            break;
+        case 12000L:
+            /* 12MHz */
+            ICS->C1 = (ICS->C1 & ~(ICS_C1_RDIV_MASK)) | ICS_C1_RDIV(3);	
+                                                                        /*12MHz分频结果是12000/512 = 23.43K*/
+            break;
+        case 16000L:
+            /* 16MHz */
+            ICS->C1 = (ICS->C1 & ~(ICS_C1_RDIV_MASK)) | ICS_C1_RDIV(4);	
+                                                                        /* 16MHz分频结果是 16000/512 = 31.25K */
+            break;
+        case 20000L:
+            /* 20MHz */
+            ICS->C1 = (ICS->C1 & ~(ICS_C1_RDIV_MASK)) | ICS_C1_RDIV(4); 
+                                                                        /*20MHz分频结果是 20000/512 = 39.0625K */
+            break;
+        case 32L:
+            /* 32KHz */
+            ICS->C1  &= ~(ICS_C1_RDIV_MASK);
+            break;
+        default:
+            break;
+    }
+}
+/*****************************************************************************//*!
+   *
+   * @ 概要 初始化ICS模块根据定义所需要的总线时钟频率.
+   * 
+   * @ 参数 pConfig  指向配置结构体.  
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_ConfigType
+   *****************************************************************************/
+
+
+void ICS_Init(ICS_ConfigType *pConfig)
+{
+  if(pConfig->u8ClkMode == ICS_CLK_MODE_FEE)
+  {    
+        pConfig->oscConfig.bIsCryst = 1;   /* OSC的输出选择选择振动器时钟源 */ 
+        pConfig->oscConfig.bWaitInit = 1;  /* 等待振荡器初始化化完成 */       
+     
+      /*选择FEE模式，OSC输出选择振荡器时钟源*/
+        FEI_to_FEE(pConfig);             
+  }
+  else if (pConfig->u8ClkMode == ICS_CLK_MODE_FEE_OSC)
+  {     
+        pConfig->oscConfig.bIsCryst = 0;     /*OSC输出时钟选择EEXTAL引脚的外部时钟源*/ 
+
+     /*选择FEE工作模式；OSC输出时钟选择EEXTAL引脚的外部时钟源*/
+        FEI_to_FEE_OSC(pConfig);                
+  }
+  else if (pConfig->u8ClkMode == ICS_CLK_MODE_FBE_OSC)
+  {
+        pConfig->oscConfig.bIsCryst = 0;  /* is clock：OSC输出时钟选择EXTAL引脚的外部时钟源 */            
+        /* 选择FBE工作模式；OSC输出时钟选择EXTAL引脚的外部时钟源*/
+        FEI_to_FBE_OSC(pConfig);               
+  } 
+	else if(pConfig->u8ClkMode == ICS_CLK_MODE_FBELP )
+	{
+	pConfig->oscConfig.bIsCryst = 1;        /* OSC的输出时钟选择选择振动器时钟源 */
+        pConfig->oscConfig.bWaitInit = 1;       /*等待振荡器初始化化完成 */		
+
+        /* 选择FBE模式，OSC的输出时钟选择选择振动器时钟源*/
+                    FEI_to_FBE(pConfig);    /*先选择PBE模式*/            
+		    FBE_to_FBELP(pConfig);   /*选择FBELP*/
+		    ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+	}
+		else if(pConfig->u8ClkMode == ICS_CLK_MODE_FBILP )
+	{
+       
+            /* OSC输出时钟选择EXTAL引脚的外部时钟源*/            
+		    pConfig->oscConfig.bIsCryst = 0; 
+     
+            /* 选择FBE模式，OSC输出时钟选择EXTAL引脚的外部时钟源*/
+              FEI_to_FBI(pConfig);               
+	      FBI_to_FBILP(pConfig); 
+	      ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+	}
+  else
+  {
+      
+       /*ICS默认工作模式FEI模式*/
+        #if defined(CPU_NV32)
+        if(((ICS->C2 & ICS_C2_BDIV_MASK)>>5) == 1)
+        {
+            ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+        }
+        #else
+            ICS->C2 = (ICS->C2 & ~(ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(0);
+        #endif
+  }
+
+}
+/*****************************************************************************//*!
+   *
+   * @ 概要 对ICS模块各寄存器进行复位.
+   * 
+   * @ 无参数   
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看  ICS_Init
+   *****************************************************************************/
+
+void ICS_DeInit(void)
+{
+    ICS->C1 = ICS_C1_DEFAULT;
+    ICS->C2 = ICS_C2_DEFAULT;
+    ICS->C3 = ICS_C3_DEFAULT;
+    ICS->C4 = ICS_C4_DEFAULT;
+    while(ICS->S != ICS_S_DEFAULT)
+        ;       
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 通过设定的参数初始化XOSC
+   * 
+   * @ 参数  pConfig   指向osc配置结构体
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   *****************************************************************************/
+void OSC_Init(OSC_ConfigType *pConfig)
+{
+	uint8   cr = 0;
+	/* 
+	 * 
+	 */
+	if(pConfig->bGain) /*高增益振荡器选择*/
+	{
+		/* high gain：选择高增益模式 */
+		cr |= OSC_CR_HGO_MASK ;		
+	}  
+	
+	if(pConfig->bRange)  /*频率范围的选择*/
+	{
+		cr |= OSC_CR_RANGE_MASK; /*选择高频范围 */	
+	}
+
+	if(pConfig->bStopEnable) /*停止模式下的OSC使能*/
+	{
+		cr |= OSC_CR_OSCSTEN_MASK; /*OSC在停止模式下保持使能*/
+	}
+
+	if(pConfig->bIsCryst)     /*OSC输出选择*/
+	{
+		cr |= OSC_CR_OSCOS_MASK; /*选择振荡器时钟*/
+	}
+
+	if(pConfig->bEnable)  /*OSC使能*/
+	{
+		cr |= OSC_CR_OSCEN_MASK;
+	}
+    
+    OSC->CR = cr;   /*数值写入控制寄存器*/
+    
+	if(pConfig->bWaitInit)
+	{
+
+		/* 
+     *等待初始化完成
+		 */
+		while(!(OSC->CR & OSC_CR_OSCINIT_MASK));
+		
+	}
+}
+
+/*****************************************************************************//*!
+   *
+   * @ 概要 重置OSC模块，使其恢复到默认状态.
+   * 
+   * @ 无输参数      
+   *
+   * @ 无返回
+   *
+   * @ 成功/失败的标准 ：无
+   * @ 参看   ICS_Init
+   *****************************************************************************/
+
+void OSC_DeInit(void)
+{
+    OSC->CR = OSC_CR_DEFAULT;
+}
+                                                	
+
+
+
+

bsp/nv32f100x/lib/src/kbi.c

@@ -0,0 +1,296 @@
+/******************************************************************************
+*
+* @brief providing APIs for configuring KBI. 
+*
+*******************************************************************************
+*
+* provide APIs for configuring KBI
+******************************************************************************/
+#include "common.h"
+#include "kbi.h"
+/******************************************************************************
+* External objects
+******************************************************************************/
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+KBI_CallbackType KBI_Callback[KBI_MAX_NO] = {(KBI_CallbackType)NULL};
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+/******************************************************************************
+* KBI api list
+*
+*//*! @addtogroup kbi_api_list
+* @{
+*******************************************************************************/
+
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief initialize KBI module.
+*        
+* @param[in]  pKBI        pointer to KBI module.
+* @param[in]  pConfig     pointer to KBI configuration structure.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_DeInit.
+*
+*****************************************************************************/
+void KBI_Init(KBI_Type *pKBI, KBI_ConfigType *pConfig)
+{
+#if defined(CPU_NV32)
+    uint16_t    i;
+    uint8_t     sc = 0;
+    uint8_t     u8Port;
+    uint8_t     u8PinPos;
+    uint16_t    u16PinMapping[KBI_MAX_NO][8] = 
+    {
+        {
+            0, 1, 2, 3, 8, 9, 10, 11           /* KBI0 pins position in GPIOA register */
+        },
+        {
+            24, 25, 26, 27, 28, 29, 30, 31      /* KBI1 pins position in GPIOA register */
+        }
+    };
+#elif defined(CPU_NV32M3)
+    uint16_t    i;
+    uint8_t     sc = 0;
+    uint8_t     u8Port;
+    uint8_t     u8PinPos;
+    uint16_t    u16PinMapping[KBI_MAX_NO][8] = 
+    {
+        {
+            0, 1, 2, 3, 8, 9, 10, 11           /* KBI0 pins position in GPIOA register */
+        },
+        {
+            20, 21, 16, 17, 18, 19, 12, 13      /* KBI1 pins position in GPIOA register */
+        }
+    };
+#elif defined(CPU_NV32M4)
+     uint32_t    i;
+     uint32_t     sc = 0;
+     uint32_t     u8Port;
+     uint32_t     u8PinPos;
+
+     uint32_t    u16PinMapping[KBI_MAX_NO][KBI_MAX_PINS_PER_PORT] =
+    {
+        {/* KBI0P0~KBI0P31 pins position in GPIOA register */
+            0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31           
+        },
+        {/* KBI1P0~KBI1P31 pins position in GPIOB register */
+			0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31		   
+        }
+    };
+#endif	 
+ 
+    
+    if(KBI0 == pKBI)
+    {
+        SIM->SCGC   |= SIM_SCGC_KBI0_MASK;             /* enable clock to KBI0 */\
+        u8Port      =  0;
+    }
+    else if (KBI1 == pKBI)
+    {        
+        SIM->SCGC   |= SIM_SCGC_KBI1_MASK;             /* enable clock to KBI1 */
+        u8Port      =  1;
+    }
+    
+    /* mask keyboard interrupts first */
+    sc          = pConfig->sBits.bMode;
+    pKBI->SC    = sc;
+
+    /* configure KBI pin polarity and others */
+    for (i = 0; i < KBI_MAX_PINS_PER_PORT; i++)
+    {
+        if(pConfig->sPin[i].bEn)
+        {
+            pKBI->PE    |= (1<<i);                      /* enable this KBI pin */
+            pKBI->ES    = (pKBI->ES & ~(1<<i)) | (pConfig->sPin[i].bEdge << i);     
+            u8PinPos = u16PinMapping[u8Port][i];
+            ASSERT(!(u8PinPos & 0x80));
+		#if defined(CPU_NV32)|| defined(CPU_NV32M3)	
+            FGPIOA->PIDR  &= ~(1<<u8PinPos);              /* enable GPIO input */     
+            FGPIOA->PDDR  &= ~(1<<u8PinPos);              /* configure pin as input */  
+            PORT->PUEL  |= (1<<u8PinPos);                 /* enable pullup for the pin */
+        #elif defined(CPU_NV32M4)
+		   if (u8Port == 0)   /* KBI0 */
+           {
+		   	FGPIOA->PIDR  &= ~(1<<u8PinPos);              /* enable GPIO input */    
+            FGPIOA->PDDR  &= ~(1<<u8PinPos);              /* configure pin as input */ 
+            PORT->PUE0  |= (1<<u8PinPos);                 /*enable pullup for the pin */
+           }
+		   else if (u8Port == 1)   /* KBI1 */
+           {
+		   	FGPIOB->PIDR  &= ~(1<<u8PinPos);              /* enable GPIO input */     
+            FGPIOB->PDDR  &= ~(1<<u8PinPos);              /* configure pin as input */ 
+            PORT->PUE1  |= (1<<u8PinPos);                 /*enable pullup for the pin */
+           }
+		#endif  
+		}
+    }
+    
+    #if defined(CPU_NV32M4)
+    /*Reset KBI_SP register*/
+	sc = pConfig->sBits.bRstKbsp<<KBI_SC_RSTKBSP_SHIFT;
+	pKBI->SC    |= sc;
+	
+    /*Real KBI_SP register enable*/
+	sc = pConfig->sBits.bKbspEn<<KBI_SC_KBSPEN_SHIFT;
+	pKBI->SC    |= sc;
+	#endif
+  
+	/* write to KBACK to clear any false interrupts */
+    pKBI->SC    = sc;
+    
+    /* enable interrupt if needed */
+    if(pConfig->sBits.bIntEn)
+    {
+        pKBI->SC    |=  KBI_SC_KBIE_MASK;
+        
+        if(KBI0 == pKBI)
+        {
+            NVIC_EnableIRQ(KBI0_IRQn);
+        }
+        else
+        {
+            NVIC_EnableIRQ(KBI1_IRQn);            
+        }
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief set up KBI callback routine.
+*        
+* @param[in] pKBI          pointer to KBI module.
+* @param[in] pfnCallback   pointer to callback routine.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+void KBI_SetCallback(KBI_Type *pKBI, KBI_CallbackType pfnCallback)
+{
+    if(KBI0 == pKBI)
+    {
+        KBI_Callback[0] = pfnCallback;
+    }
+    else
+    {
+        KBI_Callback[1] = pfnCallback;        
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief deinit the kbi module.
+*        
+* @param[in]  pKBI       pointer to KBI module.
+*         
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see KBI_Init.
+*
+*****************************************************************************/
+void KBI_DeInit(KBI_Type *pKBI)
+{
+    if(KBI0 == pKBI)
+    {
+        NVIC_DisableIRQ(KBI0_IRQn);
+    }
+    else
+    {
+        NVIC_DisableIRQ(KBI1_IRQn);        
+    }
+    
+    pKBI->PE = 0;
+    pKBI->SC = 0;
+    pKBI->ES = 0;
+    
+    if(KBI0 == pKBI)
+    {
+        SIM->SCGC   &= ~SIM_SCGC_KBI0_MASK;             /* disable clock to KBI0 */
+    }
+    else
+    {
+        SIM->SCGC   &= ~SIM_SCGC_KBI1_MASK;             /* disable clock to KBI1 */       
+    }
+}
+
+/*! @} End of acmp_api_list                                                  */
+
+/*****************************************************************************//*!
+*
+* @brief button group 0 (KBI0) interrupt service routine.
+*        
+* @param  none. 
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+
+void KBI0_Isr(void)	
+{
+  KBI0->SC |= KBI_SC_KBACK_MASK;                        /* clear interrupt flag */
+
+  if(KBI_Callback[0])
+  {
+      KBI_Callback[0]();
+  }
+}
+
+
+
+/*****************************************************************************//*!
+*
+* @brief button group 0 (KBI0) interrupt service routine.
+*        
+* @param  none. 
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+
+void KBI1_Isr(void)	
+{
+  KBI1->SC |= KBI_SC_KBACK_MASK;                        /* clear interrupt flag */
+ 
+  if(KBI_Callback[1])
+  {
+      KBI_Callback[1]();
+  }
+}
+

bsp/nv32f100x/lib/src/pit.c

@@ -0,0 +1,213 @@
+/******************************************************************************
+* @brief    Periodic Interrupt ETMer (PIT) source code. 
+*
+******************************************************************************/
+#include "common.h"
+#include "pit.h"
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+/*!
+ * @brief global variable to store PIT callbacks.
+ *
+ */
+PIT_CallbackType PIT_Callback[2] = {(PIT_CallbackType)NULL}; /*!< PIT initial callback */
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+void PIT_Ch0Isr(void);
+void PIT_Ch1Isr(void);
+
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define PIT APIs
+*
+*//*! @addtogroup pit_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief initialize pit module.
+*        
+* @param[in]   u8Channel_No channel number
+* @param[in]   pConfig point to configuration  
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void PIT_Init(uint8_t u8Channel_No, PIT_ConfigType *pConfig)
+{  
+    SIM->SCGC |= SIM_SCGC_PIT_MASK;     /*!< enable clock to PIT */
+    
+    if (pConfig->bFreeze)            
+    {                                               
+        PIT_SetDebugFreeze();            
+    } 
+    
+    if (pConfig->bModuleDis == 0) 
+    {                                              
+        PIT_Enable();       /*!< enable pit module */                                                                                
+    }  
+    
+    PIT_SetLoadVal(u8Channel_No, pConfig->u32LoadValue);  
+    
+    if (pConfig->bInterruptEn)            
+    {                                   
+        if (u8Channel_No)
+        {        
+             NVIC_EnableIRQ(PIT_CH1_IRQn);             
+        }
+        else
+        {                  
+            NVIC_EnableIRQ(PIT_CH0_IRQn);
+        }
+        PIT_ChannelEnableInt(u8Channel_No);
+    }                   
+    else                                     
+    {                     
+        NVIC_DisableIRQ(PIT_CH0_IRQn);       
+    }
+
+    if (pConfig->bChainMode)            
+    {                                               
+        PIT_ChannelEnableChain(u8Channel_No);            
+    }
+    
+    if (pConfig->bETMerEn)            
+    {                                               
+        PIT_ChannelEnable(u8Channel_No);            
+    }             
+
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief initialize pit module.
+*        
+* @param[in]   u8Channel_No channel number
+* @param[in]   u32loadvalue load value for pit register  
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void PIT_SetLoadVal(uint8_t u8Channel, uint32_t u32loadvalue)
+
+{
+    PIT->CHANNEL[u8Channel].LDVAL = u32loadvalue;   
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief pit module set call back.
+*        
+* @param[in] u8Channel_No channel number.   
+* @param[in] pfnCallback point to call back.   
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void PIT_SetCallback(uint8_t u8Channel_No, PIT_CallbackType pfnCallback)
+{
+  PIT_Callback[u8Channel_No] = pfnCallback;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief pit module de-initialize, reset pit register
+*        
+* @param none  
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void PIT_DeInit(void)
+{
+    NVIC_DisableIRQ(PIT_CH0_IRQn);
+    NVIC_DisableIRQ(PIT_CH1_IRQn);    
+    PIT_SetLoadVal(0,0);
+    PIT_SetLoadVal(1,0);
+    PIT_ChannelDisable(0);
+    PIT_ChannelDisable(1);
+    PIT_ChannelDisableInt(0);
+    PIT_ChannelDisableInt(1);
+    PIT_ChannelDisableChain(0);
+    PIT_ChannelDisableChain(1);    
+    PIT_ChannelClrFlags(0);
+    PIT_ChannelClrFlags(1);    
+    PIT_SetDebugOn();
+    PIT_Disable();
+    SIM->SCGC &= ~SIM_SCGC_PIT_MASK;
+}
+/*! @} End of pit_api_list                                                   */
+
+
+/*****************************************************************************//*!
+*
+* @brief pit module channel 0 isr.
+*        
+* @param none
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void PIT_Ch0Isr(void) 
+{   
+   PIT_ChannelClrFlags(0);  
+    
+    if (PIT_Callback[0])
+    {    
+        PIT_Callback[0]();     
+    }
+}
+    
+/*****************************************************************************//*!
+*
+* @brief pit module channel 1 isr.
+*        
+* @param none
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void PIT_Ch1Isr(void) 
+{   
+    PIT_ChannelClrFlags(1);
+    if (PIT_Callback[1])
+    {    
+        PIT_Callback[1]();     
+    }
+}    
+
+

bsp/nv32f100x/lib/src/pmc.c

@@ -0,0 +1,113 @@
+
+/******************************************************************************
+* @brief providing APIs for configuring PMC. 
+*
+*******************************************************************************
+*
+* provide APIs for configuring PMC
+******************************************************************************/
+#include "common.h"
+#include "pmc.h"
+
+/******************************************************************************
+* Constants
+******************************************************************************/
+/******************************************************************************
+* Macros
+******************************************************************************/
+/******************************************************************************
+* Types
+******************************************************************************/
+/******************************************************************************
+* Global variables
+******************************************************************************/
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* PMC api list.
+*
+*//*! @addtogroup pmc_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+*
+* @brief  configure PMC with given parameters.
+* 
+* @param[in]   pPMC_Config       PMC configuration structure.
+* @param[in]   pPMC             pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_DeInit.
+*
+*****************************************************************************/
+void PMC_Init(PMC_Type *pPMC, PMC_ConfigType *pPMC_Config)
+{
+    pPMC->SPMSC1 = pPMC_Config->sCtrlstatus.byte;
+    pPMC->SPMSC2 = pPMC_Config->sDetectVoltSelect.byte;         
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief  config the pmc register to the default mode.
+* 
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+* @see PMC_Init.
+*
+*****************************************************************************/
+void PMC_DeInit(PMC_Type *pPMC)
+{
+    pPMC->SPMSC1 = 0x1C;
+    pPMC->SPMSC2 = 0;         
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief  config the pmc mode among run, wait and stop modes.
+* 
+* @param[in]  u8PmcMode         PMC mode select.
+* @param[in]  pPMC              pointer to the PMC module.
+*
+* @return none.
+*
+* @ Pass/ Fail criteria: none.
+*
+*****************************************************************************/
+void PMC_SetMode(PMC_Type *pPMC,uint8_t u8PmcMode)
+{
+    switch(u8PmcMode & 0x3) 
+    {
+        case PmcModeRun:    
+            break;
+        case PmcModeWait:
+            wait();
+            break;
+        case PmcModeStop4:
+            /* enable LVD in stop mode */
+            pPMC->SPMSC1 |= (PMC_SPMSC1_LVDE_MASK | PMC_SPMSC1_LVDSE_MASK);	
+            stop();   
+            break;
+        case PmcModeStop3: 
+            /* disable LVD in stop mode */
+            pPMC->SPMSC1 &= ~(PMC_SPMSC1_LVDE_MASK | PMC_SPMSC1_LVDRE_MASK | PMC_SPMSC1_LVDSE_MASK);	
+            stop();  
+            break;
+        default: 
+            break;
+    }
+ 
+}
+
+/*! @} End of pmc_api_list                                                    */
+

bsp/nv32f100x/lib/src/rtc.c

@@ -0,0 +1,165 @@
+/******************************************************************************
+* @brief    Real-ETMe counter (RTC) driver source code.  
+*
+******************************************************************************/
+#include "common.h"
+#include "rtc.h"
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+/*!
+ * @brief global variable to store RTC callbacks.
+ *
+ */
+RTC_CallbackType RTC_Callback[1] = {(RTC_CallbackType)NULL};    /*!< RTC initial callback */
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+void RTC_Isr(void);
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define RTC APIs
+*
+*//*! @addtogroup rtc_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief inital RTC module
+*        
+* @param[in] pConfig point to configuration  
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void RTC_Init(RTC_ConfigType *pConfig)
+{
+    uint16_t    u16Clocksource, u16Prescler;
+    uint16_t    u16ModVal;
+    
+    u16Clocksource =0;  
+    u16Prescler    =0;
+    u16ModVal      =0;
+
+    SIM->SCGC     |= SIM_SCGC_RTC_MASK; 
+    
+    u16ModVal      = pConfig->u16ModuloValue;
+    RTC_SetModulo(u16ModVal); 
+    
+    if (pConfig->bRTCOut)
+    {
+    
+        RTC->SC= RTC_SC_RTCO_MASK;       
+    } 
+    
+    if (pConfig->bInterruptEn)
+    {
+         NVIC_EnableIRQ(RTC_IRQn);
+         RTC_EnableInt(); 
+    }
+    else      
+    {   
+        NVIC_DisableIRQ(RTC_IRQn);
+    }
+    
+    if (pConfig->bFlag)
+    {   
+        RTC_ClrFlags();         
+    }
+
+    u16Clocksource = pConfig->bClockSource; 
+    u16Prescler    = pConfig->bClockPresaler;
+     
+    RTC_SetClock(u16Clocksource,u16Prescler );
+}
+
+
+
+/*****************************************************************************//*!
+*
+* @brief set call back function for rtc module 
+*        
+* @param[in] pfnCallback point to call back function
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void RTC_SetCallback(RTC_CallbackType pfnCallback)
+{
+  RTC_Callback[0] = pfnCallback;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief de-initialize rtc module , reset rtc register
+*        
+* @param none  
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void RTC_DeInit(void)
+{
+    NVIC_DisableIRQ(RTC_IRQn);    
+    RTC->MOD = 0;
+    while(RTC->MOD);
+    
+    if(RTC_GetFlags())
+    {
+        RTC_ClrFlags();
+    }
+    
+    RTC->SC = 0;
+    while(RTC->SC);
+    SIM->SCGC &= ~SIM_SCGC_RTC_MASK;
+}
+
+/*! @} End of rtc_api_list                                                   */
+
+/*****************************************************************************//*!
+*
+* @brief RTC module interrupt service routine
+*        
+* @param none  
+*
+* @return none 
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void RTC_Isr(void) 
+{
+    RTC_ClrFlags();	       
+    if (RTC_Callback[0])
+    {    
+        RTC_Callback[0]();     
+    }
+}
+
+

bsp/nv32f100x/lib/src/sim.c

@@ -0,0 +1,348 @@
+
+/******************************************************************************
+*
+* @brief providing APIs for system integration module (SIM). 
+*
+*******************************************************************************
+*
+* provide APIs for SIM
+******************************************************************************/
+#include "common.h"
+#include "sim.h"
+
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define SIM API list
+*
+*//*! @addtogroup sim_api_list
+* @{
+*******************************************************************************/
+#if defined(CPU_NV32)
+/*****************************************************************************//*!
+   *
+   * @brief initialize SIM registers.
+   * 
+   * @param[in]  pConfig    pointer to SIM configuration.  
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   * @see SIM_ConfigType
+   *****************************************************************************/
+void SIM_Init(SIM_ConfigType *pConfig)
+{
+    uint32_t    u32Sopt;
+    uint32_t    u32PinSel;
+    uint32_t    u32Scgc;
+    uint32_t    u32BusDiv;
+    /*
+     * intialize the registers to reset default values
+     */
+    u32Sopt     = 0x0010000E;                 /* enable SWD, RESET, and NMI pins */
+    u32PinSel   = 0;
+    u32Scgc     = 0x00003000;           /* enable SWD and FLASH */
+    u32BusDiv   = 0;
+    u32BusDiv = pConfig->sBits.bBusDiv;
+    if(pConfig->sBits.bDisableNMI)
+    {
+        u32Sopt &= ~SIM_SOPT_NMIE_MASK;        
+    }
+    if(pConfig->sBits.bDisableRESET)
+    {
+        u32Sopt &= ~SIM_SOPT_RSTPE_MASK;        
+    }   
+    if(pConfig->sBits.bDisableSWD)
+    {
+        u32Sopt &= ~SIM_SOPT_SWDE_MASK;        
+    } 
+    if(pConfig->sBits.bEnableCLKOUT)
+    {
+        u32Sopt |= SIM_SOPT_CLKOE_MASK;        
+    } 
+    if(pConfig->sBits.bETMSYNC)
+    {
+        u32Sopt |= SIM_SOPT_ETMSYNC_MASK;        
+    }  
+    if(pConfig->sBits.bRXDCE)
+    {
+        u32Sopt |= SIM_SOPT_RXDCE_MASK;        
+    }
+    if(pConfig->sBits.bTXDME)
+    {
+        u32Sopt |= SIM_SOPT_TXDME_MASK;        
+    }
+    if(pConfig->sBits.bACIC)
+    {
+        u32Sopt |= SIM_SOPT_ACIC_MASK;
+    }
+        if(pConfig->sBits.bRTCC)
+    {
+        u32Sopt |= SIM_SOPT_RTCC_MASK;        
+    }
+        if(pConfig->sBits.bRXDFE)
+    {
+        u32Sopt |= SIM_SOPT_RXDFE_MASK;        
+    }
+    u32Sopt |= ((pConfig->u8BusRef & 0x07) << 16);        
+    u32Sopt |= ((pConfig->u8Delay) << 24);        
+    u32Sopt |= ((pConfig->sBits.u8ADHWT & 0x03) << 8);
+    u32PinSel = pConfig->u32PinSel;
+    u32Scgc = pConfig->u32SCGC;   
+    
+/* write SIM registers */
+    SIM->SOPT = u32Sopt;
+    SIM->PINSEL = u32PinSel;
+    SIM->SCGC = u32Scgc; 
+    SIM->BUSDIV = u32BusDiv;
+}
+#elif defined(CPU_NV32M3)
+/*****************************************************************************//*!
+   *
+   * @brief initialize SIM registers.
+   * 
+   * @param[in]  pConfig    pointer to SIM configuration.  
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   * @see SIM_ConfigType
+   *****************************************************************************/
+
+void SIM_Init(SIM_ConfigType *pConfig)
+{
+    uint32_t    u32Sopt;
+    uint32_t    u32PinSel;
+    uint32_t    u32Scgc;
+    uint32_t    u32ClockDiv;
+    /*
+     * intialize the registers to reset default values
+     */
+    u32Sopt     = 0x0010000E;                 /* enable SWD, RESET, and NMI pins */
+    u32PinSel   = 0;
+    u32Scgc     = 0x00003000;           /* enable SWD and FLASH */
+    u32ClockDiv = 0;
+    u32ClockDiv = pConfig->u32CLKDIV;
+    if(pConfig->sBits.bDisableNMI)
+    {
+        u32Sopt &= ~SIM_SOPT_NMIE_MASK;        
+    }
+    if(pConfig->sBits.bDisableRESET)
+    {
+        u32Sopt &= ~SIM_SOPT_RSTPE_MASK;        
+    }   
+    if(pConfig->sBits.bDisableSWD)
+    {
+        u32Sopt &= ~SIM_SOPT_SWDE_MASK;        
+    } 
+    if(pConfig->sBits.bEnableCLKOUT)
+    {
+        u32Sopt |= SIM_SOPT_CLKOE_MASK;        
+    } 
+    if(pConfig->sBits.bETMSYNC)
+    {
+        u32Sopt |= SIM_SOPT_ETMSYNC_MASK;        
+    }  
+    if(pConfig->sBits.bRXDCE)
+    {
+        u32Sopt |= SIM_SOPT_RXDCE_MASK;        
+    }
+    if(pConfig->sBits.bTXDME)
+    {
+        u32Sopt |= SIM_SOPT_TXDME_MASK;        
+    }
+    if(pConfig->sBits.bACTRG)
+    {
+        u32Sopt |= SIM_SOPT_ACTRG_MASK;
+    }
+    u32Sopt |= ((pConfig->u8BusRef & 0x07) << 16);        
+    u32Sopt |= ((pConfig->u8Delay) << 24);        
+    u32Sopt |= ((pConfig->sBits.u8ADHWT & 0x07) << 20);
+    u32Sopt |= ((pConfig->sBits.bRXDFE)&0x03<<8);
+    u32Sopt |= ((pConfig->sBits.bETMIC)&0x03<<6);
+
+    u32PinSel = pConfig->u32PinSel;
+    u32Scgc = pConfig->u32SCGC;    
+/* write SIM registers */
+    SIM->SOPT = u32Sopt;
+    SIM->PINSEL = u32PinSel;
+    SIM->SCGC = u32Scgc;
+    SIM->CLKDIV = u32ClockDiv;
+}
+#elif defined(CPU_NV32M4)
+/*****************************************************************************//*!
+   *
+   * @brief initialize SIM registers.
+   * 
+   * @param[in]  pConfig    pointer to SIM configuration.  
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   * @see SIM_ConfigType
+   *****************************************************************************/
+void SIM_Init(SIM_ConfigType *pConfig)
+{
+    uint32_t    u32Sopt;
+    uint32_t    u32PinSel;
+    uint32_t    u32Scgc;
+    uint32_t    u32ClockDiv;
+    /*
+     * intialize the registers to reset default values
+     */
+    u32Sopt     = 0x0E;                 /* enable SWD, RESET, and NMI pins */
+    u32PinSel   = 0;
+    u32Scgc     = 0x00003000;           /* enable SWD and FLASH */
+    u32ClockDiv = 0;
+    u32ClockDiv = pConfig->u32CLKDIV;
+    if(pConfig->sBits.bDisableNMI)
+    {
+        u32Sopt &= ~SIM_SOPT0_NMIE_MASK;        
+    }
+    if(pConfig->sBits.bDisableRESET)
+    {
+        u32Sopt &= ~SIM_SOPT0_RSTPE_MASK;        
+    }   
+    if(pConfig->sBits.bDisableSWD)
+    {
+        u32Sopt &= ~SIM_SOPT0_SWDE_MASK;        
+    } 
+    if(pConfig->sBits.bEnableCLKOUT)
+    {
+        u32Sopt |= SIM_SOPT0_CLKOE_MASK;        
+    } 
+    if(pConfig->sBits.bETMSYNC)
+    {
+        u32Sopt |= SIM_SOPT0_ETMSYNC_MASK;        
+    }  
+    if(pConfig->sBits.bRXDCE)
+    {
+        u32Sopt |= SIM_SOPT0_RXDCE_MASK;        
+    }
+    if(pConfig->sBits.bTXDME)
+    {
+        u32Sopt |= SIM_SOPT0_TXDME_MASK;        
+    }
+    if(pConfig->sBits.bACTRG)
+    {
+        u32Sopt |= SIM_SOPT0_ACTRG_MASK;
+    }
+    u32Sopt |= ((pConfig->u8BusRef & 0x07) << 16);        
+    u32Sopt |= ((pConfig->u8Delay) << 24);        
+    u32Sopt |= ((pConfig->sBits.u8ADHWT & 0x07) << 20);
+    u32Sopt |= ((pConfig->sBits.bRXDFE)&0x03<<8);
+    //u32Sopt |= ((pConfig->sBits.bETMIC)&0x03<<6);
+
+    u32PinSel = pConfig->u32PinSel;
+    u32Scgc = pConfig->u32SCGC;    
+/* write SIM registers */
+    SIM->SOPT0 = u32Sopt;
+    SIM->PINSEL = u32PinSel;
+    SIM->SCGC = u32Scgc;
+    SIM->CLKDIV = u32ClockDiv;
+}
+#endif
+
+/*****************************************************************************//*!
+   *
+   * @brief set SIM clock gating registers to enable or disable peripheral clocks.
+   * 
+   * @param[in]  u32PeripheralMask    peripherial bits mask.  
+   * @param[in]  u8GateOn             1: ON, 0: OFF.  
+   *
+   * @return none
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+
+void SIM_SetClockGating(uint32_t u32PeripheralMask, uint8_t u8GateOn)
+{
+    uint32_t    u32Scgc;
+
+    /*
+     * save original clock gating value
+     */
+    u32Scgc     = SIM->SCGC;
+    
+    if(u8GateOn)
+    {
+        u32Scgc |= u32PeripheralMask;
+    }
+    else
+    {
+        u32Scgc &= ~u32PeripheralMask;        
+    }
+
+    SIM->SCGC = u32Scgc;
+}
+
+
+/*****************************************************************************//*!
+   *
+   * @brief read the corresponding status flags.
+   * 
+   * @param[in]  u32StatusMask    indicates which status to be read. 
+   *
+   * @return status.
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+uint32_t SIM_GetStatus(uint32_t u32StatusMask)
+{
+    uint32_t    u32Status;
+
+    u32Status = SIM->SRSID & u32StatusMask;
+    return (u32Status);
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief read the corresponding ID.
+   * 
+   * @param[in]  u8ID    type of ID. 
+   *
+   * @return ID
+   *
+   * @ Pass/ Fail criteria: none.
+   * @see   IDType.
+   *****************************************************************************/
+uint8_t SIM_ReadID(IDType sID)
+{
+    uint32_t    u32ID;
+    uint8_t u8IDOffset[4] = 
+    { 
+        28, 24, 20,16
+    };  
+    u32ID = (SIM->SRSID >> u8IDOffset[sID]) & 0x0F;
+    return (u32ID);
+}
+/*! @} End of sim_api_list                                                    */
+
+
+

bsp/nv32f100x/lib/src/spi.c

@@ -0,0 +1,329 @@
+
+/******************************************************************************
+* @brief providing APIs for configuring SPI module (SPI). 
+*
+*******************************************************************************
+*
+* provide APIs for configuring SPI module (SPI).
+******************************************************************************/
+#include "common.h"
+#include "spi.h"
+
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+SPI_CallbackType SPI_Callback[MAX_SPI_NO] = {(SPI_CallbackType)NULL};
+
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+*****************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define SPI APIs
+*
+*//*! @addtogroup spi_api_list
+* @{
+*******************************************************************************/
+/*****************************************************************************//*!
+   *
+   * @brief initialize SPI as per params.
+   *        
+   * @param[in]  pSPI   point to SPI module type.
+   * @param[in]  pConfig point to configuration parameters.
+   *
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+void SPI_Init(SPI_Type *pSPI, SPI_ConfigType *pConfig)
+{
+#if defined(CPU_NV32M3)  
+     /* sanity check */
+    ASSERT((pSPI == SPI0));
+    SIM->SCGC |= SIM_SCGC_SPI0_MASK;
+#else
+    /* sanity check */
+    ASSERT((pSPI == SPI0) ||  (pSPI == SPI1));
+    
+    /* enable SPI clock gating on */
+    if( pSPI == SPI0)
+    {
+        SIM->SCGC |= SIM_SCGC_SPI0_MASK;
+    }
+    else
+    {
+        SIM->SCGC |= SIM_SCGC_SPI1_MASK;     
+    }
+#endif
+    /* configure other control bits */
+    if( pConfig->sSettings.bIntEn)
+    {
+        SPI_IntEnable(pSPI);
+#if defined(CPU_NV32M3)  
+        NVIC_EnableIRQ(SPI0_IRQn);  
+#else
+        if( pSPI == SPI0 )
+        {
+			NVIC_EnableIRQ(SPI0_IRQn);
+        }
+        else
+        {
+			NVIC_EnableIRQ(SPI1_IRQn);
+        }
+#endif
+    }
+
+    if( pConfig->sSettings.bTxIntEn)
+    {
+        SPI_TxIntEnable(pSPI);
+#if defined(CPU_NV32M3)  
+        NVIC_EnableIRQ(SPI0_IRQn);  
+#else
+        if( pSPI == SPI0 )
+        {
+			NVIC_EnableIRQ(SPI0_IRQn);
+        }
+        else
+        {
+			NVIC_EnableIRQ(SPI1_IRQn);
+        }
+#endif
+    }
+    if( pConfig->sSettings.bMasterMode)
+    {
+        SPI_SetMasterMode(pSPI);
+    }
+    else
+    {
+		SPI_SetSlaveMode(pSPI);
+    }
+
+    if( pConfig->sSettings.bClkPolarityLow)
+    {
+    	SPI_SetClockPol(pSPI,1);
+    }
+    if( pConfig->sSettings.bClkPhase1)
+    {
+        SPI_SetClockPhase(pSPI,1);
+    }else
+	{	
+     SPI_SetClockPhase(pSPI,0);
+	}  
+    if( pConfig->sSettings.bShiftLSBFirst)
+    {
+        SPI_SetLSBFirst(pSPI);
+    }
+    if( pConfig->sSettings.bMatchIntEn)
+    {
+        SPI_MatchIntEnable(pSPI);
+    }
+    if( pConfig->sSettings.bModeFaultEn)
+    {
+        SPI_ModfEnable(pSPI);
+    }
+    if( pConfig->sSettings.bMasterAutoDriveSS)
+    {
+        /* set both SSOE and MODFEN bits when auto drive slave SS is enabled */
+        SPI_SSOutputEnable(pSPI);
+        SPI_ModfEnable(pSPI);
+    }    
+ 
+    if( pConfig->sSettings.bPinAsOuput)
+    {
+        SPI_BidirPinEnable(pSPI);
+    }
+
+    if( pConfig->sSettings.bBidirectionModeEn)
+    {
+        SPI_BidirOutEnable(pSPI);
+    }
+    if( pConfig->sSettings.bStopInWaitMode)
+    {
+        SPI_ClockStopEnable(pSPI);
+    }
+    
+    if(pConfig->sSettings.bMasterMode)
+    {
+        SPI_SetBaudRate(pSPI,pConfig->u32BusClkHz,pConfig->u32BitRate);
+    }
+
+	/* enable SPI module */
+    if( pConfig->sSettings.bModuleEn)
+    {
+        SPI_Enable(pSPI);
+    }
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief SPI set band rate.
+   *        
+   * @param[in]  pSPI   point to SPI module type.
+   * @param[in]  u32BusClock   Bus clock.
+   * @param[in]  u32Bps   set spi's baudrate.
+   *
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+void SPI_SetBaudRate(SPI_Type *pSPI,uint32_t u32BusClock,uint32_t u32Bps)
+{
+	uint32_t u32BitRateDivisor;
+	uint8_t u8Sppr;
+	uint8_t u8Spr;
+    uint8_t u8ReadFlag;
+	u32BitRateDivisor = u32BusClock/u32Bps; /* calculate bit rate divisor */
+       
+    u8ReadFlag = 0;
+    /* find best fit SPPR and SPR */
+    for (u8Spr = 0; u8Spr <= 8; u8Spr++)
+    {
+        for(u8Sppr = 0; u8Sppr <= 7; u8Sppr++)
+        {
+            if((u32BitRateDivisor>>(u8Spr+1))<=(u8Sppr+1))
+            {
+                u8ReadFlag = 1;
+                break;
+            }
+        }
+        if(u8ReadFlag)
+        {
+            break;
+        }
+    }
+    if(u8Sppr >=8)
+    {
+        u8Sppr = 7;
+    }
+    if(u8Spr >8)
+    {
+        u8Spr = 8;
+    }
+    /* set bit rate */
+    pSPI->BR = SPI_BR_SPPR(u8Sppr) | SPI_BR_SPR(u8Spr);
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief implement write data to SPI.
+   *        
+   * @param[in]   pSPI  pointer to SPI module type.
+   * @param[in]   pWrBuff -- write data buffer pointer. 
+   * @param[in]   uiLength -- read/write data length.
+   * @param[out]   pRdBuff -- read data buffer pointer. 
+   * 
+   * @return  if <0, means error, 0: success.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+ResultType SPI_TransferWait(SPI_Type *pSPI, SPI_WidthType* pRdBuff, SPI_WidthType *pWrBuff,uint32 uiLength)
+{
+    ResultType err = SPI_ERR_SUCCESS;
+    uint32_t  i;
+    
+    if(!uiLength)
+    {
+        return (err);
+    }
+    for(i = 0; i < uiLength; i++)
+    {
+        while(!SPI_IsSPTEF(pSPI));
+        SPI_WriteDataReg(pSPI,pWrBuff[i]);
+        while(!SPI_IsSPRF(pSPI));
+        pRdBuff[i] = SPI_ReadDataReg(pSPI);
+    }
+    return (err);        
+}
+
+
+
+/*****************************************************************************//*!
+   *
+   * @brief Deinitialize SPI to the default state (reset value).
+   *        
+   * @param[in]   pSPI  pointer to SPI module type.
+   *         
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+void SPI_DeInit(SPI_Type *pSPI)
+{  
+    int16 i;
+    pSPI->C1 = SPI_C1_DEFAULT;
+    pSPI->C2 = SPI_C2_DEFAULT;
+    pSPI->BR = SPI_BR_DEFAULT;
+    pSPI->M  = SPI_M_DEFAULT;
+    for(i = 0; i<100; i++);                 /* wait for some cycles for the ISR exit */
+}
+
+/*****************************************************************************//*!
+   *
+   * @brief  set up SPI callback routines to be called by interrupt service routine.
+   *        
+   * @param[in]   pSPI  pointer to SPI module type.
+   * @param[in]  pfnCallback  callback routine. 
+   *  
+   * @return none.
+   *
+   * @ Pass/ Fail criteria: none.
+*****************************************************************************/
+void SPI_SetCallback(SPI_Type *pSPI,SPI_CallbackType pfnCallback)
+{
+    uint32_t    u32Port = ((uint32_t)pSPI-(uint32_t)SPI0)>>12;
+    ASSERT(u32Port <2);
+    SPI_Callback[u32Port] = pfnCallback;
+}
+
+/*! @} End of spi_api_list                                               						*/
+
+
+/*****************************************************************************//*!
+   *
+   * @brief SPI0 interrupt service routine.
+   *        
+   * @param   none.
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none.
+   *****************************************************************************/
+
+void SPI0_Isr(void)
+{
+    if( SPI_Callback[0] )
+    {
+		SPI_Callback[0]();
+    }
+}
+#ifndef CPU_NV32M3
+/*****************************************************************************//*!
+   *
+   * @brief SPI1 interrupt service routine.
+   *        
+   * @param   none.
+   * @return  none.
+   *
+   * @ Pass/ Fail criteria: none
+   *****************************************************************************/
+
+void SPI1_Isr(void)
+{
+    if( SPI_Callback[1] )
+    {
+		SPI_Callback[1]();
+    }
+}
+#endif
+
+

bsp/nv32f100x/lib/src/startup_NV32.s

@@ -0,0 +1,347 @@
+;/*****************************************************************************
+; * @file:    startup_NV32.s
+; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
+; *           NV32F100
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000200
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+                
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp  ; Top of Stack
+                DCD     Reset_Handler  ; Reset Handler
+                DCD     NMI_Handler  ; NMI Handler
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     SVC_Handler  ; SVCall Handler
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     PendSV_Handler  ; PendSV Handler
+                DCD     SysTick_Handler  ; SysTick Handler
+
+                ; External Interrupts
+                DCD     Reserved16_IRQHandler  ; Reserved interrupt 16
+                DCD     Reserved17_IRQHandler  ; Reserved interrupt 17
+                DCD     Reserved18_IRQHandler  ; Reserved interrupt 18
+                DCD     Reserved19_IRQHandler  ; Reserved interrupt 19
+                DCD     Reserved20_IRQHandler  ; Reserved interrupt 20
+                DCD     ETMRH_IRQHandler  ; ETMRH command complete/read collision interrupt
+                DCD     LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
+                DCD     IRQ_IRQHandler  ; External interrupt
+                DCD     I2C0_IRQHandler  ; I2C0 interrupt
+                DCD     Reserved25_IRQHandler  ; Reserved interrupt 25
+                DCD     SPI0_IRQHandler  ; SPI0 interrupt
+                DCD     SPI1_IRQHandler  ; SPI1 interrupt
+                DCD     UART0_IRQHandler  ; UART0 status/error interrupt
+                DCD     UART1_IRQHandler  ; UART1 status/error interrupt
+                DCD     UART2_IRQHandler  ; UART2 status/error interrupt
+                DCD     ADC0_IRQHandler  ; ADC0 interrupt
+                DCD     ACMP0_IRQHandler  ; ACMP0 interrupt
+                DCD     ETM0_IRQHandler  ; ETM0 Single interrupt vector for all sources
+                DCD     ETM1_IRQHandler  ; ETM1 Single interrupt vector for all sources
+                DCD     ETM2_IRQHandler  ; ETM2 Single interrupt vector for all sources
+                DCD     RTC_IRQHandler  ; RTC overflow
+                DCD     ACMP1_IRQHandler  ; ACMP1 interrupt
+                DCD     PIT_CH0_IRQHandler  ; PIT CH0 overflow
+                DCD     PIT_CH1_IRQHandler  ; PIT CH1 overflow
+                DCD     KBI0_IRQHandler  ; Keyboard interrupt 0
+                DCD     KBI1_IRQHandler  ; Keyboard interrupt 1
+                DCD     Reserved42_IRQHandler  ; Reserved interrupt 42
+                DCD     ICS_IRQHandler  ; MCG interrupt
+                DCD     Watchdog_IRQHandler  ; WDOG Interrupt
+                DCD     Reserved45_IRQHandler  ; Reserved interrupt 45
+                DCD     Reserved46_IRQHandler  ; Reserved interrupt 46
+                DCD     Reserved47_IRQHandler  ; Reserved interrupt 47
+__Vectors_End
+
+__Vectors_Size 	EQU     __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+;   <i> and security information that allows the MCU to restrict acces to the FTFL module.
+;   <h> Backdoor Comparison Key
+;     <o0>  Backdoor Key 0  <0x0-0xFF:2>
+;     <o1>  Backdoor Key 1  <0x0-0xFF:2>
+;     <o2>  Backdoor Key 2  <0x0-0xFF:2>
+;     <o3>  Backdoor Key 3  <0x0-0xFF:2>
+;     <o4>  Backdoor Key 4  <0x0-0xFF:2>
+;     <o5>  Backdoor Key 5  <0x0-0xFF:2>
+;     <o6>  Backdoor Key 6  <0x0-0xFF:2>
+;     <o7>  Backdoor Key 7  <0x0-0xFF:2>
+BackDoorK0      EQU     0xFF
+BackDoorK1      EQU     0xFF
+BackDoorK2      EQU     0xFF
+BackDoorK3      EQU     0xFF
+BackDoorK4      EQU     0xFF
+BackDoorK5      EQU     0xFF
+BackDoorK6      EQU     0xFF
+BackDoorK7      EQU     0xFF
+;   </h>
+;   <h> EEPROM Protection Register (EEPROT)
+;     <i> The DFPROT register defines which D-Flash sectors are protected against program and erase operations.
+;     <o.7>  DPOPEN
+;       <0=> Enables EEPROM memory protection
+;       <1=> Disables EEPROM memory protection
+;     <o.0..2> DPS
+;       <0=> Flash address range: 0x00_0000 - 0x00_001F; protected size: 32 bytes
+;       <1=> Flash address range: 0x00_0000 - 0x00_003F; protected size: 64 bytes
+;       <2=> Flash address range: 0x00_0000 - 0x00_005F; protected size: 96 bytes
+;       <3=> Flash address range: 0x00_0000 - 0x00_007F; protected size: 128 bytes
+;       <4=> Flash address range: 0x00_0000 - 0x00_009F; protected size: 160 bytes
+;       <5=> Flash address range: 0x00_0000 - 0x00_00BF; protected size: 192 bytes
+;       <6=> Flash address range: 0x00_0000 - 0x00_00DF; protected size: 224 bytes
+;       <7=> Flash address range: 0x00_0000 - 0x00_00FF; protected size: 256 bytes
+EEPROT          EQU     0xFF
+;     </h>
+;     <h> FPROT
+;       <i> P-Flash Protection Register
+;       <o.7> FPOPEN
+;         <0=> FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits FPROT1.1
+;         <1=> FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits
+;       <o.5> FPHDIS
+;         <0=> Protection/Unprotection enabled
+;         <1=> Protection/Unprotection disabled
+;       <o.3..4> FPHS
+;         <0=> Address range: 0x00_7C00-0x00_7FFF; protected size: 1 KB
+;         <1=> Address range: 0x00_7800-0x00_7FFF; protected size: 2 KB
+;         <2=> Address range: 0x00_7000-0x00_7FFF; protected size: 4 KB
+;         <3=> Address range: 0x00_6000-0x00_7FFF; protected size: 8 KB
+;       <o.5> FPLDIS
+;         <0=> Protection/Unprotection enabled
+;         <1=> Protection/Unprotection disabled
+;       <o.3..4> FPLS
+;         <0=> Address range: 0x00_0000-0x00_07FF; protected size: 2 KB
+;         <1=> Address range: 0x00_0000-0x00_0FFF; protected size: 4 KB
+;         <2=> Address range: 0x00_0000-0x00_1FFF; protected size: 8 KB
+;         <3=> Address range: 0x00_0000-0x00_3FFF; protected size: 16 KB
+FPROT         EQU     0xFF
+;     </h>
+;   </h>
+;   <h> Flash security byte (FSEC)
+;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+;     <o.0..1> SEC
+;       <2=> MCU security status is unsecure
+;       <3=> MCU security status is secure
+;         <i> Flash Security
+;         <i> This bits define the security state of the MCU.
+;     <o.6..7> KEYEN
+;       <2=> Backdoor key access enabled
+;       <3=> Backdoor key access disabled
+;         <i> Backdoor key Security Enable
+;         <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC            EQU     0xFE
+;   </h>
+;   <h> Flash Option Register (FOPT)
+FOPT            EQU     0xFE
+;   </h>
+                IF      :LNOT::DEF:RAM_TARGET
+                AREA    |.ARM.__at_0x400|, CODE, READONLY
+                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+                DCB     0xFF,       0xFF,       0xFF,       0xFF
+                DCB     EEPROT,      FPROT,     FSEC,       FOPT              ;Modified by ARM.  DCB     FPROT,      EEPROT,     FOPT,       FSEC
+                ENDIF
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  Reserved16_IRQHandler     [WEAK]
+                EXPORT  Reserved17_IRQHandler     [WEAK]
+                EXPORT  Reserved18_IRQHandler     [WEAK]
+                EXPORT  Reserved19_IRQHandler     [WEAK]
+                EXPORT  Reserved20_IRQHandler     [WEAK]
+                EXPORT  ETMRH_IRQHandler     [WEAK]
+                EXPORT  LVD_LVW_IRQHandler     [WEAK]
+                EXPORT  IRQ_IRQHandler     [WEAK]
+                EXPORT  I2C0_IRQHandler     [WEAK]
+                EXPORT  Reserved25_IRQHandler     [WEAK]
+                EXPORT  SPI0_IRQHandler     [WEAK]
+                EXPORT  SPI1_IRQHandler     [WEAK]
+                EXPORT  UART0_IRQHandler     [WEAK]
+                EXPORT  UART1_IRQHandler     [WEAK]
+                EXPORT  UART2_IRQHandler     [WEAK]
+                EXPORT  ADC0_IRQHandler     [WEAK]
+                EXPORT  ACMP0_IRQHandler     [WEAK]
+                EXPORT  ETM0_IRQHandler     [WEAK]
+                EXPORT  ETM1_IRQHandler     [WEAK]
+                EXPORT  ETM2_IRQHandler     [WEAK]
+                EXPORT  RTC_IRQHandler     [WEAK]
+                EXPORT  ACMP1_IRQHandler     [WEAK]
+                EXPORT  PIT_CH0_IRQHandler     [WEAK]
+                EXPORT  PIT_CH1_IRQHandler     [WEAK]
+                EXPORT  KBI0_IRQHandler     [WEAK]
+                EXPORT  KBI1_IRQHandler     [WEAK]
+                EXPORT  Reserved42_IRQHandler     [WEAK]
+                EXPORT  ICS_IRQHandler     [WEAK]
+                EXPORT  Watchdog_IRQHandler     [WEAK]
+                EXPORT  Reserved45_IRQHandler     [WEAK]
+                EXPORT  Reserved46_IRQHandler     [WEAK]
+                EXPORT  Reserved47_IRQHandler     [WEAK]
+                EXPORT  DefaultISR                      [WEAK]
+
+Reserved16_IRQHandler
+Reserved17_IRQHandler
+Reserved18_IRQHandler
+Reserved19_IRQHandler
+Reserved20_IRQHandler
+ETMRH_IRQHandler
+LVD_LVW_IRQHandler
+IRQ_IRQHandler
+I2C0_IRQHandler
+Reserved25_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+ADC0_IRQHandler
+ACMP0_IRQHandler
+ETM0_IRQHandler
+ETM1_IRQHandler
+ETM2_IRQHandler
+RTC_IRQHandler
+ACMP1_IRQHandler
+PIT_CH0_IRQHandler
+PIT_CH1_IRQHandler
+KBI0_IRQHandler
+KBI1_IRQHandler
+Reserved42_IRQHandler
+ICS_IRQHandler
+Watchdog_IRQHandler
+Reserved45_IRQHandler
+Reserved46_IRQHandler
+Reserved47_IRQHandler
+DefaultISR
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END

bsp/nv32f100x/lib/src/uart.c

@@ -0,0 +1,459 @@
+/******************************************************************************
+* @brief providing common UART API. 
+*
+******************************************************************************/
+#include "uart.h"
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+UART_CallbackType UART_Callback = NULL;
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+*****************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define UART APIs
+*
+*//*! @addtogroup uart_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief initialize the UART, interrupts disabled, and no hardware flow-control.
+*        
+* @param[in] pUART       base of UART port
+* @param[in] pConfig     pointer to UART configuration structure
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void UART_Init(UART_Type *pUART, UART_ConfigType *pConfig)
+{
+    uint16_t u16Sbr;
+    uint8_t u8Temp;
+    uint32_t u32SysClk = pConfig->u32SysClkHz;
+    uint32_t u32Baud = pConfig->u32Baudrate;
+
+    /* Sanity check */
+    ASSERT((pUART == UART0) || (pUART == UART1) || (pUART == UART2));
+  
+	/* Enable the clock to the selected UART */    
+    if (pUART == UART0)
+	{
+		SIM->SCGC |= SIM_SCGC_UART0_MASK;
+	}
+#if defined(CPU_NV32)  | defined(CPU_NV326)
+	else if (pUART == UART1)
+	{
+        SIM->SCGC |= SIM_SCGC_UART1_MASK;
+	}
+    else
+	{
+        SIM->SCGC |= SIM_SCGC_UART2_MASK;
+	}
+#endif    
+    /* Make sure that the transmitter and receiver are disabled while we 
+     * change settings.
+     */
+    pUART->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK );
+    
+    /* Configure the UART for 8-bit mode, no parity */
+    pUART->C1 = 0;
+    
+    /* Calculate baud settings */
+    u16Sbr = (((u32SysClk)>>4) + (u32Baud>>1))/u32Baud;
+    
+    /* Save off the current value of the UARTx_BDH except for the SBR field */
+    u8Temp = pUART->BDH & ~(UART_BDH_SBR_MASK);
+    
+    pUART->BDH = u8Temp |  UART_BDH_SBR(u16Sbr >> 8);
+    pUART->BDL = (uint8_t)(u16Sbr & UART_BDL_SBR_MASK);
+
+    /* Enable receiver and transmitter */
+    pUART->C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK );
+}
+
+/*****************************************************************************//*!
+*
+* @brief receive a character.
+*        
+* @param[in] pUART       base of UART port
+*
+* @return unsigned char
+*
+*****************************************************************************/
+uint8_t UART_GetChar(UART_Type *pUART)
+{
+
+    /* Sanity check */
+    ASSERT((pUART == UART0) || (pUART == UART1) || (pUART == UART2));
+ 
+    /* Wait until character has been received */
+    while (!(pUART->S1 & UART_S1_RDRF_MASK));
+    
+    /* Return the 8-bit data from the receiver */
+    return pUART->D;
+}
+/*****************************************************************************//*!
+*
+* @brief send a character.
+*        
+* @param[in] pUART       base of UART port
+* @param[in] u8Char      char to send
+*
+* @return none
+*
+*****************************************************************************/
+void UART_PutChar(UART_Type *pUART, uint8_t u8Char)
+{    
+    /* Wait until space is available in the FIFO */
+    while (!(pUART->S1 & UART_S1_TDRE_MASK));
+    
+    /* Send the character */
+    pUART->D = (uint8_t)u8Char;
+}
+
+/*****************************************************************************//*!
+*
+* @brief set baudrate.
+*        
+* @param[in] pUART       base of UART port
+* @param[in] pConfig     baudrate config parameters
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART_SetBaudrate(UART_Type *pUART, UART_ConfigBaudrateType *pConfig)
+{
+    uint8_t u8Temp;
+    uint16_t u16Sbr;
+    uint32_t u32SysClk    = pConfig->u32SysClkHz;
+    uint32_t u32baud       = pConfig->u32Baudrate;
+ 
+    /* Sanity check */
+    ASSERT((pUART == UART0) || (pUART == UART1) || (pUART == UART2));
+
+    /* Calculate baud settings */
+    u16Sbr = (((u32SysClk)>>4) + (u32baud>>1))/u32baud;
+
+    /* Save off the current value of the UARTx_BDH except for the SBR field */
+    u8Temp = pUART->BDH & ~(UART_BDH_SBR_MASK);
+    
+    pUART->BDH = u8Temp |  UART_BDH_SBR(u16Sbr >> 8);
+    pUART->BDL = (uint8_t)(u16Sbr & UART_BDL_SBR_MASK);
+
+    /* Enable receiver and transmitter */
+    pUART->C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK );
+
+}
+
+/*****************************************************************************//*!
+*
+* @brief enable interrupt.
+*        
+* @param[in] pUART          base of UART port
+* @param[in] InterruptType  interrupt type
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART_EnableInterrupt(UART_Type *pUART, UART_InterruptType InterruptType)
+{
+
+    /* Sanity check */
+    ASSERT((pUART == UART0) || (pUART == UART1) || (pUART == UART2));
+
+    if (InterruptType == UART_TxBuffEmptyInt)
+    {
+        pUART->C2 |= UART_C2_TIE_MASK;
+    }
+    else if (InterruptType == UART_TxCompleteInt)
+    {
+        pUART->C2 |= UART_C2_TCIE_MASK;
+    }
+    else if (InterruptType == UART_RxBuffFullInt)
+    {
+        pUART->C2 |= UART_C2_RIE_MASK;
+    }
+    else if (InterruptType == UART_IdleLineInt)
+    {
+        pUART->C2 |= UART_C2_ILIE_MASK;
+    }
+    else if (InterruptType == UART_RxOverrunInt)
+    {
+        pUART->C3 |= UART_C3_ORIE_MASK;
+    }
+    else if (InterruptType == UART_NoiseErrorInt)
+    {
+        pUART->C3 |= UART_C3_NEIE_MASK;
+    }
+    else if (InterruptType == UART_FramingErrorInt)
+    {
+        pUART->C3 |= UART_C3_FEIE_MASK;
+    } 
+    else if (InterruptType == UART_ParityErrorInt)
+    {
+        pUART->C3 |= UART_C3_FEIE_MASK;
+    } 
+    else
+    {
+        /* un-supported Interrupt type */
+    }  
+}
+
+/*****************************************************************************//*!
+*
+* @brief disable interrupt.
+*        
+* @param[in] pUART base of UART port
+* @param[in] InterruptType interrupt type
+*
+* @return none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART_DisableInterrupt(UART_Type *pUART, UART_InterruptType InterruptType)
+{
+    /* Sanity check */
+    ASSERT((pUART == UART0) || (pUART == UART1) || (pUART == UART2));
+
+
+    if (InterruptType == UART_TxBuffEmptyInt)
+    {
+        pUART->C2 &= (~UART_C2_TIE_MASK);
+    }
+    else if (InterruptType == UART_TxCompleteInt)
+    {
+        pUART->C2 &= (~UART_C2_TCIE_MASK);
+    }
+    else if (InterruptType == UART_RxBuffFullInt)
+    {
+        pUART->C2 &= (~UART_C2_RIE_MASK);
+    }
+    else if (InterruptType == UART_IdleLineInt)
+    {
+        pUART->C2 &= (~UART_C2_ILIE_MASK);
+    }
+    else if (InterruptType == UART_RxOverrunInt)
+    {
+        pUART->C3 &= (~UART_C3_ORIE_MASK);
+    }
+    else if (InterruptType == UART_NoiseErrorInt)
+    {
+        pUART->C3 &= (~UART_C3_NEIE_MASK);
+    }
+    else if (InterruptType == UART_FramingErrorInt)
+    {
+        pUART->C3 &= (~UART_C3_FEIE_MASK);
+    } 
+    else if (InterruptType == UART_ParityErrorInt)
+    {
+        pUART->C3 &= (~UART_C3_FEIE_MASK);
+    } 
+    else
+    {
+        /* un-supported interrupt type */
+    }  
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief get flags from 2 UART status registers.
+*        
+* @param[in] pUART  base of UART port
+*
+* @return       16-bit flags
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+uint16_t UART_GetFlags(UART_Type *pUART)
+{
+    uint16_t u16StatusFlags = 0;
+
+    u16StatusFlags = pUART->S2;
+    u16StatusFlags = (u16StatusFlags<<8)| pUART->S1; 
+
+    return u16StatusFlags;
+}
+/*****************************************************************************//*!
+*
+* @brief check whether the specified flag is set.
+*        
+* @param[in] pUART      base of UART port
+* @param[in] FlagType   flag type
+*
+* @return       
+*               1, flag is set
+*               0, flag is clear
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+uint8_t UART_CheckFlag(UART_Type *pUART, UART_FlagType FlagType)
+{
+    uint16_t u16StatusFlags = 0;
+
+    u16StatusFlags = UART_GetFlags(pUART);
+
+    return (u16StatusFlags & (1<<FlagType));
+}
+
+/*****************************************************************************//*!
+*
+* @brief send a series of charecters using polling mode.
+*        
+* @param[in] pUART      base of UART port
+* @param[in] pSendBuff  pointer of charecters to send
+* @param[in] u32Length  number of charecters
+*
+* @return       none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART_SendWait(UART_Type *pUART, uint8_t *pSendBuff, uint32_t u32Length)
+{
+    uint8_t u8TxChar;
+    uint32_t  i;
+    
+    for (i = 0; i < u32Length; i++)
+    {
+        u8TxChar = pSendBuff[i];
+        while (!UART_IsTxBuffEmpty(pUART))
+        {
+            #if defined(ENABLE_WDOG)
+                WDOG_Feed();
+            #endif        
+        }
+        UART_WriteDataReg(pUART, u8TxChar);        
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief receive a series of charecters using polling mode.
+*        
+* @param[in] pUART          base of UART port
+* @param[in] pReceiveBuff   pointer of charecters to receive
+* @param[in] u32Length      number of charecters
+*
+* @return       none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART_ReceiveWait(UART_Type *pUART, uint8_t *pReceiveBuff, uint32_t u32Length)
+{
+    uint8_t u8RxChar;
+    uint32_t i;
+    
+    for (i = 0; i < u32Length; i++)
+    {
+        while (!UART_IsRxBuffFull(pUART))
+        {
+            #if defined(ENABLE_WDOG)
+                WDOG_Feed();
+            #endif       
+        }    
+        u8RxChar = UART_ReadDataReg(pUART);
+        pReceiveBuff[i] = u8RxChar;
+    }
+}
+
+/*****************************************************************************//*!
+*
+* @brief wait tx complete.
+*        
+* @param[in] pUART      base of UART port
+*
+* @return       none
+*
+* @ Pass/ Fail criteria: none*****************************************************************************/
+void UART_WaitTxComplete(UART_Type *pUART)
+{
+    while (!UART_IsTxComplete(pUART));
+}
+
+/*****************************************************************************//*!
+*
+* @brief set up UART callback routines to be called by interrupt service routine.
+*        
+* @param[in]  pUART         pointer to an UART register base 
+* @param[in]  pfnCallback   callback routine
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+void UART_SetCallback(UART_CallbackType pfnCallback)
+{
+    //uint8_t    u8Port = ((uint32_t)pUART-(uint32_t)UART0)>>12;
+    UART_Callback = pfnCallback;
+}
+
+
+/*! @} End of uart_api_list */
+
+
+/*****************************************************************************//*!
+*
+* @brief uart0 interrupt service routine.
+*        
+* @param        none
+*
+* @return       none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART0_Isr(void)
+{
+    UART_Callback(UART0);
+}
+
+
+#if defined(CPU_NV32) | defined(CPU_NV326)
+/*****************************************************************************//*!
+*
+* @brief uart1 interrupt service routine.
+*        
+* @param        none
+*
+* @return       none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART1_Isr(void)
+{
+    UART_Callback(UART1);
+}
+/*****************************************************************************//*!
+*
+* @brief uart2 interrupt service routine.
+*        
+* @param        none
+*
+* @return       none
+*
+* @ Pass/ Fail criteria:
+*****************************************************************************/
+void UART2_Isr(void)
+{
+    UART_Callback(UART2);
+}
+
+
+#endif
+
+
+

bsp/nv32f100x/lib/src/wdog.c

@@ -0,0 +1,324 @@
+
+/******************************************************************************
+*
+* @brief Provide common watchdog module routines. 
+*
+* @history:
+* 	Jun. 25, 2013	modified the watch dog unlock sequence and disable sequence
+******************************************************************************/
+#include "common.h"
+#include "wdog.h"
+ 
+/******************************************************************************
+* Global variables
+******************************************************************************/
+
+/******************************************************************************
+* Constants and macros
+******************************************************************************/
+
+/******************************************************************************
+* Local types
+******************************************************************************/
+
+/******************************************************************************
+* Local function prototypes
+******************************************************************************/
+
+/******************************************************************************
+* Local variables
+******************************************************************************/
+
+/******************************************************************************
+* Local functions
+******************************************************************************/
+
+/******************************************************************************
+* Global functions
+******************************************************************************/
+
+/******************************************************************************
+* define watchdog API list
+*
+*//*! @addtogroup wdog_api_list
+* @{
+*******************************************************************************/
+
+/*****************************************************************************//*!
+*
+* @brief Watchdog ETMer disable routine.
+*        
+* @param  none 
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see WDOG_Enable
+*****************************************************************************/
+
+void WDOG_Disable(void)
+{
+    uint8_t u8Cs1 =  WDOG->CS1;  
+    uint8_t u8Cs2 =  WDOG->CS2;  
+    uint16_t u16TOVAL =  WDOG->TOVAL;  
+    uint16_t u16WIN =  WDOG->WIN;  
+
+    u8Cs1       &= ~WDOG_CS1_EN_MASK;
+
+	/* First unlock the watchdog so that we can write to registers */
+    WDOG_Unlock(); 
+    WDOG->CS2    =  u8Cs2;
+    WDOG->TOVAL  =  u16TOVAL;
+    WDOG->WIN    =  u16WIN;
+    WDOG->CS1    =  u8Cs1;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief Watchdog ETMer disable routine with update enabled.
+*        
+*   Disable watchdog but the watchdog can be enabled and updated later.
+*
+* @param  none 
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see WDOG_Enable
+*****************************************************************************/
+
+void WDOG_DisableWDOGEnableUpdate(void)
+{
+    uint8_t u8Cs1 =  WDOG->CS1;  
+    uint8_t u8Cs2 =  WDOG->CS2;  
+    uint16_t u16TOVAL =  WDOG->TOVAL;  
+    uint16_t u16WIN =  WDOG->WIN;  
+
+    u8Cs1       &= ~WDOG_CS1_EN_MASK;
+    u8Cs1       |= WDOG_CS1_UPDATE_MASK;
+
+	/* First unlock the watchdog so that we can write to registers */
+    //WDOG_Unlock(); 
+    WDOG->CS2    =  u8Cs2;
+    WDOG->TOVAL  =  u16TOVAL;
+    WDOG->WIN    =  u16WIN;
+    WDOG->CS1    =  u8Cs1;
+}
+
+/*****************************************************************************//*!
+*
+* @brief Watchdog ETMer enable routine.
+*        
+* @param  none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @see  WDOG_Disable
+*****************************************************************************/
+
+void WDOG_Enable(void)
+{
+    uint8_t u8Cs1 =  WDOG->CS1;
+    
+    u8Cs1       |= WDOG_CS1_EN_MASK;
+
+	/* First unlock the watchdog so that we can write to registers */
+    WDOG_Unlock();
+    WDOG->CS1    = u8Cs1;
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief initialize watchdog.
+*        
+* @param[in]   pConfig  poiner to watchdog configuration strcture.
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* 
+* @warning make sure that WDOG is not initialized after reset or WDOG update is enabled 
+* after reset by calling WDOG_EnableUpdate / WDOG_DisableWDOGEnableUpdate.
+*
+* @see WDOG_EnableUpdate, WDOG_DisableWDOGEnableUpdate
+*
+*****************************************************************************/
+
+void WDOG_Init(WDOG_ConfigPtr pConfig)
+{
+    uint8_t     u8Cs1;
+    uint8_t     u8Cs2;
+    uint16_t    u16Toval;
+    uint16_t    u16Win;
+    
+    u8Cs1       = 0x80;                                   /* default CS1 register value */
+    u8Cs2       = 0;
+    u16Toval    = pConfig->u16ETMeOut;
+    u16Win      = pConfig->u16WinETMe;
+        
+    if(pConfig->sBits.bDisable)
+    {
+        u8Cs1 &= ~WDOG_CS1_EN_MASK;
+    }
+    if(pConfig->sBits.bIntEnable)
+    {
+        u8Cs1 |= WDOG_CS1_INT_MASK;
+    }
+    if(pConfig->sBits.bStopEnable)
+    {
+        u8Cs1 |= WDOG_CS1_STOP_MASK;
+    }
+    if(pConfig->sBits.bDbgEnable)
+    {
+        u8Cs1 |= WDOG_CS1_DBG_MASK;
+    }
+    if(pConfig->sBits.bWaitEnable)
+    {
+        u8Cs1 |= WDOG_CS1_WAIT_MASK;
+    }
+    if(pConfig->sBits.bUpdateEnable)
+    {
+        u8Cs1 |= WDOG_CS1_UPDATE_MASK;
+    }
+    if(pConfig->sBits.bWinEnable)
+    {
+        u8Cs2 |= WDOG_CS2_WIN_MASK;
+    }
+    if(pConfig->sBits.bPrescaler)
+    {
+        u8Cs2 |= WDOG_CS2_PRES_MASK;
+    }
+    u8Cs2   |= (pConfig->sBits.bClkSrc & 0x03);
+    
+    /* write regisers */
+    WDOG_Unlock();              /* unlock watchdog first */
+    WDOG->CS2   = u8Cs2;
+
+    WDOG->TOVAL8B.TOVALL  = u16Toval;
+    WDOG->TOVAL8B.TOVALH  = u16Toval >> 8;
+    
+    WDOG->WIN8B.WINL  = u16Win;
+    WDOG->WIN8B.WINH  = u16Win >> 8;
+    
+    WDOG->CS1   = u8Cs1;                            
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief initialize watchdog to the default state.
+*        
+* @param   none 
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @warning make sure that WDOG update is enabled after reset by calling WDOG_EnableUpdate.
+* or by calling WDOG_DisableWDOGEnableUpdate.
+*
+* @see WDOG_DisableWDOGEnableUpdate, WDOG_EnableUpdate
+*
+*****************************************************************************/
+
+void WDOG_DeInit(void)
+{
+    WDOG_Unlock();
+    
+    WDOG->CS2    =  WDOG_CS2_DEFAULT_VALUE;
+    WDOG->TOVAL  =  WDOG_TOVAL_DEFAULT_VALUE;
+    WDOG->WIN    =  WDOG_WIN_DEFAULT_VALUE;    
+    WDOG->CS1    =  WDOG_CS1_DEFAULT_VALUE;
+}
+
+/*****************************************************************************//*!
+*
+* @brief feed/refresh watchdog.
+*        
+* @param   none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+*****************************************************************************/
+
+void WDOG_Feed(void)
+{
+    DisableInterrupts;
+    WDOG->CNT = 0x02A6;
+    WDOG->CNT = 0x80B4;
+    EnableInterrupts;
+}
+
+
+
+/*****************************************************************************//*!
+*
+* @brief enable update of WDOG. 
+*        
+* @param  none
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @warning  this must be the last step of writing control bits sequence.
+*****************************************************************************/
+
+void WDOG_EnableUpdate(void)
+{
+    uint8_t u8Cs1 =  WDOG->CS1;  
+    uint8_t u8Cs2 =  WDOG->CS2;  
+    uint16_t u16TOVAL =  WDOG->TOVAL;  
+    uint16_t u16WIN =  WDOG->WIN;  
+
+    u8Cs1 |= WDOG_CS1_UPDATE_MASK;
+
+	/* First unlock the watchdog so that we can write to registers */
+    WDOG_Unlock(); 
+    WDOG->CS2    =  u8Cs2;
+    WDOG->TOVAL  =  u16TOVAL;
+    WDOG->WIN    =  u16WIN;
+    WDOG->CS1    =  u8Cs1;  
+}
+
+
+/*****************************************************************************//*!
+*
+* @brief disable update of WDOG. 
+*        
+* @param  none 
+*
+* @return none
+*
+* @ Pass/ Fail criteria: none
+* @warning  this must be the last step of writing control bits sequence.
+*****************************************************************************/
+
+void WDOG_DisableUpdate(void)
+{
+    uint8_t u8Cs1 =  WDOG->CS1;  
+    uint8_t u8Cs2 =  WDOG->CS2;  
+    uint16_t u16TOVAL =  WDOG->TOVAL;  
+    uint16_t u16WIN =  WDOG->WIN;  
+
+    u8Cs1 &= ~WDOG_CS1_UPDATE_MASK;
+
+	/* First unlock the watchdog so that we can write to registers */
+    WDOG_Unlock(); 
+    WDOG->CS2    =  u8Cs2;
+    WDOG->TOVAL  =  u16TOVAL;
+    WDOG->WIN    =  u16WIN;
+    WDOG->CS1    =  u8Cs1;  
+    
+}
+
+
+/********************************************************************/
+
+/*! @} End of wdog_api_list                                                    					*/
+
+
+
+

bsp/nv32f100x/project.uvprojx

@@ -0,0 +1,716 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>nv32f100x</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060183::V5.06 update 2 (build 183)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>NV32F100FS16E</Device>
+          <Vendor>Navota MCU</Vendor>
+          <PackID>Keil.NV32F100_DFP.1.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x1FFFF800,0x2000) IROM(0x00000000,0x20000) IROM2(0x00400000,0x1400) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD1FFFF800 -FC2000 -FN2 -FF0nv32f100_128 -FS00 -FL020000 -FF1nv32f100_nvr -FS1400000 -FL11400 -FP0($$Device:NV32F100FS16E$Flash\nv32f100_128.FLM) -FP1($$Device:NV32F100FS16E$Flash\nv32f100_nvr.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:NV32F100FS16E$Device\Include\nv32f100.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:NV32F100FS16E$SVD\nv32f100S16.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\output\</OutputDirectory>
+          <OutputName>nv32f100x</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>C:\Users\HF00\Documents\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>1</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>0</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4103</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x1ffff800</StartAddress>
+                <Size>0x2000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x20000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x400000</StartAddress>
+                <Size>0x1400</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1ffff800</StartAddress>
+                <Size>0x2000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>1</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>NV32, KEIL</Define>
+              <Undefine></Undefine>
+              <IncludePath>app\inc;.;board\inc;lib\inc;..\..\include;..\..\libcpu\arm\cortex-m0;..\..\libcpu\arm\common;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>0</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc> --keep *.o(.rti_fn.*)   --keep *.o(FSymTab)</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Applications</GroupName>
+          <Files>
+            <File>
+              <FileName>application.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>app\src\application.c</FilePath>
+            </File>
+            <File>
+              <FileName>ledapp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>app\src\ledapp.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>app\src\startup.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\src\board.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\src\drv_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\src\drv_uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>start.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\src\start.c</FilePath>
+            </File>
+            <File>
+              <FileName>sysinit.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\src\sysinit.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Lib</GroupName>
+          <Files>
+            <File>
+              <FileName>acmp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\acmp.c</FilePath>
+            </File>
+            <File>
+              <FileName>adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>arm_cm0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\arm_cm0.c</FilePath>
+            </File>
+            <File>
+              <FileName>crc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\crc.c</FilePath>
+            </File>
+            <File>
+              <FileName>eeprom.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\eeprom.c</FilePath>
+            </File>
+            <File>
+              <FileName>etm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\etm.c</FilePath>
+            </File>
+            <File>
+              <FileName>flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>ics.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\ics.c</FilePath>
+            </File>
+            <File>
+              <FileName>kbi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\kbi.c</FilePath>
+            </File>
+            <File>
+              <FileName>pit.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\pit.c</FilePath>
+            </File>
+            <File>
+              <FileName>pmc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\pmc.c</FilePath>
+            </File>
+            <File>
+              <FileName>rtc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\rtc.c</FilePath>
+            </File>
+            <File>
+              <FileName>sim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\sim.c</FilePath>
+            </File>
+            <File>
+              <FileName>spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>wdog.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>lib\src\wdog.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_NV32.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>lib\src\startup_NV32.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>components.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\components.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CORTEX-M0</GroupName>
+          <Files>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m0\cpuport.c</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m0\context_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>DeviceDrivers</GroupName>
+          <Files>
+            <File>
+              <FileName>pin.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\misc\pin.c</FilePath>
+            </File>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\serial\serial.c</FilePath>
+            </File>
+            <File>
+              <FileName>spi_core.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\spi\spi_core.c</FilePath>
+            </File>
+            <File>
+              <FileName>spi_dev.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\spi\spi_dev.c</FilePath>
+            </File>
+            <File>
+              <FileName>completion.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\completion.c</FilePath>
+            </File>
+            <File>
+              <FileName>dataqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>pipe.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\pipe.c</FilePath>
+            </File>
+            <File>
+              <FileName>portal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\portal.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringbuffer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
+            </File>
+            <File>
+              <FileName>workqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\workqueue.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>symbol.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\symbol.c</FilePath>
+            </File>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\msh.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh_cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\msh_cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh_file.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\msh_file.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>

bsp/nv32f100x/rtconfig.h

@@ -0,0 +1,99 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX	   8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE	4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	32
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND	1000
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+//#define RT_DEBUG
+//#define RT_DEBUG_INIT 1
+//#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+/* #define RT_USING_HOOK */
+
+/* Using Software Timer */
+/* #define RT_USING_TIMER_SOFT */
+#define RT_TIMER_THREAD_PRIO		4
+#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_TICK_PER_SECOND	10
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+/* #define RT_USING_MAILBOX */
+
+/* Using Message Queue */
+/* #define RT_USING_MESSAGEQUEUE */
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+/* #define RT_USING_MEMPOOL */
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+#define RT_USING_TINY_SIZE
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+#define RT_USING_COMPONENTS_INIT
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+// <bool name="RT_USING_DEVICE_IPC" description="Using device communication" default="true" />
+#define RT_USING_DEVICE_IPC
+// <bool name="RT_USING_SERIAL" description="Using Serial" default="true" />
+#define RT_USING_SERIAL
+#define RT_USING_HOOK
+#define RT_USING_CPU_USAGE
+/* SECTION: Console options */
+#define RT_USING_CONSOLE
+#define RT_USING_RTTTERMINAL
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE	128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
+#define RT_CONSOLE_DEVICE_NAME	    "uart0"
+
+
+/* SECTION: finsh, a C-Express shell */
+#define RT_USING_FINSH
+#define RT_FINSHPROMRT_SIZE 16
+/* configure finsh parameters */
+#define FINSH_THREAD_PRIORITY 25
+#define FINSH_THREAD_STACK_SIZE	512
+#define FINSH_HISTORY_LINES	1
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+//#define FINSH_USING_DESCRIPTION
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_ONLY
+
+#define RT_USING_PIN
+#define RT_USING_SPI
+#define RT_DBG_APP
+
+#define RT_USING_UART0
+
+#endif

bsp/nv32f100x/rtconfig.py

@@ -0,0 +1,128 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m0'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM 	= 'gcc'
+    EXEC_PATH 	= 'G:/iot/camera_studio-win32-20160903/camera_studio/tools/arm-2014.05/bin'
+elif CROSS_TOOL == 'keil':
+    print '================ERROR============================'
+    print 'Not support iar yet!'
+    print '================================================='
+    exit(0)
+elif CROSS_TOOL == 'iar':
+    print '================ERROR============================'
+    print 'Not support iar yet!'
+    print '================================================='
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+#BUILD = 'debug'
+BUILD = 'release'
+STM32_TYPE = 'STM32L0XX'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'axf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE  + ' -DSTM32L072xx' + ' -DNULL=0'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-stm32.map,-cref,-u,Reset_Handler -T stm32_rom.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-stm32.map --scatter stm32_rom.sct'
+
+    CFLAGS += ' -I./'
+
+    EXEC_PATH += '/ARM/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D STM32F10X_HD'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --debug'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-M0'
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=None'
+    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' -Ol'
+    CFLAGS += ' --use_c++_inline'
+
+    AFLAGS = ''
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-M0'
+    AFLAGS += ' --fpu None'
+
+    LFLAGS = ' --config stm32l0xx_flash.icf'
+    LFLAGS += ' --redirect _Printf=_PrintfTiny'
+    LFLAGS += ' --redirect _Scanf=_ScanfSmall'
+    LFLAGS += ' --entry __iar_program_start'
+
+    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    POST_ACTION = ''

bsp/nv32f100x/template.uvprojx

@@ -0,0 +1,379 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>nv32f100x</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060183::V5.06 update 2 (build 183)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>NV32F100FS16E</Device>
+          <Vendor>Navota MCU</Vendor>
+          <PackID>Keil.NV32F100_DFP.1.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x1FFFF800,0x2000) IROM(0x00000000,0x20000) IROM2(0x00400000,0x1400) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD1FFFF800 -FC2000 -FN2 -FF0nv32f100_128 -FS00 -FL020000 -FF1nv32f100_nvr -FS1400000 -FL11400 -FP0($$Device:NV32F100FS16E$Flash\nv32f100_128.FLM) -FP1($$Device:NV32F100FS16E$Flash\nv32f100_nvr.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:NV32F100FS16E$Device\Include\nv32f100.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:NV32F100FS16E$SVD\nv32f100S16.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\output\</OutputDirectory>
+          <OutputName>nv32f100x</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>C:\Users\HF00\Documents\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>1</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>0</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4103</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x1ffff800</StartAddress>
+                <Size>0x2000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x20000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x400000</StartAddress>
+                <Size>0x1400</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1ffff800</StartAddress>
+                <Size>0x2000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>1</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>0</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--keep *.o(.rti_fn.*)   --keep *.o(FSymTab)</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>