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@@ -66,7 +66,6 @@
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#define ADC_OVERRUN_IRQ_EN 1
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#define ADC_FIFO_FLUSH 0
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-
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/*DAC_MIXER_CTRL: 0x20*/
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#define DAC_AG_R_EN 31 /* dac right enable bit */
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#define DAC_AG_L_EN 30 /* dac left enable bit */
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@@ -161,8 +160,6 @@
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#define ADDA_PR_WDAT 8
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#define ADDA_PR_RDAT 0
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-
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-
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/* 时钟配置相关寄存器 */
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#define R6_REG_CCU_BASE 0x01c20000
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#define R6_REG_PLL_AUDIO_CTRL (R6_REG_CCU_BASE + 0x008)
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@@ -186,7 +183,6 @@
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#define R6_REG_PD_PUL0 (R6_REG_PIO_BASE + (3 * 0x24 + 0X1c))
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#define R6_REG_PD_PUL1 (R6_REG_PIO_BASE + (3 * 0x24 + 0X20))
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-
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/* AUDIO配置相关寄存器 */
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#define R6_REG_AC_BASE 0x01c23c00
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#define R6_REG_AC_DAC_DPC (R6_REG_AC_BASE + 0x00)
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@@ -212,7 +208,6 @@
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#define REG_NDMA_BYTE_CNT (0xc)
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// #define REG_NDMA_PAR (0x300 + 0x1c)
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-
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#define NDMA_CFG_SRC_DRQ_IR_RX (0x00 << 0)
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#define NDMA_CFG_SRC_DRQ_NONE (0x01 << 0)
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#define NDMA_CFG_SRC_DRQ_SDRAM (0x11 << 0)
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jicheng0622