!404 修复riscv64浮点寄存器切换和lwp进入用户态的bug

Merge pull request !404 from 胡自成/smart-d1

components/lwp/arch/risc-v/rv64/lwp_arch.c

@@ -31,15 +31,15 @@
 #include <cpuport.h>
 #include <encoding.h>
 
-extern size_t MMUTable[];
+extern rt_ubase_t MMUTable[];
 
 int arch_expand_user_stack(void *addr)
 {
     int ret = 0;
-    size_t stack_addr = (size_t)addr;
+    rt_ubase_t stack_addr = (rt_ubase_t)addr;
 
     stack_addr &= ~PAGE_OFFSET_MASK;
-    if ((stack_addr >= (size_t)USER_STACK_VSTART) && (stack_addr < (size_t)USER_STACK_VEND))
+    if ((stack_addr >= (rt_ubase_t)USER_STACK_VSTART) && (stack_addr < (rt_ubase_t)USER_STACK_VEND))
     {
         void *map = lwp_map_user(lwp_self(), (void *)stack_addr, PAGE_SIZE, RT_FALSE);
 
@@ -59,9 +59,9 @@ void *lwp_copy_return_code_to_user_stack()
 
     if (tid->user_stack != RT_NULL)
     {
-        size_t size = (size_t)lwp_thread_return_end - (size_t)lwp_thread_return;
-        size_t userstack = (size_t)tid->user_stack + tid->user_stack_size - size;
-        memcpy((void *)userstack, lwp_thread_return, size);
+        rt_size_t size = (rt_size_t)lwp_thread_return_end - (rt_size_t)lwp_thread_return;
+        rt_size_t userstack = (rt_size_t)tid->user_stack + tid->user_stack_size - size;
+        rt_memcpy((void *)userstack, lwp_thread_return, size);
         return (void *)userstack;
     }
 
@@ -85,7 +85,7 @@ rt_ubase_t lwp_fix_sp(rt_ubase_t cursp)
         return 0;
     }
 
-    return cursp - ((size_t)lwp_thread_return_end - (size_t)lwp_thread_return);
+    return cursp - ((rt_size_t)lwp_thread_return_end - (rt_size_t)lwp_thread_return);
 }
 
 rt_thread_t rt_thread_sp_to_thread(void *spmember_addr)
@@ -110,9 +110,9 @@ void *lwp_get_user_sp(void)
 
 int arch_user_space_init(struct rt_lwp *lwp)
 {
-    size_t *mmu_table;
+    rt_ubase_t *mmu_table;
 
-    mmu_table = (size_t *)rt_pages_alloc(0);
+    mmu_table = (rt_ubase_t *)rt_pages_alloc(0);
     if (!mmu_table)
     {
         return -1;
@@ -120,7 +120,7 @@ int arch_user_space_init(struct rt_lwp *lwp)
 
     lwp->end_heap = USER_HEAP_VADDR;
 
-    memcpy(mmu_table, MMUTable, PAGE_SIZE);
+    rt_memcpy(mmu_table, MMUTable, PAGE_SIZE);
     rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_table, 4 * PAGE_SIZE);
     rt_hw_mmu_map_init(&lwp->mmu_info, (void *)USER_VADDR_START, USER_VADDR_TOP - USER_VADDR_START, (rt_size_t *)mmu_table, 0);
 

components/lwp/arch/risc-v/rv64/lwp_gcc.S

@@ -25,8 +25,13 @@
 .global lwp_user_entry
 .type lwp_user_entry, % function
 lwp_user_entry:
-    csrci sstatus, 8//set sstatus.spp = 0
+    li t0, SSTATUS_SPP | SSTATUS_SIE    // set as user mode, close interrupt
+    csrc sstatus, t0 
+    li t0, SSTATUS_SPIE // enable interrupt when return to user mode
+    csrs sstatus, t0
+
     csrw sepc, a1
+    mv a3, a2
     sret//enter user mode
 
 /*
@@ -35,7 +40,11 @@ lwp_user_entry:
 .global lwp_user_thread_entry
 .type lwp_user_thread_entry, % function
 lwp_user_thread_entry:
-    csrci sstatus, 8//set sstatus.spp = 0
+    li t0, SSTATUS_SPP | SSTATUS_SIE    // set as user mode, close interrupt
+    csrc sstatus, t0
+    li t0, SSTATUS_SPIE // enable interrupt when return to user mode
+    csrs sstatus, t0
+    
     csrw sepc, a1
     mv s0, a0
     mv s1, a1

libcpu/risc-v/t-head/c906/stackframe.h

@@ -52,52 +52,10 @@
 #endif /* ENABLE_FPU */
 
 .macro SAVE_ALL
+
 #ifdef ENABLE_FPU
-    /* save float registers */
+    /* reserve float registers */
     addi sp, sp, -CTX_FPU_REG_NR * REGBYTES
-
-    li  t0, SSTATUS_FS
-    csrs sstatus, t0
-    fsd f0,  FPU_CTX_F0_OFF(sp)
-    fsd f1,  FPU_CTX_F1_OFF(sp)
-    fsd f2,  FPU_CTX_F2_OFF(sp)
-    fsd f3,  FPU_CTX_F3_OFF(sp)
-    fsd f4,  FPU_CTX_F4_OFF(sp)
-    fsd f5,  FPU_CTX_F5_OFF(sp)
-    fsd f6,  FPU_CTX_F6_OFF(sp)
-    fsd f7,  FPU_CTX_F7_OFF(sp)
-    fsd f8,  FPU_CTX_F8_OFF(sp)
-    fsd f9,  FPU_CTX_F9_OFF(sp)
-    fsd f10, FPU_CTX_F10_OFF(sp)
-    fsd f11, FPU_CTX_F11_OFF(sp)
-    fsd f12, FPU_CTX_F12_OFF(sp)
-    fsd f13, FPU_CTX_F13_OFF(sp)
-    fsd f14, FPU_CTX_F14_OFF(sp)
-    fsd f15, FPU_CTX_F15_OFF(sp)
-    fsd f16, FPU_CTX_F16_OFF(sp)
-    fsd f17, FPU_CTX_F17_OFF(sp)
-    fsd f18, FPU_CTX_F18_OFF(sp)
-    fsd f19, FPU_CTX_F19_OFF(sp)
-    fsd f20, FPU_CTX_F20_OFF(sp)
-    fsd f21, FPU_CTX_F21_OFF(sp)
-    fsd f22, FPU_CTX_F22_OFF(sp)
-    fsd f23, FPU_CTX_F23_OFF(sp)
-    fsd f24, FPU_CTX_F24_OFF(sp)
-    fsd f25, FPU_CTX_F25_OFF(sp)
-    fsd f26, FPU_CTX_F26_OFF(sp)
-    fsd f27, FPU_CTX_F27_OFF(sp)
-    fsd f28, FPU_CTX_F28_OFF(sp)
-    fsd f29, FPU_CTX_F29_OFF(sp)
-    fsd f30, FPU_CTX_F30_OFF(sp)
-    fsd f31, FPU_CTX_F31_OFF(sp)
-
-    /* clr FS domain */
-    csrc sstatus, t0
-
-    /* clean status would clr sr_sd; */
-    li t0, SSTATUS_FS_CLEAN
-    csrs sstatus, t0
-
 #endif /* ENABLE_FPU */
 
     /* save general registers */
@@ -141,49 +99,59 @@
     STORE x31, 31 * REGBYTES(sp)
     csrr t0, sscratch
     STORE t0, 32 * REGBYTES(sp)
-.endm
 
-.macro RESTORE_ALL
-    /* restore general register */
+#ifdef ENABLE_FPU
+    /* backup sp and adjust sp to save float registers */
+    mv t1, sp
+    addi t1, t1, CTX_GENERAL_REG_NR * REGBYTES
 
-    /* resw ra to sepc */
-    LOAD x1,   0 * REGBYTES(sp)
-    csrw sepc, x1
+    li  t0, SSTATUS_FS
+    csrs sstatus, t0
+    fsd f0,  FPU_CTX_F0_OFF(t1)
+    fsd f1,  FPU_CTX_F1_OFF(t1)
+    fsd f2,  FPU_CTX_F2_OFF(t1)
+    fsd f3,  FPU_CTX_F3_OFF(t1)
+    fsd f4,  FPU_CTX_F4_OFF(t1)
+    fsd f5,  FPU_CTX_F5_OFF(t1)
+    fsd f6,  FPU_CTX_F6_OFF(t1)
+    fsd f7,  FPU_CTX_F7_OFF(t1)
+    fsd f8,  FPU_CTX_F8_OFF(t1)
+    fsd f9,  FPU_CTX_F9_OFF(t1)
+    fsd f10, FPU_CTX_F10_OFF(t1)
+    fsd f11, FPU_CTX_F11_OFF(t1)
+    fsd f12, FPU_CTX_F12_OFF(t1)
+    fsd f13, FPU_CTX_F13_OFF(t1)
+    fsd f14, FPU_CTX_F14_OFF(t1)
+    fsd f15, FPU_CTX_F15_OFF(t1)
+    fsd f16, FPU_CTX_F16_OFF(t1)
+    fsd f17, FPU_CTX_F17_OFF(t1)
+    fsd f18, FPU_CTX_F18_OFF(t1)
+    fsd f19, FPU_CTX_F19_OFF(t1)
+    fsd f20, FPU_CTX_F20_OFF(t1)
+    fsd f21, FPU_CTX_F21_OFF(t1)
+    fsd f22, FPU_CTX_F22_OFF(t1)
+    fsd f23, FPU_CTX_F23_OFF(t1)
+    fsd f24, FPU_CTX_F24_OFF(t1)
+    fsd f25, FPU_CTX_F25_OFF(t1)
+    fsd f26, FPU_CTX_F26_OFF(t1)
+    fsd f27, FPU_CTX_F27_OFF(t1)
+    fsd f28, FPU_CTX_F28_OFF(t1)
+    fsd f29, FPU_CTX_F29_OFF(t1)
+    fsd f30, FPU_CTX_F30_OFF(t1)
+    fsd f31, FPU_CTX_F31_OFF(t1)
 
-    LOAD x1,   2 * REGBYTES(sp)
-    csrw sstatus, x1
+    /* clr FS domain */
+    csrc sstatus, t0
 
-    LOAD x1,   1 * REGBYTES(sp)
+    /* clean status would clr sr_sd; */
+    li t0, SSTATUS_FS_CLEAN
+    csrs sstatus, t0
 
-    LOAD x3,   3 * REGBYTES(sp)
-    LOAD x4,   4 * REGBYTES(sp)
-    LOAD x5,   5 * REGBYTES(sp)
-    LOAD x6,   6 * REGBYTES(sp)
-    LOAD x7,   7 * REGBYTES(sp)
-    LOAD x8,   8 * REGBYTES(sp)
-    LOAD x9,   9 * REGBYTES(sp)
-    LOAD x10, 10 * REGBYTES(sp)
-    LOAD x11, 11 * REGBYTES(sp)
-    LOAD x12, 12 * REGBYTES(sp)
-    LOAD x13, 13 * REGBYTES(sp)
-    LOAD x14, 14 * REGBYTES(sp)
-    LOAD x15, 15 * REGBYTES(sp)
-    LOAD x16, 16 * REGBYTES(sp)
-    LOAD x17, 17 * REGBYTES(sp)
-    LOAD x18, 18 * REGBYTES(sp)
-    LOAD x19, 19 * REGBYTES(sp)
-    LOAD x20, 20 * REGBYTES(sp)
-    LOAD x21, 21 * REGBYTES(sp)
-    LOAD x22, 22 * REGBYTES(sp)
-    LOAD x23, 23 * REGBYTES(sp)
-    LOAD x24, 24 * REGBYTES(sp)
-    LOAD x25, 25 * REGBYTES(sp)
-    LOAD x26, 26 * REGBYTES(sp)
-    LOAD x27, 27 * REGBYTES(sp)
-    LOAD x28, 28 * REGBYTES(sp)
-    LOAD x29, 29 * REGBYTES(sp)
-    LOAD x30, 30 * REGBYTES(sp)
-    LOAD x31, 31 * REGBYTES(sp)
+#endif /* ENABLE_FPU */
+
+.endm
+
+.macro RESTORE_ALL
 
 #ifdef ENABLE_FPU
     /* restore float register  */
@@ -233,6 +201,48 @@
     csrs sstatus, t0
 
 #endif /* ENABLE_FPU */
+
+    /* restore general register */
+
+    /* resw ra to sepc */
+    LOAD x1,   0 * REGBYTES(sp)
+    csrw sepc, x1
+
+    LOAD x1,   2 * REGBYTES(sp)
+    csrw sstatus, x1
+
+    LOAD x1,   1 * REGBYTES(sp)
+
+    LOAD x3,   3 * REGBYTES(sp)
+    LOAD x4,   4 * REGBYTES(sp)
+    LOAD x5,   5 * REGBYTES(sp)
+    LOAD x6,   6 * REGBYTES(sp)
+    LOAD x7,   7 * REGBYTES(sp)
+    LOAD x8,   8 * REGBYTES(sp)
+    LOAD x9,   9 * REGBYTES(sp)
+    LOAD x10, 10 * REGBYTES(sp)
+    LOAD x11, 11 * REGBYTES(sp)
+    LOAD x12, 12 * REGBYTES(sp)
+    LOAD x13, 13 * REGBYTES(sp)
+    LOAD x14, 14 * REGBYTES(sp)
+    LOAD x15, 15 * REGBYTES(sp)
+    LOAD x16, 16 * REGBYTES(sp)
+    LOAD x17, 17 * REGBYTES(sp)
+    LOAD x18, 18 * REGBYTES(sp)
+    LOAD x19, 19 * REGBYTES(sp)
+    LOAD x20, 20 * REGBYTES(sp)
+    LOAD x21, 21 * REGBYTES(sp)
+    LOAD x22, 22 * REGBYTES(sp)
+    LOAD x23, 23 * REGBYTES(sp)
+    LOAD x24, 24 * REGBYTES(sp)
+    LOAD x25, 25 * REGBYTES(sp)
+    LOAD x26, 26 * REGBYTES(sp)
+    LOAD x27, 27 * REGBYTES(sp)
+    LOAD x28, 28 * REGBYTES(sp)
+    LOAD x29, 29 * REGBYTES(sp)
+    LOAD x30, 30 * REGBYTES(sp)
+    LOAD x31, 31 * REGBYTES(sp)
+
     /* restore user sp */
     LOAD sp, 32 * REGBYTES(sp)
 .endm

libcpu/risc-v/virt64/stackframe.h

@@ -52,52 +52,10 @@
 #endif /* ENABLE_FPU */
 
 .macro SAVE_ALL
+
 #ifdef ENABLE_FPU
-    /* save float registers */
+    /* reserve float registers */
     addi sp, sp, -CTX_FPU_REG_NR * REGBYTES
-
-    li  t0, SSTATUS_FS
-    csrs sstatus, t0
-    fsd f0,  FPU_CTX_F0_OFF(sp)
-    fsd f1,  FPU_CTX_F1_OFF(sp)
-    fsd f2,  FPU_CTX_F2_OFF(sp)
-    fsd f3,  FPU_CTX_F3_OFF(sp)
-    fsd f4,  FPU_CTX_F4_OFF(sp)
-    fsd f5,  FPU_CTX_F5_OFF(sp)
-    fsd f6,  FPU_CTX_F6_OFF(sp)
-    fsd f7,  FPU_CTX_F7_OFF(sp)
-    fsd f8,  FPU_CTX_F8_OFF(sp)
-    fsd f9,  FPU_CTX_F9_OFF(sp)
-    fsd f10, FPU_CTX_F10_OFF(sp)
-    fsd f11, FPU_CTX_F11_OFF(sp)
-    fsd f12, FPU_CTX_F12_OFF(sp)
-    fsd f13, FPU_CTX_F13_OFF(sp)
-    fsd f14, FPU_CTX_F14_OFF(sp)
-    fsd f15, FPU_CTX_F15_OFF(sp)
-    fsd f16, FPU_CTX_F16_OFF(sp)
-    fsd f17, FPU_CTX_F17_OFF(sp)
-    fsd f18, FPU_CTX_F18_OFF(sp)
-    fsd f19, FPU_CTX_F19_OFF(sp)
-    fsd f20, FPU_CTX_F20_OFF(sp)
-    fsd f21, FPU_CTX_F21_OFF(sp)
-    fsd f22, FPU_CTX_F22_OFF(sp)
-    fsd f23, FPU_CTX_F23_OFF(sp)
-    fsd f24, FPU_CTX_F24_OFF(sp)
-    fsd f25, FPU_CTX_F25_OFF(sp)
-    fsd f26, FPU_CTX_F26_OFF(sp)
-    fsd f27, FPU_CTX_F27_OFF(sp)
-    fsd f28, FPU_CTX_F28_OFF(sp)
-    fsd f29, FPU_CTX_F29_OFF(sp)
-    fsd f30, FPU_CTX_F30_OFF(sp)
-    fsd f31, FPU_CTX_F31_OFF(sp)
-
-    /* clr FS domain */
-    csrc sstatus, t0
-
-    /* clean status would clr sr_sd; */
-    li t0, SSTATUS_FS_CLEAN
-    csrs sstatus, t0
-
 #endif /* ENABLE_FPU */
 
     /* save general registers */
@@ -141,49 +99,59 @@
     STORE x31, 31 * REGBYTES(sp)
     csrr t0, sscratch
     STORE t0, 32 * REGBYTES(sp)
-.endm
 
-.macro RESTORE_ALL
-    /* restore general register */
+#ifdef ENABLE_FPU
+    /* backup sp and adjust sp to save float registers */
+    mv t1, sp
+    addi t1, t1, CTX_GENERAL_REG_NR * REGBYTES
 
-    /* resw ra to sepc */
-    LOAD x1,   0 * REGBYTES(sp)
-    csrw sepc, x1
+    li  t0, SSTATUS_FS
+    csrs sstatus, t0
+    fsd f0,  FPU_CTX_F0_OFF(t1)
+    fsd f1,  FPU_CTX_F1_OFF(t1)
+    fsd f2,  FPU_CTX_F2_OFF(t1)
+    fsd f3,  FPU_CTX_F3_OFF(t1)
+    fsd f4,  FPU_CTX_F4_OFF(t1)
+    fsd f5,  FPU_CTX_F5_OFF(t1)
+    fsd f6,  FPU_CTX_F6_OFF(t1)
+    fsd f7,  FPU_CTX_F7_OFF(t1)
+    fsd f8,  FPU_CTX_F8_OFF(t1)
+    fsd f9,  FPU_CTX_F9_OFF(t1)
+    fsd f10, FPU_CTX_F10_OFF(t1)
+    fsd f11, FPU_CTX_F11_OFF(t1)
+    fsd f12, FPU_CTX_F12_OFF(t1)
+    fsd f13, FPU_CTX_F13_OFF(t1)
+    fsd f14, FPU_CTX_F14_OFF(t1)
+    fsd f15, FPU_CTX_F15_OFF(t1)
+    fsd f16, FPU_CTX_F16_OFF(t1)
+    fsd f17, FPU_CTX_F17_OFF(t1)
+    fsd f18, FPU_CTX_F18_OFF(t1)
+    fsd f19, FPU_CTX_F19_OFF(t1)
+    fsd f20, FPU_CTX_F20_OFF(t1)
+    fsd f21, FPU_CTX_F21_OFF(t1)
+    fsd f22, FPU_CTX_F22_OFF(t1)
+    fsd f23, FPU_CTX_F23_OFF(t1)
+    fsd f24, FPU_CTX_F24_OFF(t1)
+    fsd f25, FPU_CTX_F25_OFF(t1)
+    fsd f26, FPU_CTX_F26_OFF(t1)
+    fsd f27, FPU_CTX_F27_OFF(t1)
+    fsd f28, FPU_CTX_F28_OFF(t1)
+    fsd f29, FPU_CTX_F29_OFF(t1)
+    fsd f30, FPU_CTX_F30_OFF(t1)
+    fsd f31, FPU_CTX_F31_OFF(t1)
 
-    LOAD x1,   2 * REGBYTES(sp)
-    csrw sstatus, x1
+    /* clr FS domain */
+    csrc sstatus, t0
 
-    LOAD x1,   1 * REGBYTES(sp)
+    /* clean status would clr sr_sd; */
+    li t0, SSTATUS_FS_CLEAN
+    csrs sstatus, t0
 
-    LOAD x3,   3 * REGBYTES(sp)
-    LOAD x4,   4 * REGBYTES(sp)
-    LOAD x5,   5 * REGBYTES(sp)
-    LOAD x6,   6 * REGBYTES(sp)
-    LOAD x7,   7 * REGBYTES(sp)
-    LOAD x8,   8 * REGBYTES(sp)
-    LOAD x9,   9 * REGBYTES(sp)
-    LOAD x10, 10 * REGBYTES(sp)
-    LOAD x11, 11 * REGBYTES(sp)
-    LOAD x12, 12 * REGBYTES(sp)
-    LOAD x13, 13 * REGBYTES(sp)
-    LOAD x14, 14 * REGBYTES(sp)
-    LOAD x15, 15 * REGBYTES(sp)
-    LOAD x16, 16 * REGBYTES(sp)
-    LOAD x17, 17 * REGBYTES(sp)
-    LOAD x18, 18 * REGBYTES(sp)
-    LOAD x19, 19 * REGBYTES(sp)
-    LOAD x20, 20 * REGBYTES(sp)
-    LOAD x21, 21 * REGBYTES(sp)
-    LOAD x22, 22 * REGBYTES(sp)
-    LOAD x23, 23 * REGBYTES(sp)
-    LOAD x24, 24 * REGBYTES(sp)
-    LOAD x25, 25 * REGBYTES(sp)
-    LOAD x26, 26 * REGBYTES(sp)
-    LOAD x27, 27 * REGBYTES(sp)
-    LOAD x28, 28 * REGBYTES(sp)
-    LOAD x29, 29 * REGBYTES(sp)
-    LOAD x30, 30 * REGBYTES(sp)
-    LOAD x31, 31 * REGBYTES(sp)
+#endif /* ENABLE_FPU */
+
+.endm
+
+.macro RESTORE_ALL
 
 #ifdef ENABLE_FPU
     /* restore float register  */
@@ -233,6 +201,48 @@
     csrs sstatus, t0
 
 #endif /* ENABLE_FPU */
+
+    /* restore general register */
+
+    /* resw ra to sepc */
+    LOAD x1,   0 * REGBYTES(sp)
+    csrw sepc, x1
+
+    LOAD x1,   2 * REGBYTES(sp)
+    csrw sstatus, x1
+
+    LOAD x1,   1 * REGBYTES(sp)
+
+    LOAD x3,   3 * REGBYTES(sp)
+    LOAD x4,   4 * REGBYTES(sp)
+    LOAD x5,   5 * REGBYTES(sp)
+    LOAD x6,   6 * REGBYTES(sp)
+    LOAD x7,   7 * REGBYTES(sp)
+    LOAD x8,   8 * REGBYTES(sp)
+    LOAD x9,   9 * REGBYTES(sp)
+    LOAD x10, 10 * REGBYTES(sp)
+    LOAD x11, 11 * REGBYTES(sp)
+    LOAD x12, 12 * REGBYTES(sp)
+    LOAD x13, 13 * REGBYTES(sp)
+    LOAD x14, 14 * REGBYTES(sp)
+    LOAD x15, 15 * REGBYTES(sp)
+    LOAD x16, 16 * REGBYTES(sp)
+    LOAD x17, 17 * REGBYTES(sp)
+    LOAD x18, 18 * REGBYTES(sp)
+    LOAD x19, 19 * REGBYTES(sp)
+    LOAD x20, 20 * REGBYTES(sp)
+    LOAD x21, 21 * REGBYTES(sp)
+    LOAD x22, 22 * REGBYTES(sp)
+    LOAD x23, 23 * REGBYTES(sp)
+    LOAD x24, 24 * REGBYTES(sp)
+    LOAD x25, 25 * REGBYTES(sp)
+    LOAD x26, 26 * REGBYTES(sp)
+    LOAD x27, 27 * REGBYTES(sp)
+    LOAD x28, 28 * REGBYTES(sp)
+    LOAD x29, 29 * REGBYTES(sp)
+    LOAD x30, 30 * REGBYTES(sp)
+    LOAD x31, 31 * REGBYTES(sp)
+
     /* restore user sp */
     LOAD sp, 32 * REGBYTES(sp)
 .endm