remove lpc1100 because there is a cortex-m0 branch.

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2406 bbd45198-f89e-11dd-88c7-29a3b14d5316

libcpu/arm/lpc1100/CMSIS/LPC11xx.h

@@ -1,499 +0,0 @@
-/**************************************************************************//**
- * @file     LPC11xx.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File for 
- *           NXP LPC11xx Device Series
- * @version  V1.00
- * @date     17. November 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __LPC11xx_H__
-#define __LPC11xx_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup LPC11xx_Definitions LPC11xx Definitions
-  This file defines all structures and symbols for LPC11xx:
-    - Registers and bitfields
-    - peripheral base address
-    - peripheral ID
-    - PIO definitions
-  @{
-*/
-
-
-/******************************************************************************/
-/*                Processor and Core Peripherals                              */
-/******************************************************************************/
-/** @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions
-  Configuration of the Cortex-M0 Processor and Core Peripherals
-  @{
-*/
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-
-typedef enum IRQn
-{
-/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
-  NonMaskableInt_IRQn           = -14,    /*!< 2 Non Maskable Interrupt                           */
-  HardFault_IRQn                = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                   */
-  SVCall_IRQn                   = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                     */
-  PendSV_IRQn                   = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                     */
-  SysTick_IRQn                  = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                 */
-
-/******  LPC11xx Specific Interrupt Numbers *******************************************************/
-  WAKEUP0_IRQn                  = 0,        /*!< All I/O pins can be used as wakeup source.       */
-  WAKEUP1_IRQn                  = 1,        /*!< There are 13 pins in total for LPC11xx           */
-  WAKEUP2_IRQn                  = 2,
-  WAKEUP3_IRQn                  = 3,
-  WAKEUP4_IRQn                  = 4,   
-  WAKEUP5_IRQn                  = 5,        
-  WAKEUP6_IRQn                  = 6,        
-  WAKEUP7_IRQn                  = 7,        
-  WAKEUP8_IRQn                  = 8,        
-  WAKEUP9_IRQn                  = 9,        
-  WAKEUP10_IRQn                 = 10,       
-  WAKEUP11_IRQn                 = 11,       
-  WAKEUP12_IRQn                 = 12,       
-  SSP1_IRQn                     = 14,       /*!< SSP1 Interrupt                                   */
-  I2C_IRQn                      = 15,       /*!< I2C Interrupt                                    */
-  TIMER_16_0_IRQn               = 16,       /*!< 16-bit Timer0 Interrupt                          */
-  TIMER_16_1_IRQn               = 17,       /*!< 16-bit Timer1 Interrupt                          */
-  TIMER_32_0_IRQn               = 18,       /*!< 32-bit Timer0 Interrupt                          */
-  TIMER_32_1_IRQn               = 19,       /*!< 32-bit Timer1 Interrupt                          */
-  SSP0_IRQn                     = 20,       /*!< SSP0 Interrupt                                   */
-  UART_IRQn                     = 21,       /*!< UART Interrupt                                   */
-  ADC_IRQn                      = 24,       /*!< A/D Converter Interrupt                          */
-  WDT_IRQn                      = 25,       /*!< Watchdog timer Interrupt                         */  
-  BOD_IRQn                      = 26,       /*!< Brown Out Detect(BOD) Interrupt                  */
-  EINT3_IRQn                    = 28,       /*!< External Interrupt 3 Interrupt                   */
-  EINT2_IRQn                    = 29,       /*!< External Interrupt 2 Interrupt                   */
-  EINT1_IRQn                    = 30,       /*!< External Interrupt 1 Interrupt                   */
-  EINT0_IRQn                    = 31,       /*!< External Interrupt 0 Interrupt                   */
-} IRQn_Type;
-
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */
-#define __MPU_PRESENT             0         /*!< MPU present or not                               */
-#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-/*@}*/ /* end of group LPC11xx_CMSIS */
-
-
-#include "core_cm0.h"                       /* Cortex-M0 processor and core peripherals           */
-#include "system_LPC11xx.h"                 /* System Header                                      */
-
-
-/******************************************************************************/
-/*                Device Specific Peripheral Registers structures             */
-/******************************************************************************/
-
-#if defined ( __CC_ARM   )
-#pragma anon_unions
-#endif
-
-/*------------- System Control (SYSCON) --------------------------------------*/
-/** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t SYSMEMREMAP;            /*!< Offset: 0x000 System memory remap (R/W) */
-  __IO uint32_t PRESETCTRL;             /*!< Offset: 0x004 Peripheral reset control (R/W) */
-  __IO uint32_t SYSPLLCTRL;             /*!< Offset: 0x008 System PLL control (R/W) */
-  __IO uint32_t SYSPLLSTAT;             /*!< Offset: 0x00C System PLL status (R/ ) */
-       uint32_t RESERVED0[4];
-
-  __IO uint32_t SYSOSCCTRL;             /*!< Offset: 0x020 System oscillator control (R/W) */
-  __IO uint32_t WDTOSCCTRL;             /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
-  __IO uint32_t IRCCTRL;                /*!< Offset: 0x028 IRC control (R/W) */
-       uint32_t RESERVED1[1];
-  __IO uint32_t SYSRESSTAT;             /*!< Offset: 0x030 System reset status Register (R/ ) */
-       uint32_t RESERVED2[3];
-  __IO uint32_t SYSPLLCLKSEL;           /*!< Offset: 0x040 System PLL clock source select (R/W) */	
-  __IO uint32_t SYSPLLCLKUEN;           /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
-       uint32_t RESERVED3[10];
-
-  __IO uint32_t MAINCLKSEL;             /*!< Offset: 0x070 Main clock source select (R/W) */
-  __IO uint32_t MAINCLKUEN;             /*!< Offset: 0x074 Main clock source update enable (R/W) */
-  __IO uint32_t SYSAHBCLKDIV;           /*!< Offset: 0x078 System AHB clock divider (R/W) */
-       uint32_t RESERVED4[1];
-
-  __IO uint32_t SYSAHBCLKCTRL;          /*!< Offset: 0x080 System AHB clock control (R/W) */
-       uint32_t RESERVED5[4];
-  __IO uint32_t SSP0CLKDIV;             /*!< Offset: 0x094 SSP0 clock divider (R/W) */          
-  __IO uint32_t UARTCLKDIV;             /*!< Offset: 0x098 UART clock divider (R/W) */
-  __IO uint32_t SSP1CLKDIV;             /*!< Offset: 0x09C SSP1 clock divider (R/W) */          
-       uint32_t RESERVED6[4];
-
-  __IO uint32_t SYSTICKCLKDIV;          /*!< Offset: 0x0B0 SYSTICK clock divider (R/W) */          
-       uint32_t RESERVED7[7];
-
-  __IO uint32_t WDTCLKSEL;              /*!< Offset: 0x0D0 WDT clock source select (R/W) */
-  __IO uint32_t WDTCLKUEN;              /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */
-  __IO uint32_t WDTCLKDIV;              /*!< Offset: 0x0D8 WDT clock divider (R/W) */
-       uint32_t RESERVED8[1];              
-  __IO uint32_t CLKOUTCLKSEL;           /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
-  __IO uint32_t CLKOUTUEN;              /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
-  __IO uint32_t CLKOUTDIV;              /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */       
-       uint32_t RESERVED9[5];
-  
-  __IO uint32_t PIOPORCAP0;             /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */           
-  __IO uint32_t PIOPORCAP1;             /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */   
-       uint32_t RESERVED10[18];
-
-  __IO uint32_t BODCTRL;                /*!< Offset: 0x150 BOD control (R/W) */
-       uint32_t RESERVED11[1];
-  __IO uint32_t SYSTCKCAL;              /*!< Offset: 0x158 System tick counter calibration (R/W) */
-       uint32_t RESERVED12[41];          
-
-  __IO uint32_t STARTAPRP0;             /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */     
-  __IO uint32_t STARTERP0;              /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */      
-  __IO uint32_t STARTRSRP0CLR;          /*!< Offset: 0x208 Start logic reset Register 0  ( /W) */
-  __IO uint32_t STARTSRP0;              /*!< Offset: 0x20C Start logic status Register 0 (R/W) */
-       uint32_t RESERVED14[8];
-
-  __IO uint32_t PDSLEEPCFG;             /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
-  __IO uint32_t PDAWAKECFG;             /*!< Offset: 0x234 Power-down states after wake-up (R/W) */        
-  __IO uint32_t PDRUNCFG;               /*!< Offset: 0x238 Power-down configuration Register (R/W) */
-       uint32_t RESERVED15[110];
-  __I  uint32_t DEVICE_ID;              /*!< Offset: 0x3F4 Device ID (R/ ) */
-} LPC_SYSCON_TypeDef;
-/*@}*/ /* end of group LPC11xx_SYSCON */
-
-
-/*------------- Pin Connect Block (IOCON) --------------------------------*/
-/** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t PIO2_6;                 /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */
-       uint32_t RESERVED0[1];
-  __IO uint32_t PIO2_0;                 /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */
-  __IO uint32_t RESET_PIO0_0;           /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0  (R/W) */
-  __IO uint32_t PIO0_1;                 /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */
-  __IO uint32_t PIO1_8;                 /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */
-       uint32_t RESERVED1[1];
-  __IO uint32_t PIO0_2;                 /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */
-
-  __IO uint32_t PIO2_7;                 /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */
-  __IO uint32_t PIO2_8;                 /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */
-  __IO uint32_t PIO2_1;                 /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */
-  __IO uint32_t PIO0_3;                 /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */
-  __IO uint32_t PIO0_4;                 /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */
-  __IO uint32_t PIO0_5;                 /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */
-  __IO uint32_t PIO1_9;                 /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */
-  __IO uint32_t PIO3_4;                 /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */
-
-  __IO uint32_t PIO2_4;                 /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */
-  __IO uint32_t PIO2_5;                 /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */
-  __IO uint32_t PIO3_5;                 /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */
-  __IO uint32_t PIO0_6;                 /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */
-  __IO uint32_t PIO0_7;                 /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */
-  __IO uint32_t PIO2_9;                 /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */
-  __IO uint32_t PIO2_10;                /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */
-  __IO uint32_t PIO2_2;                 /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */
-
-  __IO uint32_t PIO0_8;                 /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */
-  __IO uint32_t PIO0_9;                 /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */
-  __IO uint32_t JTAG_TCK_PIO0_10;       /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */
-  __IO uint32_t PIO1_10;                /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */
-  __IO uint32_t PIO2_11;                /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */
-  __IO uint32_t JTAG_TDI_PIO0_11;       /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */
-  __IO uint32_t JTAG_TMS_PIO1_0;        /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */
-  __IO uint32_t JTAG_TDO_PIO1_1;        /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */
-
-  __IO uint32_t JTAG_nTRST_PIO1_2;      /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */
-  __IO uint32_t PIO3_0;                 /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */
-  __IO uint32_t PIO3_1;                 /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */
-  __IO uint32_t PIO2_3;                 /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */
-  __IO uint32_t ARM_SWDIO_PIO1_3;       /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */
-  __IO uint32_t PIO1_4;                 /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */
-  __IO uint32_t PIO1_11;                /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */
-  __IO uint32_t PIO3_2;                 /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */
-
-  __IO uint32_t PIO1_5;                 /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */
-  __IO uint32_t PIO1_6;                 /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */
-  __IO uint32_t PIO1_7;                 /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */
-  __IO uint32_t PIO3_3;                 /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */
-  __IO uint32_t SCK_LOC;                /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */
-  __IO uint32_t DSR_LOC;                /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */
-  __IO uint32_t DCD_LOC;                /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */
-  __IO uint32_t RI_LOC;                 /*!< Offset: 0x0BC RI pin location Register (R/W) */
-} LPC_IOCON_TypeDef;
-/*@}*/ /* end of group LPC11xx_IOCON */
-
-
-/*------------- Power Management Unit (PMU) --------------------------*/
-/** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t PCON;                   /*!< Offset: 0x000 Power control Register (R/W) */
-  __IO uint32_t GPREG0;                 /*!< Offset: 0x004 General purpose Register 0 (R/W) */
-  __IO uint32_t GPREG1;                 /*!< Offset: 0x008 General purpose Register 1 (R/W) */
-  __IO uint32_t GPREG2;                 /*!< Offset: 0x00C General purpose Register 2 (R/W) */
-  __IO uint32_t GPREG3;                 /*!< Offset: 0x010 General purpose Register 3 (R/W) */
-  __IO uint32_t GPREG4;                 /*!< Offset: 0x014 General purpose Register 4 (R/W) */
-} LPC_PMU_TypeDef;
-/*@}*/ /* end of group LPC11xx_PMU */
-
-
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-/** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output 
-  @{
-*/
-typedef struct
-{
-  union {
-    __IO uint32_t MASKED_ACCESS[4096];  /*!< Offset: 0x0000 to 0x3FFC Port data Register for pins PIOn_0 to PIOn_11 (R/W) */
-    struct {
-         uint32_t RESERVED0[4095];
-    __IO uint32_t DATA;                 /*!< Offset: 0x3FFC Port data Register (R/W) */
-    };
-  };
-       uint32_t RESERVED1[4096];
-  __IO uint32_t DIR;                    /*!< Offset: 0x8000 Data direction Register (R/W) */
-  __IO uint32_t IS;                     /*!< Offset: 0x8004 Interrupt sense Register (R/W) */
-  __IO uint32_t IBE;                    /*!< Offset: 0x8008 Interrupt both edges Register (R/W) */
-  __IO uint32_t IEV;                    /*!< Offset: 0x800C Interrupt event Register  (R/W) */
-  __IO uint32_t IE;                     /*!< Offset: 0x8010 Interrupt mask Register (R/W) */
-  __IO uint32_t RIS;                    /*!< Offset: 0x8014 Raw interrupt status Register (R/ ) */
-  __IO uint32_t MIS;                    /*!< Offset: 0x8018 Masked interrupt status Register (R/ ) */
-  __IO uint32_t IC;                     /*!< Offset: 0x801C Interrupt clear Register (R/W) */
-} LPC_GPIO_TypeDef;
-/*@}*/ /* end of group LPC11xx_GPIO */
-
-
-/*------------- Timer (TMR) --------------------------------------------------*/
-/** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t IR;                     /*!< Offset: 0x000 Interrupt Register (R/W) */
-  __IO uint32_t TCR;                    /*!< Offset: 0x004 Timer Control Register (R/W) */
-  __IO uint32_t TC;                     /*!< Offset: 0x008 Timer Counter Register (R/W) */
-  __IO uint32_t PR;                     /*!< Offset: 0x00C Prescale Register (R/W) */
-  __IO uint32_t PC;                     /*!< Offset: 0x010 Prescale Counter Register (R/W) */
-  __IO uint32_t MCR;                    /*!< Offset: 0x014 Match Control Register (R/W) */
-  __IO uint32_t MR0;                    /*!< Offset: 0x018 Match Register 0 (R/W) */
-  __IO uint32_t MR1;                    /*!< Offset: 0x01C Match Register 1 (R/W) */
-  __IO uint32_t MR2;                    /*!< Offset: 0x020 Match Register 2 (R/W) */
-  __IO uint32_t MR3;                    /*!< Offset: 0x024 Match Register 3 (R/W) */
-  __IO uint32_t CCR;                    /*!< Offset: 0x028 Capture Control Register (R/W) */
-  __I  uint32_t CR0;                    /*!< Offset: 0x02C Capture Register 0 (R/ ) */
-       uint32_t RESERVED1[3];
-  __IO uint32_t EMR;                    /*!< Offset: 0x03C External Match Register (R/W) */
-       uint32_t RESERVED2[12];
-  __IO uint32_t CTCR;                   /*!< Offset: 0x070 Count Control Register (R/W) */
-  __IO uint32_t PWMC;                   /*!< Offset: 0x074 PWM Control Register (R/W) */
-} LPC_TMR_TypeDef;
-/*@}*/ /* end of group LPC11xx_TMR */
-
-
-/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
-/** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter 
-  @{
-*/
-typedef struct
-{
-  union {
-  __I  uint32_t  RBR;                   /*!< Offset: 0x000 Receiver Buffer  Register (R/ ) */
-  __O  uint32_t  THR;                   /*!< Offset: 0x000 Transmit Holding Register ( /W) */
-  __IO uint32_t  DLL;                   /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
-  };
-  union {
-  __IO uint32_t  DLM;                   /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
-  __IO uint32_t  IER;                   /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
-  };
-  union {
-  __I  uint32_t  IIR;                   /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
-  __O  uint32_t  FCR;                   /*!< Offset: 0x008 FIFO Control Register ( /W) */
-  };
-  __IO uint32_t  LCR;                   /*!< Offset: 0x00C Line Control Register (R/W) */
-  __IO uint32_t  MCR;                   /*!< Offset: 0x010 Modem control Register (R/W) */
-  __I  uint32_t  LSR;                   /*!< Offset: 0x014 Line Status Register (R/ ) */
-  __I  uint32_t  MSR;                   /*!< Offset: 0x018 Modem status Register (R/ ) */
-  __IO uint32_t  SCR;                   /*!< Offset: 0x01C Scratch Pad Register (R/W) */
-  __IO uint32_t  ACR;                   /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
-       uint32_t  RESERVED0;
-  __IO uint32_t  FDR;                   /*!< Offset: 0x028 Fractional Divider Register (R/W) */
-       uint32_t  RESERVED1;
-  __IO uint32_t  TER;                   /*!< Offset: 0x030 Transmit Enable Register (R/W) */
-       uint32_t  RESERVED2[6];
-  __IO uint32_t  RS485CTRL;             /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
-  __IO uint32_t  ADRMATCH;              /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
-  __IO uint32_t  RS485DLY;              /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
-  __I  uint32_t  FIFOLVL;               /*!< Offset: 0x058 FIFO Level Register (R/ ) */
-} LPC_UART_TypeDef;
-/*@}*/ /* end of group LPC11xx_UART */
-
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-/** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t CR0;                    /*!< Offset: 0x000 Control Register 0 (R/W) */
-  __IO uint32_t CR1;                    /*!< Offset: 0x004 Control Register 1 (R/W) */
-  __IO uint32_t DR;                     /*!< Offset: 0x008 Data Register (R/W) */
-  __I  uint32_t SR;                     /*!< Offset: 0x00C Status Registe (R/ ) */
-  __IO uint32_t CPSR;                   /*!< Offset: 0x010 Clock Prescale Register (R/W) */
-  __IO uint32_t IMSC;                   /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
-  __IO uint32_t RIS;                    /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
-  __IO uint32_t MIS;                    /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
-  __IO uint32_t ICR;                    /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
-} LPC_SSP_TypeDef;
-/*@}*/ /* end of group LPC11xx_SSP */
-
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-/** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t CONSET;                 /*!< Offset: 0x000 I2C Control Set Register (R/W) */
-  __I  uint32_t STAT;                   /*!< Offset: 0x004 I2C Status Register (R/ ) */
-  __IO uint32_t DAT;                    /*!< Offset: 0x008 I2C Data Register (R/W) */
-  __IO uint32_t ADR0;                   /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
-  __IO uint32_t SCLH;                   /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
-  __IO uint32_t SCLL;                   /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
-  __O  uint32_t CONCLR;                 /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
-  __IO uint32_t MMCTRL;                 /*!< Offset: 0x01C Monitor mode control register (R/W) */
-  __IO uint32_t ADR1;                   /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
-  __IO uint32_t ADR2;                   /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
-  __IO uint32_t ADR3;                   /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
-  __I  uint32_t DATA_BUFFER;            /*!< Offset: 0x02C Data buffer register ( /W) */
-  __IO uint32_t MASK0;                  /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
-  __IO uint32_t MASK1;                  /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
-  __IO uint32_t MASK2;                  /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
-  __IO uint32_t MASK3;                  /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
-} LPC_I2C_TypeDef;
-/*@}*/ /* end of group LPC11xx_I2C */
-
-
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/
-/** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t MOD;                    /*!< Offset: 0x000 Watchdog mode register (R/W) */
-  __IO uint32_t TC;                     /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
-  __O  uint32_t FEED;                   /*!< Offset: 0x008 Watchdog feed sequence register ( /W) */
-  __I  uint32_t TV;                     /*!< Offset: 0x00C Watchdog timer value register (R/ ) */
-} LPC_WDT_TypeDef;
-/*@}*/ /* end of group LPC11xx_WDT */
-
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-/** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter 
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t CR;                     /*!< Offset: 0x000       A/D Control Register (R/W) */
-  __IO uint32_t GDR;                    /*!< Offset: 0x004       A/D Global Data Register (R/W) */
-       uint32_t RESERVED0;
-  __IO uint32_t INTEN;                  /*!< Offset: 0x00C       A/D Interrupt Enable Register (R/W) */
-  __IO uint32_t DR[8];                  /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
-  __I  uint32_t STAT;                   /*!< Offset: 0x030       A/D Status Register (R/ ) */
-} LPC_ADC_TypeDef;
-/*@}*/ /* end of group LPC11xx_ADC */
-
-
-#if defined ( __CC_ARM   )
-#pragma no_anon_unions
-#endif
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/* Base addresses                                                             */
-#define LPC_FLASH_BASE        (0x00000000UL)
-#define LPC_RAM_BASE          (0x10000000UL)
-#define LPC_APB0_BASE         (0x40000000UL)
-#define LPC_AHB_BASE          (0x50000000UL)
-
-/* APB0 peripherals                                                           */
-#define LPC_I2C_BASE          (LPC_APB0_BASE + 0x00000)
-#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x04000)
-#define LPC_UART_BASE         (LPC_APB0_BASE + 0x08000)
-#define LPC_CT16B0_BASE       (LPC_APB0_BASE + 0x0C000)
-#define LPC_CT16B1_BASE       (LPC_APB0_BASE + 0x10000)
-#define LPC_CT32B0_BASE       (LPC_APB0_BASE + 0x14000)
-#define LPC_CT32B1_BASE       (LPC_APB0_BASE + 0x18000)
-#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x1C000)
-#define LPC_PMU_BASE          (LPC_APB0_BASE + 0x38000)
-#define LPC_SSP0_BASE         (LPC_APB0_BASE + 0x40000)
-#define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x44000)
-#define LPC_SYSCON_BASE       (LPC_APB0_BASE + 0x48000)
-#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x58000)
-
-/* AHB peripherals                                                            */	
-#define LPC_GPIO_BASE         (LPC_AHB_BASE  + 0x00000)
-#define LPC_GPIO0_BASE        (LPC_AHB_BASE  + 0x00000)
-#define LPC_GPIO1_BASE        (LPC_AHB_BASE  + 0x10000)
-#define LPC_GPIO2_BASE        (LPC_AHB_BASE  + 0x20000)
-#define LPC_GPIO3_BASE        (LPC_AHB_BASE  + 0x30000)
-
-/******************************************************************************/
-/*                         Peripheral declaration                             */
-/******************************************************************************/
-#define LPC_I2C               ((LPC_I2C_TypeDef    *) LPC_I2C_BASE   )
-#define LPC_WDT               ((LPC_WDT_TypeDef    *) LPC_WDT_BASE   )
-#define LPC_UART              ((LPC_UART_TypeDef   *) LPC_UART_BASE  )
-#define LPC_TMR16B0           ((LPC_TMR_TypeDef    *) LPC_CT16B0_BASE)
-#define LPC_TMR16B1           ((LPC_TMR_TypeDef    *) LPC_CT16B1_BASE)
-#define LPC_TMR32B0           ((LPC_TMR_TypeDef    *) LPC_CT32B0_BASE)
-#define LPC_TMR32B1           ((LPC_TMR_TypeDef    *) LPC_CT32B1_BASE)
-#define LPC_ADC               ((LPC_ADC_TypeDef    *) LPC_ADC_BASE   )
-#define LPC_PMU               ((LPC_PMU_TypeDef    *) LPC_PMU_BASE   )
-#define LPC_SSP0              ((LPC_SSP_TypeDef    *) LPC_SSP0_BASE  )
-#define LPC_SSP1              ((LPC_SSP_TypeDef    *) LPC_SSP1_BASE  )
-#define LPC_IOCON             ((LPC_IOCON_TypeDef  *) LPC_IOCON_BASE )
-#define LPC_SYSCON            ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
-#define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )
-#define LPC_GPIO1             ((LPC_GPIO_TypeDef   *) LPC_GPIO1_BASE )
-#define LPC_GPIO2             ((LPC_GPIO_TypeDef   *) LPC_GPIO2_BASE )
-#define LPC_GPIO3             ((LPC_GPIO_TypeDef   *) LPC_GPIO3_BASE )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* __LPC11xx_H__ */

libcpu/arm/lpc1100/CMSIS/core_cm0.c

@@ -1,455 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.c
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Source File
- * @version  V1.30
- * @date     30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include <stdint.h>
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
-  mrs r0, psp
-  bx lr
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
-  msr psp, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
-  mrs r0, msp
-  bx lr
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
-  msr msp, r0
-  bx lr
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
-  mrs r0, primask
-  bx lr
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
-  msr primask, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Control Register value
- * 
- * @return Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
-  mrs r0, control
-  bx lr
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
-  msr control, r0
-  bx lr
-}
-
-#endif /* __ARMCC_VERSION  */ 
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#pragma diag_suppress=Pe940
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
-  __ASM("rev16 r0, r0");
-  __ASM("bx lr");
-}
-
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void) __attribute__( ( naked ) );
-uint32_t __get_PSP(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, psp\n\t" 
-                  "MOV r0, %0 \n\t"
-                  "BX  lr     \n\t"  : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
-void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n\t"
-                  "BX  lr     \n\t" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void) __attribute__( ( naked ) );
-uint32_t __get_MSP(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, msp\n\t" 
-                  "MOV r0, %0 \n\t"
-                  "BX  lr     \n\t"  : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
-void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n\t"
-                  "BX  lr     \n\t" : : "r" (topOfMainStack) );
-}
-
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-uint32_t __get_PRIMASK(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-/**
- * @brief  Return the Control Register value
-* 
-*  @return Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/**
- * @brief  Reverse byte order in integer value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif

libcpu/arm/lpc1100/CMSIS/core_cm0.h

@@ -1,960 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V1.30
- * @date     30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CM0_CORE_H__
-#define __CM0_CORE_H__
-
-/** @addtogroup CMSIS_CM0_core_LintCinfiguration CMSIS CM0 Core Lint Configuration
- *
- * List of Lint messages which will be suppressed and not shown:
- *   - not yet checked
- * .
- * Note:  To re-enable a Message, insert a space before 'lint' *
- *
- */
-
-
-/** @addtogroup CMSIS_CM0_core_definitions CM0 Core Definitions
-  This file defines all structures and symbols for CMSIS core:
-    - CMSIS version number
-    - Cortex-M core registers and bitfields
-    - Cortex-M core peripheral base address
-  @{
- */
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-#define __CM0_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB   (0x30)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
-
-#define __CORTEX_M                (0x00)                                                       /*!< Cortex core                    */
-
-#include <stdint.h>                           /* Include standard types */
-
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-
-#ifndef __NVIC_PRIO_BITS
-  #define __NVIC_PRIO_BITS    2               /*!< standard definition for NVIC Priority Bits */
-#endif
-
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#ifdef __cplusplus
-  #define     __I     volatile                /*!< defines 'read only' permissions      */
-#else
-  #define     __I     volatile const          /*!< defines 'read only' permissions      */
-#endif
-#define     __O     volatile                  /*!< defines 'write only' permissions     */
-#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-/** @addtogroup CMSIS_CM0_core_register CMSIS CM0 Core Register
- @{
-*/
-
-
-/** @addtogroup CMSIS_CM0_NVIC CMSIS CM0 NVIC
-  memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
-  @{
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                      /*!< (Offset: 0x000) Interrupt Set Enable Register            */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                      /*!< (Offset: 0x080) Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                      /*!< (Offset: 0x100) Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                      /*!< (Offset: 0x180) Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IPR[8];                       /*!< (Offset: 0x3EC) Interrupt Priority Register              */
-}  NVIC_Type;
-/*@}*/ /* end of group CMSIS_CM0_NVIC */
-
-
-/** @addtogroup CMSIS_CM0_SCB CMSIS CM0 SCB
-  memory mapped structure for System Control Block (SCB)
-  @{
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                        /*!< Offset: 0x00  CPU ID Base Register                                  */
-  __IO uint32_t ICSR;                         /*!< Offset: 0x04  Interrupt Control State Register                      */
-       uint32_t RESERVED0;                                      
-  __IO uint32_t AIRCR;                        /*!< Offset: 0x0C  Application Interrupt / Reset Control Register        */
-  __IO uint32_t SCR;                          /*!< Offset: 0x10  System Control Register                               */
-  __IO uint32_t CCR;                          /*!< Offset: 0x14  Configuration Control Register                        */
-       uint32_t RESERVED1;                                      
-  __IO uint32_t SHP[2];                       /*!< Offset: 0x1C  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                        /*!< Offset: 0x24  System Handler Control and State Register             */
-       uint32_t RESERVED2[2];                                   
-  __IO uint32_t DFSR;                         /*!< Offset: 0x30  Debug Fault Status Register                           */
-} SCB_Type;                                                
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFul << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFul << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFul << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFul << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1ul << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1ul << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1ul << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1ul << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1ul << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1ul << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1ul << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFul << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1ul << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1ul << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1ul << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1ul << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1ul << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1ul << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1ul << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1ul << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1ul << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1ul << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1ul << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1ul << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1ul << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-/*@}*/ /* end of group CMSIS_CM0_SCB */
-
-
-/** @addtogroup CMSIS_CM0_SysTick CMSIS CM0 SysTick
-  memory mapped structure for SysTick
-  @{
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM0_SysTick */
-
-
-/** @addtogroup CMSIS_CM0_CoreDebug CMSIS CM0 Core Debug
-  memory mapped structure for Core Debug Register
-  @{
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                        /*!< Offset: 0x00  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                        /*!< Offset: 0x04  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                        /*!< Offset: 0x08  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                        /*!< Offset: 0x0C  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1ul << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1ul << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1ul << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1ul << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1ul << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1ul << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos         24                                             /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk         (1ul << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-/*@}*/ /* end of group CMSIS_CM0_CoreDebug */
-
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address */
-#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address           */
-#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
-#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
-#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
-
-/*@}*/ /* end of group CMSIS_CM0_core_register */
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq                __enable_fiq
-#define __disable_fault_irq               __disable_fiq
-
-#define __NOP                             __nop
-#define __WFI                             __wfi
-#define __WFE                             __wfe
-#define __SEV                             __sev
-#define __ISB()                           __isb(0)
-#define __DSB()                           __dsb(0)
-#define __DMB()                           __dmb(0)
-#define __REV                             __rev
-
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param   priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief  Return the Control Register value
- * 
- * @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else  /* (__ARMCC_VERSION >= 400000)  */
-
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-/**
- * @brief  Return the Control Register value
- * 
- * @return Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION  */ 
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
-#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }
-
-#define __NOP                                     __no_operation            /*!< no operation intrinsic in IAR Compiler */ 
-static __INLINE  void __WFI()                     { __ASM ("wfi"); }
-static __INLINE  void __WFE()                     { __ASM ("wfe"); }
-static __INLINE  void __SEV()                     { __ASM ("sev"); }
-
-/* intrinsic void __ISB(void)                                     */
-/* intrinsic void __DSB(void)                                     */
-/* intrinsic void __DMB(void)                                     */
-/* intrinsic void __set_PRIMASK();                                */
-/* intrinsic void __get_PRIMASK();                                */
-
-
-/* intrinsic uint32_t __REV(uint32_t value);                      */
-/* intrinsic uint32_t __REVSH(uint32_t value);                    */
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
-static __INLINE void __WFI()                      { __ASM volatile ("wfi"); }
-static __INLINE void __WFE()                      { __ASM volatile ("wfe"); }
-static __INLINE void __SEV()                      { __ASM volatile ("sev"); }
-static __INLINE void __ISB()                      { __ASM volatile ("isb"); }
-static __INLINE void __DSB()                      { __ASM volatile ("dsb"); }
-static __INLINE void __DMB()                      { __ASM volatile ("dmb"); }
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t  __get_PRIMASK(void);
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief  Return the Control Register value
-* 
-*  @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief  Reverse byte order in integer value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-/** @addtogroup CMSIS_CM0_Core_FunctionInterface CMSIS CM0 Core Function Interface
-  Core  Function Interface containing:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Reset Functions
-*/
-/*@{*/
-
-/* ##########################   NVIC functions  #################################### */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
-
-
-/**
- * @brief  Enable Interrupt in NVIC Interrupt Controller
- *
- * @param  IRQn   The positive number of the external interrupt to enable
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-/**
- * @brief  Disable the interrupt line for external interrupt specified
- * 
- * @param  IRQn   The positive number of the external interrupt to disable
- * 
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-/**
- * @brief  Read the interrupt pending bit for a device specific interrupt source
- * 
- * @param  IRQn    The number of the device specifc interrupt
- * @return         1 = interrupt pending, 0 = interrupt not pending
- *
- * Read the pending register in NVIC and return 1 if its status is pending, 
- * otherwise it returns 0
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-/**
- * @brief  Set the pending bit for an external interrupt
- * 
- * @param  IRQn    The number of the interrupt for set pending
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-/**
- * @brief  Clear the pending bit for an external interrupt
- *
- * @param  IRQn    The number of the interrupt for clear pending
- *
- * Clear the pending bit for the specified interrupt. 
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-/**
- * @brief  Set the priority for an interrupt
- *
- * @param  IRQn      The number of the interrupt for set priority
- * @param  priority  The priority to set
- *
- * Set the priority for the specified interrupt. The interrupt 
- * number can be positive to specify an external (device specific) 
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-  else {
-    NVIC->IPR[_IP_IDX(IRQn)] = (NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-/**
- * @brief  Read the priority for an interrupt
- *
- * @param  IRQn      The number of the interrupt for get priority
- * @return           The priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt 
- * number can be positive to specify an external (device specific) 
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
-  else {
-    return((uint32_t)((NVIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-
-/* ##################################    SysTick function  ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/**
- * @brief  Initialize and start the SysTick counter and its interrupt.
- *
- * @param   ticks   number of ticks between two interrupts
- * @return  1 = failed, 0 = successful
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate 
- * periodical interrupts.
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{ 
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-                                                               
-  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
-                   SysTick_CTRL_TICKINT_Msk   | 
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-
-
-
-/* ##################################    Reset function  ############################################ */
-
-/**
- * @brief  Initiate a system reset request.
- *
- * Initiate a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                                             /* Ensure completion of memory access */              
-  while(1);                                                                            /* wait until reset */
-}
-
-/*@}*/ /* end of group CMSIS_CM0_Core_FunctionInterface */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/ /* end of group CMSIS_CM0_core_definitions */
-
-#endif /* __CM0_CORE_H__ */
-
-/*lint -restore */

libcpu/arm/lpc1100/CMSIS/system_LPC11xx.c

@@ -1,450 +0,0 @@
-/**************************************************************************//**
- * @file     system_LPC11xx.c
- * @brief    CMSIS Cortex-M0 Device Peripheral Access Layer Source File
- *           for the NXP LPC11xx Device Series
- * @version  V1.00
- * @date     17. November 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#include <stdint.h>
-#include "LPC11xx.h"
-
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-
-/*--------------------- Clock Configuration ----------------------------------
-//
-// <e> Clock Configuration
-//   <e1> System Clock Setup
-//     <e2> System Oscillator Enable
-//       <o3.1> Select System Oscillator Frequency Range
-//                     <0=> 1 - 20 MHz
-//                     <1=> 15 - 25 MHz
-//     </e2>
-//     <e4> Watchdog Oscillator Enable
-//       <o5.0..4> Select Divider for Fclkana
-//                     <0=>   2 <1=>   4 <2=>   6 <3=>   8
-//                     <4=>  10 <5=>  12 <6=>  14 <7=>  16
-//                     <8=>  18 <9=>  20 <10=> 22 <11=> 24
-//                     <12=> 26 <13=> 28 <14=> 30 <15=> 32
-//                     <16=> 34 <17=> 36 <18=> 38 <19=> 40
-//                     <20=> 42 <21=> 44 <22=> 46 <23=> 48
-//                     <24=> 50 <25=> 52 <26=> 54 <27=> 56
-//                     <28=> 58 <29=> 60 <30=> 62 <31=> 64
-//       <o5.5..8> Select Watchdog Oscillator Analog Frequency (Fclkana)
-//                     <0=> Disabled
-//                     <1=> 0.5 MHz
-//                     <2=> 0.8 MHz
-//                     <3=> 1.1 MHz
-//                     <4=> 1.4 MHz
-//                     <5=> 1.6 MHz
-//                     <6=> 1.8 MHz
-//                     <7=> 2.0 MHz
-//                     <8=> 2.2 MHz
-//                     <9=> 2.4 MHz
-//                     <10=> 2.6 MHz
-//                     <11=> 2.7 MHz
-//                     <12=> 2.9 MHz
-//                     <13=> 3.1 MHz
-//                     <14=> 3.2 MHz
-//                     <15=> 3.4 MHz
-//     </e4>
-//     <o6> Select Input Clock for sys_pllclkin (Register: SYSPLLCLKSEL)
-//                     <0=> IRC Oscillator
-//                     <1=> System Oscillator
-//                     <2=> WDT Oscillator
-//                     <3=> Invalid
-//     <e7> Use System PLL
-//                     <i> F_pll = M * F_in
-//                     <i> F_in must be in the range of 10 MHz to 25 MHz
-//       <o8.0..4>   M: PLL Multiplier Selection
-//                     <1-32><#-1>
-//       <o8.5..6>   P: PLL Divider Selection
-//                     <0=> 2
-//                     <1=> 4
-//                     <2=> 8
-//                     <3=> 16
-//       <o8.7>      DIRECT: Direct CCO Clock Output Enable
-//       <o8.8>      BYPASS: PLL Bypass Enable
-//     </e7>
-//     <o9> Select Input Clock for Main clock (Register: MAINCLKSEL)
-//                     <0=> IRC Oscillator
-//                     <1=> Input Clock to System PLL
-//                     <2=> WDT Oscillator
-//                     <3=> System PLL Clock Out
-//   </e1>
-//   <o10.0..7> System AHB Divider <0-255>
-//                     <i> 0 = is disabled
-//   <o11.0>   SYS Clock Enable
-//   <o11.1>   ROM Clock Enable
-//   <o11.2>   RAM Clock Enable
-//   <o11.3>   FLASHREG Flash Register Interface Clock Enable
-//   <o11.4>   FLASHARRAY Flash Array Access Clock Enable
-//   <o11.5>   I2C Clock Enable
-//   <o11.6>   GPIO Clock Enable
-//   <o11.7>   CT16B0 Clock Enable
-//   <o11.8>   CT16B1 Clock Enable
-//   <o11.9>   CT32B0 Clock Enable
-//   <o11.10>  CT32B1 Clock Enable
-//   <o11.11>  SSP0 Clock Enable
-//   <o11.12>  UART Clock Enable
-//   <o11.13>  ADC Clock Enable
-//   <o11.15>  WDT Clock Enable
-//   <o11.16>  IOCON Clock Enable
-//   <o11.18>  SSP1 Clock Enable
-//
-//   <o12.0..7> SSP0 Clock Divider <0-255>
-//                     <i> 0 = is disabled
-//   <o13.0..7> UART Clock Divider <0-255>
-//                     <i> 0 = is disabled
-//   <o14.0..7> SSP1 Clock Divider <0-255>
-//                     <i> 0 = is disabled
-// </e>
-*/
-#define CLOCK_SETUP           1
-#define SYSCLK_SETUP          1
-#define SYSOSC_SETUP          1
-#define SYSOSCCTRL_Val        0x00000000
-#define WDTOSC_SETUP          0
-#define WDTOSCCTRL_Val        0x000000A0
-#define SYSPLLCLKSEL_Val      0x00000001
-#define SYSPLL_SETUP          1
-#define SYSPLLCTRL_Val        0x00000023
-#define MAINCLKSEL_Val        0x00000003
-#define SYSAHBCLKDIV_Val      0x00000001
-#define AHBCLKCTRL_Val        0x0001005F
-#define SSP0CLKDIV_Val        0x00000001
-#define UARTCLKDIV_Val        0x00000001
-#define SSP1CLKDIV_Val        0x00000001
-
-/*--------------------- Memory Mapping Configuration -------------------------
-//
-// <e> Memory Mapping
-//   <o1.0..1> System Memory Remap (Register: SYSMEMREMAP)
-//                     <0=> Bootloader mapped to address 0
-//                     <1=> RAM mapped to address 0
-//                     <2=> Flash mapped to address 0
-//                     <3=> Flash mapped to address 0
-// </e>
-*/
-#define MEMMAP_SETUP          0
-#define SYSMEMREMAP_Val       0x00000001
-
-/*
-//-------- <<< end of configuration section >>> ------------------------------
-*/
-
-/*----------------------------------------------------------------------------
-  Check the register settings
- *----------------------------------------------------------------------------*/
-#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
-#define CHECK_RSVD(val, mask)                     (val & mask)
-
-/* Clock Configuration -------------------------------------------------------*/
-#if (CHECK_RSVD((SYSOSCCTRL_Val),  ~0x00000003))
-   #error "SYSOSCCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((WDTOSCCTRL_Val),  ~0x000001FF))
-   #error "WDTOSCCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
-   #error "SYSPLLCLKSEL: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((SYSPLLCTRL_Val),  ~0x000001FF))
-   #error "SYSPLLCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((MAINCLKSEL_Val),  ~0x00000003))
-   #error "MAINCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
-   #error "SYSAHBCLKDIV: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((AHBCLKCTRL_Val),  ~0x0001FFFF))
-   #error "AHBCLKCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((SSP0CLKDIV_Val), 0, 255))
-   #error "SSP0CLKDIV: Value out of range!"
-#endif
-
-#if (CHECK_RANGE((UARTCLKDIV_Val), 0, 255))
-   #error "UARTCLKDIV: Value out of range!"
-#endif
-
-#if (CHECK_RANGE((SSP1CLKDIV_Val), 0, 255))
-   #error "SSP1CLKDIV: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((SYSMEMREMAP_Val), ~0x00000003))
-   #error "SYSMEMREMAP: Invalid values of reserved bits!"
-#endif
-
-
-/*----------------------------------------------------------------------------
-  DEFINES
- *----------------------------------------------------------------------------*/
-    
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define __XTAL            (12000000UL)    /* Oscillator frequency             */
-#define __SYS_OSC_CLK     (    __XTAL)    /* Main oscillator frequency        */
-#define __IRC_OSC_CLK     (12000000UL)    /* Internal RC oscillator frequency */
-
-
-#define __FREQSEL   ((WDTOSCCTRL_Val >> 5) & 0x0F)
-#define __DIVSEL   (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
-
-#if (CLOCK_SETUP)                         /* Clock Setup              */
-  #if (SYSCLK_SETUP)                      /* System Clock Setup       */
-    #if (WDTOSC_SETUP)                    /* Watchdog Oscillator Setup*/
-        #if  (__FREQSEL ==  0)
-          #define __WDT_OSC_CLK        ( 400000 / __DIVSEL)
-        #elif (__FREQSEL ==  1)
-          #define __WDT_OSC_CLK        ( 500000 / __DIVSEL)
-        #elif (__FREQSEL ==  2)
-          #define __WDT_OSC_CLK        ( 800000 / __DIVSEL)
-        #elif (__FREQSEL ==  3)
-          #define __WDT_OSC_CLK        (1100000 / __DIVSEL)
-        #elif (__FREQSEL ==  4)
-          #define __WDT_OSC_CLK        (1400000 / __DIVSEL)
-        #elif (__FREQSEL ==  5)
-          #define __WDT_OSC_CLK        (1600000 / __DIVSEL)
-        #elif (__FREQSEL ==  6)
-          #define __WDT_OSC_CLK        (1800000 / __DIVSEL)
-        #elif (__FREQSEL ==  7)
-          #define __WDT_OSC_CLK        (2000000 / __DIVSEL)
-        #elif (__FREQSEL ==  8)
-          #define __WDT_OSC_CLK        (2200000 / __DIVSEL)
-        #elif (__FREQSEL ==  9)
-          #define __WDT_OSC_CLK        (2400000 / __DIVSEL)
-        #elif (__FREQSEL == 10)
-          #define __WDT_OSC_CLK        (2600000 / __DIVSEL)
-        #elif (__FREQSEL == 11)
-          #define __WDT_OSC_CLK        (2700000 / __DIVSEL)
-        #elif (__FREQSEL == 12)
-          #define __WDT_OSC_CLK        (2900000 / __DIVSEL)
-        #elif (__FREQSEL == 13)
-          #define __WDT_OSC_CLK        (3100000 / __DIVSEL)
-        #elif (__FREQSEL == 14)
-          #define __WDT_OSC_CLK        (3200000 / __DIVSEL)
-        #else
-          #define __WDT_OSC_CLK        (3400000 / __DIVSEL)
-        #endif
-    #else
-          #define __WDT_OSC_CLK        (1600000 / 2)
-    #endif  // WDTOSC_SETUP
-
-    /* sys_pllclkin calculation */
-    #if   ((SYSPLLCLKSEL_Val & 0x03) == 0)
-      #define __SYS_PLLCLKIN           (__IRC_OSC_CLK)
-    #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
-      #define __SYS_PLLCLKIN           (__SYS_OSC_CLK)
-    #elif ((SYSPLLCLKSEL_Val & 0x03) == 2)
-      #define __SYS_PLLCLKIN           (__WDT_OSC_CLK)
-    #else
-      #define __SYS_PLLCLKIN           (0)
-    #endif
-
-    #if (SYSPLL_SETUP)                    /* System PLL Setup         */
-      #define  __SYS_PLLCLKOUT         (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
-    #else
-      #define  __SYS_PLLCLKOUT         (__SYS_PLLCLKIN * (1))
-    #endif  // SYSPLL_SETUP
-
-    /* main clock calculation */
-    #if   ((MAINCLKSEL_Val & 0x03) == 0)
-      #define __MAIN_CLOCK             (__IRC_OSC_CLK)
-    #elif ((MAINCLKSEL_Val & 0x03) == 1)
-      #define __MAIN_CLOCK             (__SYS_PLLCLKIN)
-    #elif ((MAINCLKSEL_Val & 0x03) == 2)
-      #define __MAIN_CLOCK             (__WDT_OSC_CLK)
-    #elif ((MAINCLKSEL_Val & 0x03) == 3)
-      #define __MAIN_CLOCK             (__SYS_PLLCLKOUT)
-    #else
-      #define __MAIN_CLOCK             (0)
-    #endif
-
-    #define __SYSTEM_CLOCK             (__MAIN_CLOCK / SYSAHBCLKDIV_Val)         
-
-  #else // SYSCLK_SETUP
-    #if (SYSAHBCLKDIV_Val == 0)
-      #define __SYSTEM_CLOCK           (0)
-    #else
-      #define __SYSTEM_CLOCK           (__XTAL / SYSAHBCLKDIV_Val)
-    #endif
-  #endif // SYSCLK_SETUP
-
-#else
-  #define __SYSTEM_CLOCK               (__XTAL)
-#endif  // CLOCK_SETUP 
-
-
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
-
-
-/*----------------------------------------------------------------------------
-  Clock functions
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
-{
-  uint32_t wdt_osc = 0;
-
-  /* Determine clock frequency according to clock register values             */
-  switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
-    case 0:  wdt_osc =  400000; break;
-    case 1:  wdt_osc =  500000; break;
-    case 2:  wdt_osc =  800000; break;
-    case 3:  wdt_osc = 1100000; break;
-    case 4:  wdt_osc = 1400000; break;
-    case 5:  wdt_osc = 1600000; break;
-    case 6:  wdt_osc = 1800000; break;
-    case 7:  wdt_osc = 2000000; break;
-    case 8:  wdt_osc = 2200000; break;
-    case 9:  wdt_osc = 2400000; break;
-    case 10: wdt_osc = 2600000; break;
-    case 11: wdt_osc = 2700000; break;
-    case 12: wdt_osc = 2900000; break;
-    case 13: wdt_osc = 3100000; break;
-    case 14: wdt_osc = 3200000; break;
-    case 15: wdt_osc = 3400000; break;
-  }
-  wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
- 
-  switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
-    case 0:                             /* Internal RC oscillator             */
-      SystemCoreClock = __IRC_OSC_CLK;
-      break;
-    case 1:                             /* Input Clock to System PLL          */
-      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
-          case 0:                       /* Internal RC oscillator             */
-            SystemCoreClock = __IRC_OSC_CLK;
-            break;
-          case 1:                       /* System oscillator                  */
-            SystemCoreClock = __SYS_OSC_CLK;
-            break;
-          case 2:                       /* WDT Oscillator                     */
-            SystemCoreClock = wdt_osc;
-            break;
-          case 3:                       /* Reserved                           */
-            SystemCoreClock = 0;
-            break;
-      }
-      break;
-    case 2:                             /* WDT Oscillator                     */
-      SystemCoreClock = wdt_osc;
-      break;
-    case 3:                             /* System PLL Clock Out               */
-      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
-          case 0:                       /* Internal RC oscillator             */
-            if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
-              SystemCoreClock = __IRC_OSC_CLK;
-            } else {
-              SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
-            }
-            break;
-          case 1:                       /* System oscillator                  */
-            if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
-              SystemCoreClock = __SYS_OSC_CLK;
-            } else {
-              SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
-            }
-            break;
-          case 2:                       /* WDT Oscillator                     */
-            if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
-              SystemCoreClock = wdt_osc;
-            } else {
-              SystemCoreClock = wdt_osc * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
-            }
-            break;
-          case 3:                       /* Reserved                           */
-            SystemCoreClock = 0;
-            break;
-      }
-      break;
-  }
-
-  SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;  
-
-}
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System.
- */
-void SystemInit (void)
-{
-#if (CLOCK_SETUP)                                 /* Clock Setup              */
-#if (SYSCLK_SETUP)                                /* System Clock Setup       */
-#if (SYSOSC_SETUP)                                /* System Oscillator Setup  */
-  uint32_t i;
-
-  LPC_SYSCON->PDRUNCFG     &= ~(1 << 5);          /* Power-up System Osc      */
-  LPC_SYSCON->SYSOSCCTRL    = SYSOSCCTRL_Val;
-  for (i = 0; i < 200; i++) __NOP();
-  LPC_SYSCON->SYSPLLCLKSEL  = SYSPLLCLKSEL_Val;   /* Select PLL Input         */
-  LPC_SYSCON->SYSPLLCLKUEN  = 0x01;               /* Update Clock Source      */
-  LPC_SYSCON->SYSPLLCLKUEN  = 0x00;               /* Toggle Update Register   */
-  LPC_SYSCON->SYSPLLCLKUEN  = 0x01;
-  while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01));     /* Wait Until Updated       */
-#if (SYSPLL_SETUP)                                /* System PLL Setup         */
-  LPC_SYSCON->SYSPLLCTRL    = SYSPLLCTRL_Val;
-  LPC_SYSCON->PDRUNCFG     &= ~(1 << 7);          /* Power-up SYSPLL          */
-  while (!(LPC_SYSCON->SYSPLLSTAT & 0x01));	      /* Wait Until PLL Locked    */
-#endif
-#endif
-#if (WDTOSC_SETUP)                                /* Watchdog Oscillator Setup*/
-  LPC_SYSCON->WDTOSCCTRL    = WDTOSCCTRL_Val;
-  LPC_SYSCON->PDRUNCFG     &= ~(1 << 6);          /* Power-up WDT Clock       */
-#endif
-  LPC_SYSCON->MAINCLKSEL    = MAINCLKSEL_Val;     /* Select PLL Clock Output  */
-  LPC_SYSCON->MAINCLKUEN    = 0x01;               /* Update MCLK Clock Source */
-  LPC_SYSCON->MAINCLKUEN    = 0x00;               /* Toggle Update Register   */
-  LPC_SYSCON->MAINCLKUEN    = 0x01;
-  while (!(LPC_SYSCON->MAINCLKUEN & 0x01));       /* Wait Until Updated       */
-#endif
-
-  LPC_SYSCON->SYSAHBCLKDIV  = SYSAHBCLKDIV_Val;
-  LPC_SYSCON->SYSAHBCLKCTRL = AHBCLKCTRL_Val;
-  LPC_SYSCON->SSP0CLKDIV    = SSP0CLKDIV_Val;
-  LPC_SYSCON->UARTCLKDIV    = UARTCLKDIV_Val;
-  LPC_SYSCON->SSP1CLKDIV    = SSP1CLKDIV_Val;
-#endif
-
-
-#if (MEMMAP_SETUP || MEMMAP_INIT)       /* Memory Mapping Setup               */
-  LPC_SYSCON->SYSMEMREMAP = SYSMEMREMAP_Val;
-#endif
-}

libcpu/arm/lpc1100/CMSIS/system_LPC11xx.h

@@ -1,64 +0,0 @@
-/**************************************************************************//**
- * @file     system_LPC11xx.h
- * @brief    CMSIS Cortex-M0 Device Peripheral Access Layer Header File
- *           for the NXP LPC11xx Device Series
- * @version  V1.00
- * @date     17. November 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC11xx_H
-#define __SYSTEM_LPC11xx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock 
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC11x_H */

libcpu/arm/lpc1100/context_rvds.S

@@ -1,175 +0,0 @@
-;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2009, RT-Thread Development Team
-; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
-; *
-; * Change Logs:
-; * Date           Author       Notes
-; * 2010-01-25     Bernard      first version
-; */
-
-;/**
-; * @addtogroup LPC1100
-; */
-;/*@{*/
-
-NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
-NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
-NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
-
-	AREA |.text|, CODE, READONLY, ALIGN=2
-	THUMB
-	REQUIRE8
-	PRESERVE8
-
-	IMPORT rt_thread_switch_interrupt_flag
-	IMPORT rt_interrupt_from_thread
-	IMPORT rt_interrupt_to_thread
-
-;/*
-; * rt_base_t rt_hw_interrupt_disable();
-; */
-rt_hw_interrupt_disable    PROC
-	EXPORT  rt_hw_interrupt_disable
-	MRS		r0, PRIMASK
-	CPSID   I
-	BX		LR
-	ENDP
-
-;/*
-; * void rt_hw_interrupt_enable(rt_base_t level);
-; */
-rt_hw_interrupt_enable    PROC
-	EXPORT  rt_hw_interrupt_enable
-	MSR		PRIMASK, r0
-	BX      LR
-	ENDP
-
-;/*
-; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
-; * r0 --> from
-; * r1 --> to
-; */
-rt_hw_context_switch_interrupt
-	EXPORT rt_hw_context_switch_interrupt
-rt_hw_context_switch    PROC
-	EXPORT rt_hw_context_switch
-
-	; set rt_thread_switch_interrupt_flag to 1
-	LDR 	r2, =rt_thread_switch_interrupt_flag
-	LDR 	r3, [r2]
-	CMP 	r3, #1
-	BEQ 	_reswitch
-	MOVS 	r3, #0x1
-	STR 	r3, [r2]
-
-	LDR 	r2, =rt_interrupt_from_thread	; set rt_interrupt_from_thread
-	STR 	r0, [r2]
-
-_reswitch
-	LDR 	r2, =rt_interrupt_to_thread		; set rt_interrupt_to_thread
-	STR 	r1, [r2]
-
-    LDR     r0, =NVIC_INT_CTRL      		; trigger the PendSV exception (causes context switch)
-    LDR     r1, =NVIC_PENDSVSET
-	STR     r1, [r0]
-	BX      LR
-	ENDP
-
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
-; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
-rt_hw_pend_sv	PROC
-	EXPORT rt_hw_pend_sv
-
-	; disable interrupt to protect context switch
-	MRS		r2, PRIMASK
-	CPSID   I
-
-	; get rt_thread_switch_interrupt_flag
-	LDR		r0, =rt_thread_switch_interrupt_flag
-	LDR		r1, [r0]
-	CMP		r1, #0x00
-	BEQ		pendsv_exit				; pendsv already handled
-
-	; clear rt_thread_switch_interrupt_flag to 0
-	MOVS	r1, #0x00
-	STR		r1, [r0]
-
-	LDR		r0, =rt_interrupt_from_thread
-	LDR		r1, [r0]
-	CMP		r1, #0x00
-	BEQ		swtich_to_thread    	; skip register save at the first time
-
-	MRS     r1, psp                 ; get from thread stack pointer
-	SUBS	r1, r1, #0x10
-	LDR		r0, [r0]
-	STR		r1, [r0]				; update from thread stack pointer
-	STMIA	r1!, {r4 - r7}			; push r4 - r7 register
-
-swtich_to_thread
-	LDR		r1, =rt_interrupt_to_thread
-	LDR		r1, [r1]
-	LDR		r1, [r1]				; load thread stack pointer
-
-	LDMIA	r1!, {r4 - r7}			; pop r4 - r7 register
-	MSR		psp, r1					; update stack pointer
-
-pendsv_exit
-	; restore interrupt
-	MSR		PRIMASK, r2
-
-	MOVS	r0, #0x04
-	RSBS	r0, #0
-	BX		r0
-	ENDP
-
-;/*
-; * void rt_hw_context_switch_to(rt_uint32 to);
-; * r0 --> to
-; * this fucntion is used to perform the first thread switch
-; */
-rt_hw_context_switch_to    PROC
-	EXPORT rt_hw_context_switch_to
-	; set to thread
-	LDR		r1, =rt_interrupt_to_thread
-	STR		r0, [r1]
-
-	; set from thread to 0
-	LDR		r1, =rt_interrupt_from_thread
-	MOVS	r0, #0x0
-	STR		r0, [r1]
-
-	; set interrupt flag to 1
-	LDR 	r1, =rt_thread_switch_interrupt_flag
-	MOVS 	r0, #1
-	STR 	r0, [r1]
-
-	; set the PendSV exception priority
-    ; LDR     r0, =NVIC_SYSPRI2
-    ; LDR     r1, =NVIC_PENDSV_PRI
-    ; STR     r1, [r0]
-
-	; trigger the PendSV exception (causes context switch)
-    LDR     r0, =NVIC_INT_CTRL
-    LDR     r1, =NVIC_PENDSVSET
-    STR     r1, [r0]
-
-	; enable interrupts at processor level
-    CPSIE   I
-
-	; never reach here!
-	ENDP
-
-; compatible with old version
-rt_hw_interrupt_thread_switch PROC
-	EXPORT rt_hw_interrupt_thread_switch
-	BX		lr
-	ENDP
-
-	END

libcpu/arm/lpc1100/cpu.c

@@ -1,42 +0,0 @@
-/*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-25     Bernard      first version
- */
-
-#include <rtthread.h>
-
-/**
- * @addtogroup LPC1100
- */
-/*@{*/
-
-/**
- * reset cpu by dog's time-out
- *
- */
-void rt_hw_cpu_reset()
-{
-	/*NOTREACHED*/
-}
-
-/**
- *  shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown()
-{
-	rt_kprintf("shutdown...\n");
-
-	RT_ASSERT(0);
-}
-
-/*@}*/

libcpu/arm/lpc1100/fault.c

@@ -1,47 +0,0 @@
-/*
- * File      : fault.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-25     Bernard      first version
- */
-#include <rtthread.h>
-
-struct stack_contex
-{
-	rt_uint32_t r0;
-	rt_uint32_t r1;
-	rt_uint32_t r2;
-	rt_uint32_t r3;
-	rt_uint32_t r12;
-	rt_uint32_t lr;
-	rt_uint32_t pc;
-	rt_uint32_t psr;
-};
-
-extern void rt_hw_interrupt_thread_switch(void);
-extern long list_thread(void);
-extern rt_thread_t rt_current_thread;
-void rt_hw_hard_fault_exception(struct stack_contex* contex)
-{
-	rt_kprintf("psr: 0x%08x\n", contex->psr);
-	rt_kprintf(" pc: 0x%08x\n", contex->pc);
-	rt_kprintf(" lr: 0x%08x\n", contex->lr);
-	rt_kprintf("r12: 0x%08x\n", contex->r12);
-	rt_kprintf("r03: 0x%08x\n", contex->r3);
-	rt_kprintf("r02: 0x%08x\n", contex->r2);
-	rt_kprintf("r01: 0x%08x\n", contex->r1);
-	rt_kprintf("r00: 0x%08x\n", contex->r0);
-
-	rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name);
-#ifdef RT_USING_FINSH
-	list_thread();
-#endif
-	while (1);
-}

libcpu/arm/lpc1100/fault_rvds.S

@@ -1,32 +0,0 @@
-;/*
-; * File      : fault_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
-; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
-; *
-; * Change Logs:
-; * Date           Author       Notes
-; * 2010-01-25     Bernard      first version
-; */
-
-    AREA |.text|, CODE, READONLY, ALIGN=2
-    THUMB
-    REQUIRE8
-    PRESERVE8
-
-    IMPORT rt_hw_hard_fault_exception
-
-rt_hw_hard_fault    PROC
-    EXPORT rt_hw_hard_fault
-
-    ; get current context
-    MRS     r0, psp                 ; get fault thread stack pointer
-    PUSH    {lr}
-    BL      rt_hw_hard_fault_exception
-    POP     {pc}
-    ENDP
-
-    END

libcpu/arm/lpc1100/interrupt.c

@@ -1,21 +0,0 @@
-/*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-25     Bernard      first version
- */
-
-#include <rtthread.h>
-
-/* exception and interrupt handler table */
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint8_t rt_thread_switch_interrupt_flag;
-
-/*@}*/

libcpu/arm/lpc1100/stack.c

@@ -1,54 +0,0 @@
-/*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-01-25     Bernard      first version
- */
-#include <rtthread.h>
-
-/**
- * @addtogroup LPC1100
- */
-/*@{*/
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-	rt_uint8_t *stack_addr, void *texit)
-{
-	unsigned long *stk;
-
-	stk 	 = (unsigned long *)stack_addr;
-	*(stk)   = 0x01000000L;					/* PSR */
-	*(--stk) = (unsigned long)tentry;		/* entry point, pc */
-	*(--stk) = (unsigned long)texit;		/* lr */
-	*(--stk) = 0;							/* r12 */
-	*(--stk) = 0;							/* r3 */
-	*(--stk) = 0;							/* r2 */
-	*(--stk) = 0;							/* r1 */
-	*(--stk) = (unsigned long)parameter;	/* r0 : argument */
-	*(--stk) = 0;							/* r7 */
-	*(--stk) = 0;							/* r6 */
-	*(--stk) = 0;							/* r5 */
-	*(--stk) = 0;							/* r4 */
-
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
-}
-
-/*@}*/

libcpu/arm/lpc1100/start_rvds.S

@@ -1,252 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC11xx.s
-; * @purpose: CMSIS Cortex-M0 Core Device Startup File 
-; *           for the NXP LPC11xx Device Series 
-; * @version: V1.0
-; * @date:    25. Nov. 2008
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2008 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
-; * processor based microcontrollers.  This file can be freely distributed 
-; * within development tools that are supporting such ARM based processors. 
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000100
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-				IMPORT rt_hw_hard_fault
-				IMPORT rt_hw_pend_sv
-				IMPORT rt_hw_timer_handler
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     rt_hw_hard_fault          ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     rt_hw_pend_sv             ; PendSV Handler
-                DCD     rt_hw_timer_handler       ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WAKEUP_IRQHandler         ; 15 wakeup sources for all the
-                DCD     WAKEUP_IRQHandler         ; I/O pins starting from PIO0 (0:11)
-                DCD     WAKEUP_IRQHandler         ; all 40 are routed to the same ISR                       
-                DCD     WAKEUP_IRQHandler                         
-                DCD     WAKEUP_IRQHandler                        
-                DCD     WAKEUP_IRQHandler
-                DCD     WAKEUP_IRQHandler
-                DCD     WAKEUP_IRQHandler                       
-                DCD     WAKEUP_IRQHandler                         
-                DCD     WAKEUP_IRQHandler                        
-                DCD     WAKEUP_IRQHandler
-                DCD     WAKEUP_IRQHandler
-                DCD     WAKEUP_IRQHandler         ; PIO1 (0:11)
-                DCD     CAN_IRQHandler            ; CAN                
-                DCD     SSP1_IRQHandler           ; SSP1               
-                DCD     I2C_IRQHandler            ; I2C
-                DCD     TIMER16_0_IRQHandler      ; 16-bit Timer0
-                DCD     TIMER16_1_IRQHandler      ; 16-bit Timer1
-                DCD     TIMER32_0_IRQHandler      ; 32-bit Timer0
-                DCD     TIMER32_1_IRQHandler      ; 32-bit Timer1
-                DCD     SSP0_IRQHandler           ; SSP0
-                DCD     UART_IRQHandler           ; UART
-                DCD     USB_IRQHandler            ; USB IRQ
-                DCD     USB_FIQHandler            ; USB FIQ
-                DCD     ADC_IRQHandler            ; A/D Converter
-                DCD     WDT_IRQHandler            ; Watchdog timer
-                DCD     BOD_IRQHandler            ; Brown Out Detect
-                DCD     FMC_IRQHandler            ; IP2111 Flash Memory Controller
-                DCD     PIOINT3_IRQHandler        ; PIO INT3
-                DCD     PIOINT2_IRQHandler        ; PIO INT2
-                DCD     PIOINT1_IRQHandler        ; PIO INT1
-                DCD     PIOINT0_IRQHandler        ; PIO INT0
-
-
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)                
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WAKEUP_IRQHandler         [WEAK]
-				EXPORT  CAN_IRQHandler            [WEAK]
-				EXPORT  SSP1_IRQHandler           [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  TIMER16_0_IRQHandler      [WEAK]
-                EXPORT  TIMER16_1_IRQHandler      [WEAK]
-                EXPORT  TIMER32_0_IRQHandler      [WEAK]
-                EXPORT  TIMER32_1_IRQHandler      [WEAK]
-                EXPORT  SSP0_IRQHandler           [WEAK]
-                EXPORT  UART_IRQHandler           [WEAK]
-
-                EXPORT  USB_IRQHandler            [WEAK]
-                EXPORT  USB_FIQHandler            [WEAK]
-                EXPORT  ADC_IRQHandler            [WEAK]
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  BOD_IRQHandler            [WEAK]
-                EXPORT  FMC_IRQHandler            [WEAK]
-                EXPORT  PIOINT3_IRQHandler        [WEAK]
-                EXPORT  PIOINT2_IRQHandler        [WEAK]
-                EXPORT	PIOINT1_IRQHandler        [WEAK]
-                EXPORT	PIOINT0_IRQHandler        [WEAK]
-
-
-WAKEUP_IRQHandler
-CAN_IRQHandler
-SSP1_IRQHandler
-I2C_IRQHandler
-TIMER16_0_IRQHandler
-TIMER16_1_IRQHandler
-TIMER32_0_IRQHandler
-TIMER32_1_IRQHandler
-SSP0_IRQHandler
-UART_IRQHandler
-USB_IRQHandler
-USB_FIQHandler
-ADC_IRQHandler
-WDT_IRQHandler
-BOD_IRQHandler
-FMC_IRQHandler
-PIOINT3_IRQHandler  
-PIOINT2_IRQHandler 
-PIOINT1_IRQHandler
-PIOINT0_IRQHandler
-
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-                
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-                
-                ELSE
-                
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-__user_initial_stackheap
-
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-
-                ALIGN
-
-                ENDIF
-
-
-                END