sync branch rt-smart. (#6641)

* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>

.github/workflows/action.yml

@@ -38,7 +38,7 @@ jobs:
          - {RTT_BSP: "apm32/apm32f103xe-minibroard", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "ft2004", RTT_TOOL_CHAIN: "sourcery-arm"}
+        #  - {RTT_BSP: "ft2004", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "at91/at91sam9g45", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "at91/at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"}
@@ -108,7 +108,6 @@ jobs:
          - {RTT_BSP: "nrf5x/nrf52833", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "nrf5x/nrf52840", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm"}
-         - {RTT_BSP: "qemu-vexpress-gemini", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "sam7x", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f072-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f091-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}

bsp/allwinner/README.md

@@ -0,0 +1,3 @@
+# allwinner-bsp
+
+针对全志芯片的rt-smart bsp，包括D1/D1s（RISC-V64）

bsp/qemu-vexpress-gemini/.config → bsp/allwinner/d1/.config

@@ -6,32 +6,26 @@
 #
 # RT-Thread Kernel
 #
-CONFIG_RT_NAME_MAX=6
+CONFIG_RT_NAME_MAX=20
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+CONFIG_RT_USING_SMART=y
 # CONFIG_RT_USING_SMP is not set
-CONFIG_RT_ALIGN_SIZE=4
+CONFIG_RT_ALIGN_SIZE=8
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
-CONFIG_RT_THREAD_PRIORITY_32=y
-# CONFIG_RT_THREAD_PRIORITY_256 is not set
-CONFIG_RT_THREAD_PRIORITY_MAX=32
-CONFIG_RT_TICK_PER_SECOND=1000
-CONFIG_RT_USING_OVERFLOW_CHECK=y
+# CONFIG_RT_THREAD_PRIORITY_32 is not set
+CONFIG_RT_THREAD_PRIORITY_256=y
+CONFIG_RT_THREAD_PRIORITY_MAX=256
+CONFIG_RT_TICK_PER_SECOND=100
+# CONFIG_RT_USING_OVERFLOW_CHECK is not set
 CONFIG_RT_USING_HOOK=y
-CONFIG_RT_HOOK_USING_FUNC_PTR=y
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
-CONFIG_IDLE_THREAD_STACK_SIZE=512
-# CONFIG_RT_USING_TIMER_SOFT is not set
-
-#
-# kservice optimization
-#
-# CONFIG_RT_KSERVICE_USING_STDLIB is not set
-# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
-# CONFIG_RT_USING_TINY_FFS is not set
-# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+CONFIG_IDLE_THREAD_STACK_SIZE=16384
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=16384
 CONFIG_RT_DEBUG=y
-CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_COLOR is not set
 # CONFIG_RT_DEBUG_INIT_CONFIG is not set
 # CONFIG_RT_DEBUG_THREAD_CONFIG is not set
 # CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
@@ -57,16 +51,11 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
 # Memory Management
 #
 CONFIG_RT_USING_MEMPOOL=y
-CONFIG_RT_USING_SMALL_MEM=y
-# CONFIG_RT_USING_SLAB is not set
 # CONFIG_RT_USING_MEMHEAP is not set
-CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
-# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
-# CONFIG_RT_USING_SLAB_AS_HEAP is not set
-# CONFIG_RT_USING_USERHEAP is not set
 # CONFIG_RT_USING_NOHEAP is not set
-# CONFIG_RT_USING_MEMTRACE is not set
-# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMTRACE=y
 CONFIG_RT_USING_HEAP=y
 
 #
@@ -74,131 +63,263 @@ CONFIG_RT_USING_HEAP=y
 #
 CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_DEVICE_OPS is not set
-CONFIG_RT_USING_INTERRUPT_INFO=y
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
-CONFIG_RT_CONSOLEBUF_SIZE=128
-CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-CONFIG_RT_VER_NUM=0x40101
-CONFIG_ARCH_ARM=y
-CONFIG_RT_USING_CPU_FFS=y
-CONFIG_ARCH_ARM_CORTEX_A=y
-# CONFIG_RT_SMP_AUTO_BOOT is not set
-CONFIG_RT_USING_GIC_V2=y
-# CONFIG_RT_USING_GIC_V3 is not set
-CONFIG_ARCH_ARM_CORTEX_A9=y
+CONFIG_RT_CONSOLEBUF_SIZE=256
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
+CONFIG_RT_VER_NUM=0x50000
+CONFIG_ARCH_CPU_64BIT=y
+CONFIG_RT_USING_CACHE=y
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+CONFIG_ARCH_MM_MMU=y
+CONFIG_RT_USING_USERSPACE=y
+CONFIG_KERNEL_VADDR_START=0x150000000
+CONFIG_PV_OFFSET=0x0
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV64=y
 
 #
 # RT-Thread Components
 #
 CONFIG_RT_USING_COMPONENTS_INIT=y
-# CONFIG_RT_USING_USER_MAIN is not set
-# CONFIG_RT_USING_LEGACY is not set
-CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=16384
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
 CONFIG_RT_USING_FINSH=y
+CONFIG_RT_USING_MSH=y
 CONFIG_FINSH_USING_MSH=y
 CONFIG_FINSH_THREAD_NAME="tshell"
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
 CONFIG_FINSH_USING_SYMTAB=y
-CONFIG_FINSH_CMD_SIZE=80
-CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
 CONFIG_FINSH_USING_DESCRIPTION=y
 # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=8192
+CONFIG_FINSH_CMD_SIZE=80
 # CONFIG_FINSH_USING_AUTH is not set
 CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
 CONFIG_RT_USING_DFS=y
-CONFIG_DFS_USING_POSIX=y
 CONFIG_DFS_USING_WORKDIR=y
-CONFIG_DFS_FILESYSTEMS_MAX=2
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
-CONFIG_DFS_FD_MAX=4
+CONFIG_DFS_FILESYSTEMS_MAX=8
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+CONFIG_DFS_FD_MAX=32
 # CONFIG_RT_USING_DFS_MNTTABLE is not set
-# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=8
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
 CONFIG_RT_USING_DFS_DEVFS=y
-# CONFIG_RT_USING_DFS_ROMFS is not set
+CONFIG_RT_USING_DFS_ROMFS=y
+# CONFIG_RT_USING_DFS_CROMFS is not set
 # CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_FAL is not set
-# CONFIG_RT_USING_LWP is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS_NFS is not set
 
 #
 # Device Drivers
 #
 CONFIG_RT_USING_DEVICE_IPC=y
-# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
 CONFIG_RT_USING_SERIAL=y
-CONFIG_RT_USING_SERIAL_V1=y
-# CONFIG_RT_USING_SERIAL_V2 is not set
 CONFIG_RT_SERIAL_USING_DMA=y
 CONFIG_RT_SERIAL_RB_BUFSZ=64
+CONFIG_RT_USING_TTY=y
+# CONFIG_RT_TTY_DEBUG is not set
 # CONFIG_RT_USING_CAN is not set
-# CONFIG_RT_USING_HWTIMER is not set
+CONFIG_RT_USING_HWTIMER=y
 # CONFIG_RT_USING_CPUTIME is not set
-# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_I2C_DEBUG is not set
+CONFIG_RT_USING_I2C_BITOPS=y
+# CONFIG_RT_I2C_BITOPS_DEBUG is not set
 # CONFIG_RT_USING_PHY is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
-# CONFIG_RT_USING_PWM is not set
+CONFIG_RT_USING_NULL=y
+CONFIG_RT_USING_ZERO=y
+CONFIG_RT_USING_RANDOM=y
+CONFIG_RT_USING_PWM=y
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
-# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_FDT is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 # CONFIG_RT_USING_SPI is not set
-# CONFIG_RT_USING_WDT is not set
+CONFIG_RT_USING_WDT=y
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
-# CONFIG_RT_USING_TOUCH is not set
+CONFIG_RT_USING_TOUCH=y
+# CONFIG_RT_USING_LCD is not set
 # CONFIG_RT_USING_HWCRYPTO is not set
 # CONFIG_RT_USING_PULSE_ENCODER is not set
 # CONFIG_RT_USING_INPUT_CAPTURE is not set
 # CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
 
 #
 # Using USB
 #
-# CONFIG_RT_USING_USB is not set
 # CONFIG_RT_USING_USB_HOST is not set
 # CONFIG_RT_USING_USB_DEVICE is not set
 
 #
-# C/C++ and POSIX layer
-#
-CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
-
-#
-# POSIX (Portable Operating System Interface) layer
+# POSIX layer and C standard library
 #
-# CONFIG_RT_USING_POSIX_FS is not set
-CONFIG_RT_USING_POSIX_DELAY=y
-CONFIG_RT_USING_POSIX_CLOCK=y
-# CONFIG_RT_USING_POSIX_TIMER is not set
-CONFIG_RT_USING_PTHREADS=y
-CONFIG_PTHREAD_NUM_MAX=8
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_NEWLIB is not set
+CONFIG_RT_USING_MUSL=y
+# CONFIG_RT_USING_MLIB is not set
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_GETLINE is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+CONFIG_RT_USING_POSIX_CLOCKTIME=y
 # CONFIG_RT_USING_MODULE is not set
 
 #
-# Interprocess Communication (IPC)
+# Network
 #
-# CONFIG_RT_USING_POSIX_PIPE is not set
-CONFIG_RT_USING_POSIX_MESSAGE_QUEUE=y
-CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y
 
 #
-# Socket is in the 'Network' category
+# Socket abstraction layer
+#
+CONFIG_RT_USING_SAL=y
+
+#
+# protocol stack implement
+#
+CONFIG_SAL_USING_LWIP=y
+CONFIG_SAL_USING_POSIX=y
+# CONFIG_SAL_USING_AF_UNIX is not set
+
+#
+# Network interface device
+#
+CONFIG_RT_USING_NETDEV=y
+CONFIG_NETDEV_USING_IFCONFIG=y
+CONFIG_NETDEV_USING_PING=y
+CONFIG_NETDEV_USING_NETSTAT=y
+CONFIG_NETDEV_USING_AUTO_DEFAULT=y
+# CONFIG_NETDEV_USING_IPV6 is not set
+CONFIG_NETDEV_IPV4=1
+CONFIG_NETDEV_IPV6=0
+# CONFIG_NETDEV_IPV6_SCOPES is not set
+
+#
+# light weight TCP/IP stack
+#
+CONFIG_RT_USING_LWIP=y
+# CONFIG_RT_USING_LWIP141 is not set
+# CONFIG_RT_USING_LWIP202 is not set
+CONFIG_RT_USING_LWIP212=y
+# CONFIG_RT_USING_LWIP_IPV6 is not set
+CONFIG_RT_LWIP_MEM_ALIGNMENT=4
+CONFIG_RT_LWIP_IGMP=y
+CONFIG_RT_LWIP_ICMP=y
+# CONFIG_RT_LWIP_SNMP is not set
+CONFIG_RT_LWIP_DNS=y
+CONFIG_RT_LWIP_DHCP=y
+CONFIG_IP_SOF_BROADCAST=1
+CONFIG_IP_SOF_BROADCAST_RECV=1
+
+#
+# Static IPv4 Address
+#
+CONFIG_RT_LWIP_IPADDR="192.168.1.30"
+CONFIG_RT_LWIP_GWADDR="192.168.1.1"
+CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
+CONFIG_RT_LWIP_UDP=y
+CONFIG_RT_LWIP_TCP=y
+CONFIG_RT_LWIP_RAW=y
+# CONFIG_RT_LWIP_PPP is not set
+CONFIG_RT_MEMP_NUM_NETCONN=8
+CONFIG_RT_MEMP_NUM_TCPIP_MSG_API=16
+CONFIG_RT_MEMP_NUM_TCPIP_MSG_INPKT=16
+CONFIG_RT_LWIP_PBUF_NUM=16
+CONFIG_RT_LWIP_PBUF_STRUCT_NUM=16
+CONFIG_RT_LWIP_NETBUF_NUM=16
+CONFIG_RT_LWIP_RAW_PCB_NUM=4
+CONFIG_RT_LWIP_UDP_PCB_NUM=4
+CONFIG_RT_UDP_RECVMBOX_SIZE=16
+CONFIG_RT_RECV_BUFSIZE_DEFAULT=64
+CONFIG_RT_LWIP_TCP_PCB_NUM=4
+CONFIG_RT_LWIP_TCP_SEG_NUM=40
+CONFIG_RT_LWIP_TCP_SND_BUF=8196
+CONFIG_RT_LWIP_TCP_WND=8196
+CONFIG_RT_TCP_RECVMBOX_SIZE=16
+CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
+CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
+CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=8192
+# CONFIG_LWIP_NO_RX_THREAD is not set
+# CONFIG_LWIP_NO_TX_THREAD is not set
+CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
+CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=8192
+CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
+CONFIG_RT_LWIP_REASSEMBLY_FRAG=y
+CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
+CONFIG_LWIP_NETIF_LINK_CALLBACK=1
+CONFIG_SO_REUSE=1
+CONFIG_LWIP_SO_RCVTIMEO=1
+CONFIG_LWIP_SO_SNDTIMEO=1
+CONFIG_LWIP_SO_RCVBUF=1
+CONFIG_LWIP_SO_LINGER=0
+# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
+CONFIG_LWIP_NETIF_LOOPBACK=0
+# CONFIG_RT_LWIP_STATS is not set
+# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
+CONFIG_RT_LWIP_USING_PING=y
+# CONFIG_RT_LWIP_DEBUG is not set
+
+#
+# AT commands
 #
-# CONFIG_RT_USING_CPLUSPLUS is not set
+# CONFIG_RT_USING_AT is not set
+# CONFIG_LWIP_USING_DHCPD is not set
 
 #
-# Network
+# VBUS(Virtual Software BUS)
 #
-# CONFIG_RT_USING_SAL is not set
-# CONFIG_RT_USING_NETDEV is not set
-# CONFIG_RT_USING_LWIP is not set
-# CONFIG_RT_USING_AT is not set
+# CONFIG_RT_USING_VBUS is not set
 
 #
 # Utilities
@@ -206,23 +327,15 @@ CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
-# CONFIG_RT_USING_VAR_EXPORT is not set
 # CONFIG_RT_USING_RT_LINK is not set
-CONFIG_RT_USING_VBUS=y
-# CONFIG_RT_USING_VBUS_RFS is not set
-# CONFIG_RT_USING_VBUS_RSHELL is not set
-CONFIG_RT_VBUS_USING_TESTS=y
-CONFIG__RT_VBUS_RING_BASE=0x6f800000
-CONFIG__RT_VBUS_RING_SZ=2097152
-CONFIG_RT_VBUS_GUEST_VIRQ=14
-CONFIG_RT_VBUS_HOST_VIRQ=15
-CONFIG_RT_VBUS_SHELL_DEV_NAME="vbser0"
-CONFIG_RT_VBUS_RFS_DEV_NAME="rfs"
-
-#
-# RT-Thread Utestcases
-#
-# CONFIG_RT_USING_UTESTCASES is not set
+CONFIG_RT_USING_LWP=y
+CONFIG_RT_LWP_MAX_NR=30
+CONFIG_LWP_TASK_STACK_SIZE=16384
+CONFIG_RT_CH_MSG_MAX_NR=1024
+CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
+CONFIG_LWP_TID_MAX_NR=64
+CONFIG_RT_LWP_SHM_MAX_NR=64
+# CONFIG_LWP_UNIX98_PTY is not set
 
 #
 # RT-Thread online packages
@@ -396,7 +509,6 @@ CONFIG_RT_VBUS_RFS_DEV_NAME="rfs"
 # CONFIG_PKG_USING_VT100 is not set
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_GUIENGINE is not set
-# CONFIG_PKG_USING_PERSIMMON is not set
 
 #
 # tools packages
@@ -444,6 +556,7 @@ CONFIG_RT_VBUS_RFS_DEV_NAME="rfs"
 # CONFIG_PKG_USING_HASH_MATCH is not set
 # CONFIG_PKG_USING_FIRE_PID_CURVE is not set
 # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
 
 #
 # system packages
@@ -479,7 +592,6 @@ CONFIG_RT_VBUS_RFS_DEV_NAME="rfs"
 # CONFIG_PKG_USING_UC_CLK is not set
 # CONFIG_PKG_USING_UC_COMMON is not set
 # CONFIG_PKG_USING_UC_MODBUS is not set
-# CONFIG_PKG_USING_RTDUINO is not set
 # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
@@ -566,6 +678,7 @@ CONFIG_RT_VBUS_RFS_DEV_NAME="rfs"
 # CONFIG_PKG_USING_BEEP is not set
 # CONFIG_PKG_USING_EASYBLINK is not set
 # CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
 # CONFIG_PKG_USING_CAN_YMODEM is not set
 # CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
 # CONFIG_PKG_USING_QLED is not set
@@ -682,61 +795,94 @@ CONFIG_RT_VBUS_RFS_DEV_NAME="rfs"
 # CONFIG_PKG_USING_QPARAM is not set
 
 #
-# Privated Packages of RealThread
-#
-# CONFIG_PKG_USING_CODEC is not set
-# CONFIG_PKG_USING_PLAYER is not set
-# CONFIG_PKG_USING_MPLAYER is not set
-# CONFIG_PKG_USING_PERSIMMON_SRC is not set
-# CONFIG_PKG_USING_JS_PERSIMMON is not set
-# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
-
-#
-# Network Utilities
-#
-# CONFIG_PKG_USING_WICED is not set
-# CONFIG_PKG_USING_CLOUDSDK is not set
-# CONFIG_PKG_USING_POWER_MANAGER is not set
-# CONFIG_PKG_USING_RT_OTA is not set
-# CONFIG_PKG_USING_RTINSIGHT is not set
-# CONFIG_PKG_USING_SMARTCONFIG is not set
-# CONFIG_PKG_USING_RTX is not set
-# CONFIG_RT_USING_TESTCASE is not set
-# CONFIG_PKG_USING_NGHTTP2 is not set
-# CONFIG_PKG_USING_AVS is not set
-# CONFIG_PKG_USING_ALI_LINKKIT is not set
-# CONFIG_PKG_USING_STS is not set
-# CONFIG_PKG_USING_DLMS is not set
-# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
-# CONFIG_PKG_USING_ZBAR is not set
-# CONFIG_PKG_USING_MCF is not set
-# CONFIG_PKG_USING_URPC is not set
-# CONFIG_PKG_USING_DCM is not set
-# CONFIG_PKG_USING_EMQ is not set
-# CONFIG_PKG_USING_CFGM is not set
-# CONFIG_PKG_USING_RT_CMSIS_DAP is not set
-# CONFIG_PKG_USING_SMODULE is not set
-# CONFIG_PKG_USING_SNFD is not set
-# CONFIG_PKG_USING_UDBD is not set
-# CONFIG_PKG_USING_BENCHMARK is not set
-# CONFIG_PKG_USING_UBJSON is not set
-# CONFIG_PKG_USING_DATATYPE is not set
-# CONFIG_PKG_USING_FASTFS is not set
-# CONFIG_PKG_USING_RIL is not set
-# CONFIG_PKG_USING_WATCH_DCM_SVC is not set
-# CONFIG_PKG_USING_WATCH_APP_FWK is not set
-# CONFIG_PKG_USING_GUI_TEST is not set
-# CONFIG_PKG_USING_PMEM is not set
-# CONFIG_PKG_USING_LWRDP is not set
-# CONFIG_PKG_USING_MASAN is not set
-# CONFIG_PKG_USING_BSDIFF_LIB is not set
-# CONFIG_PKG_USING_PRC_DIFF is not set
-
-#
-# RT-Thread Smart
-#
-# CONFIG_PKG_USING_UKERNEL is not set
-# CONFIG_PKG_USING_TRACE_AGENT is not set
-CONFIG_SOC_VEXPRESS_GEMINI=y
-# CONFIG_RT_USING_UART0 is not set
-CONFIG_RT_USING_UART1=y
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Sensor libraries
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+
+#
+# Display libraries
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+
+#
+# Timing libraries
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Project libraries
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+CONFIG_BOARD_allwinnerd1=y
+CONFIG_ENABLE_FPU=y
+# CONFIG_RT_USING_USERSPACE_32BIT_LIMIT is not set
+CONFIG___STACKSIZE__=16384
+
+#
+# General Drivers Configuration
+#
+
+#
+# General Purpose UARTs
+#
+# CONFIG_BSP_USING_UART1 is not set
+CONFIG_BSP_USING_WDT=y
+CONFIG_BSP_USING_RTC=y
+CONFIG_RT_USING_SUNXI_HAL=y
+
+#
+# UART Devices
+#
+CONFIG_DRIVERS_UART=y
+# CONFIG_HAL_TEST_UART is not set
+# CONFIG_SUNXI_UART_SUPPORT_POLL is not set
+# CONFIG_SUNXI_UART_REGISTER_UART0 is not set
+# CONFIG_SUNXI_UART_REGISTER_UART1 is not set
+# CONFIG_SUNXI_UART_REGISTER_UART2 is not set
+# CONFIG_SUNXI_UART_REGISTER_UART3 is not set
+
+#
+# CCMU Devices
+#
+CONFIG_DRIVERS_CCMU=y
+CONFIG_DRIVERS_SUNXI_CLK=y
+# CONFIG_DRIVERS_SUNXI_CCU is not set
+# CONFIG_HAL_TEST_CLK is not set
+
+#
+# DMA Devices
+#
+CONFIG_DRIVERS_DMA=y
+# CONFIG_HAL_TEST_DMA is not set
+
+#
+# GPIO Devices
+#
+CONFIG_DRIVERS_GPIO=y
+# CONFIG_HAL_TEST_GPIO is not set
+
+#
+# Video support for sunxi
+#
+# CONFIG_DISP2_SUNXI is not set
+
+#
+# SDMMC Devices
+#
+# CONFIG_DRIVERS_SDMMC is not set
+
+#
+# TWI Devices
+#
+# CONFIG_DRIVERS_TWI is not set

bsp/allwinner/d1/.gitignore

@@ -0,0 +1,11 @@
+__pycache__/
+*.bin
+*.elf
+*.map
+build/
+.sconsign.dblite
+cconfig.h
+.vscode/
+rtconfig.pyc
+*.old
+sdcard.bat

bsp/allwinner/d1/Kconfig

@@ -0,0 +1,47 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config BOARD_allwinnerd1
+    bool
+    select ARCH_RISCV64
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select RT_USING_CACHE
+    select ARCH_MM_MMU
+    default y
+
+config RT_USING_USERSPACE
+    bool
+    default y
+
+config ENABLE_FPU
+    bool "Enable FPU"
+    default y
+
+config RT_USING_USERSPACE_32BIT_LIMIT
+    bool "Enable userspace 32bit limit"
+    default n
+
+config __STACKSIZE__
+    int "stack size for interrupt"
+    default 4096
+
+source "../libraries/drivers/Kconfig"
+source "../libraries/Kconfig"

bsp/allwinner/d1/README.md

@@ -0,0 +1,84 @@
+# RT-Thread全志D1移植
+
+全志 d1-allwinner-nezha 属于 riscv64 平台
+
+## 编译环境搭建
+
+- 拉取 RT-Thread Smart的代码仓库 `git clone https://gitee.com/guozhanxin/rtthread-smart.git`
+
+### windows 环境
+
+- 打开 RT-Thread ENV 工具
+
+- 进入 tools 目录 `cd tools`
+
+- 拉取 `riscv64`平台的编译工具 `python get_toolchain.py riscv64`
+
+- 返回上级目录 `cd ..`
+
+- 设置环境变量 `./smart-env.bat`
+
+### ubuntu 环境
+
+- 打开 ubuntu shell 终端
+
+- 进入 tools 目录 `cd tools`
+
+- 拉取 `riscv64`平台的编译工具 `python get_toolchain.py riscv64`
+
+- 返回上级目录 `cd ..`
+
+- 设置环境变量 `source smart-env.sh riscv64`
+
+### 编译环境验证
+
+- 输入：`riscv64-unknown-linux-musl-gcc -v`
+
+## 开发与编译
+
+- windows 下使用RT-Thread ENV 工具， `menuconfig` 配置工程，`scons` 编译工程
+
+- ubuntu 下 使用shell 终端： `scons --menuconfig` 配置工程， `scons` 编译工程
+
+
+## 下载验证
+
+- 编译完后，通过：mkimage 生成 img 镜像文件，这个img 镜像文件可以使用 U-boot 引导启动
+
+- 启动方式一般有：SD卡启动、NandFlash启动、网络引导启动
+
+- windows 下使用全志的：`AllwinnertechPhoeniSuitRelease20201225`
+
+- 可以使用 xfel 工具进行烧写NandFlash
+
+## 运行效果
+
+```c
+## Booting kernel from Legacy Image at 45000000 ...
+   Image Name:   
+   Image Type:   RISC-V Linux Kernel Image (uncompressed)
+   Data Size:    249576 Bytes = 243.7 KiB
+   Load Address: 45000000
+   Entry Point:  45000000
+   Verifying Checksum ... OK
+[01.861]
+Starting kernel ...
+heap: [0x45077bb0 - 0x48277bb0]
+ \ | /
+- RT -     Thread Smart Operating System
+ / | \     5.0.0 build Jun 18 2022
+ 2006 - 2020 Copyright by rt-thread team
+file system initialization done!
+Hello RISC-V
+msh />
+
+```
+
+## 参考文档
+
+- [https://club.rt-thread.org/ask/article/389ac36250b57737.html](https://club.rt-thread.org/ask/article/389ac36250b57737.html)
+
+
+
+
+

bsp/qemu-vexpress-gemini/SConscript → bsp/allwinner/d1/SConscript

@@ -1,8 +1,8 @@
 # for module compiling
 import os
-Import('RTT_ROOT')
+from building import *
 
-cwd = str(Dir('#'))
+cwd = GetCurrentDir()
 objs = []
 list = os.listdir(cwd)
 

bsp/allwinner/d1/SConstruct

@@ -0,0 +1,63 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+import sys
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+rtconfig.CPU='c906'
+rtconfig.VENDOR="t-head"
+rtconfig.ARCH='risc-v'
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+d1_library = 'sunxi-hal'
+rtconfig.BSP_LIBRARY_TYPE = d1_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, d1_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
+
+# include libos
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'libos', 'SConscript')))
+
+stack_size = 4096
+
+stack_lds = open('link_stacksize.lds', 'w')
+if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__')
+stack_lds.write('__STACKSIZE__ = %d;' % stack_size)
+stack_lds.close()
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/allwinner/d1/applications/SConscript

@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/qemu-vexpress-gemini/drivers/serial.h → bsp/allwinner/d1/applications/main.c

@@ -5,16 +5,16 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2013-03-30     Bernard      the first verion
  */
 
-#ifndef __UART_H__
-#define __UART_H__
-
-#include <board.h>
-
-int rt_hw_uart_init(void);
-
-#endif
+#include <rtthread.h>
+#include <rthw.h>
+#include <stdio.h>
+#include <string.h>
 
+int main(void)
+{
+    printf("Hello RISC-V\n");
 
+    return 0;
+}

bsp/allwinner/d1/applications/mnt.c

@@ -0,0 +1,21 @@
+#include <rtthread.h>
+
+#ifdef RT_USING_DFS
+#include <dfs_fs.h>
+#include <dfs_romfs.h>
+
+int mnt_init(void)
+{
+
+    rt_thread_mdelay(200);
+
+    if (dfs_mount("boot", "/", "elm", 0, 0) != 0)
+    {
+        rt_kprintf("Dir /boot mount failed!\n");
+    }
+
+    rt_kprintf("file system initialization done!\n");
+    return 0;
+}
+INIT_ENV_EXPORT(mnt_init);
+#endif

bsp/allwinner/d1/applications/romfs.c

@@ -0,0 +1,13 @@
+#include <dfs_romfs.h>
+
+static const struct romfs_dirent _romfs_root[] = {
+    {ROMFS_DIRENT_DIR, "etc", RT_NULL, 0},
+    {ROMFS_DIRENT_DIR, "mnt", RT_NULL, 0},
+    {ROMFS_DIRENT_DIR, "boot", RT_NULL, 0},
+    {ROMFS_DIRENT_DIR, "boot-resource", RT_NULL, 0},
+    {ROMFS_DIRENT_DIR, "bin", RT_NULL, 0}
+};
+
+const struct romfs_dirent romfs_root = {
+    ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root) / sizeof(_romfs_root[0])};
+

bsp/allwinner/d1/board/SConscript

@@ -0,0 +1,19 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+objs = [group]
+
+list = os.listdir(cwd)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

bsp/allwinner/d1/board/board.c

@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-01-30     lizhirui     first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "tick.h"
+
+#include "drv_uart.h"
+#include "encoding.h"
+#include "stack.h"
+#include "sbi.h"
+#include "riscv.h"
+#include "stack.h"
+
+#include "hal_gpio.h"
+#include "hal_clk.h"
+#include "hal_uart.h"
+#include "hal_dma.h"
+
+#ifdef RT_USING_USERSPACE
+    #include "riscv_mmu.h"
+    #include "mmu.h"
+    #include "page.h"
+    #include "lwp_arch.h"
+
+    //这个结构体描述了buddy system的页分配范围
+    rt_region_t init_page_region =
+    {
+        (rt_size_t)RT_HW_PAGE_START,
+        (rt_size_t)RT_HW_PAGE_END
+    };
+
+    //内核页表
+    volatile rt_size_t MMUTable[__SIZE(VPN2_BIT)] __attribute__((aligned(4 * 1024)));
+    rt_mmu_info mmu_info;
+
+#endif
+
+//初始化BSS节区
+void init_bss(void)
+{
+    unsigned int *dst;
+
+    dst = &__bss_start;
+    while (dst < &__bss_end)
+    {
+        *dst++ = 0;
+    }
+}
+
+static void __rt_assert_handler(const char *ex_string, const char *func, rt_size_t line)
+{
+    rt_kprintf("(%s) assertion failed at function:%s, line number:%d \n", ex_string, func, line);
+    asm volatile("ebreak":::"memory");
+}
+
+//BSP的C入口
+void primary_cpu_entry(void)
+{
+    extern void entry(void);
+
+    //初始化BSS
+    init_bss();
+    //关中断
+    rt_hw_interrupt_disable();
+    rt_assert_set_hook(__rt_assert_handler);
+    //启动RT-Thread Smart内核
+    entry();
+}
+
+
+//这个初始化程序由内核主动调用，此时调度器还未启动，因此在此不能使用依赖线程上下文的函数
+void rt_hw_board_init(void)
+{
+#ifdef RT_USING_USERSPACE
+    rt_page_init(init_page_region);
+    rt_hw_mmu_map_init(&mmu_info,(void *)USER_VADDR_START, USER_VADDR_TOP - USER_VADDR_START, (rt_size_t *)MMUTable, 0);
+    rt_hw_mmu_kernel_map_init(&mmu_info, 0x00000000UL, USER_VADDR_START - 1);
+    //将低1GB MMIO区域设置为无Cache与Strong Order访存模式
+    MMUTable[0] &= ~PTE_CACHE;
+    MMUTable[0] &= ~PTE_SHARE;
+    MMUTable[0] |= PTE_SO;
+    rt_hw_mmu_switch((void *)MMUTable);
+#endif
+    /* initalize interrupt */
+    rt_hw_interrupt_init();
+#ifdef RT_USING_HEAP
+    rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t) RT_HW_HEAP_BEGIN, (rt_ubase_t) RT_HW_HEAP_END);
+    /* initialize memory system */
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+    /* init hal hardware */
+    hal_clock_init();
+    hal_gpio_init();
+    hal_uart_init(0);
+    hal_dma_init();
+
+    /* init rtthread hardware */
+    rt_hw_uart_init();
+    rt_hw_tick_init();
+
+#ifdef RT_USING_CONSOLE
+    /* set console device */
+    rt_console_set_device("uart");
+#endif /* RT_USING_CONSOLE */
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+void rt_hw_cpu_reset(void)
+{
+    sbi_shutdown();
+    while(1);
+}
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);

bsp/allwinner/d1/board/board.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-01-30     lizhirui     first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <rtconfig.h>
+
+extern unsigned int __bss_start;
+extern unsigned int __bss_end;
+
+#define RT_HW_HEAP_BEGIN    ((void *)&__bss_end)
+#define RT_HW_HEAP_END      ((void *)(((rt_size_t)RT_HW_HEAP_BEGIN) + 50 * 1024 * 1024))
+#define RT_HW_PAGE_START RT_HW_HEAP_END
+#define RT_HW_PAGE_END ((void *)(((rt_size_t)RT_HW_PAGE_START) + 50 * 1024 * 1024))
+
+void rt_hw_board_init(void);
+void rt_init_user_mem(struct rt_thread *thread, const char *name, unsigned long *entry);
+
+#endif

bsp/allwinner/d1/generateimg.sh

@@ -0,0 +1,2 @@
+#!/bin/sh
+mkimage -A riscv -O linux -T kernel -C none -a 0x45000000 -e 0x45000000 -d rtthread.bin rtthread.img

bsp/allwinner/d1/link.lds

@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/12     bernard      The first version
+ */
+
+INCLUDE "link_stacksize.lds"
+
+OUTPUT_ARCH( "riscv" )
+
+/*
+ * Memory layout:
+ * 0x10200000 - 0x10201000: Bootloader
+ * 0x10201000 - 0x10A00000: Kernel
+ * 0x10A00000 - 0x11200000: Heap
+ */
+
+MEMORY
+{
+   SRAM : ORIGIN = 0x45000000, LENGTH = 0x7FF000
+}
+
+ENTRY(_start)
+SECTIONS
+{
+    . = 0x45000000 ;
+
+    /* __STACKSIZE__ = 4096; */
+
+    .start :
+    {
+        *(.start);
+    } > SRAM
+
+    . = ALIGN(8);
+
+    .text : 
+    {
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+     
+        /* section information for finsh shell */
+        . = ALIGN(8);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(8);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(8);
+
+        /* section information for initial. */
+        . = ALIGN(8);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(8);
+
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+        . = ALIGN(8);
+        _etext = .;
+    } > SRAM
+
+    .eh_frame_hdr : 
+    { 
+         *(.eh_frame_hdr) 
+         *(.eh_frame_entry)
+    } > SRAM
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
+
+    . = ALIGN(8);
+
+    .data : 
+    {
+        *(.data)
+        *(.data.*)
+    
+        *(.data1)
+        *(.data1.*)
+
+        . = ALIGN(8);
+        PROVIDE( __global_pointer$ = . + 0x800 );
+
+        *(.sdata)
+        *(.sdata.*)
+    } > SRAM
+    
+    . = ALIGN(8);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+    } > SRAM
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE(__dtors_end__ = .);
+    } > SRAM
+
+    /* stack for dual core */
+    .stack :
+    {
+        . = ALIGN(64);
+        __stack_start__ = .;
+
+        . += __STACKSIZE__;
+        __stack_cpu0 = .;
+
+        . += __STACKSIZE__;
+        __stack_cpu1 = .;
+    } > SRAM
+
+    . = ALIGN(8);
+
+    .osdebug :
+    {
+        _osdebug_start = .;
+        . += 87K;
+        _osdebug_end = .;
+    } > SRAM
+
+    . = ALIGN(8);
+
+    .sbss : 
+    {
+    __bss_start = .;
+        *(.sbss)
+        *(.sbss.*)
+        *(.dynsbss)
+        *(.scommon)
+    } > SRAM
+
+    .bss :
+    {
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        *(COMMON)
+    __bss_end = .;
+    } > SRAM
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/allwinner/d1/link_stacksize.lds

@@ -0,0 +1 @@
+__STACKSIZE__ = 16384;

bsp/allwinner/d1/rtconfig.h

@@ -0,0 +1,351 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 20
+#define RT_USING_SMART
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_256
+#define RT_THREAD_PRIORITY_MAX 256
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 16384
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 16384
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_MEMTRACE
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 256
+#define RT_CONSOLE_DEVICE_NAME "uart"
+#define RT_VER_NUM 0x50000
+#define ARCH_CPU_64BIT
+#define RT_USING_CACHE
+#define ARCH_MM_MMU
+#define RT_USING_USERSPACE
+#define KERNEL_VADDR_START 0x150000000
+#define PV_OFFSET 0x0
+#define ARCH_RISCV
+#define ARCH_RISCV64
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 16384
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define RT_USING_MSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 8192
+#define FINSH_CMD_SIZE 80
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 8
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define DFS_FD_MAX 32
+#define RT_USING_DFS_ELMFAT
+
+/* elm-chan's FatFs, Generic FAT Filesystem Module */
+
+#define RT_DFS_ELM_CODE_PAGE 437
+#define RT_DFS_ELM_WORD_ACCESS
+#define RT_DFS_ELM_USE_LFN_3
+#define RT_DFS_ELM_USE_LFN 3
+#define RT_DFS_ELM_MAX_LFN 255
+#define RT_DFS_ELM_DRIVES 8
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+#define RT_DFS_ELM_REENTRANT
+#define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_ROMFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_TTY
+#define RT_USING_HWTIMER
+#define RT_USING_I2C
+#define RT_USING_I2C_BITOPS
+#define RT_USING_PIN
+#define RT_USING_NULL
+#define RT_USING_ZERO
+#define RT_USING_RANDOM
+#define RT_USING_PWM
+#define RT_USING_RTC
+#define RT_USING_WDT
+#define RT_USING_TOUCH
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_MUSL
+#define RT_USING_POSIX
+#define RT_USING_POSIX_CLOCKTIME
+
+/* Network */
+
+/* Socket abstraction layer */
+
+#define RT_USING_SAL
+
+/* protocol stack implement */
+
+#define SAL_USING_LWIP
+#define SAL_USING_POSIX
+
+/* Network interface device */
+
+#define RT_USING_NETDEV
+#define NETDEV_USING_IFCONFIG
+#define NETDEV_USING_PING
+#define NETDEV_USING_NETSTAT
+#define NETDEV_USING_AUTO_DEFAULT
+#define NETDEV_IPV4 1
+#define NETDEV_IPV6 0
+
+/* light weight TCP/IP stack */
+
+#define RT_USING_LWIP
+#define RT_USING_LWIP212
+#define RT_LWIP_MEM_ALIGNMENT 4
+#define RT_LWIP_IGMP
+#define RT_LWIP_ICMP
+#define RT_LWIP_DNS
+#define RT_LWIP_DHCP
+#define IP_SOF_BROADCAST 1
+#define IP_SOF_BROADCAST_RECV 1
+
+/* Static IPv4 Address */
+
+#define RT_LWIP_IPADDR "192.168.1.30"
+#define RT_LWIP_GWADDR "192.168.1.1"
+#define RT_LWIP_MSKADDR "255.255.255.0"
+#define RT_LWIP_UDP
+#define RT_LWIP_TCP
+#define RT_LWIP_RAW
+#define RT_MEMP_NUM_NETCONN 8
+#define RT_MEMP_NUM_TCPIP_MSG_API 16
+#define RT_MEMP_NUM_TCPIP_MSG_INPKT 16
+#define RT_LWIP_PBUF_NUM 16
+#define RT_LWIP_PBUF_STRUCT_NUM 16
+#define RT_LWIP_NETBUF_NUM 16
+#define RT_LWIP_RAW_PCB_NUM 4
+#define RT_LWIP_UDP_PCB_NUM 4
+#define RT_UDP_RECVMBOX_SIZE 16
+#define RT_RECV_BUFSIZE_DEFAULT 64
+#define RT_LWIP_TCP_PCB_NUM 4
+#define RT_LWIP_TCP_SEG_NUM 40
+#define RT_LWIP_TCP_SND_BUF 8196
+#define RT_LWIP_TCP_WND 8196
+#define RT_TCP_RECVMBOX_SIZE 16
+#define RT_LWIP_TCPTHREAD_PRIORITY 10
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
+#define RT_LWIP_TCPTHREAD_STACKSIZE 8192
+#define RT_LWIP_ETHTHREAD_PRIORITY 12
+#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
+#define RT_LWIP_REASSEMBLY_FRAG
+#define LWIP_NETIF_STATUS_CALLBACK 1
+#define LWIP_NETIF_LINK_CALLBACK 1
+#define SO_REUSE 1
+#define LWIP_SO_RCVTIMEO 1
+#define LWIP_SO_SNDTIMEO 1
+#define LWIP_SO_RCVBUF 1
+#define LWIP_SO_LINGER 0
+#define LWIP_NETIF_LOOPBACK 0
+#define RT_LWIP_USING_PING
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+#define RT_USING_LWP
+#define RT_LWP_MAX_NR 30
+#define LWP_TASK_STACK_SIZE 16384
+#define RT_CH_MSG_MAX_NR 1024
+#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
+#define LWP_TID_MAX_NR 64
+#define RT_LWP_SHM_MAX_NR 64
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Sensor libraries */
+
+
+/* Display libraries */
+
+
+/* Timing libraries */
+
+
+/* Project libraries */
+
+#define BOARD_allwinnerd1
+#define ENABLE_FPU
+#define __STACKSIZE__ 16384
+
+/* General Drivers Configuration */
+
+/* General Purpose UARTs */
+
+#define BSP_USING_WDT
+#define BSP_USING_RTC
+#define RT_USING_SUNXI_HAL
+
+/* UART Devices */
+
+#define DRIVERS_UART
+
+/* CCMU Devices */
+
+#define DRIVERS_CCMU
+#define DRIVERS_SUNXI_CLK
+
+/* DMA Devices */
+
+#define DRIVERS_DMA
+
+/* GPIO Devices */
+
+#define DRIVERS_GPIO
+
+/* Video support for sunxi */
+
+
+/* SDMMC Devices */
+
+
+/* TWI Devices */
+
+
+#endif

bsp/allwinner/d1/rtconfig.py

@@ -0,0 +1,56 @@
+import os
+
+# toolchains options
+ARCH        ='risc-v'
+VENDOR      ='t-head'
+CPU         ='c906'
+CROSS_TOOL  ='gcc'
+
+RTT_ROOT = os.getenv('RTT_ROOT') or os.path.join(os.getcwd(),'..','..','..')
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/opt/riscv64_musl/bin'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    #PREFIX  = 'riscv64-unknown-elf-'
+    PREFIX  = os.getenv('RTT_CC_PREFIX') or 'riscv64-unknown-linux-musl-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE  = ' -mcmodel=medany -march=rv64imafdc -mabi=lp64'
+    CFLAGS  = DEVICE + ' -fvar-tracking -ffreestanding -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields '
+    AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' + ' -lsupc++ -lgcc -static'
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -ggdb'
+        AFLAGS += ' -ggdb'
+    else:
+        CFLAGS += ' -O2 -Os'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

bsp/allwinner/d1s/.config

@@ -0,0 +1,957 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=20
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+CONFIG_RT_USING_SMART=y
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+# CONFIG_RT_USING_OVERFLOW_CHECK is not set
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=16384
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=16384
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+CONFIG_RT_KPRINTF_USING_LONGLONG=y
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_MEMTRACE=y
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=256
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50000
+CONFIG_ARCH_CPU_64BIT=y
+CONFIG_RT_USING_CACHE=y
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_MM_MMU=y
+CONFIG_RT_USING_USERSPACE=y
+CONFIG_KERNEL_VADDR_START=0x150000000
+CONFIG_PV_OFFSET=0
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV64=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=16384
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=8192
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=8
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+CONFIG_DFS_FD_MAX=32
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=936
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=8
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_TMPFS is not set
+CONFIG_RT_USING_FAL=y
+CONFIG_FAL_DEBUG_CONFIG=y
+CONFIG_FAL_DEBUG=1
+CONFIG_FAL_PART_HAS_TABLE_CFG=y
+# CONFIG_FAL_USING_SFUD_PORT is not set
+CONFIG_RT_USING_LWP=y
+CONFIG_RT_LWP_MAX_NR=30
+CONFIG_LWP_TASK_STACK_SIZE=16384
+CONFIG_RT_CH_MSG_MAX_NR=1024
+CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
+CONFIG_LWP_TID_MAX_NR=64
+CONFIG_RT_LWP_SHM_MAX_NR=64
+# CONFIG_LWP_UNIX98_PTY is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=4096
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_USING_SERIAL_V1 is not set
+CONFIG_RT_USING_SERIAL_V2=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_USING_TTY=y
+# CONFIG_RT_TTY_DEBUG is not set
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+CONFIG_RT_USING_NULL=y
+CONFIG_RT_USING_ZERO=y
+CONFIG_RT_USING_RANDOM=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+CONFIG_RT_USING_WDT=y
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+CONFIG_RT_USING_DEV_BUS=y
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+CONFIG_RT_USING_POSIX_STDIO=y
+CONFIG_RT_USING_POSIX_POLL=y
+CONFIG_RT_USING_POSIX_SELECT=y
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+CONFIG_RT_USING_POSIX_TERMIOS=y
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_POSIX_MMAN is not set
+CONFIG_RT_USING_POSIX_DELAY=y
+CONFIG_RT_USING_POSIX_CLOCK=y
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+CONFIG_RT_USING_POSIX_PIPE=y
+CONFIG_RT_USING_POSIX_PIPE_SIZE=512
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Sensor libraries
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+
+#
+# Display libraries
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+
+#
+# Timing libraries
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Project libraries
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+CONFIG_BOARD_allwinnerd1s=y
+CONFIG_ENABLE_FPU=y
+# CONFIG_RT_USING_USERSPACE_32BIT_LIMIT is not set
+CONFIG___STACKSIZE__=16384
+
+#
+# General Drivers Configuration
+#
+CONFIG_BSP_USING_M7=y
+
+#
+# General Purpose UARTs
+#
+CONFIG_BSP_USING_UART0=y
+CONFIG_UART0_TX_USING_GPIOE2=y
+# CONFIG_UART0_TX_USING_GPIOF2 is not set
+CONFIG_UART0_RX_USING_GPIOE3=y
+# CONFIG_UART0_RX_USING_GPIOF4 is not set
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_UART4 is not set
+# CONFIG_BSP_USING_UART5 is not set
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_TOUCH is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_PWM is not set
+CONFIG_BSP_USING_SDMMC=y
+CONFIG_SD_CARD_CHECK=y
+CONFIG_BSP_USING_FS=y
+# CONFIG_BSP_USING_LCD is not set
+
+#
+# Board extended module Drivers
+#
+# CONFIG_BSP_USING_RW007 is not set
+CONFIG_RT_USING_SUNXI_HAL=y
+
+#
+# UART Devices
+#
+# CONFIG_DRIVERS_UART is not set
+
+#
+# CCMU Devices
+#
+CONFIG_DRIVERS_CCMU=y
+# CONFIG_DRIVERS_SUNXI_CLK is not set
+CONFIG_DRIVERS_SUNXI_CCU=y
+# CONFIG_HAL_TEST_CCU is not set
+
+#
+# DMA Devices
+#
+CONFIG_DRIVERS_DMA=y
+# CONFIG_HAL_TEST_DMA is not set
+
+#
+# GPIO Devices
+#
+CONFIG_DRIVERS_GPIO=y
+# CONFIG_HAL_TEST_GPIO is not set
+
+#
+# Video support for sunxi
+#
+CONFIG_DISP2_SUNXI=y
+CONFIG_SUNXI_DISP2_FB_DISABLE_ROTATE=y
+# CONFIG_SUNXI_DISP2_FB_ROTATION_SUPPORT is not set
+# CONFIG_HAL_TEST_DISP is not set
+# CONFIG_FPGA_V7_PLATFORM is not set
+# CONFIG_SUNXI_DISP2_FB_DECOMPRESS_LZMA is not set
+# CONFIG_HDMI_DISP2_SUNXI is not set
+# CONFIG_HDMI2_DISP2_SUNXI is not set
+# CONFIG_HDMI_EP952_DISP2_SUNXI is not set
+# CONFIG_TV_DISP2_SUNXI is not set
+# CONFIG_VDPO_DISP2_SUNXI is not set
+# CONFIG_EDP_DISP2_SUNXI is not set
+# CONFIG_DISP2_SUNXI_BOOT_COLORBAR is not set
+
+#
+# LCD panels select
+#
+# CONFIG_LCD_SUPPORT_GG1P4062UTSW is not set
+# CONFIG_LCD_SUPPORT_DX0960BE40A1 is not set
+# CONFIG_LCD_SUPPORT_TFT720X1280 is not set
+# CONFIG_LCD_SUPPORT_FD055HD003S is not set
+CONFIG_LCD_SUPPORT_HE0801A068=y
+# CONFIG_LCD_SUPPORT_ILI9341 is not set
+# CONFIG_LCD_SUPPORT_LH219WQ1 is not set
+# CONFIG_LCD_SUPPORT_LS029B3SX02 is not set
+# CONFIG_LCD_SUPPORT_LT070ME05000 is not set
+# CONFIG_LCD_SUPPORT_S6D7AA0X01 is not set
+# CONFIG_LCD_SUPPORT_T27P06 is not set
+# CONFIG_LCD_SUPPORT_TFT720_1280 is not set
+# CONFIG_LCD_SUPPORT_TFT08006 is not set
+# CONFIG_LCD_SUPPORT_TFTRGB is not set
+# CONFIG_LCD_SUPPORT_WTQ05027D01 is not set
+# CONFIG_LCD_SUPPORT_H245QBN02 is not set
+# CONFIG_LCD_SUPPORT_ST7789V is not set
+# CONFIG_LCD_SUPPORT_ST7796S is not set
+# CONFIG_LCD_SUPPORT_ST7701S is not set
+# CONFIG_LCD_SUPPORT_T30P106 is not set
+# CONFIG_LCD_SUPPORT_TO20T20000 is not set
+# CONFIG_LCD_SUPPORT_FRD450H40014 is not set
+# CONFIG_LCD_SUPPORT_S2003T46G is not set
+CONFIG_LCD_SUPPORT_WILLIAMLCD=y
+CONFIG_LCD_SUPPORT_LQ101R1SX03=y
+CONFIG_LCD_SUPPORT_INET_DSI_PANEL=y
+# CONFIG_LCD_SUPPORT_WTL096601G03 is not set
+# CONFIG_LCD_SUPPORT_RT13QV005D is not set
+# CONFIG_LCD_SUPPORT_ST7789V_CPU is not set
+# CONFIG_LCD_SUPPORT_VVX07H005A10 is not set
+
+#
+# Display engine feature select
+#
+# CONFIG_DISP2_SUNXI_SUPPORT_SMBL is not set
+CONFIG_DISP2_SUNXI_SUPPORT_ENAHNCE=y
+
+#
+# Soc and board select
+#
+
+#
+# Board Select
+#
+# CONFIG_V459_PERF1 is not set
+# CONFIG_F133_FPGA is not set
+# CONFIG_VVX07H005A10_MIPI is not set
+# CONFIG_TFT08006_MIPI is not set
+# CONFIG_TFT_RGB is not set
+# CONFIG_HE0801A068_MIPI is not set
+# CONFIG_DEFAULT_LVDS is not set
+
+#
+# Soc Select
+#
+# CONFIG_ARCH_SUN8IW19 is not set
+# CONFIG_ARCH_SUN20IW1 is not set
+
+#
+# SDMMC Devices
+#
+CONFIG_DRIVERS_SDMMC=y
+CONFIG_USE_SD=y
+CONFIG_USE_SDIO=y
+# CONFIG_USE_MMC is not set
+CONFIG_DETECT_CARD=y
+CONFIG_SDC_DMA_USED=y
+CONFIG_SDIO_IRQ_SUPPORT=y
+# CONFIG_SD_TEST is not set
+CONFIG_SDC_DMA_BUF_SIZE=64
+CONFIG_DRIVERS_SDC_CDPIN_PRESENT_VAL=0
+
+#
+# SPI Devices
+#
+CONFIG_DRIVERS_SPI=y
+# CONFIG_HAL_TEST_SPI is not set
+
+#
+# TWI Devices
+#
+CONFIG_DRIVERS_TWI=y
+# CONFIG_HAL_TEST_TWI is not set
+
+#
+# G2D Devices
+#
+CONFIG_DRIVERS_G2D=y
+# CONFIG_HAL_TEST_G2D is not set
+# CONFIG_DRIVERS_USB is not set
+
+#
+# CE Devices
+#
+CONFIG_DRIVERS_CE=y
+# CONFIG_HAL_TEST_CE is not set
+
+#
+# EFUSE Devices
+#
+CONFIG_DRIVERS_EFUSE=y
+# CONFIG_HAL_TEST_EFUSE is not set

bsp/allwinner/d1s/.gitignore

@@ -0,0 +1,11 @@
+__pycache__/
+*.bin
+*.elf
+*.map
+build/
+.sconsign.dblite
+cconfig.h
+.vscode/
+rtconfig.pyc
+*.old
+sdcard.bat

bsp/allwinner/d1s/Kconfig

@@ -0,0 +1,47 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config BOARD_allwinnerd1s
+    bool
+    select ARCH_RISCV64
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select RT_USING_CACHE
+    select ARCH_MM_MMU
+    default y
+
+config RT_USING_USERSPACE
+    bool
+    default y
+
+config ENABLE_FPU
+    bool "Enable FPU"
+    default y
+
+config RT_USING_USERSPACE_32BIT_LIMIT
+    bool "Enable userspace 32bit limit"
+    default n
+
+config __STACKSIZE__
+    int "stack size for interrupt"
+    default 4096
+
+source "../libraries/drivers/Kconfig"
+source "../libraries/Kconfig"

bsp/allwinner/d1s/README-M7.md

@@ -0,0 +1,283 @@
+# 基于柿饼M7运行 RT-Smart
+
+## 准备工作
+
+#### 开发环境
+
+推荐使用 ubuntu20.04(虚拟机/docker/服务器) + Window10/11
+
+- ubuntu：用于编译、开发、打包镜像
+- windows：用于下载打包好的镜像
+
+#### 常用工具
+
+**Ubuntu:**
+
+```bash
+sudo apt install libncurses5-dev scons gcc qemu-system
+```
+
+- qemu：用于仿真运行RISC-V程序
+- gcc：用于编译menucofig的程序
+- libncurses5-dev ：menucofig功能依赖此库
+- scons：编译RT-Smart需要的构建工具
+
+**Windows:**
+
+- vscode：windows上安装，用于远程连接ubuntu系统，可以在win上体验原生的linux开发环境。
+- MobaXterm：终端工具，可以ssh远程ubuntu系统，也可以通过串口连接柿饼M7模块
+- env_riscv_1.1.3.zip：针对risc-v平台的ENV工具。
+
+#### 相关仓库权限
+
+- https://gitee.com/rtthread/rt-thread ：rtthread内核仓库，以submodule的形式存在于rtthread-smart仓库中，这里使用的是rt-smart分支
+
+获取上面的仓库权限，并将rtthread-smart克隆到ubuntu系统目录下。目录结构如下所示：
+
+在做好上面的准备后，就可以真正的开始搭建RT-Smart的开发环境了。
+
+## 模拟仿真环境搭建
+
+在真实的硬件上开发之前，可以先搭建基于QEMU的模拟仿真环境。
+
+参考这篇文章，完成 qemu-riscv64 上 RT-Smart 环境搭建：https://gitee.com/guozhanxin/rtthread-smart/tree/master/docs/risc-v64
+
+最后能够在 qemu-riscv64 上正常运行RT-Smart系统，并运行一个 `hello.elf` 用户态应用。
+
+```
+msh /bin>hello.elf
+msh /bin>hello world!
+```
+
+## 真实硬件环境搭建
+
+#### 硬件连接
+
+按照下图中的连接方式，为开发板供电，并使用USB转TTL工具连接串口调试。
+
+<img src="figures/board.png" style="zoom:50%;" />
+
+#### 驱动安装
+
+1. 按住下载模式按钮的情况下为开发板上电。
+
+2. 解压tools目录下fel驱动安装.zip文件。参照如下所示的“驱动安装示意图”，安装fel驱动。
+
+![1662705678296](figures/fel_driver.png)
+
+#### 连接串口工具
+
+打开 MobaXterm 终端工具，并连接到对应的端口，波特率为：500000。
+
+>  注意：如果系统没有固件的话，不会有任何输出，是正常现象。
+
+<img src="figures/mobaxterm.png" alt="1662708288766" style="zoom: 50%;" />
+
+#### 制作系统固件
+
+参照 qemu-riscv64 上编译内核的步骤，配置环境变量，并使用 scons 命令编译 RT-Smart 内核
+
+编译完内核之后，会自动执行打包命令 `./mksdimg.sh` 打包出sd.bin镜像文件。此文件将在后面的步骤中借助下载工具，下载到 D1s 上运行。
+
+#### 烧录系统内核
+
+我们借助fel工具烧录系统内核。
+
+1. 解压tools目录下的 xfel_v1.2.9.7z 文件，里面包含三个文件
+
+```shell
+boot0_sdcard_sun20iw1p1_f133.bin   ---- 第一次烧录需要烧录此boot文件
+sd.bin                             ---- 打包好的系统内核镜像
+xfel.exe                           ---- 烧录工具
+```
+
+2. 解压tools目录下 env_riscv_1.1.3.zip 文件，打开env工具，并进入解压好的 xfel_v1.2.9 目录下。运行下面的命令烧录系统内核
+
+- 烧录boot镜像： xfel.exe write 8192 boot0_sdcard_sun20iw1p1_f133.bin
+- 烧录内核镜像： xfel.exe sd write 57344 sd.bin
+- 复位系统： xfel.exe reset
+
+>  注意：执行烧录命令前，需要使开发板处于fel下载模式（按住下载按钮并上电）
+
+日志如下所示：
+
+```shell
+11714@DESKTOP-VEL6MD9 E:\workspace\d1s-smart\env_riscv_1.1.3
+> cd E:\workspace\d1s-smart\xfel_v1.2.9
+
+11714@DESKTOP-VEL6MD9 E:\workspace\d1s-smart\xfel_v1.2.9
+> xfel.exe write 8192 boot0_sdcard_sun20iw1p1_f133.bin
+ERROR: Can't found any FEL device  ----  如果开发板没有处于fel下载模式的话，会提示错误。
+
+## 第一次使用需要先烧录boot镜像文件
+11714@DESKTOP-VEL6MD9 E:\workspace\d1s-smart\xfel_v1.2.9
+> xfel.exe write 8192 boot0_sdcard_sun20iw1p1_f133.bin
+100% [================================================] 48.000 KB, 364.927 KB/s
+
+## 烧录内核镜像文件
+11714@DESKTOP-VEL6MD9 E:\workspace\d1s-smart\xfel_v1.2.9
+> xfel.exe sd write 57344 sd.bin
+write 7240Kbytes
+swap buf:00023E00,len=512, cmdlen=512
+Found SD card 126877696 bytes
+100% [================================================] 7.070 MB, 219.468 KB/s
+
+## 复位系统
+11714@DESKTOP-VEL6MD9 E:\workspace\d1s-smart\xfel_v1.2.9
+> xfel.exe reset
+usb bulk recv error
+```
+
+如果此时连接着 MobaXterm 终端工具，可以看到系统以及正常启动，并可以通过 **msh** 命令和系统交互了。
+
+```bash
+[I/I2C] I2C bus [i2c2] registered
+
+ \ | /
+- RT -     Thread Smart Operating System
+ / | \     5.0.0 build Oct 20 2022
+ 2006 - 2020 Copyright by rt-thread team
+lwIP-2.0.2 initialized!
+winusb class register done.
+set samplerate:48000
+set samplebits:16
+set channels:2
+set volume:80%
+hal_sdc_create 0
+card_detect insert
+Initial card success. capacity :121MB
+sdmmc bytes_per_secotr:200, sector count:3c800
+found part[0], begin: 8388608, size: 90.0MB
+found partition:sd0 of mbr at offset 0000000000004000, size:000000000002d000
+found part[1], begin: 102760448, size: 23.0MB
+found partition:sd1 of mbr at offset 0000000000031000, size:000000000000b800
+hal_sdc_create 1
+card_detect insert
+Initial card success. capacity :7624MB
+sdmmc bytes_per_secotr:200, sector count:ee4000
+found part[0], begin: 512, size: 4194303.1023GB
+found partition:sd0 of mbr at offset 0000000000000001, size:ffffffffffffffff
+[I/sal.skt] Socket Abstraction Layer initialize success.
+[D/FAL] (fal_flash_init:47) Flash device |                  sdcard0 | addr: 0x00000000 | len: 0x07900000 | blk_size: 0x00000200 |initialized finish.
+```
+
+#### 运行用户态应用(可选)
+
+在 D1s 上运行系统应用有两种方式：一种是制作 `sdroot.bin` 并借助 `xfel工具` 烧录到 `sdmmc` 对应的位置上；二是使用 romfs 的方式，和内核镜像编译在一起，然后整个的烧录到 `sdmmc` 上。
+
+**1、借助 romfs 运行用户态应用**
+
+romfs 方式优点：打包、调试方便，无需外部 emmc 挂载文件系统，使能 romfs 文件系统即可使用，缺点是 romfs 是只读文件系统。
+
+这部分可以参考 qemu-riscv64 上运行用户态应用的部分。使用 python 命令将 userapps 下 root 目录下的用户态应用打包为  `romfs.c` ，并重新编译系统内核，重复上面的系统内核烧录步骤。最后复位并运行系统。参照下面的运行日志，运行对应的用户态应用。
+
+```bash
+msh />cd bin
+msh /bin>ls
+Directory /bin:
+syslogd.elf         423024
+ping.elf            368104
+webserver.elf       510216
+hello.elf           366096
+em.elf              601336
+pong.elf            367024
+syslog.elf          391128
+vi.elf              528096
+hdc_test.elf        367520
+ntp.elf             392168
+mmapctrl.elf        366992
+pmq.elf             371600
+webclient.elf       413784
+lwIPKit.elf         998504
+msh /bin>hello.elf
+msh /bin>hello world!
+```
+
+**2、在存储设备上运行用户态应用**
+
+sdroot.bin 挂载方式优点：使用 emmc 存储设备的文件系统是可读可写的，更加灵活方便。
+
+首先下载 RT-Smart 用户态应用代码：
+
+```
+git clone https://github.com/RT-Thread/userapps.git
+```
+
+![](figures\MQ1.png)
+
+拷贝之前克隆好的 rtthread rt-smart 分支的仓库到 `userapps` 目录下，进入 `userapps` 目录，使用 scons 编译用户态程序，然后运行 `./mksdcard.sh` 打包脚本，将生成的 `sdroot.bin` 复制到 window 下存在 `xfel.exe ` 的目录下，使用以下命令即可烧录用户态程序到存储设备 :
+
+```bash
+xfel.exe sd write 8388608 sdroot.bin
+```
+
+参照下面的运行日志，运行对应的用户态应用：
+
+```C
+msh />ls
+Directory /:
+bin                 <DIR>
+data                <DIR>
+Directory /bin:
+syslogd.elf         423024
+ping.elf            368104
+webserver.elf       510216
+hello.elf           366096
+em.elf              601336
+pong.elf            367024
+syslog.elf          391128
+vi.elf              528096
+hdc_test.elf        367520
+ntp.elf             392168
+mmapctrl.elf        366992
+pmq.elf             371600
+webclient.elf       413784
+lwIPKit.elf         998504
+msh /bin>hello.elf
+msh /bin>hello world!
+```
+
+## D1S-EMMC 分区示意图
+
+![](figures/emmc_partition.png)
+
+## Q&A
+
+Q：使用 `VSCode` 发现有些已经定义的宏变灰，头文件报错：
+
+A：打开 `VSCode`，按下 “Crtl+Shift+P” 打开 `VSCode` 的控制台，然后输入 “C/C++: **Edit configurations(JSON)** ”，打开 C/C++编辑配置文件，添加如下配置选项
+
+```json
+{
+    "configurations": [
+        {
+            "name": "Linux",
+            "includePath": [
+                "${workspaceFolder}/**",
+                "${workspaceFolder}/bsp/allwinner/d1s",
+                "${workspaceFolder}/include",
+                "${workspaceFolder}/components/drivers/include",
+                "${workspaceFolder}/bsp/allwinner/libraries/sunxi-hal/include"
+            ],
+            "defines": [],
+            "compilerPath": "/usr/bin/gcc",
+            "cStandard": "gnu17",
+            "cppStandard": "gnu++14",
+            "intelliSenseMode": "linux-gcc-x64"
+        }
+    ],
+    "version": 4
+}
+```
+
+---
+
+Q：开机后，出现了 **mount** 失败的错误
+
+![](figures/mount.png)
+
+A：原因是没有下载 all_bin/sdroot.bin(用户态) 固件导致，重新烧录 all_bin/sdroot.bin 到 8388608 地址后，即可 mount 成功，，烧录命令如下：
+
+```bash
+xfel.exe sd write 8388608 all.bin/sdroot.bin
+```

bsp/allwinner/d1s/README-MQ.md

@@ -0,0 +1,183 @@
+# 基于麻雀D1运行 RT-Smart
+
+### 下载代码
+
+下载 RT-Smart 用户态应用代码：
+
+```
+git clone https://github.com/RT-Thread/userapps.git
+```
+
+![](figures/MQ1.png)
+
+进入到 `userapps` 目录，克隆 RT-Thread rt-smart 分支
+
+```shell
+git clone -b rt-smart https://gitee.com/rtthread/rt-thread.git
+```
+
+![](figures/MQ2.png)
+
+### 配置工具链
+
+在 userapps\tools 目录下运行 `get_toolchain.py` 的脚本，会下载对应的工具链并展开到 userapps\tools\gun_gcc 目录。后面的工具链名称可以是 arm | riscv64。
+
+因为 D1S 是 RISCV-64 架构的，所以输入下面的命令：
+
+```
+python3 get_toolchain.py riscv64
+```
+
+在 userapps 目录下，运行 `smart-env.sh` 配置工具链路径，目前支持的参数可以是 arm | riscv64
+
+```
+source smart-env.sh riscv64
+```
+
+![](figures/MQ3.png)
+
+
+### 编译内核程序
+
+进入 `rt-thread/bsp/allwinner/d1s` 目录下，执行以下命令拉取一下软件包
+
+* 注：若系统没有安装 env，需要手动输入 `scons --menuconfig` 命令手动下载 env
+
+```shell
+source ~/.env/env.sh
+pkgs --update
+```
+
+使用 scons 命令进行编译，编译成功后会在 `userapps/rt-thread/bsp/allwinner/d1s` 目录下生成 sd.bin，这个文件就是我们需要烧录到开发板中的文件，它包括了 uboot.dtb，opensbi，rtthread.bin。
+
+### 烧录程序
+
+1、首先准备一张容量在 128G 以内的空白 TF卡
+
+2、使用 fdisk 分区。将 TF卡 挂载到 ubuntu 系统后，使用 df 查看设备路径。笔者使用的 32GB TF卡，扇区大小 512 字节，我们需要预留前 8M 的空间，那么计算得知分区扇区开始于：16384，使用命令：`sudo fdisk /dev/sdb`，选择：o，n，p，1，16384，回车。
+
+```shell
+Command (m for help): o
+Created a new DOS disklabel with disk identifier 0x3668b987.
+
+Command (m for help): n
+Partition type
+   p   primary (0 primary, 0 extended, 4 free)
+   e   extended (container for logical partitions)
+Select (default p): p
+Partition number (1-4, default 1): 1
+First sector (2048-62410751, default 2048): 16384
+Last sector, +sectors or +size{K,M,G,T,P} (16384-62410751, default 62410751): 
+
+Created a new partition 1 of type 'Linux' and of size 29.8 GiB.
+
+Command (m for help): w
+The partition table has been altered.
+```
+
+正确的分区效果如下：
+
+![](figures/MQ5.png)
+
+然后格式化 sdb1 分区为 fat32 格式：
+
+```shell
+$ sudo mkfs -t fat /dev/sdb1
+```
+
+这里可以使用 **Gparted** 工具可视化查看一下分区状况：
+
+![](figures/MQ6.png)
+
+3、接下来使用以下命令烧录 RT-SMART 内核：
+
+```shell
+sudo dd if=boot0_sdcard_sun20iw1p1.bin of=/dev/sdb bs=1024 seek=8
+sudo dd if=sd.bin of=/dev/sdb bs=1024 seek=56
+```
+
+* 注：**boot0_sdcard_sun20iw1p1.bin** 文件在 `userapps/rt-thread/bsp/allwinner/d1s/tools` 路径下
+* 这里的 /dev/sdb 设备要根据自己的选择
+
+下面是烧录成功的显示：
+
+![](figures/MQ7.png)
+
+### 启动 RT-Smart
+
+方式二（TF 卡）启动：
+
+此时将 TF 卡放入开发板，串口0（底部排针的7，8脚），串口波特率 500000，然后上电，如下 RT-Smart 已经成功启动
+
+![](figures/MQ8.png)
+
+```shell
+ \ | /
+- RT -     Thread Smart Operating System
+ / | \     5.0.0 build Nov  1 2022
+ 2006 - 2022 Copyright by rt-thread team
+lwIP-2.0.2 initialized!
+hal_sdc_create 0
+card_detect insert
+Initial card success. capacity :30436MB
+sdmmc bytes_per_secotr:200, sector count:3b72400
+found part[0], begin: 8388608, size: 29.732GB
+found partition:sd0 of mbr at offset 0000000000004000, size:0000000003b6e400
+hal_sdc_create 1
+card_detect insert
+Initial card failed!!
+[E/drv-sdmmc] init sdmmc failed!
+[E/drv-sdmmc] sdmmc_init failed!
+[I/sal.skt] Socket Abstraction Layer initialize success.
+[D/FAL] (fal_flash_init:47) Flash device |                  sdcard0 | addr: 0x00000000 | len: 0x76e480000 | blk_size: 0x00000200 |initialized finish.
+[I/FAL] ==================== FAL partition table ====================
+[I/FAL] | name       | flash_dev |   offset   |    length  |
+[I/FAL] -------------------------------------------------------------
+[I/FAL] | download   | sdcard0   | 0x00800000 | 0x00800000 |
+[I/FAL] | easyflash  | sdcard0   | 0x01000000 | 0x00100000 |
+[I/FAL] | filesystem | sdcard0   | 0x01100000 | 0x00c00000 |
+[I/FAL] =============================================================
+[I/FAL] RT-Thread Flash Abstraction Layer initialize success.
+Hello RISC-V
+[W/DBG] disp:[parser_disp_init_para 575]of_property_read screen1_output_type fail
+msh />Mount "sd0p0" on "/" success
+msh />
+```
+
+### 编译用户态程序
+
+进入 `userapps` 目录下，使用 scons 编译用户态程序，编译好的文件会生成在 `root/bin` 目录下。
+
+![](figures/MQ9.png)
+
+### 运行用户态程序
+
+从 `root/bin` 目录下拷贝出 hello 程序，到 TF卡 的文件系统中。
+
+![](https://oss-club.rt-thread.org/uploads/20221101/f7709c3708b1d45f496e10c040d99f10.png)
+
+拔出 TF 卡，插入到开发板，上电。即可体验属于自己的 helloworld 程序了。
+
+```shell
+msh /bin>ls
+Directory /bin:
+dbkit_client.elf    616960
+elmFATKit.elf       373880
+em.elf              585504
+hdc_test.elf        339976
+hello.elf           339624
+lvgl.elf            1382168
+lwIPKit.elf         976784
+mmapctrl.elf        339976
+ntp.elf             363560
+ping.elf            344208
+pmq.elf             345176
+pong.elf            339624
+syslog.elf          364736
+syslogd.elf         377560
+vi.elf              446568
+webclient.elf       358048
+msh /bin>
+msh /bin>hello.elf
+msh /bin>hello world!
+```

bsp/allwinner/d1s/README.md

@@ -0,0 +1,4 @@
+# 全志 D1s 运行 RT-Smart
+
+* [基于柿饼M7运行 RT-Smart](./README-M7.md)
+* [基于麻雀MQ运行 RT-Smart](./README-MQ.md)

bsp/allwinner/d1s/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/allwinner/d1s/SConstruct

@@ -0,0 +1,101 @@
+import os
+import sys
+import rtconfig
+import platform
+import subprocess
+import uuid
+
+from rtconfig import RTT_ROOT
+import sys
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+rtconfig.CPU='c906'
+rtconfig.VENDOR="t-head"
+rtconfig.ARCH='risc-v'
+
+SDK_ROOT = os.path.abspath('../')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# set spawn
+def ourspawn(sh, escape, cmd, args, e):
+    filename = str(uuid.uuid4())
+    newargs = ' '.join(args[1:])
+    cmdline = cmd + " " + newargs
+    if (len(cmdline) > 16 * 1024):
+        f = open(filename, 'w')
+        f.write(' '.join(args[1:]).replace('\\', '/'))
+        f.close()
+        # exec
+        cmdline = cmd + " @" + filename
+    proc = subprocess.Popen(cmdline, stdin=subprocess.PIPE, stdout=subprocess.PIPE,
+        stderr=subprocess.PIPE, shell = False, env = e)
+    data, err = proc.communicate()
+    rv = proc.wait()
+    def res_output(_output, _s):
+        if len(_s):
+            if isinstance(_s, str):
+                _output(_s)
+            elif isinstance(_s, bytes):
+                _output(str(_s, 'UTF-8'))
+            else:
+                _output(str(_s))
+    res_output(sys.stderr.write, err)
+    res_output(sys.stdout.write, data)
+    if os.path.isfile(filename):
+        os.remove(filename)
+    return rv
+
+if platform.system() == 'Windows':
+    env['SPAWN'] = ourspawn
+
+hal_library = 'sunxi-hal'
+rtconfig.BSP_LIBRARY_TYPE = hal_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hal_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
+
+# include libos
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'libos', 'SConscript')))
+
+if rtconfig.PLATFORM == 'gcc':
+    env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group'
+
+stack_size = 4096
+
+stack_lds = open('link_stacksize.lds', 'w')
+if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__')
+stack_lds.write('__STACKSIZE__ = %d;' % stack_size)
+stack_lds.close()
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/allwinner/d1s/applications/SConscript

@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/allwinner/d1s/applications/main.c

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#include <rtthread.h>
+#include <stdio.h>
+
+int main(void)
+{
+    printf("Hello RISC-V\n");
+
+#ifdef BSP_USING_LCD
+    extern int rt_hw_lcd_init(void);
+    rt_hw_lcd_init();
+#endif // BSP_USING_LCD
+
+    return 0;
+}

bsp/allwinner/d1s/applications/mnt.c

@@ -0,0 +1,130 @@
+/*
+ * COPYRIGHT (C) 2012-2022, Shanghai Real-Thread Technology Co., Ltd
+ * All rights reserved.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-02-08     RT-Thread    the first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <unistd.h>
+#include "drv_pin.h"
+
+#ifdef BSP_USING_SDMMC
+#include "drv_sdmmc.h"
+#endif
+
+#ifdef RT_USING_FAL
+#include "fal.h"
+#endif
+
+#ifdef RT_USING_DFS
+#include <dfs_fs.h>
+
+#define SD_CHECK_PIN GET_PIN(GPIO_PORT_G, GPIO_PIN_3)
+
+int sd_check_thread_entry(void *p)
+{
+    rt_uint8_t old_sd_check = 0;
+
+    /* 挂载sd0分区 */
+    if (RT_NULL != rt_device_find("sd0p0"))
+    {
+        if (dfs_mount("sd0p0", "/", "elm", 0, 0) == 0)
+        {
+            rt_kprintf("Mount \"sd0p0\" on \"/\" success\n");
+        }
+        else
+        {
+            rt_kprintf("Mount \"sd0p0\" on \"/\" fail\n");
+            return -1;
+        }
+
+        /* 挂载sd1分区 */
+        if (RT_NULL != rt_device_find("sd0p1"))
+        {
+            if (dfs_mount("sd0p1", "/", "elm", 0, 0) == 0)
+            {
+                rt_kprintf("Mount \"sd0p1\" on \"/\" success\n");
+            }
+            else
+            {
+                rt_kprintf("Mount \"sd0p1\" on \"/data\" fail\n");
+            }
+        }
+
+        while (1)
+        {
+#ifdef SD_CARD_CHECK
+            if (!rt_pin_read(SD_CHECK_PIN) && !old_sd_check) // mount
+#else
+            if (!old_sd_check) // mount
+#endif
+            {
+                sd_mmc1_init();
+                /* 挂载sd2分区 */
+                if (RT_NULL != rt_device_find("sd1p0"))
+                {
+
+                    if (access("/mnt", 0) != 0)
+                    {
+                        mkdir("/mnt", 0777);
+                    }
+
+                    if (dfs_mount("sd1p0", "/mnt", "elm", 0, 0) == 0)
+                    {
+                        rt_kprintf("Mount \"sd1p0\" on \"/mnt\" success\n");
+                    }
+                    else
+                    {
+                        rt_kprintf("Mount \"sd1p0\" on \"/mnt\" fail\n");
+                    }
+                }
+                old_sd_check = 1;
+            }
+#ifdef SD_CARD_CHECK
+            else if (rt_pin_read(SD_CHECK_PIN) && old_sd_check) // unmount
+            {
+                if (RT_NULL != rt_device_find("sd1p0"))
+                {
+
+                    if (dfs_unmount("/mnt") == 0)
+                    {
+                        rt_kprintf("unMount \"sd1p0\" on \"/mnt\" success\n");
+                    }
+                    else
+                    {
+                        rt_kprintf("unMount \"sd1p0\" on \"/mnt\" fail\n");
+                    }
+                }
+                sd_mmc1_deinit();
+                old_sd_check = 0;
+            }
+#endif
+            rt_thread_delay(RT_TICK_PER_SECOND);
+        }
+    }
+    return 0;
+}
+
+int mnt_init(void)
+{
+#ifdef RT_USING_FAL
+    {
+        rt_thread_t thread = NULL;
+
+        rt_pin_mode(SD_CHECK_PIN, PIN_MODE_INPUT_PULLUP);
+
+        thread = rt_thread_create("sd", sd_check_thread_entry, NULL, 4096, 21, 10);
+        if (thread == NULL)
+        {
+            return -1;
+        }
+        rt_thread_startup(thread);
+    }
+#endif
+    return 0;
+}
+INIT_ENV_EXPORT(mnt_init);
+#endif

bsp/allwinner/d1s/board/SConscript

@@ -0,0 +1,19 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+objs = [group]
+
+list = os.listdir(cwd)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

bsp/allwinner/d1s/board/board.c

@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-01-30     lizhirui     first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "tick.h"
+
+#include "drv_uart.h"
+#include "encoding.h"
+#include "stack.h"
+#include "sbi.h"
+#include "riscv.h"
+#include "stack.h"
+
+#include "hal_gpio.h"
+#include "hal_clk.h"
+#include "hal_uart.h"
+#include "hal_dma.h"
+
+#ifdef RT_USING_USERSPACE
+#include "riscv_mmu.h"
+#include "mmu.h"
+#include "page.h"
+#include "lwp_arch.h"
+
+// 这个结构体描述了buddy system的页分配范围
+rt_region_t init_page_region =
+    {
+        (rt_size_t)RT_HW_PAGE_START,
+        (rt_size_t)RT_HW_PAGE_END};
+
+// 内核页表
+volatile rt_size_t MMUTable[__SIZE(VPN2_BIT)] __attribute__((aligned(4 * 1024)));
+rt_mmu_info mmu_info;
+
+#endif
+
+// 初始化BSS节区
+void init_bss(void)
+{
+    unsigned int *dst;
+
+    dst = &__bss_start;
+    while (dst < &__bss_end)
+    {
+        *dst++ = 0;
+    }
+}
+
+static void __rt_assert_handler(const char *ex_string, const char *func, rt_size_t line)
+{
+    rt_kprintf("(%s) assertion failed at function:%s, line number:%d \n", ex_string, func, line);
+    asm volatile("ebreak" ::
+                     : "memory");
+}
+
+// BSP的C入口
+void primary_cpu_entry(void)
+{
+    extern void entry(void);
+
+    // 初始化BSS
+    init_bss();
+    // 关中断
+    rt_hw_interrupt_disable();
+    rt_assert_set_hook(__rt_assert_handler);
+    // 启动RT-Thread Smart内核
+    entry();
+}
+
+// 这个初始化程序由内核主动调用，此时调度器还未启动，因此在此不能使用依赖线程上下文的函数
+void rt_hw_board_init(void)
+{
+#ifdef RT_USING_USERSPACE
+    rt_page_init(init_page_region);
+    rt_hw_mmu_map_init(&mmu_info, (void *)USER_VADDR_START, USER_VADDR_TOP - USER_VADDR_START, (rt_size_t *)MMUTable, 0);
+    rt_hw_mmu_kernel_map_init(&mmu_info, 0x00000000UL, USER_VADDR_START - 1);
+    // 将低1GB MMIO区域设置为无Cache与Strong Order访存模式
+    MMUTable[0] &= ~PTE_CACHE;
+    MMUTable[0] &= ~PTE_SHARE;
+    MMUTable[0] |= PTE_SO;
+    rt_hw_mmu_switch((void *)MMUTable);
+#endif
+    /* initalize interrupt */
+    rt_hw_interrupt_init();
+#ifdef RT_USING_HEAP
+    rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t)RT_HW_HEAP_BEGIN, (rt_ubase_t)RT_HW_HEAP_END);
+    /* initialize memory system */
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+    /* init hal hardware */
+    hal_clock_init();
+    hal_gpio_init();
+    hal_dma_init();
+
+    /* init rtthread hardware */
+    rt_hw_uart_init();
+    rt_hw_tick_init();
+
+#ifdef RT_USING_CONSOLE
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif /* RT_USING_CONSOLE */
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}

bsp/allwinner/d1s/board/board.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-01-30     lizhirui     first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <rtconfig.h>
+
+extern unsigned int __bss_start;
+extern unsigned int __bss_end;
+
+#define RAM_SIZE    (64 * 1024 * 1024)
+#define RAM_BASE    (0x40000000)
+#define RAM_END     (RAM_BASE + RAM_SIZE)
+
+#define RT_HW_HEAP_BEGIN    ((void *)&__bss_end)
+#define RT_HW_HEAP_END      ((void *)(((rt_size_t)RT_HW_HEAP_BEGIN) + 16 * 1024 * 1024))
+#define RT_HW_PAGE_START RT_HW_HEAP_END
+#define RT_HW_PAGE_END ((void *)(RAM_END))
+
+void rt_hw_board_init(void);
+void rt_init_user_mem(struct rt_thread *thread, const char *name, unsigned long *entry);
+
+#endif

bsp/allwinner/d1s/link.lds

@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/12     bernard      The first version
+ */
+
+INCLUDE "link_stacksize.lds"
+
+OUTPUT_ARCH( "riscv" )
+
+/*
+ * Memory layout:
+ * 0x10200000 - 0x10201000: Bootloader
+ * 0x10201000 - 0x10A00000: Kernel
+ * 0x10A00000 - 0x11200000: Heap
+ */
+
+MEMORY
+{
+   SRAM : ORIGIN = 0x40400000, LENGTH = 60M
+}
+
+ENTRY(_start)
+SECTIONS
+{
+    . = 0x40400000 ;
+
+    /* __STACKSIZE__ = 4096; */
+
+    .start :
+    {
+        *(.start);
+    } > SRAM
+
+    . = ALIGN(8);
+
+    .text :
+    {
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(8);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(8);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(8);
+
+        /* section information for initial. */
+        . = ALIGN(8);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(8);
+
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+        . = ALIGN(8);
+        _etext = .;
+    } > SRAM
+
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
+         *(.eh_frame_entry)
+    } > SRAM
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
+
+    . = ALIGN(8);
+
+    .data :
+    {
+        *(.data)
+        *(.data.*)
+
+        *(.data1)
+        *(.data1.*)
+
+        . = ALIGN(8);
+        PROVIDE( __global_pointer$ = . + 0x800 );
+
+        *(.sdata)
+        *(.sdata.*)
+    } > SRAM
+
+    . = ALIGN(8);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+    } > SRAM
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE(__dtors_end__ = .);
+    } > SRAM
+
+    /* stack for dual core */
+    .stack :
+    {
+        . = ALIGN(64);
+        __stack_start__ = .;
+
+        . += __STACKSIZE__;
+        __stack_cpu0 = .;
+
+        . += __STACKSIZE__;
+        __stack_cpu1 = .;
+    } > SRAM
+
+    . = ALIGN(8);
+
+    .osdebug :
+    {
+        _osdebug_start = .;
+        . += 87K;
+        _osdebug_end = .;
+    } > SRAM
+
+    . = ALIGN(8);
+
+    .sbss :
+    {
+    __bss_start = .;
+        *(.sbss)
+        *(.sbss.*)
+        *(.dynsbss)
+        *(.scommon)
+    } > SRAM
+
+    .bss :
+    {
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        *(COMMON)
+    __bss_end = .;
+    } > SRAM
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/allwinner/d1s/link_stacksize.lds

@@ -0,0 +1 @@
+__STACKSIZE__ = 16384;

bsp/allwinner/d1s/mksdimg.sh

@@ -0,0 +1,5 @@
+#/bin/sh
+./mkimage -T sunxi_toc1 -d toc1.cfg sd.bin
+# offset: 8K of spl，+48K of toc1
+#sudo dd if=boot0_sdcard_sun20iw1p1_d1s.bin of=/dev/sdb bs=1024 seek=8
+#sudo dd if=sd.bin of=/dev/sdb bs=1024 seek=56

bsp/allwinner/d1s/ports/SConscript

@@ -0,0 +1,12 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+list = os.listdir(cwd)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

bsp/allwinner/d1s/ports/fal/SConscript

@@ -0,0 +1,23 @@
+
+from building import *
+import rtconfig
+
+cwd     = GetCurrentDir()
+
+src = []
+
+src     += Glob('*.c')
+if not GetDepend('BSP_USING_NORFLASH'):
+    SrcRemove(src, ['fal_norflash_sfud_port.c'])
+
+CPPPATH = [cwd]
+LOCAL_CCFLAGS = ''
+
+if rtconfig.CROSS_TOOL == 'gcc':
+    LOCAL_CCFLAGS += ' -std=c99'
+elif rtconfig.CROSS_TOOL == 'keil':
+    LOCAL_CCFLAGS += ' --c99'
+
+group = DefineGroup('fal', src, depend = ['RT_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CCFLAGS = LOCAL_CCFLAGS)
+
+Return('group')

bsp/allwinner/d1s/ports/fal/fal_cfg.h

@@ -0,0 +1,51 @@
+/*
+ * File      : fal_cfg.h
+ * This file is part of FAL (Flash Abstraction Layer) package
+ * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-17     armink       the first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtconfig.h>
+#include <board.h>
+
+#define NOR_FLASH_DEV_NAME             "norflash0"
+
+/* ===================== Flash device Configuration ========================= */
+//extern const struct fal_flash_dev stm32f2_onchip_flash;
+extern struct fal_flash_dev sd_card;
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &sd_card,                                                        \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                              \
+{                                                                                   \
+    {FAL_PART_MAGIC_WORD, "download",   "sdcard0",  0x800000,   8*1024*1024, 0},    \
+    {FAL_PART_MAGIC_WORD, "easyflash",  "sdcard0",  0x1000000,  1*1024*1024, 0},    \
+    {FAL_PART_MAGIC_WORD, "filesystem", "sdcard0",  0x1100000,  12*1024*1024, 0},   \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */

bsp/allwinner/d1s/ports/fal/fal_init.c

@@ -0,0 +1,8 @@
+#include <rtthread.h>
+#include <fal.h>
+
+int fal_init_auto(void)
+{
+    return fal_init();
+}
+INIT_COMPONENT_EXPORT(fal_init_auto);

bsp/allwinner/d1s/ports/fal/fal_norflash_sfud_port.c

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-26     RT-Thread    the first version
+ */
+
+#include <rtconfig.h>
+#ifdef RT_USING_FAL
+#include <rthw.h>
+
+#include <fal.h>
+#include <sfud.h>
+
+static int init(void);
+static int read(long offset, uint8_t *buf, size_t size);
+static int write(long offset, const uint8_t *buf, size_t size);
+static int erase(long offset, size_t size);
+
+extern sfud_flash sfud_norflash0;
+struct fal_flash_dev nor_flash0 =
+{
+    "norflash0",
+     0,
+     16 * 1024 * 1024,
+     4096,
+     {init, read, write, erase}
+};
+
+static int read(long offset, uint8_t *buf, size_t size)
+{
+    sfud_read(&sfud_norflash0, nor_flash0.addr + offset, size, buf);
+    return size;
+}
+
+static int write(long offset, const uint8_t *buf, size_t size)
+{
+    if (sfud_write(&sfud_norflash0, nor_flash0.addr + offset, size, buf) != SFUD_SUCCESS)
+    {
+        return -1;
+    }
+
+    return size;
+}
+
+static int erase(long offset, size_t size)
+{
+    if (sfud_erase(&sfud_norflash0, nor_flash0.addr + offset, size) != SFUD_SUCCESS)
+    {
+        return -1;
+    }
+
+    return size;
+}
+
+static int init(void)
+{
+    nor_flash0.len = sfud_norflash0.chip.capacity;
+    nor_flash0.blk_size = sfud_norflash0.chip.erase_gran;
+
+    return 0;
+}
+
+#endif

bsp/allwinner/d1s/ports/fal/fal_sd_sfud_port.c

@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-26     armink       the first version
+ */
+
+#include <fal.h>
+#include <rthw.h>
+#include <rtthread.h>
+#include <dfs_fs.h>
+
+#ifdef BSP_USING_SDMMC
+#include "drv_sdmmc.h"
+
+rt_device_t sd_dev;
+#define SECTOR_SIZE 512
+static int init(void);
+static int read(long offset, uint8_t *buf, size_t size);
+static int write(long offset, const uint8_t *buf, size_t size);
+static int erase(long offset, size_t size);
+
+struct fal_flash_dev sd_card = {
+    "sdcard0",  /* name string match yml file */
+    0,
+    128 * 1024 * 1024,
+    512,
+    {init, read, write, erase}
+};
+
+static int read(long offset, uint8_t *buf, size_t size)
+{
+    rt_size_t sector_pos;
+    rt_size_t sector_offset;
+    rt_size_t remain_size = size;
+    rt_size_t req_size;
+    ALIGN(4) uint8_t buffer[SECTOR_SIZE];
+
+    while (remain_size)
+    {
+        sector_offset = offset & (SECTOR_SIZE - 1);  //块内偏移
+        sector_pos = offset / SECTOR_SIZE;          //块位置
+        rt_device_read(sd_dev, sector_pos, buffer, SECTOR_SIZE / 512);  //读取一个块
+        req_size = (SECTOR_SIZE - sector_offset) > remain_size ? remain_size : (SECTOR_SIZE - sector_offset);
+        memcpy(buf, buffer + sector_offset, req_size);
+        buf += req_size;
+        offset += req_size;
+        remain_size -= req_size;
+    }
+
+    return size;
+}
+
+static int write(long offset, const uint8_t *buf, size_t size)
+{
+    rt_size_t sector_pos;
+    rt_size_t sector_offset;
+    rt_size_t remain_size = size;
+    rt_size_t req_size;
+    ALIGN(4) uint8_t buffer[SECTOR_SIZE];
+
+    while (remain_size)
+    {
+        sector_offset = offset & (SECTOR_SIZE - 1);  //块内偏移
+        sector_pos = offset / SECTOR_SIZE;          //块位置
+
+        rt_device_read(sd_dev, sector_pos, buffer, SECTOR_SIZE / 512);  //读取一个块
+        req_size = (SECTOR_SIZE - sector_offset) > remain_size ? remain_size : (SECTOR_SIZE - sector_offset);
+        memcpy(buffer + sector_offset, buf, req_size);
+        rt_device_write(sd_dev, sector_pos, buffer, SECTOR_SIZE / 512); //写回sd卡
+        buf += req_size;
+        offset += req_size;
+        remain_size -= req_size;
+    }
+
+    return size;
+}
+
+static int erase(long offset, size_t size)
+{
+    return size;
+}
+
+static int init(void)
+{
+    sd_dev = rt_device_find("sdmmc0");
+    if (RT_NULL == sd_dev)
+    {
+        return -1;
+    }
+    rt_device_open(sd_dev, RT_DEVICE_OFLAG_RDWR);
+    struct dev_sdmmc *dev_sdmmc = (struct dev_sdmmc *)sd_dev->user_data;
+    sd_card.len = (size_t)dev_sdmmc->geometry.bytes_per_sector * dev_sdmmc->geometry.sector_count;
+    sd_card.blk_size = dev_sdmmc->geometry.bytes_per_sector;
+
+    return 0;
+}
+#endif

bsp/allwinner/d1s/ports/partition/SConscript

@@ -0,0 +1,11 @@
+from building import *
+import rtconfig
+
+cwd = GetCurrentDir()
+
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('partition', src, depend = ['BSP_USING_SDMMC'], CPPPATH = CPPPATH)
+
+Return('group')

bsp/allwinner/d1s/ports/partition/partition.c

@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016-09-20     Bernard      the first version
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "partition.h"
+
+// #define PARTITION_DEBUG
+
+#ifdef PARTITION_DEBUG
+#define DEBUG_TRACE         rt_kprintf("[part] "); rt_kprintf
+#else
+#define DEBUG_TRACE(...)
+#endif
+
+struct partition_device
+{
+    struct rt_device parent;            /* parent block device */
+
+    int sector_size;
+    int block_size;
+
+    struct rt_device *block_device;
+    const struct rt_partition *partition;
+};
+
+/* RT-Thread device interface */
+static rt_err_t partition_init(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_err_t partition_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+static rt_err_t partition_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+#if RTTHREAD_VERSION >= 30000
+static rt_err_t partition_control(rt_device_t dev, int cmd, void *args)
+#else
+static rt_err_t partition_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+#endif
+{
+    struct partition_device *part;
+
+    part = (struct partition_device*) dev;
+    RT_ASSERT(part != RT_NULL);
+
+    if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
+    {
+        struct rt_device_blk_geometry *geometry;
+
+        geometry = (struct rt_device_blk_geometry *)args;
+        if (geometry == RT_NULL) return -RT_ERROR;
+
+        geometry->bytes_per_sector = part->sector_size;
+        geometry->sector_count = part->partition->size / part->sector_size;
+        geometry->block_size = part->block_size;
+    }
+
+    return RT_EOK;
+}
+
+static rt_size_t partition_read(rt_device_t dev,
+                                   rt_off_t pos,
+                                   void* buffer,
+                                   rt_size_t size)
+{
+    struct partition_device *part;
+
+    part = (struct partition_device*) dev;
+    RT_ASSERT(part != RT_NULL);
+
+    DEBUG_TRACE("read block: %d, size=%d\n", pos + part->partition->offset/part->sector_size, size);
+
+    return rt_device_read(part->block_device, pos + part->partition->offset/part->sector_size, buffer, size);
+}
+
+static rt_size_t partition_write(rt_device_t dev,
+                                    rt_off_t pos,
+                                    const void* buffer,
+                                    rt_size_t size)
+{
+    struct partition_device *part;
+
+    part = (struct partition_device*) dev;
+    RT_ASSERT(part != RT_NULL);
+
+    if (part->partition->flags & PARTITION_WRITEABLE)
+    {
+        DEBUG_TRACE("write block: %d, size=%d\n", pos + part->partition->offset/part->sector_size, size);
+
+        return rt_device_write(part->block_device, pos + part->partition->offset/part->sector_size,
+                buffer, size);
+    }
+
+    DEBUG_TRACE("read-only partition!\n");
+    return 0;
+}
+
+int rt_partition_init(const char* flash_device, const struct rt_partition* parts, rt_size_t num)
+{
+    struct rt_device *device;
+    struct partition_device *part_dev;
+    const struct rt_partition* part;
+    struct rt_device_blk_geometry geometry;
+
+    device = (struct rt_device *)rt_device_find(flash_device);
+    if(device == RT_NULL)
+    {
+        DEBUG_TRACE("block device %s not found!\r\n", flash_device);
+        return -RT_ENOSYS;
+    }
+
+    /* open the block device */
+    rt_device_open(device, RT_DEVICE_OFLAG_RDWR);
+    /* get block device geometry */
+    rt_device_control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry);
+
+    /* create each partition device */
+    while(num --)
+    {
+        part = parts ++;
+        part_dev = (struct partition_device*)rt_malloc (sizeof(struct partition_device));
+        if (part_dev)
+        {
+            part_dev->block_device = device;
+            part_dev->partition = part;
+            part_dev->sector_size = geometry.bytes_per_sector;
+            part_dev->block_size  = geometry.block_size;
+
+            /* register device */
+            part_dev->parent.type    = RT_Device_Class_Block;
+            part_dev->parent.init    = partition_init;
+            part_dev->parent.open    = partition_open;
+            part_dev->parent.close   = partition_close;
+            part_dev->parent.read    = partition_read;
+            part_dev->parent.write   = partition_write;
+            part_dev->parent.control = partition_control;
+            /* no private */
+            part_dev->parent.user_data = RT_NULL;
+
+            DEBUG_TRACE("add partition: %s\n", part->name);
+            rt_device_register(RT_DEVICE(part_dev), part->name,
+                               RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
+        }
+    }
+
+    return RT_EOK;
+}

bsp/allwinner/d1s/ports/partition/partition.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016-09-20     Bernard      the first version
+ */
+
+#ifndef PARTITION_H__
+#define PARTITION_H__
+
+#define PARTITION_RDONLY          0x000
+#define PARTITION_WRITEABLE       0x100     /* Device is writable */
+#define PARTITION_POWERUP_LOCK    0x200     /* Always locked after reset */
+
+struct rt_partition
+{
+    char name[8];
+
+    rt_uint32_t offset;
+    rt_uint32_t size;
+
+    rt_uint32_t flags;
+};
+
+int rt_partition_init(const char* flash_device, const struct rt_partition* parts, rt_size_t num);
+
+#endif

bsp/allwinner/d1s/ports/wifi/SConscript

@@ -0,0 +1,11 @@
+from building import *
+import rtconfig
+
+cwd = GetCurrentDir()
+
+src = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+group = DefineGroup('rw007', src, depend = ['PKG_USING_RW007'], CPPPATH = CPPPATH)
+
+Return('group')

bsp/allwinner/d1s/ports/wifi/rw007_pin_port.c

@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-04     RT-Thread    the first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <drv_spi.h>
+#include <board.h>
+#include <drv_pin.h>
+#include <spi_wifi_rw007.h>
+
+#define DBG_ENABLE
+#define DBG_SECTION_NAME "RW007_PORT"
+#define DBG_LEVEL DBG_LOG
+#include <rtdbg.h>
+
+#define SPI_BUS_NAME "spi0"
+#define SPI_DEV_NAME "spi01"
+#define INT_BUSY_PIN GET_PIN(GPIO_PORT_G, GPIO_PIN_4) //PG4
+#define RESET_PIN GET_PIN(GPIO_PORT_G, GPIO_PIN_5)    //PF4
+
+#define RW007_WORKING_STATION_MODE
+
+extern void spi_wifi_isr(int vector);
+
+static void rw007_gpio_init(void)
+{
+    rt_pin_mode(RESET_PIN, PIN_MODE_OUTPUT);
+    rt_pin_mode(INT_BUSY_PIN, PIN_MODE_INPUT);
+
+    rt_pin_write(RESET_PIN, PIN_LOW);
+    rt_thread_delay(rt_tick_from_millisecond(100));
+    rt_pin_write(RESET_PIN, PIN_HIGH);
+
+    while (!rt_pin_read(INT_BUSY_PIN))
+    {
+        rt_thread_delay(5);
+    }
+
+    rt_thread_delay(rt_tick_from_millisecond(200)); //Time-delay waiting device activated
+    rt_pin_mode(INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP);
+}
+
+static void _rw007_int(int argc, char *args[])
+{
+    int v;
+
+    v = atoi(args[1]);
+
+    rt_pin_mode(RESET_PIN, PIN_MODE_OUTPUT);
+    rt_pin_write(RESET_PIN, v);
+}
+MSH_CMD_EXPORT_ALIAS(_rw007_int, _rw007_int, rw007 int pin);
+
+static void _rw007_reset(void)
+{
+    rt_pin_mode(RESET_PIN, PIN_MODE_OUTPUT);
+    rt_pin_write(RESET_PIN, PIN_LOW);
+    rt_thread_delay(rt_tick_from_millisecond(100));
+    rt_pin_write(RESET_PIN, PIN_HIGH);
+}
+MSH_CMD_EXPORT_ALIAS(_rw007_reset, rw007_reset, rw007 reset);
+
+void wifi_init_thread_entry(void *p)
+{
+    char sn_version[32];
+
+    rw007_gpio_init();
+
+#ifdef PKG_USING_DM9051
+    extern int dm9051_auto_init(void);
+    dm9051_auto_init();
+#endif
+
+    rt_hw_wifi_init(SPI_DEV_NAME);
+#ifdef RW007_WORKING_STATION_MODE
+    rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION);
+#else
+    rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP);
+#endif
+
+    if (rw007_sn_get(sn_version) != RT_EOK)
+    {
+        LOG_E("rw007 get sn fail !!!");
+    }
+    LOG_I("rw007  sn: [%s]", sn_version);
+
+    if (rw007_version_get(sn_version) != RT_EOK)
+    {
+        LOG_E("rw007 get version fail !!!");
+    }
+    LOG_I("rw007 ver: [%s]", sn_version);
+
+    rt_thread_mdelay(1000);
+}
+
+int rt_rw007_init(void)
+{
+    rt_thread_t thread = NULL;
+
+    thread = rt_thread_create("wifi_init", wifi_init_thread_entry, NULL, 4096, 15, 10);
+    if (thread == NULL)
+    {
+        return -1;
+    }
+
+    return rt_thread_startup(thread);
+}
+#ifdef BSP_USING_SPI0
+INIT_COMPONENT_EXPORT(rt_rw007_init);
+// MSH_CMD_EXPORT_ALIAS(rt_rw007_init, rw007_init, rw007 init);
+#endif
+
+static void int_wifi_irq(void *p)
+{
+    ((void)p);
+    spi_wifi_isr(0);
+}
+
+void spi_wifi_hw_init(void)
+{
+    rt_pin_mode(INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP);
+    rt_pin_attach_irq(INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0);
+    rt_pin_irq_enable(INT_BUSY_PIN, RT_TRUE);
+}

bsp/allwinner/d1s/rtconfig.h

@@ -0,0 +1,348 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 20
+#define RT_USING_SMART
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 16384
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 16384
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_KPRINTF_USING_LONGLONG
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_MEMTRACE
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 256
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50000
+#define ARCH_CPU_64BIT
+#define RT_USING_CACHE
+#define ARCH_MM_MMU
+#define RT_USING_USERSPACE
+#define KERNEL_VADDR_START 0x150000000
+#define PV_OFFSET 0
+#define ARCH_RISCV
+#define ARCH_RISCV64
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 16384
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 8192
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 8
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define DFS_FD_MAX 32
+#define RT_USING_DFS_ELMFAT
+
+/* elm-chan's FatFs, Generic FAT Filesystem Module */
+
+#define RT_DFS_ELM_CODE_PAGE 936
+#define RT_DFS_ELM_WORD_ACCESS
+#define RT_DFS_ELM_USE_LFN_3
+#define RT_DFS_ELM_USE_LFN 3
+#define RT_DFS_ELM_LFN_UNICODE_0
+#define RT_DFS_ELM_LFN_UNICODE 0
+#define RT_DFS_ELM_MAX_LFN 255
+#define RT_DFS_ELM_DRIVES 8
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+#define RT_DFS_ELM_REENTRANT
+#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
+#define RT_USING_DFS_DEVFS
+#define RT_USING_FAL
+#define FAL_DEBUG_CONFIG
+#define FAL_DEBUG 1
+#define FAL_PART_HAS_TABLE_CFG
+#define RT_USING_LWP
+#define RT_LWP_MAX_NR 30
+#define LWP_TASK_STACK_SIZE 16384
+#define RT_CH_MSG_MAX_NR 1024
+#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
+#define LWP_TID_MAX_NR 64
+#define RT_LWP_SHM_MAX_NR 64
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V2
+#define RT_USING_TTY
+#define RT_USING_PIN
+#define RT_USING_NULL
+#define RT_USING_ZERO
+#define RT_USING_RANDOM
+#define RT_USING_RTC
+#define RT_USING_WDT
+#define RT_USING_DEV_BUS
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+#define RT_USING_POSIX_FS
+#define RT_USING_POSIX_DEVIO
+#define RT_USING_POSIX_STDIO
+#define RT_USING_POSIX_POLL
+#define RT_USING_POSIX_SELECT
+#define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_DELAY
+#define RT_USING_POSIX_CLOCK
+
+/* Interprocess Communication (IPC) */
+
+#define RT_USING_POSIX_PIPE
+#define RT_USING_POSIX_PIPE_SIZE 512
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Sensor libraries */
+
+
+/* Display libraries */
+
+
+/* Timing libraries */
+
+
+/* Project libraries */
+
+#define BOARD_allwinnerd1s
+#define ENABLE_FPU
+#define __STACKSIZE__ 16384
+
+/* General Drivers Configuration */
+
+#define BSP_USING_M7
+
+/* General Purpose UARTs */
+
+#define BSP_USING_UART0
+#define UART0_TX_USING_GPIOE2
+#define UART0_RX_USING_GPIOE3
+#define BSP_USING_SDMMC
+#define SD_CARD_CHECK
+#define BSP_USING_FS
+
+/* Board extended module Drivers */
+
+#define RT_USING_SUNXI_HAL
+
+/* UART Devices */
+
+
+/* CCMU Devices */
+
+#define DRIVERS_CCMU
+#define DRIVERS_SUNXI_CCU
+
+/* DMA Devices */
+
+#define DRIVERS_DMA
+
+/* GPIO Devices */
+
+#define DRIVERS_GPIO
+
+/* Video support for sunxi */
+
+#define DISP2_SUNXI
+#define SUNXI_DISP2_FB_DISABLE_ROTATE
+
+/* LCD panels select */
+
+#define LCD_SUPPORT_HE0801A068
+#define LCD_SUPPORT_WILLIAMLCD
+#define LCD_SUPPORT_LQ101R1SX03
+#define LCD_SUPPORT_INET_DSI_PANEL
+
+/* Display engine feature select */
+
+#define DISP2_SUNXI_SUPPORT_ENAHNCE
+
+/* Soc and board select */
+
+/* Board Select */
+
+
+/* Soc Select */
+
+
+/* SDMMC Devices */
+
+#define DRIVERS_SDMMC
+#define USE_SD
+#define USE_SDIO
+#define DETECT_CARD
+#define SDC_DMA_USED
+#define SDIO_IRQ_SUPPORT
+#define SDC_DMA_BUF_SIZE 64
+#define DRIVERS_SDC_CDPIN_PRESENT_VAL 0
+
+/* SPI Devices */
+
+#define DRIVERS_SPI
+
+/* TWI Devices */
+
+#define DRIVERS_TWI
+
+/* G2D Devices */
+
+#define DRIVERS_G2D
+
+/* CE Devices */
+
+#define DRIVERS_CE
+
+/* EFUSE Devices */
+
+#define DRIVERS_EFUSE
+
+#endif

bsp/allwinner/d1s/rtconfig.py

@@ -0,0 +1,56 @@
+import os
+
+# toolchains options
+ARCH        ='risc-v'
+VENDOR      ='t-head'
+CPU         ='c906'
+CROSS_TOOL  ='gcc'
+
+RTT_ROOT = os.getenv('RTT_ROOT') or os.path.join(os.getcwd(),'..','..','..')
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/opt/riscv64_musl/bin'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    #PREFIX  = 'riscv64-unknown-elf-'
+    PREFIX  = os.getenv('RTT_CC_PREFIX') or 'riscv64-unknown-linux-musl-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE  = ' -mcmodel=medany -march=rv64imafdc -mabi=lp64'
+    CFLAGS  = DEVICE + ' -fvar-tracking -ffreestanding -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields '
+    AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' + ' -lsupc++ -lgcc -static'
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -ggdb'
+        AFLAGS += ' -ggdb'
+    else:
+        CFLAGS += ' -O2 -Os'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + './mksdimg.sh\n'

bsp/allwinner/d1s/toc1.cfg

@@ -0,0 +1,10 @@
+[opensbi]
+file = sbi.bin
+addr = 0x40000000
+[dtb]
+file = u-boot.dtb
+addr = 0x40200000
+[kernel]
+file = rtthread.bin
+addr = 0x40400000
+

bsp/allwinner/libraries/.gitignore

@@ -0,0 +1,2 @@
+.vscode/
+*.o

bsp/allwinner/libraries/Kconfig

@@ -0,0 +1,18 @@
+menuconfig RT_USING_SUNXI_HAL
+    bool "HAL library from sunxi"
+    default n
+
+if RT_USING_SUNXI_HAL
+    source "$BSP_DIR/../libraries/sunxi-hal/hal/source/uart/Kconfig"
+    source "$BSP_DIR/../libraries/sunxi-hal/hal/source/ccmu/Kconfig"
+    source "$BSP_DIR/../libraries/sunxi-hal/hal/source/dma/Kconfig"
+    source "$BSP_DIR/../libraries/sunxi-hal/hal/source/gpio/Kconfig"
+    source "$BSP_DIR/../libraries/sunxi-hal/hal/source/disp2/Kconfig"
+    source "$BSP_DIR/../libraries/sunxi-hal/hal/source/sdmmc/Kconfig"
+    source "$BSP_DIR/../libraries/sunxi-hal/hal/source/spi/Kconfig"
+    source "$BSP_DIR/../libraries/sunxi-hal/hal/source/twi/Kconfig"
+    source "$BSP_DIR/../libraries/sunxi-hal/hal/source/g2d_rcq/Kconfig"
+    source "$BSP_DIR/../libraries/sunxi-hal/hal/source/usb/Kconfig"
+    source "$BSP_DIR/../libraries/sunxi-hal/hal/source/ce/Kconfig"
+    source "$BSP_DIR/../libraries/sunxi-hal/hal/source/efuse/Kconfig"    
+endif

bsp/allwinner/libraries/README.md

@@ -0,0 +1,3 @@
+# allwinner-libraries
+
+针对全志芯片的外设驱动库

bsp/allwinner/libraries/SConscript

@@ -0,0 +1,18 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+if not GetDepend('RT_USING_SUNXI_HAL'):
+    Return('objs')
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/allwinner/libraries/drivers/Kconfig

@@ -0,0 +1,283 @@
+menu "General Drivers Configuration"
+
+choice
+    prompt "Choose Board"
+
+    default BSP_USING_M7
+
+    config BSP_USING_M7
+        bool "Persimmon M7 board"
+endchoice
+
+menu "General Purpose UARTs"
+
+menuconfig BSP_USING_UART0
+    bool "Enable UART0"
+    default y
+    if BSP_USING_UART0
+        choice
+            prompt "UART0 TX PIN"
+            default UART0_TX_USING_GPIOE2 if BOARD_allwinnerd1s
+            default UART0_TX_USING_GPIOB8 if BOARD_allwinnerd1
+
+            if BOARD_allwinnerd1
+            config UART0_TX_USING_GPIOB8
+                bool "GPIOB08"
+            endif
+            config UART0_TX_USING_GPIOE2
+                bool "GPIOE02"
+            config UART0_TX_USING_GPIOF2
+                bool "GPIOF02"
+        endchoice
+        choice
+            prompt "UART0 RX PIN"
+            default UART0_RX_USING_GPIOE3 if BOARD_allwinnerd1s
+            default UART0_RX_USING_GPIOB9 if BOARD_allwinnerd1
+
+            if BOARD_allwinnerd1
+            config UART0_RX_USING_GPIOB9
+                bool "GPIOB09"
+            endif
+            config UART0_RX_USING_GPIOE3
+                bool "GPIOE03"
+            config UART0_RX_USING_GPIOF4
+                bool "GPIOF04"
+        endchoice
+    endif
+
+menuconfig BSP_USING_UART1
+    bool "Enable UART1"
+    default n
+    if BSP_USING_UART1
+        choice
+            prompt "UART1 TX PIN"
+            config UART1_TX_USING_GPIOD21
+                bool "GPIOD21"
+            config UART1_TX_USING_GPIOE10
+                bool "GPIOE10"
+            config UART1_TX_USING_GPIOG6
+                bool "GPIOG06"
+            config UART1_TX_USING_GPIOG12
+                bool "GPIOG12"
+        endchoice
+        choice
+            prompt "UART1 RX PIN"
+            config UART1_RX_USING_GPIOD22
+                bool "GPIOD22"
+            config UART1_RX_USING_GPIOE11
+                bool "GPIOE11"
+            config UART1_RX_USING_GPIOG7
+                bool "GPIOG07"
+            config UART1_RX_USING_GPIOG13
+                bool "GPIOG13"
+        endchoice
+    endif
+
+menuconfig BSP_USING_UART2
+    bool "Enable UART2"
+    default n
+    if BSP_USING_UART2
+        choice
+            prompt "UART2 TX PIN"
+            config UART2_TX_USING_GPIOD1
+                bool "GPIOD01"
+            config UART2_TX_USING_GPIOE2
+                bool "GPIOE02"
+        endchoice
+        choice
+            prompt "UART2 RX PIN"
+            config UART2_RX_USING_GPIOD2
+                bool "GPIOD02"
+            config UART2_RX_USING_GPIOE3
+                bool "GPIOE03"
+        endchoice
+    endif
+
+menuconfig BSP_USING_UART3
+    bool "Enable UART3"
+    default n
+    if BSP_USING_UART3
+        choice
+            prompt "UART3 TX PIN"
+            config UART3_TX_USING_GPIOB6
+                bool "GPIOB06"
+            config UART3_TX_USING_GPIOC6
+                bool "GPIOC06"
+            config UART3_TX_USING_GPIOD10
+                bool "GPIOD10"
+            config UART3_TX_USING_GPIOE8
+                bool "GPIOE08"
+            config UART3_TX_USING_GPIOG0
+                bool "GPIOG00"
+            config UART3_TX_USING_GPIOG8
+                bool "GPIOG08"
+        endchoice
+        choice
+            prompt "UART3 RX PIN"
+            config UART3_RX_USING_GPIOB7
+                bool "GPIOB07"
+            config UART3_RX_USING_GPIOC7
+                bool "GPIOC07"
+            config UART3_RX_USING_GPIOD11
+                bool "GPIOD11"
+            config UART3_RX_USING_GPIOE9
+                bool "GPIOE09"
+            config UART3_RX_USING_GPIOG1
+                bool "GPIOG01"
+            config UART3_RX_USING_GPIOG9
+                bool "GPIOG09"
+        endchoice
+    endif
+
+menuconfig BSP_USING_UART4
+    bool "Enable UART4"
+    default n
+    if BSP_USING_UART4
+        choice
+            prompt "UART4 TX PIN"
+            config UART4_TX_USING_GPIOB2
+                bool "GPIOB02"
+            config UART4_TX_USING_GPIOD7
+                bool "GPIOD07"
+            config UART4_TX_USING_GPIOE4
+                bool "GPIOE04"
+            config UART4_TX_USING_GPIOG2
+                bool "GPIOG02"
+        endchoice
+        choice
+            prompt "UART4 RX PIN"
+            config UART4_RX_USING_GPIOB3
+                bool "GPIOB03"
+            config UART4_RX_USING_GPIOD8
+                bool "GPIOD08"
+            config UART4_RX_USING_GPIOE5
+                bool "GPIOE05"
+            config UART4_TX_USING_GPIOG3
+                bool "GPIOG03"
+        endchoice
+    endif
+
+menuconfig BSP_USING_UART5
+    bool "Enable UART5"
+    default n
+    if BSP_USING_UART5
+        choice
+            prompt "UART5 TX PIN"
+            config UART5_TX_USING_GPIOB4
+                bool "GPIOB04"
+            config UART5_TX_USING_GPIOD5
+                bool "GPIOD05"
+            config UART5_TX_USING_GPIOE6
+                bool "GPIOE06"
+            config UART5_TX_USING_GPIOG4
+                bool "GPIOG04"
+        endchoice
+        choice
+            prompt "UART5 RX PIN"
+            config UART5_RX_USING_GPIOB5
+                bool "GPIOB05"
+            config UART5_RX_USING_GPIOD6
+                bool "GPIOD06"
+            config UART5_RX_USING_GPIOE7
+                bool "GPIOE07"
+            config UART5_RX_USING_GPIOG5
+                bool "GPIOG05"
+        endchoice
+    endif
+
+endmenu
+
+config BSP_USING_WDT
+    bool "Enable WatchDog Timer"
+    select RT_USING_WDT
+    default n
+
+config BSP_USING_RTC
+    bool "Enable RTC driver"
+    select RT_USING_RTC
+    select BSP_USING_WDT
+    default n
+
+menuconfig BSP_USING_I2C
+    bool "Enable I2C driver"
+    select RT_USING_I2C
+    default n
+
+    if BSP_USING_I2C
+    config BSP_USING_I2C0
+        bool "Enable I2C0"
+        default n
+    config BSP_USING_I2C1
+        bool "Enable I2C1"
+        default n
+    config BSP_USING_I2C2
+        bool "Enable I2C2"
+        default n
+    config BSP_USING_I2C3
+        bool "Enable I2C3"
+        default n
+    endif
+
+menuconfig BSP_USING_TOUCH
+    bool "Enable TOUCH"
+    default n
+    select RT_USING_TOUCH
+    select RT_TOUCH_PIN_IRQ
+    select BSP_USING_I2C
+    select BSP_USING_I2C2
+    if BSP_USING_TOUCH
+    config TOUCH_I2C_NAME
+        string "touch i2c driver name"
+        default "i2c2"
+    endif
+
+menuconfig BSP_USING_SPI
+    bool "Enabel spi driver"
+    default n
+    select RT_USING_SPI
+    if BSP_USING_SPI
+    config BSP_USING_SPI0
+        bool "Enable SPI0"
+        default n
+    config BSP_USING_SPI1
+        bool "Enable SPI1"
+        default n
+    endif
+
+config BSP_USING_PWM
+    bool "Enable pwm driver"
+    default n
+    select RT_USING_PWM
+
+config BSP_USING_SDMMC
+    bool "Enable sdmmc driver"
+    default y
+
+config SD_CARD_CHECK
+    bool "Automatic detection of SD cards"
+    default y
+
+menuconfig BSP_USING_FS
+    bool "Enable File System"
+    select RT_USING_DFS
+    select BSP_USING_SDMMC
+    select RT_USING_FAL
+    select FAL_DEBUG_CONFIG
+    select FAL_PART_HAS_TABLE_CFG
+    default y
+
+menuconfig BSP_USING_LCD
+    bool "Enable LCD"
+    select BSP_USING_PWM
+    default n
+
+menu "Board extended module Drivers"
+    menuconfig BSP_USING_RW007
+        bool "Enable RW007"
+        default n
+        select PKG_USING_RW007
+        select BSP_USING_SPI
+        select BSP_USING_SPI0
+endmenu
+        
+endmenu

bsp/allwinner/libraries/drivers/SConscript

@@ -0,0 +1,39 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = ['drv_uart.c', 'drv_pin.c']
+
+CPPPATH = [cwd]
+
+if GetDepend('BSP_USING_WDT'):
+    src += ['drv_wdt.c']
+
+if GetDepend('BSP_USING_RTC'):
+    src += ['drv_rtc.c']
+
+if GetDepend('BSP_USING_I2C'):
+    src += ['drv_i2c.c']
+
+if GetDepend('BSP_USING_SPI'):
+    src += ['drv_spi.c']
+
+if GetDepend('BSP_USING_PWM'):
+    src += ['drv_pwm.c']
+
+if GetDepend('BSP_USING_LCD'):
+    src += ['drv_lcd.c']
+    src += ['lcd_cfg.c']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+objs = [group]
+
+list = os.listdir(cwd)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

bsp/allwinner/libraries/drivers/drv_i2c.c

@@ -0,0 +1,342 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * 2021-11-19     xieyangrun     first version
+ */
+
+#include <rthw.h>
+#include <rtdevice.h>
+
+#include "sunxi_hal_twi.h"
+
+#define DBG_LVL DBG_WARNING
+#define DBG_TAG "drv/i2c"
+#include <rtdbg.h>
+
+struct hal_i2c_bus
+{
+    struct rt_i2c_bus_device parent;
+    twi_port_t id;
+    struct rt_mutex lock;
+};
+
+//connect am drv to rt drv.
+static rt_size_t _i2c_master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg *msgs, rt_uint32_t num)
+{
+    struct hal_i2c_bus *_i2c_bus = (struct hal_i2c_bus *)bus;
+    struct rt_i2c_msg *msg;
+    twi_msg_t *twi_msg;
+    int i;
+    twi_status_t status;
+    extern twi_status_t hal_twi_xfer(twi_port_t port, twi_msg_t *msgs, int32_t num);
+
+
+    twi_msg = rt_malloc(sizeof(*twi_msg) * num);
+    if (!twi_msg)
+    {
+        LOG_E("i2c xfer malloc(%d) failure\n", sizeof(*twi_msg) * num);
+        return -RT_ENOMEM;
+    }
+
+    for (i = 0; i < num; i++)
+    {
+        msg = &msgs[i];
+        if (msg->flags == RT_I2C_RD)
+        {
+            twi_msg[i].flags = TWI_M_RD;
+        }
+        else if(msg->flags == RT_I2C_WR)
+        {
+            twi_msg[i].flags = 0;
+        }
+
+        if (_i2c_bus->parent.flags & RT_I2C_DEV_CTRL_10BIT)
+        {
+            twi_msg[i].flags |= TWI_M_TEN;
+        }
+
+        twi_msg[i].addr = msg->addr;
+        twi_msg[i].len = msg->len;
+        twi_msg[i].buf = msg->buf;
+    }
+
+    rt_mutex_take(&_i2c_bus->lock, RT_WAITING_FOREVER);
+    status = hal_twi_xfer(_i2c_bus->id, twi_msg, i);
+    rt_mutex_release(&_i2c_bus->lock);
+
+    if (status != TWI_STATUS_OK)
+    {
+        i = 0;
+        LOG_E("i2c xfer failure\n");
+    }
+
+    rt_free(twi_msg);
+
+    return i;
+}
+
+static const struct rt_i2c_bus_device_ops _i2c_ops =
+{
+    _i2c_master_xfer,
+    RT_NULL,
+    RT_NULL
+};
+
+#ifdef BSP_USING_I2C0
+static struct hal_i2c_bus _i2c_bus_0 = {
+    .id = TWI_MASTER_0
+};
+#endif
+
+#ifdef BSP_USING_I2C1
+static struct hal_i2c_bus _i2c_bus_1 = {
+    .id = TWI_MASTER_1,
+};
+#endif
+
+#ifdef BSP_USING_I2C2
+static struct hal_i2c_bus _i2c_bus_2 = {
+    .id = TWI_MASTER_2,
+};
+#endif
+
+#ifdef BSP_USING_I2C3
+static struct hal_i2c_bus _i2c_bus_3 = {
+    .id = TWI_MASTER_3,
+};
+#endif
+
+#define CFG_GPIO_PORT(p) ((p) - 'A' + 1)
+
+static const user_gpio_set_t _i2c_gpio_cfg[][2] = {
+    {// twi0
+        {
+            .gpio_name = "twi0.sck",
+            .port = CFG_GPIO_PORT('B'),
+            .port_num = 3, // PB3
+            .mul_sel = 4,
+            .pull = 1, // pull up
+            .drv_level = 3,
+            .data = 1,
+        },
+        {
+            .gpio_name = "twi0.sda",
+            .port = CFG_GPIO_PORT('B'),
+            .port_num = 2, // PB2
+            .mul_sel = 4,
+            .pull = 1, // pull up
+            .drv_level = 3,
+            .data = 1,
+        }
+    },
+    {// twi1
+        {
+            .gpio_name = "twi1.sck",
+            .port = CFG_GPIO_PORT('B'),
+            .port_num = 4, // PB4
+            .mul_sel = 4,
+            .pull = 1, // pull up
+            .drv_level = 3,
+            .data = 1,
+        },
+        {
+            .gpio_name = "twi1.sda",
+            .port = CFG_GPIO_PORT('B'),
+            .port_num = 5, // PB5
+            .mul_sel = 4,
+            .pull = 1, // pull up
+            .drv_level = 3,
+            .data = 1,
+        }
+    },
+#ifdef BSP_USING_MANGOPI // mango board
+    {// twi2
+        {
+            .gpio_name = "twi2.sck",
+            .port = CFG_GPIO_PORT('E'),
+            .port_num = 12, // PE12
+            .mul_sel = 2,
+            .pull = 1, // pull up
+            .drv_level = 3,
+            .data = 1,
+        },
+        {
+            .gpio_name = "twi2.sda",
+            .port = CFG_GPIO_PORT('E'),
+            .port_num = 13, // PE13
+            .mul_sel = 2,
+            .pull = 1, // pull up
+            .drv_level = 3,
+            .data = 1,
+        }
+    },
+#elif defined(BSP_USING_M7)
+    {// twi2
+        {
+            .gpio_name = "twi2.sck",
+            .port = CFG_GPIO_PORT('G'),
+            .port_num = 6, // PG6
+            .mul_sel = 3,
+            .pull = 1, // pull up
+            .drv_level = 3,
+            .data = 1,
+        },
+        {
+            .gpio_name = "twi2.sda",
+            .port = CFG_GPIO_PORT('G'),
+            .port_num = 7, // PG7
+            .mul_sel = 3,
+            .pull = 1, // pull up
+            .drv_level = 3,
+            .data = 1,
+        }
+    },
+#endif
+    {// twi3
+        {
+            .gpio_name = "twi3.sck",
+            .port = CFG_GPIO_PORT('B'),
+            .port_num = 6, // PB6
+            .mul_sel = 4,
+            .pull = 1, // pull up
+            .drv_level = 3,
+            .data = 1,
+        },
+        {
+            .gpio_name = "twi3.sda",
+            .port = CFG_GPIO_PORT('B'),
+            .port_num = 7, // PB7
+            .mul_sel = 4,
+            .pull = 1, // pull up
+            .drv_level = 3,
+            .data = 1,
+        }
+    },
+};
+
+int hal_i2c_gpio_cfg_load(user_gpio_set_t *gpio_cfg, int32_t GPIONum, int id)
+{
+    int i;
+
+    if (id > sizeof(_i2c_gpio_cfg) / sizeof(_i2c_gpio_cfg[0]))
+    {
+        rt_kprintf("twi id %d>%d\n", id, sizeof(_i2c_gpio_cfg) / sizeof(_i2c_gpio_cfg[0]));
+        return -1;
+    }
+
+    /* twi0 */
+    for (i = 0; i < GPIONum; i++)
+    {
+        memcpy(gpio_cfg, &_i2c_gpio_cfg[id][i], sizeof(user_gpio_set_t));
+        gpio_cfg++;
+    }
+
+    return 0;
+}
+
+static int _i2c_dev_register(struct hal_i2c_bus* bus, const char* name)
+{
+    rt_mutex_init(&bus->lock, name, RT_IPC_FLAG_PRIO);
+
+    hal_twi_init(bus->id);
+    bus->parent.ops = &_i2c_ops;
+
+    if (rt_i2c_bus_device_register(&bus->parent, name) != RT_EOK)
+    {
+        LOG_E("i2c bus register:%s failure\n", name);
+        return -1;
+    }
+
+    return 0;
+}
+
+int rt_hw_i2c_init(void)
+{
+#ifdef BSP_USING_I2C0
+    /* init i2c bus device */
+    _i2c_dev_register(&_i2c_bus_0, "i2c0");
+#endif
+
+#ifdef BSP_USING_I2C1
+    /* init i2c bus device */
+    _i2c_dev_register(&_i2c_bus_1, "i2c1");
+#endif
+
+#ifdef BSP_USING_I2C2
+    _i2c_dev_register(&_i2c_bus_2, "i2c2");
+#endif
+
+#ifdef BSP_USING_I2C3
+    _i2c_dev_register(&_i2c_bus_3, "i2c3");
+#endif
+
+    //rt_kprintf("i2c_init!\n");
+
+    return 0;
+}
+// #ifdef RT_USING_COMPONENTS_INIT
+INIT_BOARD_EXPORT(rt_hw_i2c_init);
+// #endif
+
+static void _i2c_test(int argc, char *args[])
+{
+    struct rt_i2c_bus_device *i2c_bus;
+    struct rt_i2c_msg msg[2];
+    uint8_t buf[3] = {0x12, 0x34, 0x56};
+
+    if (argc < 2) return;
+
+    i2c_bus = (struct rt_i2c_bus_device*)rt_device_find("i2c2");
+    if (!i2c_bus)
+    {
+        rt_kprintf("i2c2 not found\n");
+        return;
+    }
+
+    msg[0].addr = 0x36;
+    msg[0].flags = 0;
+    msg[0].buf = buf;
+    msg[0].len = sizeof(buf);
+
+    msg[1].addr = 0x36;
+    msg[1].flags = RT_I2C_RD;
+    msg[1].buf = buf;
+    msg[1].len = sizeof(buf);
+
+    if (atoi(args[1]) == 0)
+    {
+        rt_i2c_transfer(i2c_bus, &msg[0], 1);
+    }
+    else
+    {
+        rt_i2c_transfer(i2c_bus, &msg[0], 2);
+    }
+}
+MSH_CMD_EXPORT_ALIAS(_i2c_test, i2c_test, i2c bus test);
+
+static void _pin_test(void)
+{
+    int i;
+    rt_base_t pin;
+
+    pin = GPIO_PE10;
+
+    rt_pin_mode(pin, PIN_MODE_OUTPUT);
+
+    for (i = 0; i < 20; i++)
+    {
+        rt_pin_write(pin, !!(i & 1));
+        rt_thread_mdelay(2);
+    }
+}
+MSH_CMD_EXPORT_ALIAS(_pin_test, pin_test, gpio pin test);
+
+/*@}*/
+
+
+
+
+

bsp/allwinner/libraries/drivers/drv_lcd.c

@@ -0,0 +1,703 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-04-12     RT-Thread    the first version
+ */
+
+#include "rtthread.h"
+#include <rthw.h>
+#include <string.h>
+#include <stdatomic.h>
+
+#include "interrupt.h"
+#include "mmu.h"
+#include "cache.h"
+
+#ifdef BSP_USING_LCD
+
+#include "drv_lcd.h"
+#include "lcd_cfg.h"
+
+#ifdef RT_USING_USERSPACE
+#include <page.h>
+#include <lwp_user_mm.h>
+#endif
+
+#include <video/sunxi_display2.h>
+#include "dev_disp.h"
+
+#define DEFAULT_SCREEN (0)
+
+#define LCD_DRV_FB_SZ (lcd_drv->lcd_info.width * lcd_drv->lcd_info.height * sizeof(rt_uint32_t))
+
+enum state_buff
+{
+    EMPTY,
+    FULL
+};
+
+enum lcd_evt
+{
+    LCD_EVT_VSYNC = 1,
+};
+
+struct buff_info
+{
+    rt_uint32_t *buff;
+    rt_uint32_t *buff_phy;
+    enum state_buff status;
+};
+
+/* kind of a candidate for the official lcd driver framework */
+struct lcd_device
+{
+    struct rt_device lcd;
+    struct rt_device_graphic_info lcd_info; /* rtdef.h */
+    struct rt_event lcd_evt;
+    int use_screen; /* screen index */
+
+    void *framebuffer;
+    void *framebuffer_phy;
+
+    atomic_uint refresh_flag;        /* atom flag,  0: nothing. 1:framebuffer ==> front_buf. 2:back_buf ==> front_buf.  */
+    struct buff_info front_buf_info; /* TCON hardware framebuffer */
+    struct buff_info back_buf_info;  /* rotate swap framebuffer */
+
+    const struct lcd_cfg_panel_info *panel;
+};
+typedef struct lcd_device *lcd_device_t;
+
+static struct disp_layer_config layer_cfg;
+static struct lcd_device _lcd_device;
+static const struct lcd_cfg_panel_info *_panel;
+static int lcd_status = 0;
+static rt_uint8_t lcd_bn = 80;
+#define LCD_PWM_DEV_CHANNEL 1
+
+extern void rt_hw_cpu_dcache_clean(void *addr, int size);
+extern int disp_ioctl(int cmd, void *arg);
+extern int disp_probe(void);
+
+/* set up the lcd pin function */
+static void lcd_gpio_config(void)
+{
+    int i;
+    gpio_pin_t pin;
+    gpio_muxsel_t function_index;
+    gpio_driving_level_t level;
+
+    if (_panel->bl_pin >= 0)
+    {
+        hal_gpio_set_direction(_panel->bl_pin, GPIO_DIRECTION_OUTPUT); // bl_pin
+        hal_gpio_set_driving_level(_panel->bl_pin, 3);
+        hal_gpio_set_data(_panel->bl_pin, _panel->bl_level);
+    }
+
+    if (_panel->pwr_pin >= 0)
+    {
+        hal_gpio_set_direction(_panel->pwr_pin, GPIO_DIRECTION_OUTPUT); // pwr_pin
+        hal_gpio_set_driving_level(_panel->pwr_pin, 3);
+        hal_gpio_set_data(_panel->pwr_pin, 0);
+        rt_thread_delay(10);
+        hal_gpio_set_data(_panel->pwr_pin, _panel->pwr_level);
+        rt_thread_delay(10);
+        lcd_status = _panel->pwr_level;
+    }
+
+    if (_panel->bl_mode == 0)
+    {
+        hal_gpio_set_direction(_panel->bl_gpio_pin, GPIO_DIRECTION_OUTPUT);
+        hal_gpio_set_driving_level(_panel->bl_gpio_pin, 3);
+        hal_gpio_set_data(_panel->bl_gpio_pin, _panel->bl_gpio_level);
+    }
+    else
+    {
+        lcd_bn = _panel->bl_pwm_val;
+        set_lcd_backlight(lcd_bn);
+    }
+}
+
+void *lcd_get_framebuffer(void *dev)
+{
+    return ((struct lcd_device *)dev)->framebuffer;
+}
+
+s32 lcd_vsync_event_process(u32 sel)
+{
+    lcd_device_t lcd_drv = &_lcd_device;
+    uint32_t refresh_flag = atomic_exchange(&lcd_drv->refresh_flag, 0); // read-modify-write, read & clean.
+
+    if (refresh_flag != 0)
+    {
+        uint32_t len = (uint32_t)lcd_drv->lcd_info.width * lcd_drv->lcd_info.height * (lcd_drv->lcd_info.bits_per_pixel / 8);
+        uint32_t len_stage1 = 1024;
+        void *dst = lcd_drv->front_buf_info.buff;
+        const void *src = lcd_drv->framebuffer;
+
+        if (refresh_flag == 1)
+        {
+            src = lcd_drv->framebuffer;
+        }
+        else if (refresh_flag == 2)
+        {
+            src = lcd_drv->back_buf_info.buff;
+        }
+        else
+        {
+            // TODO: error
+        }
+
+        memcpy((uint32_t *)dst, (uint32_t *)src, len_stage1);
+        rt_hw_cpu_dcache_clean(dst, len_stage1);
+
+        memcpy((uint32_t *)(dst + len_stage1), (uint32_t *)(src + len_stage1), len - len_stage1);
+        rt_hw_cpu_dcache_clean((uint32_t *)(dst + len_stage1), len - len_stage1);
+
+        rt_event_send(&lcd_drv->lcd_evt, LCD_EVT_VSYNC);
+    }
+
+    rt_event_send(&lcd_drv->lcd_evt, LCD_EVT_VSYNC);
+}
+
+static void _framebuffer_rotate_mirror(void *src_buf, void *dst_buf,
+                                       const struct rt_device_graphic_info *lcd_info, const struct lcd_cfg_panel_info *_panel_info)
+{
+    lcd_device_t lcd_drv = &_lcd_device;
+    memcpy(dst_buf, src_buf, LCD_DRV_FB_SZ);
+}
+
+/* Multi-layer is not supported now. */
+#ifdef GUIENGINE_USING_MULTI_LAYER
+#include <rtgui/rtgui_layer.h>
+struct debe_info
+{
+    int index;
+    void *buffer;
+    rt_uint32_t bf_size;
+};
+static struct debe_info _debe_use[3];
+#endif
+
+/* pixel format, only 565 (2 bytes) or 666 (4 bytes) are supported */
+static inline int _lcd_format_get(rt_uint8_t pixel_format)
+{
+    switch (pixel_format)
+    {
+    case RTGRAPHIC_PIXEL_FORMAT_RGB565:
+        return DISP_FORMAT_RGB_565;
+    case RTGRAPHIC_PIXEL_FORMAT_ARGB888:
+        return DISP_FORMAT_ARGB_8888;
+    default:
+        return -1;
+    }
+}
+
+static int _lcd_drv_init(lcd_device_t lcd_drv)
+{
+    unsigned long arg[6] = {0};
+    void *framebuffer = RT_NULL;
+    void *frontbuf = RT_NULL;
+    void *backbuf = RT_NULL;
+
+    /*
+     * The event is used for the synchronization between updating the
+     * framebuffer and flushing the screen.
+     */
+    rt_event_init(&lcd_drv->lcd_evt, "lcd_evt", RT_IPC_FLAG_FIFO);
+
+    /* the lcd device information defined by RT-Thread */
+    arg[0] = lcd_drv->use_screen;
+    lcd_drv->lcd_info.width = (rt_uint16_t)disp_ioctl(DISP_GET_SCN_WIDTH, arg);
+    lcd_drv->lcd_info.height = (rt_uint16_t)disp_ioctl(DISP_GET_SCN_HEIGHT, arg);
+    lcd_drv->lcd_info.bits_per_pixel = 32;
+    lcd_drv->lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_ARGB888; /* should be coherent to adding layers */
+
+    /* allocate the framebuffer, the front buffer and the back buffer */
+    /* framebuffer */
+#ifdef RT_USING_USERSPACE
+    framebuffer = rt_pages_alloc(rt_page_bits(LCD_DRV_FB_SZ));
+#else
+    framebuffer = rt_malloc(LCD_DRV_FB_SZ);
+#endif
+    if (!framebuffer)
+    {
+        rt_kprintf("malloc framebuffer fail\n");
+        goto out;
+    }
+    lcd_drv->lcd_info.framebuffer = framebuffer;
+    lcd_drv->framebuffer = framebuffer;
+    lcd_drv->framebuffer_phy = (void *)((size_t)framebuffer + PV_OFFSET);
+    memset(framebuffer, 0, LCD_DRV_FB_SZ);
+    rt_hw_cpu_dcache_clean(lcd_drv->framebuffer, LCD_DRV_FB_SZ);
+#ifdef RT_USING_USERSPACE
+    frontbuf = rt_pages_alloc(rt_page_bits(LCD_DRV_FB_SZ));
+#else
+    frontbuf = rt_malloc(LCD_DRV_FB_SZ);
+#endif
+    if (!frontbuf)
+    {
+        rt_kprintf("malloc frontbuf fail\n");
+        goto out;
+    }
+    lcd_drv->front_buf_info.buff = frontbuf;
+    lcd_drv->front_buf_info.buff_phy = (void *)((size_t)frontbuf + PV_OFFSET);
+    memset(frontbuf, 0, LCD_DRV_FB_SZ);
+    rt_hw_cpu_dcache_clean(lcd_drv->front_buf_info.buff, LCD_DRV_FB_SZ);
+
+    if ((lcd_drv->panel) && (lcd_drv->panel->swap_flag != 0))
+    {
+        /* backbuf */
+#ifdef RT_USING_USERSPACE
+        backbuf = rt_pages_alloc(rt_page_bits(LCD_DRV_FB_SZ));
+#else
+        backbuf = rt_malloc(LCD_DRV_FB_SZ);
+#endif
+        if (!backbuf)
+        {
+            rt_kprintf("malloc backbuf fail\n");
+            goto out;
+        }
+        lcd_drv->back_buf_info.buff = backbuf;
+        lcd_drv->back_buf_info.buff_phy = (void *)((size_t)backbuf + PV_OFFSET);
+        memset(backbuf, 0, LCD_DRV_FB_SZ);
+        rt_hw_cpu_dcache_clean(lcd_drv->back_buf_info.buff, LCD_DRV_FB_SZ);
+    }
+
+    return RT_EOK;
+out:
+    if (framebuffer)
+    {
+#ifdef RT_USING_USERSPACE
+        rt_free_align(framebuffer);
+#else
+        rt_free(framebuffer);
+#endif
+    }
+
+    if (frontbuf)
+    {
+#ifdef RT_USING_USERSPACE
+        rt_free_align(frontbuf);
+#else
+        rt_free(frontbuf);
+#endif
+    }
+
+    if (backbuf)
+    {
+#ifdef RT_USING_USERSPACE
+        rt_free_align(backbuf);
+#else
+        rt_free(backbuf);
+#endif
+    }
+
+    return -RT_ERROR;
+}
+
+static int _lcd_layer_init(lcd_device_t lcd_drv)
+{
+    int format;
+    int ret;
+    unsigned long arg[6] = {0};
+
+    format = _lcd_format_get(lcd_drv->lcd_info.pixel_format);
+    if (format < 0)
+    {
+        rt_kprintf("lcd init faile pixel_format:%d\n", lcd_drv->lcd_info.pixel_format);
+        return -RT_ERROR;
+    }
+
+    // config layer info
+    memset(&layer_cfg, 0, sizeof(layer_cfg));
+    layer_cfg.info.b_trd_out = 0;
+    layer_cfg.channel = de_feat_get_num_vi_chns(lcd_drv->use_screen); // skip vi channel
+    layer_cfg.layer_id = 0;
+    layer_cfg.info.fb.format = format;
+    layer_cfg.info.fb.crop.x = 0;
+    layer_cfg.info.fb.crop.y = 0;
+    layer_cfg.info.fb.crop.width = lcd_drv->lcd_info.width;
+    layer_cfg.info.fb.crop.height = lcd_drv->lcd_info.height;
+    layer_cfg.info.fb.crop.width = layer_cfg.info.fb.crop.width << 32;
+    layer_cfg.info.fb.crop.height = layer_cfg.info.fb.crop.height << 32;
+    layer_cfg.info.fb.align[0] = 4;
+    layer_cfg.info.mode = 0; // LAYER_MODE_BUFFER
+    layer_cfg.info.alpha_mode = 1;
+    layer_cfg.info.alpha_value = 255;
+    layer_cfg.info.zorder = 0;
+    layer_cfg.info.screen_win.x = 0;
+    layer_cfg.info.screen_win.y = 0;
+    layer_cfg.info.screen_win.width = lcd_drv->lcd_info.width;
+    layer_cfg.info.screen_win.height = lcd_drv->lcd_info.height;
+
+    layer_cfg.info.fb.size[0].width = lcd_drv->lcd_info.width;
+    layer_cfg.info.fb.size[0].height = lcd_drv->lcd_info.height;
+    layer_cfg.info.fb.size[1].width = lcd_drv->lcd_info.width;
+    layer_cfg.info.fb.size[1].height = lcd_drv->lcd_info.height;
+    layer_cfg.info.fb.size[2].width = lcd_drv->lcd_info.width;
+    layer_cfg.info.fb.size[2].height = lcd_drv->lcd_info.height;
+
+    layer_cfg.info.fb.addr[0] = (size_t)lcd_drv->front_buf_info.buff_phy;
+
+    /* INTERLEAVED */
+    layer_cfg.info.fb.addr[0] = (unsigned long long)(layer_cfg.info.fb.addr[0] + lcd_drv->lcd_info.width * lcd_drv->lcd_info.height / 3 * 0);
+    layer_cfg.info.fb.addr[1] = (unsigned long long)(layer_cfg.info.fb.addr[0] + lcd_drv->lcd_info.width * lcd_drv->lcd_info.height / 3 * 1);
+    layer_cfg.info.fb.addr[2] = (unsigned long long)(layer_cfg.info.fb.addr[0] + lcd_drv->lcd_info.width * lcd_drv->lcd_info.height / 3 * 2);
+    layer_cfg.info.fb.trd_right_addr[0] = (unsigned int)(layer_cfg.info.fb.addr[0] + lcd_drv->lcd_info.width * lcd_drv->lcd_info.height * 3 / 2);
+    layer_cfg.info.fb.trd_right_addr[1] = (unsigned int)(layer_cfg.info.fb.trd_right_addr[0] + lcd_drv->lcd_info.width * lcd_drv->lcd_info.height);
+    layer_cfg.info.fb.trd_right_addr[2] = (unsigned int)(layer_cfg.info.fb.trd_right_addr[0] + lcd_drv->lcd_info.width * lcd_drv->lcd_info.height * 3 / 2);
+
+    layer_cfg.enable = 1;
+
+    arg[0] = lcd_drv->use_screen;
+    arg[1] = (unsigned long)&layer_cfg;
+    arg[2] = 1;
+    arg[3] = 0;
+    ret = disp_ioctl(DISP_LAYER_SET_CONFIG, (void *)arg);
+    if (0 != ret)
+    {
+        rt_kprintf("fail to set layer cfg %d\n", ret);
+        return -RT_ERROR;
+    }
+
+    arg[0] = lcd_drv->use_screen;
+    arg[1] = 1; // enable
+    arg[2] = 0;
+    ret = disp_ioctl(DISP_VSYNC_EVENT_EN, (void *)arg);
+    if (0 != ret)
+    {
+        rt_kprintf("fail to set vsync enable %d\n", ret);
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/* Add the first layer, then enable the interrupt */
+static rt_err_t rt_lcd_init(rt_device_t dev)
+{
+    lcd_device_t lcd_drv = (lcd_device_t)dev;
+
+    RT_ASSERT(lcd_drv != RT_NULL);
+
+    static int lcd_init = 0;
+
+    if (lcd_init)
+    {
+        return RT_EOK;
+    }
+    lcd_init = 1;
+
+    _panel = load_lcd_config_from_xml();
+    lcd_drv->panel = _panel;
+
+    if (disp_probe() != 0)
+    {
+        rt_kprintf("lcd disp probe failure\n");
+        return -RT_ERROR;
+    }
+
+    lcd_gpio_config();
+
+    if (_lcd_drv_init(lcd_drv) != RT_EOK)
+    {
+        rt_kprintf("lcd drv init failure\n");
+        return -RT_ERROR;
+    }
+
+    if (_lcd_layer_init(lcd_drv) != RT_EOK)
+    {
+        rt_kprintf("disp layer init failure\n");
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+struct lcd_device *g_lcd = RT_NULL;
+
+void turn_on_lcd_backlight(void)
+{
+    if (_panel->bl_pin >= 0)
+    {
+        hal_gpio_set_direction(_panel->bl_pin, GPIO_DIRECTION_OUTPUT); // bl_pin
+        hal_gpio_set_driving_level(_panel->bl_pin, 3);
+        hal_gpio_set_data(_panel->bl_pin, 1);
+    }
+
+    if (_panel->pwr_pin >= 0)
+    {
+        hal_gpio_set_direction(_panel->pwr_pin, GPIO_DIRECTION_OUTPUT); // pwr_pin
+        hal_gpio_set_driving_level(_panel->pwr_pin, 3);
+        hal_gpio_set_data(_panel->pwr_pin, 1);
+    }
+    if (_panel->bl_mode == 0)
+    {
+        hal_gpio_set_direction(_panel->bl_gpio_pin, GPIO_DIRECTION_OUTPUT);
+        hal_gpio_set_driving_level(_panel->bl_gpio_pin, 3);
+        hal_gpio_set_data(_panel->bl_gpio_pin, 1);
+    }
+    else
+    {
+        struct rt_device_pwm *pwm_dev;
+        pwm_dev = (struct rt_device_pwm *)rt_device_find(_panel->bl_pwm_name);
+        if (pwm_dev == RT_NULL)
+        {
+            rt_kprintf("%s open fail\n", _panel->bl_pwm_name);
+            return;
+        }
+        rt_pwm_set(pwm_dev, LCD_PWM_DEV_CHANNEL, 1000000000 / _panel->bl_pwm_hz, lcd_bn * (10000000 / _panel->bl_pwm_hz));
+        rt_pwm_enable(pwm_dev, LCD_PWM_DEV_CHANNEL);
+    }
+    lcd_status = 1;
+}
+
+void turn_down_lcd_backlight(void)
+{
+
+    if (_panel->bl_pin >= 0)
+    {
+        hal_gpio_set_direction(_panel->bl_pin, GPIO_DIRECTION_OUTPUT); // bl_pin
+        hal_gpio_set_driving_level(_panel->bl_pin, 3);
+        hal_gpio_set_data(_panel->bl_pin, 0);
+    }
+
+    if (_panel->pwr_pin >= 0)
+    {
+        hal_gpio_set_direction(_panel->pwr_pin, GPIO_DIRECTION_OUTPUT); // pwr_pin
+        hal_gpio_set_driving_level(_panel->pwr_pin, 3);
+        hal_gpio_set_data(_panel->pwr_pin, 0);
+    }
+    if (_panel->bl_mode == 0)
+    {
+        hal_gpio_set_direction(_panel->bl_gpio_pin, GPIO_DIRECTION_OUTPUT);
+        hal_gpio_set_driving_level(_panel->bl_gpio_pin, 3);
+        hal_gpio_set_data(_panel->bl_gpio_pin, 0);
+    }
+    else
+    {
+        struct rt_device_pwm *pwm_dev;
+        pwm_dev = (struct rt_device_pwm *)rt_device_find(_panel->bl_pwm_name);
+        if (pwm_dev == RT_NULL)
+        {
+            rt_kprintf("%s open fail\n", _panel->bl_pwm_name);
+            return;
+        }
+        rt_pwm_set(pwm_dev, LCD_PWM_DEV_CHANNEL, 1000000000 / _panel->bl_pwm_hz, 0 * (10000000 / _panel->bl_pwm_hz));
+        rt_pwm_enable(pwm_dev, LCD_PWM_DEV_CHANNEL);
+    }
+    lcd_status = 0;
+    return;
+}
+
+void set_lcd_backlight(rt_uint8_t value)
+{
+    struct rt_device_pwm *pwm_dev;
+    pwm_dev = (struct rt_device_pwm *)rt_device_find(_panel->bl_pwm_name);
+    if (pwm_dev == RT_NULL)
+    {
+        rt_kprintf("%s open fail\n", _panel->bl_pwm_name);
+        return;
+    }
+    rt_pwm_set(pwm_dev, LCD_PWM_DEV_CHANNEL, 1000000000 / _panel->bl_pwm_hz, value * (10000000 / _panel->bl_pwm_hz));
+    rt_pwm_enable(pwm_dev, LCD_PWM_DEV_CHANNEL);
+}
+
+rt_uint8_t get_lcd_backlight(void)
+{
+    int result = 0;
+    struct rt_device_pwm *pwm_dev;
+    struct rt_pwm_configuration cfg = {0};
+
+    pwm_dev = (struct rt_device_pwm *)rt_device_find(_panel->bl_pwm_name);
+    cfg.channel = LCD_PWM_DEV_CHANNEL;
+    rt_pwm_get(pwm_dev, LCD_PWM_DEV_CHANNEL);
+
+    return cfg.pulse / (10000000 / _panel->bl_pwm_hz);
+}
+
+static rt_err_t rt_lcd_control(rt_device_t dev, int cmd, void *args)
+{
+    struct lcd_device *lcd_drv = (struct lcd_device *)dev;
+
+    switch (cmd)
+    {
+    case RTGRAPHIC_CTRL_RECT_UPDATE:
+    {
+        unsigned long arg[6] = {0};
+        int ret;
+
+        // clean event.
+        rt_event_recv(&lcd_drv->lcd_evt, LCD_EVT_VSYNC, RT_EVENT_FLAG_CLEAR | RT_EVENT_FLAG_OR, 0, NULL);
+
+        // rotate and set refresh_flag
+        if ((lcd_drv->panel) && (lcd_drv->panel->swap_flag != 0))
+        {
+            _framebuffer_rotate_mirror(lcd_drv->framebuffer, lcd_drv->back_buf_info.buff, &lcd_drv->lcd_info, _panel);
+            rt_hw_cpu_dcache_clean(lcd_drv->back_buf_info.buff, LCD_DRV_FB_SZ);
+            atomic_store(&lcd_drv->refresh_flag, 2); // lcd_drv->refresh_flag = 2;
+        }
+        else
+        {
+            atomic_store(&lcd_drv->refresh_flag, 1); // lcd_drv->refresh_flag = 1;
+        }
+
+        // wait irq
+        rt_err_t result = rt_event_recv(&lcd_drv->lcd_evt, LCD_EVT_VSYNC, RT_EVENT_FLAG_CLEAR | RT_EVENT_FLAG_OR, RT_TICK_PER_SECOND / 20, NULL);
+        if (result != RT_EOK)
+        {
+            rt_kprintf("RTGRAPHIC_CTRL_RECT_UPDATE wait LCD_EVT_VSYNC:%d\n", result);
+        }
+
+        break;
+    }
+    case RTGRAPHIC_CTRL_POWERON:
+        if (lcd_status == 0)
+        {
+#ifdef WATCH_APP_FWK_USING_SCREEN_MGT
+            extern void watch_screen_time_update(void);
+            watch_screen_time_update();
+#endif
+            turn_on_lcd_backlight();
+            rt_kprintf("lcd driver control power on.\n");
+            lcd_status = 1;
+        }
+        break;
+    case RTGRAPHIC_CTRL_POWEROFF:
+        if (lcd_status == 1)
+        {
+            lcd_status = 0;
+            turn_down_lcd_backlight();
+            rt_kprintf("lcd driver control power off.\n");
+        }
+        break;
+    case RTGRAPHIC_CTRL_SET_BRIGHTNESS:
+        lcd_bn = *((rt_uint8_t *)args);
+        // TODO::if can SET_BRIGHTNESS
+        set_lcd_backlight(lcd_bn);
+        rt_kprintf("lcd driver control set brightness: %d.\n", lcd_bn);
+        break;
+
+    case RTGRAPHIC_CTRL_GET_BRIGHTNESS:
+        lcd_bn = get_lcd_backlight();
+        *((rt_uint8_t *)args) = lcd_bn;
+        // TODO::if can GET_BRIGHTNESS
+        rt_kprintf("lcd driver control get brightness: %d.\n", lcd_bn);
+        break;
+    case RTGRAPHIC_CTRL_GET_INFO:
+        memcpy(args, &lcd_drv->lcd_info, sizeof(struct rt_device_graphic_info));
+        break;
+    case FBIOGET_FSCREENINFO:
+    {
+        struct fb_fix_screeninfo *info = (struct fb_fix_screeninfo *)args;
+        strncpy(info->id, "lcd", sizeof(info->id));
+        info->smem_len = LCD_DRV_FB_SZ;
+#ifdef RT_USING_USERSPACE
+        info->smem_start = (size_t)lwp_map_user_phy(lwp_self(), RT_NULL, lcd_drv->framebuffer_phy, info->smem_len, 1);
+#else
+        info->smem_start = (size_t)lcd_drv->framebuffer_phy;
+#endif
+        info->line_length = lcd_drv->lcd_info.width * sizeof(rt_uint32_t);
+        memset((void *)info->smem_start, 0, info->smem_len);
+    }
+    case RTGRAPHIC_CTRL_SET_MODE:
+        break;
+    }
+    return RT_EOK;
+}
+
+/* set up the 'lcd_device' and register it */
+int rt_hw_lcd_init(void)
+{
+    struct lcd_device *lcd_drv = &_lcd_device;
+
+    g_lcd = lcd_drv;
+    /* the content of tcon control registers can be loaded from a xml file ? */
+    // _panel = load_config_from_xml();
+    memset(lcd_drv, 0, sizeof(struct lcd_device));
+
+    lcd_drv->use_screen = DEFAULT_SCREEN;
+
+    /* initialize device structure, the type of 'lcd' is 'rt_device' */
+    lcd_drv->lcd.type = RT_Device_Class_Graphic;
+    lcd_drv->lcd.init = rt_lcd_init;
+    lcd_drv->lcd.open = RT_NULL;
+    lcd_drv->lcd.close = RT_NULL;
+    lcd_drv->lcd.control = rt_lcd_control;
+    lcd_drv->lcd.user_data = (void *)&lcd_drv->lcd_info;
+
+    /* register lcd device to RT-Thread */
+    rt_device_register(&lcd_drv->lcd, "lcd", RT_DEVICE_FLAG_RDWR);
+
+    // #if !defined(RT_USING_USERSPACE) && !defined(PKG_USING_JS_PERSIMMON)
+    rt_lcd_init((rt_device_t)lcd_drv);
+    // #endif
+
+    return RT_EOK;
+}
+// INIT_DEVICE_EXPORT(rt_hw_lcd_init);
+
+static int lcd_draw_point(int args, char *argv[])
+{
+    struct lcd_device *lcd_drv = g_lcd;
+    int x = 0;
+    int y = 0;
+    int i, k;
+
+    rt_kprintf("lcd_draw_point\n");
+
+    x = atoi(argv[1]);
+    y = atoi(argv[2]);
+
+    if (x >= lcd_drv->lcd_info.width)
+        x = lcd_drv->lcd_info.width - 1;
+    if (y >= lcd_drv->lcd_info.height)
+        y = lcd_drv->lcd_info.height - 1;
+    if (x < 0)
+        x = 0;
+    if (y < 0)
+        y = 0;
+
+    rt_kprintf("Darw point is x:%d,y:%d\n", x, y);
+
+    // memset(lcd->framebuffer, 0, sizeof(rt_uint32_t) * lcd_drv->lcd_info.width * lcd_drv->lcd_info.height);
+
+    for (i = y - 100; i < y + 100; i++)
+    {
+        if (i < 0)
+            continue;
+        if (i >= lcd_drv->lcd_info.height)
+            break;
+        for (k = x - 100; k < x + 100; k++)
+        {
+            if (k < 0)
+                continue;
+            if (k >= lcd_drv->lcd_info.width)
+                break;
+
+            *((uint32_t *)lcd_drv->framebuffer + lcd_drv->lcd_info.width * i + k) = 0xff00ff00;
+        }
+    }
+
+    *((uint32_t *)lcd_drv->framebuffer + lcd_drv->lcd_info.width * y + x) = 0xffff0000;
+    // *((uint32_t *)lcd->framebuffer + lcd_drv->lcd_info.width * y + x + 2) = 0xff00ff00;
+
+    rt_hw_cpu_dcache_clean(lcd_drv->framebuffer, LCD_DRV_FB_SZ);
+    rt_lcd_control((rt_device_t)g_lcd, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
+
+    return 0;
+}
+MSH_CMD_EXPORT(lcd_draw_point, draw a point on lcd);
+
+void lcd_pwm_test(int argc, char **argv)
+{
+    set_lcd_backlight(atoi(argv[1]));
+}
+
+MSH_CMD_EXPORT(lcd_pwm_test, set pwm);
+
+#endif

bsp/allwinner/libraries/drivers/drv_lcd.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-04-12     RT-Thread    the first version
+ */
+
+#ifndef __DRV_LCD_H__
+#define __DRV_LCD_H__
+
+#include <stdint.h>
+
+#define REVERSE_X       (1<<0)
+#define REVERSE_Y       (1<<1)
+#define REVERSE_MODE    (1<<2)
+
+int rt_hw_lcd_init(void);
+
+#define FBIOGET_FSCREENINFO     0x4602
+
+struct fb_fix_screeninfo
+{
+    char id[16];
+    unsigned long smem_start;
+    uint32_t smem_len;
+
+    uint32_t line_length;
+};
+rt_uint8_t get_lcd_backlight(void);
+void set_lcd_backlight(rt_uint8_t value);
+void turn_down_lcd_backlight(void);
+void turn_on_lcd_backlight(void);
+
+#endif

bsp/allwinner/libraries/drivers/drv_pin.c

@@ -0,0 +1,145 @@
+#include <rthw.h>
+#include <rtdevice.h>
+#include <hal_gpio.h>
+
+static void hal_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
+{
+    switch (mode)
+    {
+        case PIN_MODE_OUTPUT:
+            hal_gpio_set_direction(pin,GPIO_DIRECTION_OUTPUT);
+            break;
+        case PIN_MODE_INPUT:
+            hal_gpio_set_direction(pin,GPIO_DIRECTION_INPUT);
+            break;
+        case PIN_MODE_INPUT_PULLDOWN:
+            hal_gpio_set_pull(pin, GPIO_PULL_DOWN);
+            hal_gpio_set_direction(pin,GPIO_DIRECTION_INPUT);
+            break;
+        case PIN_MODE_INPUT_PULLUP:
+            hal_gpio_set_pull(pin,GPIO_PULL_UP);
+            hal_gpio_set_direction(pin,GPIO_DIRECTION_INPUT);
+            break;
+        case PIN_MODE_OUTPUT_OD:
+            hal_gpio_set_pull(pin, GPIO_PULL_DOWN_DISABLED);
+            hal_gpio_set_direction(pin,GPIO_DIRECTION_OUTPUT);
+            break;
+    }
+}
+
+static void hal_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
+{
+    hal_gpio_set_data(pin,value);
+}
+
+static int hal_pin_read(struct rt_device *device, rt_base_t pin)
+{
+    gpio_data_t value;
+    hal_gpio_get_data(pin,&value);
+    return (int)value;
+}
+
+static rt_err_t hal_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                       rt_uint32_t mode, void (*hdr)(void *args),
+                                       void *args)
+{
+    rt_base_t level = 0;
+    uint32_t irq;
+    int ret = 0;
+
+    ret = hal_gpio_to_irq(pin, &irq);
+    if (ret < 0)
+    {
+        rt_kprintf("gpio to irq error, irq num:%lu error num: %d", irq, ret);
+        return RT_ERROR;
+    }
+
+    level = rt_hw_interrupt_disable();
+    hal_gpio_set_debounce(pin, 1); // enable debounce 24Mhz
+    ret = hal_gpio_irq_attach(irq, hdr, mode + 1, args);
+    if (ret < 0)
+    {
+        rt_hw_interrupt_enable(level);
+        rt_kprintf("request irq error, irq num:%lu error num: %d", irq, ret);
+        return RT_ERROR;
+    }
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t hal_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    rt_base_t level = 0;
+    uint32_t irq;
+    int ret;
+
+    ret = hal_gpio_to_irq(pin, &irq);
+    if (ret < 0)
+    {
+        rt_kprintf("gpio to irq error, irq num:%lu error num: %d", irq, ret);
+        return RT_ERROR;
+    }
+
+    level = rt_hw_interrupt_disable();
+    ret = hal_gpio_irq_free(irq);
+    if (ret < 0)
+    {
+        rt_hw_interrupt_enable(level);
+        rt_kprintf("free irq error, error num: %d", ret);
+        return RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+static rt_err_t hal_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+    uint32_t irq;
+    int ret;
+
+    ret = hal_gpio_to_irq(pin, &irq);
+    if (ret < 0)
+    {
+        rt_kprintf("gpio to irq error, irq num:%lu error num: %d", irq, ret);
+        return RT_ERROR;
+    }
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        ret = hal_gpio_irq_enable(irq);
+        if (ret < 0)
+        {
+            rt_kprintf("request irq error, error num: %d", ret);
+            return RT_ERROR;
+        }
+    }
+    else
+    {
+        ret = hal_gpio_irq_disable(irq);
+        if (ret < 0)
+        {
+            rt_kprintf("disable irq error, irq num:%lu, error num: %d", irq, ret);
+            return RT_ERROR;
+        }
+    }
+
+    return RT_EOK;
+}
+
+static const struct rt_pin_ops gpio_ops =
+{
+    hal_pin_mode,
+    hal_pin_write,
+    hal_pin_read,
+    hal_pin_attach_irq,
+    hal_pin_detach_irq,
+    hal_pin_irq_enable,
+    RT_NULL,
+};
+
+int hal_hw_pin_init(void)
+{
+    return rt_device_pin_register("pin", &gpio_ops, RT_NULL);
+}
+
+INIT_BOARD_EXPORT(hal_hw_pin_init);

bsp/allwinner/libraries/drivers/drv_pin.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-04-12     RT-Thread    the first version
+ */
+
+#ifndef __DRV_PIN_H__
+#define __DRV_PIN_H__
+
+#include <hal_gpio.h>
+
+/* IO port */
+enum gpio_port
+{
+    GPIO_PORT_RESERVED0 = 0,
+    GPIO_PORT_B,
+    GPIO_PORT_C,
+    GPIO_PORT_D,
+    GPIO_PORT_E,
+    GPIO_PORT_F,
+    GPIO_PORT_G,
+    GPIO_PORT_NUM,
+};
+
+/* IO pin */
+enum gpio_pin
+{
+    GPIO_PIN_0 = 0,
+    GPIO_PIN_1,
+    GPIO_PIN_2,
+    GPIO_PIN_3,
+    GPIO_PIN_4,
+    GPIO_PIN_5,
+    GPIO_PIN_6,
+    GPIO_PIN_7,
+    GPIO_PIN_8,
+    GPIO_PIN_9,
+    GPIO_PIN_10,
+    GPIO_PIN_11,
+    GPIO_PIN_12,
+    GPIO_PIN_13,
+    GPIO_PIN_14,
+    GPIO_PIN_15,
+    GPIO_PIN_16,
+    GPIO_PIN_17,
+    GPIO_PIN_18,
+    GPIO_PIN_19,
+    GPIO_PIN_20,
+    GPIO_PIN_21,
+    GPIO_PIN_22,
+    GPIO_PIN_NUM,
+};
+
+#define HAL_GPIO(bank,num) GPIO_P##bank##num
+
+#define GET_GPIO_PORT(PIN)       (PIN / 32)
+#define GET_GPIO_PIN(PIN)        (PIN % 32)
+#define GET_PIN(PORTx, PIN)      (rt_base_t)(32 * PORTx + PIN)
+
+#endif

bsp/allwinner/libraries/drivers/drv_pwm.c

@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author           Notes
+ * 2021-12-13     JasonHu          the first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include <sunxi_hal_pwm.h>
+
+#define PWM_CHANNEL_MAX     (8) /* 0-7*/
+
+#if defined(RT_USING_PWM) && defined(BSP_USING_PWM)
+
+struct rt_hal_pwm
+{
+    struct rt_device_pwm parent;
+
+    rt_uint32_t period[PWM_CHANNEL_MAX];
+    rt_uint32_t pulse[PWM_CHANNEL_MAX];
+    rt_uint32_t status;
+};
+
+static struct rt_hal_pwm _hal_pwm_device;
+static struct rt_pwm_configuration configuration = {1, 100000, 100000, RT_TRUE};
+
+static rt_err_t set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
+{
+    struct rt_hal_pwm *hal_pwm_device = (struct rt_hal_pwm *)device;
+
+    LOG_D("drv_pwm.c set channel %d: period: %d, pulse: %d\n", configuration->channel, configuration->period, configuration->pulse);
+
+    hal_pwm_device->period[configuration->channel] = configuration->period;
+    hal_pwm_device->pulse[configuration->channel] = configuration->pulse;
+
+    return RT_EOK;
+}
+
+static rt_err_t get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
+{
+    struct rt_hal_pwm *hal_pwm_device = (struct rt_hal_pwm *)device;
+
+    configuration->period = hal_pwm_device->period[configuration->channel];
+    configuration->pulse = hal_pwm_device->pulse[configuration->channel];
+    LOG_D("drv_pwm.c get channel %d: period: %d, pulse: %d\n", configuration->channel, configuration->period, configuration->pulse);
+
+    return RT_EOK;
+}
+
+static rt_err_t control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+    rt_err_t result = RT_EOK;
+    struct rt_pwm_configuration * configuration = (struct rt_pwm_configuration *)arg;
+
+    struct rt_hal_pwm *hal_pwm_device = (struct rt_hal_pwm *)device;
+
+    LOG_D("drv_pwm.c control cmd: %d. \n", cmd);
+
+    if (configuration->channel > (PWM_CHANNEL_MAX - 1))
+    {
+        LOG_E("drv_pwm.c control channel: %d not support! \n", configuration->channel);
+        return -RT_EIO;
+    }
+
+    LOG_D("PWM: channel:%d", configuration->channel);
+
+    if (cmd == PWM_CMD_ENABLE)
+    {
+        LOG_D("PWM_CMD_ENABLE");
+        struct pwm_config pwm_cfg;
+        pwm_cfg.polarity = PWM_POLARITY_NORMAL;
+        pwm_cfg.duty_ns =  hal_pwm_device->pulse[configuration->channel];
+        pwm_cfg.period_ns = hal_pwm_device->period[configuration->channel];
+        hal_pwm_device->status = 1;
+        if (hal_pwm_control(configuration->channel, &pwm_cfg) != 0)
+        {
+            result = -RT_EIO;
+        }
+    }
+    else if (cmd == PWM_CMD_DISABLE)
+    {
+        LOG_D("PWM_CMD_DISABLE");
+        struct pwm_config pwm_cfg;
+        pwm_cfg.polarity = PWM_POLARITY_NORMAL;
+        pwm_cfg.duty_ns =  0; /* set as 0 for no duty */
+        pwm_cfg.period_ns = hal_pwm_device->period[configuration->channel];
+        hal_pwm_device->status = 0;
+        if (hal_pwm_control(configuration->channel, &pwm_cfg) != 0)
+        {
+            result = -RT_EIO;
+        }
+        else
+        {
+            hal_pwm_disable_controller(configuration->channel);
+        }
+    }
+    else if (cmd == PWM_CMD_SET)
+    {
+        LOG_D("PWM_CMD_SET");
+        result = set(device, (struct rt_pwm_configuration *)arg);
+        if(hal_pwm_device->status)
+        {
+            struct pwm_config pwm_cfg;
+            pwm_cfg.polarity = PWM_POLARITY_NORMAL;
+            pwm_cfg.duty_ns =  hal_pwm_device->pulse[configuration->channel];
+            pwm_cfg.period_ns = hal_pwm_device->period[configuration->channel];
+            if (hal_pwm_control(configuration->channel, &pwm_cfg) != 0)
+            {
+                result = -RT_EIO;
+            }
+        }
+    }
+    else if (cmd == PWM_CMD_GET)
+    {
+        LOG_D("PWM_CMD_GET");
+        result = get(device, (struct rt_pwm_configuration *)arg);
+    }
+
+    return result;
+}
+
+static const struct rt_pwm_ops pwm_ops =
+{
+    control,
+};
+
+int rt_hw_pwm_init(void)
+{
+    /* add pwm initial. */
+    if (hal_pwm_init() != 0)
+    {
+        LOG_E("init pwm failed!");
+        return -1;
+    }
+    _hal_pwm_device.status = 0;
+    return rt_device_pwm_register(&_hal_pwm_device.parent, "pwm", &pwm_ops, RT_NULL);
+}
+INIT_DEVICE_EXPORT(rt_hw_pwm_init);
+
+#endif /* RT_USING_PWM && BSP_USING_PWM */

bsp/allwinner/libraries/drivers/drv_rtc.c

@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-17     JasonHu      first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <string.h>
+#include <time.h>
+#include <rtdbg.h>
+
+#include <sunxi_hal_rtc.h>
+
+#ifdef RT_USING_RTC
+
+static rt_err_t rtc_init(struct rt_device *dev)
+{
+    if (hal_rtc_init() != 0)
+    {
+        LOG_E("init rtc hal failed!");
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args)
+{
+    rt_err_t result = RT_EOK;
+    struct tm time_temp;
+    struct tm *time_now;
+    struct rtc_time hal_rtc_time;
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_RTC_GET_TIME:
+
+        if (hal_rtc_gettime(&hal_rtc_time) != 0)
+        {
+            LOG_E("rtc gettime failed!\n");
+            return -RT_ERROR;
+        }
+
+        time_temp.tm_sec = hal_rtc_time.tm_sec;
+        time_temp.tm_min = hal_rtc_time.tm_min;
+        time_temp.tm_hour = hal_rtc_time.tm_hour;
+        time_temp.tm_mday = hal_rtc_time.tm_mday;
+        time_temp.tm_mon = hal_rtc_time.tm_mon;
+        time_temp.tm_year = hal_rtc_time.tm_year;
+
+        *((time_t *)args) = mktime(&time_temp);
+        break;
+    case RT_DEVICE_CTRL_RTC_SET_TIME:
+
+        rt_enter_critical();
+        /* converts calendar time time into local time. */
+        time_now = localtime((const time_t *)args);
+        /* copy the statically located variable */
+        memcpy(&time_temp, time_now, sizeof(struct tm));
+        /* unlock scheduler. */
+        rt_exit_critical();
+
+        hal_rtc_time.tm_sec = time_temp.tm_sec;
+        hal_rtc_time.tm_min = time_temp.tm_min;
+        hal_rtc_time.tm_hour = time_temp.tm_hour;
+        hal_rtc_time.tm_mday = time_temp.tm_mday;
+        hal_rtc_time.tm_mon = time_temp.tm_mon;
+        hal_rtc_time.tm_year = time_temp.tm_year;
+        if (hal_rtc_settime(&hal_rtc_time) != 0)
+        {
+            LOG_E("rtc settime failed!\n");
+            return -RT_ERROR;
+        }
+        break;
+    default:
+        return -RT_EINVAL;
+    }
+
+    return result;
+}
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops rt_hw_rtc_ops =
+{
+    rtc_init,
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    rtc_control
+};
+#endif
+
+int rt_hw_rtc_init(void)
+{
+    rt_err_t ret = RT_EOK;
+    static struct rt_device rtc_dev;
+
+    rtc_dev.type = RT_Device_Class_RTC;
+    rtc_dev.rx_indicate = RT_NULL;
+    rtc_dev.tx_complete = RT_NULL;
+
+#ifdef RT_USING_DEVICE_OPS
+    rtc_dev.ops = &rt_hw_rtc_ops;
+#else
+    rtc_dev.init = rtc_init;
+    rtc_dev.open = RT_NULL;
+    rtc_dev.close = RT_NULL;
+    rtc_dev.read = RT_NULL;
+    rtc_dev.write = RT_NULL;
+    rtc_dev.control = rtc_control;
+#endif
+
+    rtc_dev.user_data = RT_NULL;
+
+#ifdef BSP_USING_RTC
+    ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR);
+#endif
+
+    return ret;
+}
+INIT_DEVICE_EXPORT(rt_hw_rtc_init);
+
+#endif

bsp/allwinner/libraries/drivers/drv_spi.c

@@ -0,0 +1,392 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author          Notes
+ * 2021-12-15     JasonHu         first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+
+#include "drv_spi.h"
+
+#define DBG_TAG     "DRV.SPI"
+#define DBG_LVL     DBG_LOG
+#include <rtdbg.h>
+#include <sunxi_hal_spi.h>
+
+#ifdef BSP_USING_SPI
+
+struct hw_spi_bus
+{
+    struct rt_spi_bus parent;
+    hal_spi_master_port_t port;
+};
+
+#define BSP_SPI_MAX_HZ         SPI_MAX_FREQUENCY
+
+#if defined (BSP_USING_SPI0)
+#define SPI0_BUS_NAME      "spi0"
+#define SPI0_BUS_DEVICE0_NAME      "spi01"
+
+struct hw_spi_bus spi0_bus;
+
+#endif /* BSP_USING_SPI0 */
+
+#if defined (BSP_USING_SPI1)
+#define SPI1_BUS_NAME      "spi1"
+#define SPI1_BUS_DEVICE0_NAME      "spi11"
+
+struct hw_spi_bus spi1_bus;
+
+#endif /* BSP_USING_SPI1 */
+
+static rt_err_t hw_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
+{
+    RT_ASSERT(cfg != RT_NULL);
+    RT_ASSERT(device != RT_NULL);
+
+    struct hw_spi_bus *spi_dev = RT_NULL;
+    hal_spi_master_config_t hal_cfg;
+
+    LOG_D("configure mode:%x, clk:%d\n", cfg->mode, cfg->max_hz);
+
+    /* trans cfg to hal cfg */
+    spi_dev = (struct hw_spi_bus *)(device->parent.user_data);
+
+    if (cfg->max_hz > BSP_SPI_MAX_HZ)
+        cfg->max_hz = BSP_SPI_MAX_HZ;
+
+    /* set default frequency */
+    hal_cfg.clock_frequency = cfg->max_hz;
+    hal_cfg.slave_port = HAL_SPI_MASTER_SLAVE_0; /* only support slave 0 */
+
+    /* byte order */
+    if (cfg->mode & RT_SPI_MSB)
+    {
+        hal_cfg.bit_order = HAL_SPI_MASTER_MSB_FIRST;
+    }
+    else
+    {
+        hal_cfg.bit_order = HAL_SPI_MASTER_LSB_FIRST;
+    }
+
+    if(cfg->mode & RT_SPI_CPOL)
+    {
+        hal_cfg.cpol = HAL_SPI_MASTER_CLOCK_POLARITY1;
+    }
+    else
+    {
+        hal_cfg.cpol = HAL_SPI_MASTER_CLOCK_POLARITY0;
+    }
+
+    if(cfg->mode & RT_SPI_CPHA)
+    {
+        hal_cfg.cpha = HAL_SPI_MASTER_CLOCK_PHASE1;
+    }
+    else
+    {
+        hal_cfg.cpha = HAL_SPI_MASTER_CLOCK_PHASE0;
+    }
+
+    if (cfg->mode & RT_SPI_NO_CS)
+    {
+        hal_cfg.csmode = HAL_SPI_MASTER_CS_AUTO;
+    }
+    else
+    {
+        hal_cfg.csmode = HAL_SPI_MASTER_CS_SOFT;
+    }
+
+    if (hal_spi_hw_config(spi_dev->port, &hal_cfg) != SPI_MASTER_OK)
+    {
+        return -RT_EIO;
+    }
+
+    return RT_EOK;
+}
+
+static rt_uint32_t hw_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    spi_master_status_t ret = SPI_MASTER_OK;
+    hal_spi_master_transfer_t tr;
+    struct hw_spi_bus *spi_dev = RT_NULL;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device->bus != RT_NULL);
+    RT_ASSERT(device->parent.user_data != RT_NULL);
+
+    spi_dev = (struct hw_spi_bus *)(device->parent.user_data);
+
+    tr.rx_buf = message->recv_buf;
+    tr.rx_len = message->recv_buf == RT_NULL ? 0 : message->length;
+    tr.tx_buf = message->send_buf;
+    tr.tx_len = message->send_buf == RT_NULL ? 0 : message->length;
+    tr.dummy_byte = 0;
+    tr.tx_single_len = message->send_buf == RT_NULL ? 0 : message->length;
+    tr.rx_nbits = SPI_NBITS_SINGLE;
+    tr.tx_nbits = SPI_NBITS_SINGLE;
+
+    if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS))
+    {
+        if (device->config.mode & RT_SPI_CS_HIGH)
+        {
+            hal_spi_cs(spi_dev->port, 1);
+        }
+        else
+        {
+            hal_spi_cs(spi_dev->port, 0);
+        }
+    }
+
+    if (message->length > 0)
+    {
+        ret = hal_spi_xfer(spi_dev->port, &tr);
+    }
+
+    // FIXME: GCC O3 maybe not execute.
+    if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS))
+    {
+        if (device->config.mode & RT_SPI_CS_HIGH)
+        {
+            hal_spi_cs(spi_dev->port, 0);
+        }
+        else
+        {
+            hal_spi_cs(spi_dev->port, 1);
+        }
+    }
+
+    if (ret != SPI_MASTER_OK)
+    {
+        LOG_E("xfer err ret:%ld", ret);
+        return -RT_EIO;
+    }
+
+    return message->length;
+}
+
+/**
+ * attach a spi device on bus
+ */
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name)
+{
+    rt_err_t ret = RT_EOK;
+    struct hw_spi_bus *hw_spi = RT_NULL;
+
+    struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+    RT_ASSERT(spi_device != RT_NULL);
+#ifdef BSP_USING_SPI0
+    if (!rt_strcmp(bus_name, SPI0_BUS_NAME))
+    {
+        hw_spi = &spi0_bus;
+    }
+    else
+#endif
+#ifdef BSP_USING_SPI1
+    if (!rt_strcmp(bus_name, SPI0_BUS_NAME))
+    {
+        hw_spi = &spi1_bus;
+    }
+    else
+#endif
+    {
+        return -RT_EIO;
+    }
+    /* TODO: attach device */
+    ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, hw_spi);
+    return ret;
+}
+
+static struct rt_spi_ops hw_spi_ops =
+{
+    .configure = hw_spi_configure,
+    .xfer = hw_spi_xfer
+};
+
+#endif /* BSP_USING_SPI */
+
+/* used to init spi bus */
+static hal_spi_master_config_t default_hal_cfg = {
+    .bit_order = HAL_SPI_MASTER_MSB_FIRST,
+    .clock_frequency = 5000000,//SPI_MOD_CLK,
+    .cpha = HAL_SPI_MASTER_CLOCK_PHASE0,
+    .cpol = HAL_SPI_MASTER_CLOCK_POLARITY0,
+    .slave_port = HAL_SPI_MASTER_SLAVE_0,
+    .csmode = HAL_SPI_MASTER_CS_SOFT,
+};
+
+int rt_hw_spi_init(void)
+{
+#if defined (BSP_USING_SPI0)
+    spi0_bus.port = HAL_SPI_MASTER_0;
+    if (hal_spi_init(spi0_bus.port, &default_hal_cfg) != SPI_MASTER_OK)
+    {
+        LOG_E("hal init %s bus failed!", SPI0_BUS_NAME);
+        return -1;
+    }
+    rt_spi_bus_register(&spi0_bus.parent, SPI0_BUS_NAME, &hw_spi_ops);
+
+    rt_hw_spi_device_attach(SPI0_BUS_NAME, SPI0_BUS_DEVICE0_NAME);
+#endif /* BSP_USING_SPI0 */
+
+#if defined (BSP_USING_SPI1)
+    spi1_bus.port = HAL_SPI_MASTER_1;
+    if (hal_spi_init(spi1_bus.port, &default_hal_cfg) != SPI_MASTER_OK)
+    {
+        LOG_E("hal init %s bus failed!", SPI1_BUS_NAME);
+        return -1;
+    }
+    rt_spi_bus_register(&spi1_bus.parent, SPI1_BUS_NAME, &hw_spi_ops);
+    rt_hw_spi_device_attach(SPI1_BUS_NAME, SPI1_BUS_DEVICE0_NAME);
+
+#endif /* BSP_USING_SPI1 */
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_spi_init);
+
+#define CFG_GPIO_PORT(p) ((p) - 'A' + 1)
+
+int32_t hal_spi_gpio_cfg_count(const char *secname)
+{
+    return 4;
+}
+
+static const user_gpio_set_t _spi_gpio_cfg[][4] = {
+    {// spi0
+        {
+            .gpio_name = "spi0_sclk",
+            .port = CFG_GPIO_PORT('C'),
+            .port_num = 2, // PC02
+            .mul_sel = 2,
+            .pull = 0, // no pull
+            .drv_level = 3,
+            .data = 0,
+        },
+        {
+            .gpio_name = "spi0_cs",
+            .port = CFG_GPIO_PORT('C'),
+            .port_num = 3, // PC03
+            .mul_sel = 2,
+            .pull = 1, // pull up
+            .drv_level = 3,
+            .data = 0,
+        },
+        {
+            .gpio_name = "spi0_mosi",
+            .port = CFG_GPIO_PORT('C'),
+            .port_num = 4, // PC04
+            .mul_sel = 2,
+            .pull = 0, // no pull
+            .drv_level = 3,
+            .data = 0,
+        },
+        {
+            .gpio_name = "spi0_miso",
+            .port = CFG_GPIO_PORT('C'),
+            .port_num = 5, // PC05
+            .mul_sel = 2,
+            .pull = 0, // no pull
+            .drv_level = 3,
+            .data = 0,
+        }
+    },
+};
+
+int hal_spi_gpio_cfg_load(user_gpio_set_t *gpio_cfg, int32_t GPIONum, int id)
+{
+    int i;
+
+    if (id > sizeof(_spi_gpio_cfg) / sizeof(_spi_gpio_cfg[0]))
+    {
+        rt_kprintf("spi id %d>%d\n", id, sizeof(_spi_gpio_cfg) / sizeof(_spi_gpio_cfg[0]));
+        return -1;
+    }
+
+    /* twi0 */
+    for (i = 0; i < GPIONum; i++)
+    {
+        memcpy(gpio_cfg, &_spi_gpio_cfg[id][i], sizeof(user_gpio_set_t));
+        gpio_cfg++;
+    }
+
+    return 0;
+}
+
+/*
+ * 程序清单：这是一个 SPI 设备使用例程
+ * 例程导出了 spi_w25q_sample 命令到控制终端
+ * 命令调用格式：spi_w25q_sample spi10
+ * 命令解释：命令第二个参数是要使用的SPI设备名称，为空则使用默认的SPI设备
+ * 程序功能：通过SPI设备读取 w25q 的 ID 数据
+*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define SPI_DEVICE_NAME     "spi01"
+
+static void spi_sample(int argc, char *argv[])
+{
+    struct rt_spi_device *spi_dev;
+    static char cmd[200];
+    static char recv_data[200];
+    rt_uint8_t id[5] = {0};
+    int i;
+    rt_err_t err;
+    int type;
+
+    type = atoi(argv[1]);
+
+    for (i = 0; i < sizeof(cmd); i++)
+    {
+        cmd[i] = i + 1;
+    }
+
+    /* 查找 spi 设备获取设备句柄 */
+    spi_dev = (struct rt_spi_device *)rt_device_find(SPI_DEVICE_NAME);
+    if (!spi_dev)
+    {
+        rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_DEVICE_NAME);
+    }
+    else
+    {
+        struct rt_spi_configuration spi_cfg;
+        spi_cfg.max_hz = 5000000;
+        spi_cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB;
+        spi_cfg.data_width = 8;
+
+        rt_spi_configure(spi_dev, &spi_cfg);
+        if (type == 1)
+        {
+            err = rt_spi_transfer(spi_dev, cmd, recv_data, sizeof(recv_data));
+        }
+        else if (type == 2)
+        {
+            err = rt_spi_send_then_recv(spi_dev, cmd, sizeof(cmd), recv_data, sizeof(recv_data));
+        }
+        else if (type == 3)
+        {
+            err = rt_spi_send(spi_dev, cmd, sizeof(cmd));
+        }
+        else if (type == 4)
+        {
+            err = rt_spi_send_then_send(spi_dev, cmd, sizeof(cmd), cmd, sizeof(cmd));
+        }
+        else if (type == 5)
+        {
+            err = rt_spi_recv(spi_dev, recv_data, sizeof(recv_data));
+        }
+        // err = rt_spi_send(spi_dev, cmd, sizeof(cmd));
+        if (err != sizeof(cmd))
+        {
+            rt_kprintf("spi send error:%d\n", err);
+        }
+    }
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(spi_sample, spi w25q sample);

bsp/allwinner/libraries/drivers/drv_spi.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author          Notes
+ * 2021-12-15     JasonHu         first version
+ */
+
+#ifndef __DRV_SPI_H__
+#define __DRV_SPI_H__
+
+#include <rtthread.h>
+
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name);
+
+#endif /* __DRV_SPI_H__ */

bsp/allwinner/libraries/drivers/drv_uart.c

@@ -0,0 +1,1053 @@
+/*
+ * Copyright (c) 2019-2020, Xim
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include <rthw.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+#include <stdio.h>
+
+#define DBG_TAG "DRV.UART"
+#define DBG_LVL DBG_WARNING
+#include <rtdbg.h>
+
+#include <hal_clk.h>
+#include <hal_reset.h>
+#include <hal_gpio.h>
+
+#define UART_DEFAULT_BAUDRATE 500000
+
+#ifdef UART0_TX_USING_GPIOB8
+#define UART0_TX GPIOB(8)
+#define UART0_TX_FUNCTION 6
+#elif defined(UART0_TX_USING_GPIOE2)
+#define UART0_TX GPIOE(2)
+#define UART0_TX_FUNCTION 6
+#elif defined(UART0_TX_USING_GPIOF2)
+#define UART0_TX GPIOF(2)
+#define UART0_TX_FUNCTION 3
+#endif
+
+#ifdef UART0_RX_USING_GPIOB9
+#define UART0_RX GPIOB(9)
+#define UART0_RX_FUNCTION 6
+#elif defined(UART0_RX_USING_GPIOE3)
+#define UART0_RX GPIOE(3)
+#define UART0_RX_FUNCTION 6
+#elif defined(UART0_RX_USING_GPIOF4)
+#define UART0_RX GPIOF(4)
+#define UART0_RX_FUNCTION 3
+#endif
+
+#ifdef UART1_TX_USING_GPIOD21
+#define UART1_TX GPIOD(21)
+#define UART1_TX_FUNCTION 4
+#elif defined(UART1_TX_USING_GPIOE10)
+#define UART1_TX GPIOE(10)
+#define UART1_TX_FUNCTION 3
+#elif defined(UART1_TX_USING_GPIOG6)
+#define UART1_TX GPIOG(6)
+#define UART1_TX_FUNCTION 3
+#elif defined(UART1_TX_USING_GPIOG12)
+#define UART1_TX GPIOG(12)
+#define UART1_TX_FUNCTION 7
+#endif
+
+#ifdef UART1_RX_USING_GPIOD22
+#define UART1_RX GPIOD(22)
+#define UART1_RX_FUNCTION 4
+#elif defined(UART1_RX_USING_GPIOE11)
+#define UART1_RX GPIOE(11)
+#define UART1_RX_FUNCTION 3
+#elif defined(UART1_RX_USING_GPIOG7)
+#define UART1_RX GPIOG(7)
+#define UART1_RX_FUNCTION 3
+#elif defined(UART1_RX_USING_GPIOG13)
+#define UART1_RX GPIOG(13)
+#define UART1_RX_FUNCTION 7
+#endif
+
+#ifdef UART2_TX_USING_GPIOD1
+#define UART2_TX GPIOD(1)
+#define UART2_TX_FUNCTION 5
+#elif defined(UART2_TX_USING_GPIOE2)
+#define UART2_TX GPIOE(2)
+#define UART2_TX_FUNCTION 3
+#endif
+
+#ifdef UART2_RX_USING_GPIOD2
+#define UART2_RX GPIOD(2)
+#define UART2_RX_FUNCTION 5
+#elif defined(UART2_RX_USING_GPIOE3)
+#define UART2_RX GPIOE(3)
+#define UART2_RX_FUNCTION 3
+#endif
+
+#ifdef UART3_TX_USING_GPIOB6
+#define UART3_TX GPIOB(6)
+#define UART3_TX_FUNCTION 7
+#elif defined(UART3_TX_USING_GPIOC6)
+#define UART3_TX GPIOC(6)
+#define UART3_TX_FUNCTION 4
+#elif defined(UART3_TX_USING_GPIOD10)
+#define UART3_TX GPIOD(10)
+#define UART3_TX_FUNCTION 5
+#elif defined(UART3_TX_USING_GPIOE8)
+#define UART3_TX GPIOE(8)
+#define UART3_TX_FUNCTION 5
+#elif defined(UART3_TX_USING_GPIOG0)
+#define UART3_TX GPIOG(0)
+#define UART3_TX_FUNCTION 3
+#elif defined(UART3_TX_USING_GPIOG8)
+#define UART3_TX GPIOG(8)
+#define UART3_TX_FUNCTION 5
+#endif
+
+#ifdef UART3_RX_USING_GPIOB7
+#define UART3_RX GPIOB(7)
+#define UART3_RX_FUNCTION 7
+#elif defined(UART3_RX_USING_GPIOC7)
+#define UART3_RX GPIOC(7)
+#define UART3_RX_FUNCTION 4
+#elif defined(UART3_RX_USING_GPIOD11)
+#define UART3_RX GPIOD(11)
+#define UART3_RX_FUNCTION 5
+#elif defined(UART3_RX_USING_GPIOE9)
+#define UART3_RX GPIOE(9)
+#define UART3_RX_FUNCTION 5
+#elif defined(UART3_RX_USING_GPIOG1)
+#define UART3_RX GPIOG(1)
+#define UART3_RX_FUNCTION 3
+#elif defined(UART3_RX_USING_GPIOG9)
+#define UART3_RX GPIOG(9)
+#define UART3_RX_FUNCTION 5
+#endif
+
+#ifdef UART4_TX_USING_GPIOB2
+#define UART4_TX GPIOB(2)
+#define UART4_TX_FUNCTION 7
+#elif defined(UART4_TX_USING_GPIOD7)
+#define UART4_TX GPIOD(7)
+#define UART4_TX_FUNCTION 5
+#elif defined(UART4_TX_USING_GPIOE4)
+#define UART4_TX GPIOE(4)
+#define UART4_TX_FUNCTION 3
+#elif defined(UART4_TX_USING_GPIOG2)
+#define UART4_TX GPIOG(2)
+#define UART4_TX_FUNCTION 5
+#endif
+
+#ifdef UART4_RX_USING_GPIOB3
+#define UART4_RX GPIOB(3)
+#define UART4_RX_FUNCTION 7
+#elif defined(UART4_RX_USING_GPIOD8)
+#define UART4_RX GPIOD(8)
+#define UART4_RX_FUNCTION 5
+#elif defined(UART4_RX_USING_GPIOE5)
+#define UART4_RX GPIOE(5)
+#define UART4_RX_FUNCTION 3
+#elif defined(UART4_TX_USING_GPIOG3)
+#define UART4_RX GPIOG(3)
+#define UART4_RX_FUNCTION 5
+#endif
+
+#ifdef UART5_TX_USING_GPIOB4
+#define UART5_TX GPIOB(4)
+#define UART5_TX_FUNCTION 7
+#elif defined(UART5_TX_USING_GPIOD5)
+#define UART5_TX GPIOD(5)
+#define UART5_TX_FUNCTION 5
+#elif defined(UART5_TX_USING_GPIOE6)
+#define UART5_TX GPIOE(6)
+#define UART5_TX_FUNCTION 3
+#elif defined(UART5_TX_USING_GPIOG4)
+#define UART5_TX GPIOG(4)
+#define UART5_TX_FUNCTION 3
+#endif
+
+#ifdef UART5_RX_USING_GPIOB5
+#define UART5_RX GPIOB(5)
+#define UART5_RX_FUNCTION 7
+#elif defined(UART5_RX_USING_GPIOD6)
+#define UART5_RX GPIOD(6)
+#define UART5_RX_FUNCTION 5
+#elif defined(UART5_RX_USING_GPIOE7)
+#define UART5_RX GPIOE(7)
+#define UART5_RX_FUNCTION 3
+#elif defined(UART5_RX_USING_GPIOG5)
+#define UART5_RX GPIOG(5)
+#define UART5_RX_FUNCTION 3
+#endif
+
+#define SUNXI_CLK_UART0 CLK_BUS_UART0;
+#define SUNXI_RST_UART0 RST_BUS_UART0;
+
+#define SUNXI_CLK_UART1 CLK_BUS_UART1;
+#define SUNXI_RST_UART1 RST_BUS_UART1;
+
+#define SUNXI_CLK_UART2 CLK_BUS_UART2;
+#define SUNXI_RST_UART2 RST_BUS_UART2;
+
+#define SUNXI_CLK_UART3 CLK_BUS_UART3;
+#define SUNXI_RST_UART3 RST_BUS_UART3;
+
+#define SUNXI_CLK_UART4 CLK_BUS_UART4;
+#define SUNXI_RST_UART4 RST_BUS_UART4;
+
+#define SUNXI_CLK_UART5 CLK_BUS_UART5;
+#define SUNXI_RST_UART5 RST_BUS_UART5;
+
+#define SUNXI_IRQ_UART0 (18)
+#define SUNXI_IRQ_UART1 (19)
+#define SUNXI_IRQ_UART2 (20)
+#define SUNXI_IRQ_UART3 (21)
+#define SUNXI_IRQ_UART4 (22)
+#define SUNXI_IRQ_UART5 (23)
+
+#define SUNXI_UART0_BASE (0x02500000)
+#define SUNXI_UART1_BASE (0x02500400)
+#define SUNXI_UART2_BASE (0x02500800)
+#define SUNXI_UART3_BASE (0x02500c00)
+#define SUNXI_UART4_BASE (0x02501000)
+#define SUNXI_UART5_BASE (0x02501400)
+
+/*
+ * Register definitions for UART
+ */
+#define UART_RHB (0x00)
+#define UART_RBR (0x00)   /* receive buffer register */
+#define UART_THR (0x00)   /* transmit holding register */
+#define UART_DLL (0x00)   /* divisor latch low register */
+#define UART_DLH (0x04)   /* diviso latch high register */
+#define UART_IER (0x04)   /* interrupt enable register */
+#define UART_IIR (0x08)   /* interrupt identity register */
+#define UART_FCR (0x08)   /* FIFO control register */
+#define UART_LCR (0x0c)   /* line control register */
+#define UART_MCR (0x10)   /* modem control register */
+#define UART_LSR (0x14)   /* line status register */
+#define UART_MSR (0x18)   /* modem status register */
+#define UART_SCH (0x1c)   /* scratch register */
+#define UART_USR (0x7c)   /* status register */
+#define UART_TFL (0x80)   /* transmit FIFO level */
+#define UART_RFL (0x84)   /* RFL */
+#define UART_HALT (0xa4)  /* halt tx register */
+#define UART_RS485 (0xc0) /* RS485 control and status register */
+
+/*
+ * register bit field define
+ */
+
+/* Interrupt Enable Register */
+#define UART_IER_MASK (0xff)
+#define UART_IER_PTIME (BIT(7))
+#define UART_IER_RS485 (BIT(4))
+#define UART_IER_MSI (BIT(3))
+#define UART_IER_RLSI (BIT(2))
+#define UART_IER_THRI (BIT(1))
+#define UART_IER_RDI (BIT(0))
+/* Interrupt ID Register */
+#define UART_IIR_FEFLAG_MASK (BIT(6) | BIT(7))
+#define UART_IIR_IID_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
+#define UART_IIR_IID_MSTA (0)
+#define UART_IIR_IID_NOIRQ (1)
+#define UART_IIR_IID_THREMP (2)
+#define UART_IIR_IID_RXDVAL (4)
+#define UART_IIR_IID_LINESTA (6)
+#define UART_IIR_IID_BUSBSY (7)
+#define UART_IIR_IID_CHARTO (12)
+/* FIFO Control Register */
+#define UART_FCR_RXTRG_MASK (BIT(6) | BIT(7))
+#define UART_FCR_RXTRG_1CH (0 << 6)
+#define UART_FCR_RXTRG_1_4 (1 << 6)
+#define UART_FCR_RXTRG_1_2 (2 << 6)
+#define UART_FCR_RXTRG_FULL (3 << 6)
+#define UART_FCR_TXTRG_MASK (BIT(4) | BIT(5))
+#define UART_FCR_TXTRG_EMP (0 << 4)
+#define UART_FCR_TXTRG_2CH (1 << 4)
+#define UART_FCR_TXTRG_1_4 (2 << 4)
+#define UART_FCR_TXTRG_1_2 (3 << 4)
+#define UART_FCR_TXFIFO_RST (BIT(2))
+#define UART_FCR_RXFIFO_RST (BIT(1))
+#define UART_FCR_FIFO_EN (BIT(0))
+/* Line Control Register */
+#define UART_LCR_DLAB (BIT(7))
+#define UART_LCR_SBC (BIT(6))
+#define UART_LCR_PARITY_MASK (BIT(5) | BIT(4))
+#define UART_LCR_EPAR (1 << 4)
+#define UART_LCR_OPAR (0 << 4)
+#define UART_LCR_PARITY (BIT(3))
+#define UART_LCR_STOP (BIT(2))
+#define UART_LCR_DLEN_MASK (BIT(1) | BIT(0))
+#define UART_LCR_WLEN5 (0)
+#define UART_LCR_WLEN6 (1)
+#define UART_LCR_WLEN7 (2)
+#define UART_LCR_WLEN8 (3)
+/* Modem Control Register */
+#define UART_MCR_MODE_MASK (BIT(7) | BIT(6))
+#define UART_MCR_MODE_RS485 (2 << 6)
+#define UART_MCR_MODE_SIRE (1 << 6)
+#define UART_MCR_MODE_UART (0 << 6)
+#define UART_MCR_AFE (BIT(5))
+#define UART_MCR_LOOP (BIT(4))
+#define UART_MCR_RTS (BIT(1))
+#define UART_MCR_DTR (BIT(0))
+/* Line Status Rigster */
+#define UART_LSR_RXFIFOE (BIT(7))
+#define UART_LSR_TEMT (BIT(6))
+#define UART_LSR_THRE (BIT(5))
+#define UART_LSR_BI (BIT(4))
+#define UART_LSR_FE (BIT(3))
+#define UART_LSR_PE (BIT(2))
+#define UART_LSR_OE (BIT(1))
+#define UART_LSR_DR (BIT(0))
+#define UART_LSR_BRK_ERROR_BITS (0x1E) /* BI, FE, PE, OE bits */
+/* Modem Status Register */
+#define UART_MSR_DCD (BIT(7))
+#define UART_MSR_RI (BIT(6))
+#define UART_MSR_DSR (BIT(5))
+#define UART_MSR_CTS (BIT(4))
+#define UART_MSR_DDCD (BIT(3))
+#define UART_MSR_TERI (BIT(2))
+#define UART_MSR_DDSR (BIT(1))
+#define UART_MSR_DCTS (BIT(0))
+#define UART_MSR_ANY_DELTA (0x0F)
+#define MSR_SAVE_FLAGS (UART_MSR_ANY_DELTA)
+/* Status Register */
+#define UART_USR_RFF (BIT(4))
+#define UART_USR_RFNE (BIT(3))
+#define UART_USR_TFE (BIT(2))
+#define UART_USR_TFNF (BIT(1))
+#define UART_USR_BUSY (BIT(0))
+/* Halt Register */
+#define UART_HALT_LCRUP (BIT(2))
+#define UART_HALT_FORCECFG (BIT(1))
+#define UART_HALT_HTX (BIT(0))
+/* RS485 Control and Status Register */
+#define UART_RS485_RXBFA (BIT(3))
+#define UART_RS485_RXAFA (BIT(2))
+
+typedef enum
+{
+    UART_0 = 0,
+    UART_1,
+    UART_2,
+    UART_3,
+    UART_4,
+    UART_5,
+    UART_MAX,
+} uart_port_t;
+
+/* This enum defines word length of the UART frame. */
+typedef enum
+{
+    UART_WORD_LENGTH_5 = 0,
+    UART_WORD_LENGTH_6,
+    UART_WORD_LENGTH_7,
+    UART_WORD_LENGTH_8,
+} uart_word_length_t;
+
+/* This enum defines stop bit of the UART frame. */
+typedef enum
+{
+    UART_STOP_BIT_1 = 0,
+    UART_STOP_BIT_2,
+} uart_stop_bit_t;
+
+/* This enum defines parity of the UART frame. */
+typedef enum
+{
+    UART_PARITY_NONE = 0,
+    UART_PARITY_ODD,
+    UART_PARITY_EVEN
+} uart_parity_t;
+
+struct sunxi_uart
+{
+    uart_port_t uart_port;
+    uint32_t irqno;
+
+    rt_uint16_t uart_dma_flag;
+    struct rt_completion tx_fifo_empty;
+};
+
+static const size_t _uart_base[] =
+    {
+        SUNXI_UART0_BASE, SUNXI_UART1_BASE, SUNXI_UART2_BASE, SUNXI_UART3_BASE, SUNXI_UART4_BASE, SUNXI_UART5_BASE};
+
+static const uint32_t _uart_irqn[] =
+    {
+        SUNXI_IRQ_UART0, SUNXI_IRQ_UART1, SUNXI_IRQ_UART2, SUNXI_IRQ_UART3, SUNXI_IRQ_UART4, SUNXI_IRQ_UART5};
+
+static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
+static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg);
+static int _uart_putc(struct rt_serial_device *serial, char c);
+static int _uart_getc(struct rt_serial_device *serial);
+static rt_size_t _uart_transmit(struct rt_serial_device *serial,
+                                rt_uint8_t *buf, rt_size_t size, rt_uint32_t tx_flag);
+
+const struct rt_uart_ops _uart_ops =
+    {
+        _uart_configure,
+        _uart_control,
+        _uart_putc,
+        _uart_getc,
+        _uart_transmit};
+
+#ifdef BSP_USING_UART0
+struct rt_serial_device serial0;
+struct sunxi_uart uart0 = {
+    .uart_port = UART_0,
+    .irqno = SUNXI_IRQ_UART0};
+#endif
+
+#ifdef BSP_USING_UART1
+struct rt_serial_device serial1;
+struct sunxi_uart uart1 = {
+    .uart_port = UART_1,
+    .irqno = SUNXI_IRQ_UART1};
+#endif
+
+#ifdef BSP_USING_UART2
+struct rt_serial_device serial2;
+struct sunxi_uart uart2 = {
+    .uart_port = UART_2,
+    .irqno = SUNXI_IRQ_UART2};
+#endif
+
+#ifdef BSP_USING_UART3
+struct rt_serial_device serial3;
+struct sunxi_uart uart3 = {
+    .uart_port = UART_3,
+    .irqno = SUNXI_IRQ_UART3};
+#endif
+
+#ifdef BSP_USING_UART4
+struct rt_serial_device serial4;
+struct sunxi_uart uart4 = {
+    .uart_port = UART_4,
+    .irqno = SUNXI_IRQ_UART4};
+#endif
+
+#ifdef BSP_USING_UART5
+struct rt_serial_device serial5;
+struct sunxi_uart uart5 = {
+    .uart_port = UART_5,
+    .irqno = SUNXI_IRQ_UART5};
+#endif
+
+static void uart_set_baudrate(uart_port_t uart_port, uint32_t baudrate)
+{
+    size_t uart_base;
+    uint32_t quot, uart_clk;
+    uint8_t lcr;
+
+    uart_base = SUNXI_UART0_BASE + uart_port * 0x400;
+    uart_clk = 24000000; /* FIXME: fixed to 24MHz */
+
+    quot = (uart_clk + 8 * baudrate) / (16 * baudrate);
+
+    lcr = hal_readb(uart_base + UART_LCR);
+
+    /* hold tx so that uart will update lcr and baud in the gap of tx */
+    hal_writeb(UART_HALT_HTX | UART_HALT_FORCECFG, uart_base + UART_HALT);
+    hal_writeb(lcr | UART_LCR_DLAB, uart_base + UART_LCR);
+    hal_writeb(quot >> 8, uart_base + UART_DLH);
+    hal_writeb(quot & 0xFFu, uart_base + UART_DLL);
+    hal_writeb(UART_HALT_HTX | UART_HALT_FORCECFG | UART_HALT_LCRUP, uart_base + UART_HALT);
+    /* FIXME: implement timeout */
+    while (hal_readb(uart_base + UART_HALT) & UART_HALT_LCRUP)
+        ;
+
+    /* In fact there are two DLABs(DLAB and DLAB_BAK) in the hardware implementation.
+     * The DLAB_BAK is sellected only when SW_UART_HALT_FORCECFG is set to 1,
+     * and this bit can be access no matter uart is busy or not.
+     * So we select the DLAB_BAK always by leaving SW_UART_HALT_FORCECFG to be 1. */
+    hal_writeb(lcr, uart_base + UART_LCR);
+    hal_writeb(UART_HALT_FORCECFG, uart_base + UART_HALT);
+}
+
+static void uart_set_format(uart_port_t uart_port, uint8_t data_bits, uint8_t stop_bits, uint8_t parity)
+{
+    size_t uart_base;
+    uint8_t lcr;
+
+    uart_base = SUNXI_UART0_BASE + uart_port * 0x400;
+
+    lcr = hal_readb(uart_base + UART_LCR);
+
+    /* set word length */
+    lcr &= ~(UART_LCR_DLEN_MASK);
+    switch (data_bits)
+    {
+    case 5:
+        lcr |= UART_LCR_WLEN5;
+        break;
+    case 6:
+        lcr |= UART_LCR_WLEN6;
+        break;
+    case 7:
+        lcr |= UART_LCR_WLEN7;
+        break;
+    case 8:
+    default:
+        lcr |= UART_LCR_WLEN8;
+        break;
+    }
+
+    /* set stop bit */
+    switch (stop_bits)
+    {
+    case 1:
+    default:
+        lcr &= ~(UART_LCR_STOP);
+        break;
+    case 2:
+        lcr |= UART_LCR_STOP;
+        break;
+    }
+
+    /* set parity bit */
+    lcr &= ~(UART_LCR_PARITY_MASK);
+    switch (parity)
+    {
+    case PARITY_NONE:
+        lcr &= ~(UART_LCR_PARITY);
+        break;
+    case PARITY_ODD:
+        lcr |= UART_LCR_PARITY;
+        break;
+    case PARITY_EVEN:
+        lcr |= UART_LCR_PARITY;
+        lcr |= UART_LCR_EPAR;
+        break;
+    }
+
+    hal_writeb(lcr, uart_base + UART_LCR);
+}
+
+static void uart_set_fifo(uart_port_t uart_port)
+{
+    size_t uart_base;
+    uint8_t fcr;
+
+    uart_base = SUNXI_UART0_BASE + uart_port * 0x400;
+
+    fcr = UART_FCR_RXTRG_1_2 | UART_FCR_TXTRG_EMP | UART_FCR_FIFO_EN;
+
+    hal_writeb(fcr, uart_base + UART_FCR);
+}
+
+static void uart_forcechange(uart_port_t uart_port)
+{
+    size_t uart_base;
+    uint32_t value;
+
+    uart_base = SUNXI_UART0_BASE + uart_port * 0x400;
+
+    value = hal_readb(uart_base + UART_HALT);
+    value |= UART_HALT_FORCECFG;
+    hal_writeb(value, uart_base + UART_HALT);
+}
+
+static void uart_set_isr(uart_port_t uart_port, uint8_t enable, uint32_t irq_type)
+{
+    size_t uart_base;
+    uint32_t value;
+
+    uart_base = SUNXI_UART0_BASE + uart_port * 0x400;
+
+    value = hal_readb(uart_base + UART_IER);
+
+    if (enable)
+    {
+        value |= irq_type;
+    }
+    else
+    {
+        value &= ~irq_type;
+    }
+    hal_writeb(value, uart_base + UART_IER);
+}
+
+/*
+ * UART interface
+ */
+static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct sunxi_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    serial->config = *cfg;
+    uart = serial->parent.user_data;
+
+    uart_set_format(uart->uart_port, cfg->data_bits, cfg->stop_bits, cfg->parity);
+    uart_set_baudrate(uart->uart_port, cfg->baud_rate);
+    uart_set_fifo(uart->uart_port);
+    uart_forcechange(uart->uart_port);
+
+    return RT_EOK;
+}
+
+static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct sunxi_uart *uart;
+    rt_uint32_t channel = 1;
+#ifdef RT_USING_SERIAL_V2
+    rt_ubase_t ctrl_flag = 0;
+    rt_ubase_t ctrl_arg;
+#endif
+
+    uart = serial->parent.user_data;
+
+    RT_ASSERT(uart != RT_NULL);
+    RT_ASSERT(channel != 3);
+
+#ifdef RT_USING_SERIAL_V2
+    ctrl_arg = (rt_ubase_t)arg;
+
+    if (ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING))
+    {
+        ctrl_flag |= RT_DEVICE_FLAG_INT_RX;
+    }
+    else if (ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING))
+    {
+        if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
+        {
+            ctrl_flag = RT_DEVICE_FLAG_DMA_TX;
+        }
+        else
+        {
+            ctrl_flag = RT_DEVICE_FLAG_INT_TX;
+        }
+    }
+#endif
+
+    LOG_D("uart%d control cmd:%x, arg:%x\n", uart->uart_port, cmd, ctrl_arg);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+#ifdef RT_USING_SERIAL_V2
+        if (ctrl_flag & RT_DEVICE_FLAG_INT_RX)
+#else
+        if ((size_t)arg == RT_DEVICE_FLAG_INT_RX)
+#endif
+        {
+            uart_set_isr(uart->uart_port, 0, UART_IER_RDI | UART_IER_RLSI);
+        }
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+#ifdef RT_USING_SERIAL_V2
+        if (ctrl_flag & RT_DEVICE_FLAG_INT_RX)
+#else
+        if ((size_t)arg == RT_DEVICE_FLAG_INT_RX)
+#endif
+        {
+            uart_set_isr(uart->uart_port, 1, UART_IER_RDI | UART_IER_RLSI);
+        }
+        break;
+#ifdef RT_USING_SERIAL_V2
+    case RT_DEVICE_CTRL_CONFIG:
+        if (ctrl_flag & RT_DEVICE_FLAG_INT_RX)
+        {
+            uart_set_isr(uart->uart_port, 1, UART_IER_RDI | UART_IER_RLSI);
+        }
+        break;
+
+    case RT_DEVICE_CHECK_OPTMODE:
+        if (ctrl_flag & RT_DEVICE_FLAG_DMA_TX)
+        {
+            return RT_SERIAL_TX_BLOCKING_NO_BUFFER;
+        }
+        else
+        {
+            return RT_SERIAL_TX_BLOCKING_BUFFER;
+        }
+#endif /* RT_USING_SERIAL_V2 */
+    }
+
+    return (RT_EOK);
+}
+
+static int _uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct sunxi_uart *uart;
+    size_t uart_base;
+
+    uart = serial->parent.user_data;
+
+    uart_base = SUNXI_UART0_BASE + uart->uart_port * 0x400;
+
+    /* FIFO status, contain valid data */
+    while (!(hal_readl(uart_base + UART_USR) & UART_USR_TFNF))
+        ;
+
+    hal_writeb(c, uart_base + UART_THR);
+
+    // wait TX FIFO and the TX shift Register are empty.
+    while (!(hal_readl(uart_base + UART_LSR) & UART_LSR_TEMT))
+        ;
+
+    return 1;
+}
+
+static int _uart_getc(struct rt_serial_device *serial)
+{
+    struct sunxi_uart *uart;
+    size_t uart_base;
+    int data = -1;
+
+    uart = serial->parent.user_data;
+    uart_base = SUNXI_UART0_BASE + uart->uart_port * 0x400;
+
+    while (!(hal_readl(uart_base + UART_RFL) & 0x1FFu))
+        ;
+
+    /* Receive Data Available */
+    if (hal_readl(uart_base + UART_USR) & UART_USR_RFNE)
+    {
+        data = hal_readb(uart_base + UART_RBR);
+    }
+
+    return data;
+}
+
+static rt_size_t _uart_transmit(struct rt_serial_device *serial,
+                                rt_uint8_t *buf, rt_size_t size, rt_uint32_t tx_flag)
+{
+    struct sunxi_uart *uart;
+    size_t uart_base;
+
+    uart = serial->parent.user_data;
+    uart_base = SUNXI_UART0_BASE + uart->uart_port * 0x400;
+
+    if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
+    {
+        uint32_t remain = size;
+
+        while (remain)
+        {
+            uint32_t write_count = 0;
+
+            while (remain && (hal_readl(uart_base + UART_USR) & UART_USR_TFNF))
+            {
+                rt_uint8_t c = *buf++;
+                hal_writeb(c, uart_base + UART_THR);
+                remain--;
+                write_count++;
+            }
+
+            while (write_count)
+            {
+                if (hal_readl(uart_base + UART_LSR) & UART_LSR_TEMT)
+                {
+                    break;
+                }
+
+                rt_completion_init(&(uart->tx_fifo_empty));
+                uart_set_isr(uart->uart_port, 1, UART_IER_THRI);
+
+                rt_err_t result = rt_completion_wait(&(uart->tx_fifo_empty), 100); // TODO: timeout calc by baud-rate.
+                if (result == RT_EOK)
+                {
+                    break;
+                }
+            }
+        }
+
+        /* last byte, must wait TEMT(transmitter Empty). TODO: need delay? */
+        while (1)
+        {
+            if (hal_readl(uart_base + UART_LSR) & UART_LSR_TEMT)
+            {
+                break;
+            }
+        }
+
+        {
+            struct rt_serial_tx_fifo *tx_fifo = RT_NULL;
+            tx_fifo = (struct rt_serial_tx_fifo *)serial->serial_tx;
+            tx_fifo->activated = RT_FALSE;
+            rt_completion_done(&(tx_fifo->tx_cpt));
+        }
+
+        return size;
+    }
+
+    return 0;
+}
+
+/**
+ * this function will called when uart interrupt occur!
+ */
+static void uart_irq_handler(int vector, void *param)
+{
+    size_t uart_base;
+    uint32_t iir, lsr;
+    struct rt_serial_device *serial;
+    struct sunxi_uart *uart;
+
+    LOG_D("serial3:%p, uart3:%p\n", &serial3, &uart3);
+    serial = (struct rt_serial_device *)param;
+    uart = (struct sunxi_uart *)serial->parent.user_data;
+
+    LOG_D("isr serial:%p, uart:%p, name:%s\n", serial, uart, serial->parent.parent.name);
+
+    uart_base = SUNXI_UART0_BASE + uart->uart_port * 0x400;
+    iir = hal_readb(uart_base + UART_IIR) & UART_IIR_IID_MASK;
+    lsr = hal_readb(uart_base + UART_LSR);
+
+    LOG_D("IRQ uart%d lsr is %08x \n", uart->uart_port, lsr);
+    if (iir == UART_IIR_IID_BUSBSY)
+    {
+        (void)hal_readb(uart_base + UART_USR);
+
+        /*
+         * Before reseting lcr, we should ensure than uart is not in busy
+         * state. Otherwise, a new busy interrupt will be introduced.
+         * It is wise to set uart into loopback mode, since it can cut down the
+         * serial in, then we should reset fifo(in my test, busy state
+         * (UART_USR_BUSY) can't be cleard until the fifo is empty).
+         */
+        hal_writeb(hal_readb(uart_base + UART_MCR) | UART_MCR_LOOP, uart_base + UART_MCR);
+
+        hal_writeb(UART_FCR_FIFO_EN, uart_base + UART_FCR);
+        hal_writeb(UART_FCR_TXFIFO_RST | UART_FCR_RXFIFO_RST | UART_FCR_FIFO_EN, uart_base + UART_FCR);
+        hal_writeb(0, uart_base + UART_FCR);
+
+        uart_set_fifo(uart->uart_port);
+        (void)hal_readb(uart_base + UART_FCR);
+
+        hal_writeb(hal_readb(uart_base + UART_MCR) & ~UART_MCR_LOOP, uart_base + UART_MCR); /* exit loopback mode. */
+    }
+    else
+    {
+        if (lsr & (UART_LSR_DR | UART_LSR_BI))
+        {
+#ifdef RT_USING_SERIAL_V2
+            struct rt_serial_rx_fifo *rx_fifo;
+            uint8_t data;
+
+            rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
+            RT_ASSERT(rx_fifo != RT_NULL);
+
+            do
+            {
+                data = hal_readb(uart_base + UART_RBR);
+                rt_ringbuffer_putchar(&(rx_fifo->rb), data);
+                lsr = hal_readb(uart_base + UART_LSR);
+            } while (lsr & UART_LSR_DR);
+
+#endif
+
+            rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+        }
+        else if (iir & UART_IIR_IID_CHARTO)
+        /* has charto irq but no dr lsr? just read and ignore */
+        {
+            hal_readb(uart_base + UART_RBR);
+        }
+
+        /* if (lsr & UART_LSR_THRE)
+        {
+            uart_handle_tx(uart_port);
+        }*/
+    }
+
+    if (iir == UART_IIR_IID_THREMP)
+    {
+        uart_set_isr(uart->uart_port, 0, UART_IER_THRI);
+        rt_completion_done(&(uart->tx_fifo_empty));
+    }
+}
+
+static int uart_clk_init(int bus, uint8_t enable)
+{
+    hal_clk_status_t ret;
+    hal_reset_type_t reset_type = HAL_SUNXI_RESET;
+    u32 reset_id;
+    hal_clk_type_t clk_type = HAL_SUNXI_CCU;
+    hal_clk_id_t clk_id;
+    hal_clk_t clk;
+    struct reset_control *reset;
+
+    switch (bus)
+    {
+    case 0:
+        clk_id = SUNXI_CLK_UART0;
+        reset_id = SUNXI_RST_UART0;
+        break;
+    case 1:
+        clk_id = SUNXI_CLK_UART1;
+        reset_id = SUNXI_RST_UART1;
+        break;
+    case 2:
+        clk_id = SUNXI_CLK_UART2;
+        reset_id = SUNXI_RST_UART2;
+        break;
+    case 3:
+        clk_id = SUNXI_CLK_UART3;
+        reset_id = SUNXI_RST_UART3;
+        break;
+    case 4:
+        clk_id = SUNXI_CLK_UART4;
+        reset_id = SUNXI_RST_UART4;
+        break;
+    case 5:
+        clk_id = SUNXI_CLK_UART5;
+        reset_id = SUNXI_RST_UART5;
+        break;
+    default:
+        LOG_E("uart%d is invalid\n", bus);
+        return -1;
+    }
+
+    if (enable)
+    {
+        reset = hal_reset_control_get(reset_type, reset_id);
+        hal_reset_control_deassert(reset);
+        hal_reset_control_put(reset);
+
+        clk = hal_clock_get(clk_type, clk_id);
+        ret = hal_clock_enable(clk);
+        if (ret)
+        {
+            LOG_E("[uart%d] couldn't enable clk!\n", bus);
+            return -1;
+        }
+    }
+    else
+    {
+        clk = hal_clock_get(clk_type, clk_id);
+        ret = hal_clock_disable(clk);
+        if (ret)
+        {
+            LOG_E("[uart%d] couldn't disable clk!\n", bus);
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+static void uart_pinctrl_init(uart_port_t uart_port)
+{
+    switch (uart_port)
+    {
+#ifdef BSP_USING_UART0
+    case UART_0:
+        hal_gpio_set_pull(UART0_RX, GPIO_PULL_UP);
+        hal_gpio_pinmux_set_function(UART0_TX, UART0_TX_FUNCTION); // TX
+        hal_gpio_pinmux_set_function(UART0_RX, UART0_RX_FUNCTION); // RX
+        break;
+#endif
+#ifdef BSP_USING_UART1
+    case UART_1:
+        hal_gpio_set_pull(UART1_RX, GPIO_PULL_UP);
+        hal_gpio_pinmux_set_function(UART1_TX, UART1_TX_FUNCTION); // TX
+        hal_gpio_pinmux_set_function(UART1_RX, UART1_RX_FUNCTION); // RX
+        break;
+#endif
+#ifdef BSP_USING_UART2
+    case UART_2:
+        hal_gpio_set_pull(UART2_RX, GPIO_PULL_UP);
+        hal_gpio_pinmux_set_function(UART2_TX, UART2_TX_FUNCTION); // TX
+        hal_gpio_pinmux_set_function(UART2_RX, UART2_RX_FUNCTION); // RX
+        break;
+#endif
+#ifdef BSP_USING_UART3
+    case UART_3:
+        hal_gpio_set_pull(UART3_RX, GPIO_PULL_UP);
+        hal_gpio_pinmux_set_function(UART3_TX, UART3_TX_FUNCTION); // TX
+        hal_gpio_pinmux_set_function(UART3_RX, UART3_RX_FUNCTION); // RX
+        break;
+#endif
+#ifdef BSP_USING_UART4
+    case UART_4:
+        hal_gpio_set_pull(UART4_RX, GPIO_PULL_UP);
+        hal_gpio_pinmux_set_function(UART4_TX, UART4_TX_FUNCTION); // TX
+        hal_gpio_pinmux_set_function(UART4_RX, UART4_RX_FUNCTION); // RX
+        break;
+#endif
+#ifdef BSP_USING_UART5
+    case UART_5:
+        hal_gpio_set_pull(UART5_RX, GPIO_PULL_UP);
+        hal_gpio_pinmux_set_function(UART5_TX, UART5_TX_FUNCTION); // TX
+        hal_gpio_pinmux_set_function(UART5_RX, UART5_RX_FUNCTION); // RX
+        break;
+#endif
+    default:
+        LOG_E("[uart%d] not support \n", uart_port);
+        break;
+    }
+}
+
+static int uart_init(const char *name, struct sunxi_uart *uart, struct rt_serial_device *serial)
+{
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    uart_clk_init(uart->uart_port, 1);
+    uart_pinctrl_init(uart->uart_port);
+
+    serial->ops = &_uart_ops;
+    serial->config = config;
+    serial->config.rx_bufsz = 256;
+    serial->config.tx_bufsz = 0;
+    serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
+
+    if (strcmp(name, RT_CONSOLE_DEVICE_NAME) == 0)
+    {
+        uart->uart_dma_flag = 0;
+        rt_hw_serial_register(serial, name, RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
+    }
+    else
+    {
+        uart->uart_dma_flag = RT_DEVICE_FLAG_DMA_TX;
+        rt_hw_serial_register(serial, name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
+    }
+
+    rt_hw_interrupt_install(uart->irqno, uart_irq_handler, serial, name);
+    rt_hw_interrupt_umask(uart->irqno);
+
+    return 0;
+}
+
+/*
+ * UART Initiation
+ */
+int rt_hw_uart_init(void)
+{
+#ifdef BSP_USING_UART0
+    uart_init("uart0", &uart0, &serial0);
+#endif
+
+#ifdef BSP_USING_UART1
+    uart_init("uart1", &uart1, &serial1);
+#endif
+
+#ifdef BSP_USING_UART2
+    uart_init("uart2", &uart2, &serial2);
+#endif
+
+#ifdef BSP_USING_UART3
+    uart_init("uart3", &uart3, &serial3);
+#endif
+
+#ifdef BSP_USING_UART4
+    uart_init("uart4", &uart4, &serial4);
+#endif
+
+#ifdef BSP_USING_UART5
+    uart_init("uart5", &uart5, &serial5);
+#endif
+
+    return 0;
+}

bsp/allwinner/libraries/drivers/drv_uart.h

@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2019-2020, Xim
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+int rt_hw_uart_init(void);
+
+#endif /* __DRV_UART_H__ */

bsp/allwinner/libraries/drivers/drv_wdt.c

@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-15     JasonHu      first version
+ */
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+#include <sunxi_hal_watchdog.h>
+
+#define DBG_SECTION_NAME "wdt"
+#include <rtdbg.h>
+
+#if defined(RT_USING_WDT) && defined(BSP_USING_WDT)
+
+/* hardware only support (1-16)s */
+static rt_uint32_t wdg_timeout = 0;
+
+static rt_err_t wdg_init(rt_watchdog_t *wdt)
+{
+    wdg_timeout = 0;
+    hal_watchdog_init();
+    return RT_EOK;
+}
+
+static rt_err_t wdg_control(rt_watchdog_t *wdt, int cmd, void *arg)
+{
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+        if (arg)
+        {
+            wdg_timeout = *(rt_uint32_t *)arg;
+        }
+        else
+        {
+            LOG_E("arg is NULL!");
+            return RT_EIO;
+        }
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+        if (arg)
+        {
+            *((rt_uint32_t *)arg) = wdg_timeout;
+        }
+        else
+        {
+            LOG_E("arg is NULL!");
+            return RT_EIO;
+        }
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMELEFT:
+        LOG_E("not support RT_DEVICE_CTRL_WDT_GET_TIMELEFT on this platform!");
+        if (arg)
+        {
+            *((rt_uint32_t *)arg) = 0;
+        }
+        else
+        {
+            LOG_E("arg is NULL!");
+        }
+        return RT_EIO;
+    case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+        hal_watchdog_feed();
+        break;
+    case RT_DEVICE_CTRL_WDT_START:
+        hal_watchdog_start(wdg_timeout);
+        break;
+    case RT_DEVICE_CTRL_WDT_STOP:
+        hal_watchdog_stop(wdg_timeout);
+        break;
+    default:
+        return RT_EIO;
+    }
+    return RT_EOK;
+}
+
+static const struct rt_watchdog_ops wdg_pos =
+{
+    wdg_init,
+    wdg_control,
+};
+
+static rt_watchdog_t wdg;
+
+int rt_hw_wdg_init(void)
+{
+    wdg.ops = &wdg_pos;
+    rt_hw_watchdog_register(&wdg, "wdt", 0, RT_NULL);
+    return RT_EOK;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_wdg_init);
+
+void rt_hw_cpu_reset(void)
+{
+    rt_hw_interrupt_disable();
+    hal_watchdog_start(1);
+    while(1);
+}
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
+
+#endif /* RT_USING_WDT && BSP_USING_WDT */

bsp/allwinner/libraries/drivers/lcd_cfg.c

@@ -0,0 +1,1224 @@
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <hal_clk.h>
+#include <hal_gpio.h>
+#include "disp_sys_intf.h"
+#include "disp_board_config.h"
+
+#include <rtthread.h>
+
+#include "lcd_cfg.h"
+
+struct property_t *g_lcd0_config = NULL;
+static struct lcd_cfg_panel_info _panel_info = DEFAULT_LCD_CONFIG;
+
+struct property_t g_lcd0_config_rgb[] = {
+    {
+        .name = "lcd_used",
+        .type = PROPERTY_INTGER,
+        .v.value = 1,
+    },
+    {
+        .name = "lcd_driver_name",
+        .type = PROPERTY_STRING,
+        .v.str = "default_lcd",
+    },
+    {
+        .name = "lcd_if",
+        .type = PROPERTY_INTGER,
+        .v.value = 0, /* LCD_IF_HV */
+    },
+    {
+        .name = "lcd_hv_if",
+        .type = PROPERTY_INTGER,
+        .v.value = 0, /* LCD_HV_IF_PRGB_1CYC */
+    },
+    {
+        .name = "lcd_x",
+        .type = PROPERTY_INTGER,
+        .v.value = 480, //
+    },
+    {
+        .name = "lcd_y",
+        .type = PROPERTY_INTGER,
+        .v.value = 272,
+    },
+    {
+        .name = "lcd_width",
+        .type = PROPERTY_INTGER,
+        .v.value = 80,
+    },
+    {
+        .name = "lcd_height",
+        .type = PROPERTY_INTGER,
+        .v.value = 47,
+    },
+    {
+        .name = "lcd_dclk_freq",
+        .type = PROPERTY_INTGER,
+        .v.value = 10,
+    },
+    /* lcd_ht = lcd_x + lcd_hspw + lcd_hbp + lcd_hfp */
+    {
+        .name = "lcd_ht",
+        .type = PROPERTY_INTGER,
+        .v.value = 592,
+    },
+    {
+        .name = "lcd_hbp",
+        .type = PROPERTY_INTGER,
+        .v.value = 56,
+    },
+    {
+        .name = "lcd_hspw",
+        .type = PROPERTY_INTGER,
+        .v.value = 40,
+    },
+    /* lcd_vt = lcd_y + lcd_vspw + lcd_vbp + lcd_vfp */
+    {
+        .name = "lcd_vt",
+        .type = PROPERTY_INTGER,
+        .v.value = 286,
+    },
+    {
+        .name = "lcd_vspw",
+        .type = PROPERTY_INTGER,
+        .v.value = 5,
+    },
+    {
+        .name = "lcd_vbp",
+        .type = PROPERTY_INTGER,
+        .v.value = 6,
+    },
+    {
+        .name = "lcd_frm",
+        .type = PROPERTY_INTGER,
+        .v.value = 1,
+    },
+    {
+        .name = "lcd_io_phase",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_gamma_en",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_bright_curve_en",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_cmap_en",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "deu_mode",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcdgamma4iep",
+        .type = PROPERTY_INTGER,
+        .v.value = 22,
+    },
+    {
+        .name = "smart_color",
+        .type = PROPERTY_INTGER,
+        .v.value = 90,
+    },
+
+    // backlight enable
+    {
+        .name = "lcd_gpio_1",
+        .type = PROPERTY_GPIO,
+        .v.gpio_list = {
+            .gpio = GPIOG(13),
+            .mul_sel = GPIO_DIRECTION_OUTPUT,
+            .pull = 0,
+            .drv_level = 3,
+            .data = 1,
+        },
+    },
+    {
+        .name = "lcd_backlight",
+        .type = PROPERTY_INTGER,
+        .v.value = 50,
+    },
+    {
+        .name = "lcd_pwm_used",
+        .type = PROPERTY_INTGER,
+        .v.value = 1,
+    },
+    {
+        .name = "lcd_pwm_ch",
+        .type = PROPERTY_INTGER,
+        .v.value = 1,
+    },
+    {
+        .name = "lcd_pwm_freq",
+        .type = PROPERTY_INTGER,
+        .v.value = 1000,
+    },
+    {
+        .name = "lcd_pwm_pol",
+        .type = PROPERTY_INTGER,
+        .v.value = 1,
+    },
+    {
+        .name = "lcd_pwm_max_limit",
+        .type = PROPERTY_INTGER,
+        .v.value = 255,
+    },
+    /* POWER-vcc */
+    {
+        .name = "lcd_gpio_0",
+        .type = PROPERTY_GPIO,
+        .v.gpio_list = {
+            .gpio = GPIOG(15),
+            .mul_sel = GPIO_DIRECTION_OUTPUT,
+            .pull = 0,
+            .drv_level = 3,
+            .data = 1,
+        },
+    },
+    // gpio
+    {
+        .name = "LCD0_D2",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(0),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D3",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(1),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D4",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(2),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D5",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(3),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D6",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(4),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D7",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(5),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D10",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(6),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D11",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(7),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D12",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(8),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D13",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(9),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D14",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(10),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D15",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(11),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D18",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(12),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D19",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(13),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D20",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(14),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D21",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(15),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D22",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(16),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D23",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(17),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_CLK",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(18),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_DE",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(19),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_HSYNC",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(20),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_VSYNC",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(21),
+            .mul_sel = 2,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    }};
+
+struct property_t g_lcd0_config_mipi[] = {
+    {
+        .name = "lcd_used",
+        .type = PROPERTY_INTGER,
+        .v.value = 1,
+    },
+    {
+        .name = "lcd_driver_name",
+        .type = PROPERTY_STRING,
+        .v.str = "tft08006",
+    },
+    {
+        .name = "lcd_backlight",
+        .type = PROPERTY_INTGER,
+        .v.value = 50,
+    },
+    {
+        .name = "lcd_if",
+        .type = PROPERTY_INTGER,
+        .v.value = LCD_IF_DSI,
+    },
+    {
+        .name = "lcd_x",
+        .type = PROPERTY_INTGER,
+        .v.value = 540,
+    },
+    {
+        .name = "lcd_y",
+        .type = PROPERTY_INTGER,
+        .v.value = 960, // 1280
+    },
+    {
+        .name = "lcd_width",
+        .type = PROPERTY_INTGER,
+        .v.value = 52,
+    },
+    {
+        .name = "lcd_height",
+        .type = PROPERTY_INTGER,
+        .v.value = 52,
+    },
+    {
+        .name = "lcd_dclk_freq",
+        .type = PROPERTY_INTGER,
+        .v.value = 43,
+    },
+    {
+        .name = "lcd_pwm_used",
+        .type = PROPERTY_INTGER,
+        .v.value = 1,
+    },
+    {
+        .name = "lcd_pwm_ch",
+        .type = PROPERTY_INTGER,
+        .v.value = 1,
+    },
+    {
+        .name = "lcd_pwm_freq",
+        .type = PROPERTY_INTGER,
+        .v.value = 50000,
+    },
+    {
+        .name = "lcd_pwm_pol",
+        .type = PROPERTY_INTGER,
+        .v.value = 1,
+    },
+    {
+        .name = "lcd_pwm_max_limit",
+        .type = PROPERTY_INTGER,
+        .v.value = 255,
+    },
+    {
+        .name = "lcd_hbp",
+        .type = PROPERTY_INTGER,
+        .v.value = 88,
+    },
+    {
+        .name = "lcd_ht",
+        .type = PROPERTY_INTGER,
+        .v.value = 721,
+    },
+    {
+        .name = "lcd_hspw",
+        .type = PROPERTY_INTGER,
+        .v.value = 56,
+    },
+    {
+        .name = "lcd_vbp",
+        .type = PROPERTY_INTGER,
+        .v.value = 23,
+    },
+    {
+        .name = "lcd_vt",
+        .type = PROPERTY_INTGER,
+        .v.value = 996,
+    },
+    {
+        .name = "lcd_vspw",
+        .type = PROPERTY_INTGER,
+        .v.value = 10,
+    },
+    {
+        .name = "lcd_frm",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_io_phase",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_gamma_en",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_bright_curve_en",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_cmap_en",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "deu_mode",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcdgamma4iep",
+        .type = PROPERTY_INTGER,
+        .v.value = 22,
+    },
+    {
+        .name = "smart_color",
+        .type = PROPERTY_INTGER,
+        .v.value = 90,
+    },
+    {
+        .name = "lcd_dsi_if",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_dsi_lane",
+        .type = PROPERTY_INTGER,
+        .v.value = 2,
+    },
+    {
+        .name = "lcd_dsi_format",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_dsi_te",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_fsync_act_time",
+        .type = PROPERTY_INTGER,
+        .v.value = 1000,
+    },
+    {
+        .name = "lcd_fsync_dis_time",
+        .type = PROPERTY_INTGER,
+        .v.value = 1000,
+    },
+
+    // backlight enable
+    /*
+    {
+        .name = "lcd_gpio_1",
+        .type = PROPERTY_GPIO,
+        .v.gpio_list = {
+            .gpio = GPIOE(11),
+            .mul_sel = GPIO_DIRECTION_OUTPUT,
+            .pull = 0,
+            .drv_level = 3,
+            .data = 1,
+        },
+    },
+    */
+    /* DSI reset */
+    // {
+    //  .name = "lcd_gpio_0",
+    //  .type = PROPERTY_GPIO,
+    //  .v.gpio_list = {
+    //      .gpio = GPIOG(13),
+    //      .mul_sel = GPIO_DIRECTION_OUTPUT,
+    //      .pull = 0,
+    //      .drv_level = 3,
+    //      .data = 1,
+    //  },
+    // },
+    // gpio
+    {
+        .name = "LCD0_D0",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(0),
+            .mul_sel = 4,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D1",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(1),
+            .mul_sel = 4,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D2",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(2),
+            .mul_sel = 4,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D3",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(3),
+            .mul_sel = 4,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D4",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(4),
+            .mul_sel = 4,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D5",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(5),
+            .mul_sel = 4,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D6",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(6),
+            .mul_sel = 4,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D7",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(7),
+            .mul_sel = 4,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D8",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(8),
+            .mul_sel = 4,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D9",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(9),
+            .mul_sel = 4,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+};
+
+struct property_t g_lcd0_config_lvds[] = {
+    {
+        .name = "lcd_used",
+        .type = PROPERTY_INTGER,
+        .v.value = 1,
+    },
+    {
+        .name = "lcd_driver_name",
+        .type = PROPERTY_STRING,
+        .v.str = "default_lcd",
+    },
+    {
+        .name = "lcd_backlight",
+        .type = PROPERTY_INTGER,
+        .v.value = 150,
+    },
+    {
+        .name = "lcd_if",
+        .type = PROPERTY_INTGER,
+        .v.value = LCD_IF_LVDS,
+    },
+    {
+        .name = "lcd_x",
+        .type = PROPERTY_INTGER,
+        .v.value = 1920,
+    },
+    {
+        .name = "lcd_y",
+        .type = PROPERTY_INTGER,
+        .v.value = 1080,
+    },
+    {
+        .name = "lcd_width",
+        .type = PROPERTY_INTGER,
+        .v.value = 150,
+    },
+    {
+        .name = "lcd_height",
+        .type = PROPERTY_INTGER,
+        .v.value = 94,
+    },
+    {
+        .name = "lcd_dclk_freq",
+        .type = PROPERTY_INTGER,
+        .v.value = 71 * 2, // dual lvds, freq=single*2.
+    },
+    {
+        .name = "lcd_rb_swap",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_pwm_used",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_pwm_ch",
+        .type = PROPERTY_INTGER,
+        .v.value = 7,
+    },
+    {
+        .name = "lcd_pwm_freq",
+        .type = PROPERTY_INTGER,
+        .v.value = 50000,
+    },
+    {
+        .name = "lcd_pwm_pol",
+        .type = PROPERTY_INTGER,
+        .v.value = 1,
+    },
+    {
+        .name = "lcd_pwm_max_limit",
+        .type = PROPERTY_INTGER,
+        .v.value = 255,
+    },
+    {
+        .name = "lcd_hbp",
+        .type = PROPERTY_INTGER,
+        .v.value = 90, // P19: Tblk(h) period 74-90-140
+    },
+    {
+        .name = "lcd_ht",
+        .type = PROPERTY_INTGER,
+        .v.value = (960 + 90) * 2, // x+hbp P19: Th period 1034-1050-1100
+    },
+    {
+        .name = "lcd_hspw",
+        .type = PROPERTY_INTGER,
+        .v.value = 10,
+    },
+    {
+        .name = "lcd_vbp",
+        .type = PROPERTY_INTGER,
+        .v.value = 50, // P19: Tblk(v) period 12-50-738
+    },
+    {
+        .name = "lcd_vt",
+        .type = PROPERTY_INTGER,
+        .v.value = (1080 + 50) + 50, // y+vbp P19: Tv period 1092-1130-1818
+    },
+    {
+        .name = "lcd_vspw",
+        .type = PROPERTY_INTGER,
+        .v.value = 5,
+    },
+    {
+        .name = "lcd_lvds_if",
+        .type = PROPERTY_INTGER,
+        .v.value = LCD_LVDS_IF_DUAL_LINK,
+    },
+    {
+        .name = "lcd_lvds_colordepth",
+        .type = PROPERTY_INTGER,
+        .v.value = LCD_LVDS_8bit,
+    },
+    {
+        .name = "lcd_lvds_mode",
+        .type = PROPERTY_INTGER,
+        .v.value = LCD_LVDS_MODE_NS,
+    },
+    {
+        .name = "lcd_frm",
+        .type = PROPERTY_INTGER,
+        .v.value = 1,
+    },
+    {
+        .name = "lcd_io_phase",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_hv_clk_phase",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_hv_sync_polarity",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_gamma_en",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_bright_curve_en",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcd_cmap_en",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "deu_mode",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "lcdgamma4iep",
+        .type = PROPERTY_INTGER,
+        .v.value = 22,
+    },
+    {
+        .name = "smart_color",
+        .type = PROPERTY_INTGER,
+        .v.value = 90,
+    },
+
+    // gpio
+    {
+        .name = "LCD0_D0",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(0),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D1",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(1),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D2",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(2),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D3",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(3),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D4",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(4),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D5",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(5),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D6",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(6),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D7",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(7),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D8",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(8),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D9",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(9),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+#if 1
+    {
+        .name = "LCD0_D14",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(10),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D15",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(11),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D18",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(12),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D19",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(13),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D20",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(14),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D21",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(15),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D22",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(16),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_D23",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(17),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_CLK",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(18),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+    {
+        .name = "LCD0_DE",
+        .type = PROPERTY_PIN,
+        .v.gpio_list = {
+            .gpio = GPIOD(19),
+            .mul_sel = 3,
+            .pull = 0,
+            .drv_level = 3,
+        },
+    },
+#endif
+
+};
+
+struct property_t g_lcd1_config[] = {
+    {
+        .name = "lcd_used",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+};
+
+struct property_t g_disp_config[] = {
+    {
+        .name = "disp_init_enable",
+        .type = PROPERTY_INTGER,
+        .v.value = 1,
+    },
+    {
+        .name = "disp_mode",
+        .type = PROPERTY_INTGER,
+        .v.value = 0, /* DISP_INIT_MODE_SCREEN0 */
+    },
+    {
+        .name = "screen0_output_type",
+        .type = PROPERTY_INTGER,
+        .v.value = 1, /* DISP_OUTPUT_TYPE_LCD */
+    },
+    {
+        .name = "screen0_output_mode",
+        .type = PROPERTY_INTGER,
+        .v.value = 4,
+    },
+    {
+        .name = "screen0_output_format",
+        .type = PROPERTY_INTGER,
+        .v.value = 1,
+    },
+    {
+        .name = "screen0_output_bits",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "screen0_output_eotf",
+        .type = PROPERTY_INTGER,
+        .v.value = 4,
+    },
+    {
+        .name = "screen0_output_cs",
+        .type = PROPERTY_INTGER,
+        .v.value = 257,
+    },
+    {
+        .name = "screen0_output_dvi_hdmi",
+        .type = PROPERTY_INTGER,
+        .v.value = 2,
+    },
+    {
+        .name = "screen0_output_range",
+        .type = PROPERTY_INTGER,
+        .v.value = 2,
+    },
+    {
+        .name = "screen0_output_scan",
+        .type = PROPERTY_INTGER,
+        .v.value = 0,
+    },
+    {
+        .name = "screen0_output_aspect_ratio",
+        .type = PROPERTY_INTGER,
+        .v.value = 8,
+    },
+};
+
+u32 g_lcd0_config_len = sizeof(g_lcd0_config_rgb) / sizeof(struct property_t);
+u32 g_lcd1_config_len = sizeof(g_lcd1_config) / sizeof(struct property_t);
+u32 g_disp_config_len = sizeof(g_disp_config) / sizeof(struct property_t);
+
+static struct property_t *_lcd_property_find(const char *name, struct property_t *_config, const u32 config_len)
+{
+    u32 i;
+
+    for (i = 0; i < config_len; i++)
+    {
+        if (_config[i].type != PROPERTY_INTGER)
+        {
+            continue;
+        }
+
+        if (!strcmp(name, _config[i].name))
+        {
+            return _config + i;
+        }
+    }
+
+    return NULL;
+}
+
+#ifndef LCD_XML_CONFIG_FILE
+#define LCD_CONFIG_FILE "/etc/lcd_config.xml"
+#else
+#define LCD_CONFIG_FILE LCD_XML_CONFIG_FILE
+#endif
+const struct lcd_cfg_panel_info *load_lcd_config_from_xml(void)
+{
+    struct property_t *_config_item;
+    static rt_uint8_t init_state = 0;
+
+    rt_enter_critical();
+    if (init_state == 0)
+    {
+        init_state = 1;
+        rt_exit_critical();
+    }
+    else
+    {
+        rt_exit_critical();
+
+        while (init_state != 2)
+        {
+            rt_thread_mdelay(10);
+        }
+        goto _RET;
+    }
+
+    g_lcd0_config = g_lcd0_config_rgb;
+    g_lcd0_config_len = sizeof(g_lcd0_config_rgb) / sizeof(struct property_t);
+_RET:
+
+    init_state = 2;
+    _config_item = _lcd_property_find("lcd_x", g_lcd0_config, g_lcd0_config_len);
+    _panel_info.width = _config_item->v.value;
+    _config_item = _lcd_property_find("lcd_y", g_lcd0_config, g_lcd0_config_len);
+    _panel_info.height = _config_item->v.value;
+
+    return &_panel_info;
+}

bsp/allwinner/libraries/drivers/lcd_cfg.h

@@ -0,0 +1,89 @@
+#ifndef _LCD_CFG_H_
+#define _LCD_CFG_H_
+
+#include <stdint.h>
+
+#define COORD_Y_REVERSE    (1<<0)
+#define COORD_X_REVERSE    (1<<1)
+#define COORD_XY_EXCHANGE  (1<<2)
+
+
+#define DEFAULT_LCD_CONFIG {\
+    type: "rgb",\
+    width:480,\
+    height:272,\
+    bits_pixel:18,\
+    timing:\
+    {\
+        pixel_clock_hz:10000000,\
+        h_front_porch:8,\
+        h_back_porch:43,\
+        h_sync_len:4,\
+        v_front_porch:8,\
+        v_back_porch:12,\
+        v_sync_len:4,\
+        h_sync_active:0,\
+        v_sync_active:0,\
+        den_active:1,\
+        clk_active:1\
+    },\
+    swap_flag:0,\
+    ctp_flag:0,\
+    bl_mode:1,\
+    bl_gpio_pin:GPIOB(6),\
+    bl_gpio_level:1,\
+    bl_pwm_name: "pwm",\
+    bl_pwm_hz:1000,\
+    bl_pwm_pol:0,\
+    bl_pwm_val:60,\
+    bl_pin:GPIOG(13),\
+    bl_level:1,\
+    pwr_pin:GPIOG(15),\
+    pwr_level:1,\
+    lane:4\
+}
+
+struct panel_timing
+{
+    int pixel_clock_hz;
+    int h_front_porch;
+    int h_back_porch;
+    int h_sync_len;
+    int v_front_porch;
+    int v_back_porch;
+    int v_sync_len;
+    int h_sync_active;
+    int v_sync_active;
+    int den_active;
+    int clk_active;
+};
+typedef struct panel_timing *panel_timing_t;
+
+struct lcd_cfg_panel_info
+{
+    rt_int8_t type[8];
+    int width;
+    int height;
+    int bits_pixel;
+    struct panel_timing timing;
+    int swap_flag;
+    int ctp_flag;
+
+    int bl_mode;
+    int bl_gpio_pin;
+    int bl_gpio_level;
+    rt_int8_t bl_pwm_name[8];
+    int bl_pwm_hz;
+    int bl_pwm_pol;
+    int bl_pwm_val;
+    int bl_pin;
+    int bl_level;
+    int pwr_pin;
+    int pwr_level;
+    int lane;
+
+};
+
+const struct lcd_cfg_panel_info* load_lcd_config_from_xml(void);
+
+#endif

bsp/allwinner/libraries/drivers/sdmmc/SConscript

@@ -0,0 +1,20 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+SrcRemove(src, ['sdmmc_part.c'])
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = ['BSP_USING_SDMMC'], CPPPATH = CPPPATH)
+
+objs = [group]
+
+list = os.listdir(cwd)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

bsp/allwinner/libraries/drivers/sdmmc/drv_sdmmc.c

@@ -0,0 +1,522 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-10-29     JasonHu      first version
+ */
+
+#include <stddef.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <rtthread.h>
+
+#ifdef BSP_USING_SDMMC
+
+#include <typedef.h>
+#include <kapi.h>
+#include <init.h>
+#include <blkpart.h>
+#include <sdmmc/hal_sdhost.h>
+#include <sdmmc/card.h>
+#include <sdmmc/sys/sys_debug.h>
+#include <sdmmc/sdmmc.h>
+#include <sdmmc/sd_test.h>
+#include <drv_sdmmc.h>
+
+#include <dfs_file.h>
+#include <unistd.h>
+#include <stdio.h> /* rename() */
+#include <sys/stat.h>
+#include <sys/statfs.h> /* statfs() */
+#include "partition.h"
+
+#define DBG_LEVEL DBG_LOG
+#define DBG_SECTION_NAME "drv-sdmmc"
+#include <rtdbg.h>
+
+#ifdef CONFIG_SUPPORT_SDMMC_CACHE
+#include "sdmmc_cache.h"
+#endif
+
+// #define DETECT_BY_GPIO
+
+#ifndef CONFIG_SDC_DMA_BUF_SIZE
+#define SDC_ALIGN_DMA_BUF_SIZE (64 * 1024)
+#else
+#define SDC_ALIGN_DMA_BUF_SIZE (CONFIG_SDC_DMA_BUF_SIZE * 1024)
+#endif
+
+#define SDXC_MAX_TRANS_LEN SDC_ALIGN_DMA_BUF_SIZE
+
+#ifndef ALIGN_DOWN
+#define ALIGN_DOWN(size, align) ((size) & ~((align)-1))
+#endif
+
+#ifndef MIN
+#define MIN(a, b) (a > b ? b : a)
+#endif
+
+static int _register_blk_part_device(rt_device_t dev, const char *dev_name)
+{
+    uint8_t *mbr_buf = NULL;
+    int ret = 0;
+    int i = 0;
+    struct rt_partition *part_table;
+    int part_count = 0;
+    int alloc_part_count = 2;
+
+    /* NOTICE: get block geometry fisrt time here, then you can read/write sdmmc. */
+    struct dev_sdmmc *dev_sdmmc = (struct dev_sdmmc *)dev->user_data;
+    if (dev->control(dev, RT_DEVICE_CTRL_BLK_GETGEOME, &dev_sdmmc->geometry) != RT_EOK)
+    {
+        LOG_E("device get geometry failed!");
+        return -RT_EIO;
+    }
+
+    rt_kprintf("sdmmc bytes_per_secotr:%x, sector count:%x\n", dev_sdmmc->geometry.bytes_per_sector, dev_sdmmc->geometry.sector_count);
+
+    /*read the mbr*/
+    mbr_buf = rt_malloc(dev_sdmmc->geometry.bytes_per_sector);
+    if (!mbr_buf)
+    {
+        return -RT_ENOMEM;
+    }
+    rt_memset(mbr_buf, 0, dev_sdmmc->geometry.bytes_per_sector);
+
+    part_table = rt_malloc(sizeof(struct rt_partition) * alloc_part_count);
+    if (!part_table)
+    {
+        return -RT_ENOMEM;
+    }
+
+    if (dev->read(dev, 0, mbr_buf, 1) != 1)
+    {
+        LOG_E("device read mbr 1-sector failure\n");
+        ret = -RT_ERROR;
+        goto err;
+    }
+
+    for (i = 0;; i++)
+    {
+        rt_err_t status;
+        struct dfs_partition part;
+
+        status = dfs_filesystem_get_partition(&part, mbr_buf, i);
+        if (status != RT_EOK)
+        {
+            if (i == 0)
+            {
+                snprintf(part_table[0].name, 6, "sd%dp%d", dev_sdmmc->host_id, i);
+                part_table[0].offset = 8 * 1024 * 1024;
+                part_table[0].size = dev_sdmmc->geometry.bytes_per_sector * dev_sdmmc->geometry.sector_count - part_table[0].offset;
+                part_table[0].flags = PARTITION_WRITEABLE;
+                part_count = 1;
+
+                rt_kprintf("not found partition of mbr, construct sd0 at offset 8M, size:%p\n", part_table[0].size);
+            }
+            break;
+        }
+        else
+        {
+            if (part_count >= alloc_part_count)
+            {
+                rt_kprintf("part_count1:%d\n", part_count);
+
+                struct rt_partition *new_part_table;
+
+                alloc_part_count *= 2;
+
+                new_part_table = rt_realloc(part_table, alloc_part_count * sizeof(struct rt_partition));
+                if (new_part_table != RT_NULL)
+                {
+                    part_table = new_part_table;
+                }
+                else
+                {
+                    break;
+                }
+            }
+            rt_kprintf("found partition:sd%d of mbr at offset %p, size:%p\n", i, part.offset, part.size);
+            snprintf(part_table[part_count].name, 6, "sd%dp%d", dev_sdmmc->host_id, i);
+            part_table[part_count].offset = part.offset * dev_sdmmc->geometry.bytes_per_sector;
+            // rt_kprintf("bytes_per_sector:%d\n", dev_sdmmc->geometry.bytes_per_sector);
+            // rt_kprintf("part_table_offset:%d\n", part.offset * dev_sdmmc->geometry.bytes_per_sector);
+            part_table[part_count].size = part.size * dev_sdmmc->geometry.bytes_per_sector;
+            part_table[part_count].flags = PARTITION_WRITEABLE;
+            part_count++;
+        }
+    }
+
+err:
+    if (part_count > 0)
+    {
+        ret = rt_partition_init(dev_name, part_table, part_count);
+    }
+    if (mbr_buf != NULL)
+    {
+        rt_free(mbr_buf);
+    }
+
+    if (ret != 0)
+    {
+        if (part_table != NULL)
+        {
+            rt_free(part_table);
+        }
+    }
+
+    return ret;
+}
+
+rt_err_t sdmmc_init(rt_device_t dev)
+{
+    int ret = -1;
+
+    struct dev_sdmmc *dev_priv = (struct dev_sdmmc *)dev->user_data;
+    int host_id = dev_priv->host_id;
+
+    dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+    int32_t internal_card = 0x00;
+
+    SDC_InitTypeDef sdc_param = {0};
+    sdc_param.debug_mask = (ROM_INF_MASK |
+                            ROM_WRN_MASK | ROM_ERR_MASK | ROM_ANY_MASK);
+
+    esCFG_GetKeyValue("sdcard_global", "internal_card", (int32_t *)&internal_card, 1);
+
+    if (((internal_card >> host_id) & 0x01) == 1)
+    {
+        sdc_param.cd_mode = CARD_ALWAYS_PRESENT;
+        LOG_D("cd_mode CARD_ALWAYS_PRESENT!");
+    }
+    else
+    {
+#ifndef DETECT_BY_GPIO
+        sdc_param.cd_mode = CARD_ALWAYS_PRESENT;
+#else
+        sdc_param.cd_mode = CARD_DETECT_BY_GPIO_IRQ;
+#endif
+    }
+    sdc_param.cd_cb = &card_detect;
+    sdc_param.dma_use = 1;
+
+    if (mmc_test_init(host_id, &sdc_param, 1))
+    {
+        dev->flag &= ~RT_DEVICE_FLAG_ACTIVATED;
+        LOG_E("init sdmmc failed!");
+        return ret;
+    }
+    LOG_D("host_id =%d!", host_id);
+
+    /* wait timeout to sync with sdmmc init done */
+    int mdelay = 500;
+    while (!hal_sdc_init_timeout() && mdelay > 0)
+    {
+        rt_thread_mdelay(50);
+        mdelay -= 50;
+    }
+    return 0;
+}
+
+rt_err_t sdmmc_deinit(rt_device_t dev)
+{
+    struct dev_sdmmc *dev_priv = (struct dev_sdmmc *)dev->user_data;
+    int host_id = dev_priv->host_id;
+    mmc_test_exit(host_id, host_id);
+    return 0;
+}
+
+static rt_size_t sdmmc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+    ssize_t ret, rsz, trsz, msz = 0;
+    struct rt_device_blk_geometry *geometry;
+    uint8_t *data = buffer;
+    struct dev_sdmmc *dev_priv = (struct dev_sdmmc *)dev->user_data;
+    struct mmc_card *card = mmc_card_open(dev_priv->host_id);
+
+    if (card == NULL)
+    {
+        LOG_E("mmc open fail");
+        return 0;
+    }
+
+    if (size == 0)
+    {
+        return 0;
+    }
+
+    // rt_kprintf("sd read, pos:%llu, blkcnt:%llu\n", pos, size);
+
+    geometry = &dev_priv->geometry;
+
+    if (pos >= geometry->sector_count)
+    {
+        LOG_E("read offset %lu over part sector %llu", pos, geometry->sector_count);
+        return 0;
+    }
+
+    if (pos + size > geometry->sector_count)
+    {
+        LOG_E("over limit: offset %lu + size %lu over %llu",
+              pos, size, geometry->sector_count);
+        return 0;
+    }
+
+    trsz = 0;
+    msz = SDXC_MAX_TRANS_LEN / geometry->bytes_per_sector;
+    while (size > 0)
+    {
+        if (size < msz)
+        {
+            rsz = size;
+        }
+        else
+        {
+            rsz = msz;
+        }
+
+        ret = mmc_block_read(card, data, pos, rsz);
+        if (ret)
+        {
+            LOG_E("read failed - %d", (int)ret);
+            break;
+        }
+
+        trsz += rsz;
+        size -= rsz;
+        data += rsz * geometry->bytes_per_sector;
+        pos += rsz;
+    }
+
+    mmc_card_close(dev_priv->host_id);
+
+    return trsz;
+}
+
+static rt_err_t sdmmc_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return 0;
+}
+
+static rt_err_t sdmmc_close(rt_device_t dev)
+{
+    return 0;
+}
+
+static rt_size_t sdmmc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    int err = -1;
+    ssize_t ret, wsz, twsz, msz = 0;
+    struct rt_device_blk_geometry *geometry;
+    uint8_t *data = (uint8_t *)buffer;
+
+    struct dev_sdmmc *dev_priv = (struct dev_sdmmc *)dev->user_data;
+    struct mmc_card *card = mmc_card_open(dev_priv->host_id);
+    if (card == NULL)
+    {
+        LOG_E("mmc open fail");
+        return -EIO;
+    }
+
+    if (size == 0)
+    {
+        return 0;
+    }
+
+    geometry = &dev_priv->geometry;
+
+    if (pos >= geometry->sector_count)
+    {
+        LOG_E("read offset %lu over part size %llu", pos, geometry->sector_count);
+        return 0;
+    }
+
+    if (pos + size > geometry->sector_count)
+    {
+        LOG_E("over limit: offset %lu + size %lu over %llu",
+              pos, size, geometry->sector_count);
+        return 0;
+    }
+
+    twsz = 0;
+    msz = SDXC_MAX_TRANS_LEN / geometry->bytes_per_sector;
+    while (size > 0)
+    {
+        if (size < msz)
+        {
+            wsz = size;
+        }
+        else
+        {
+            wsz = msz;
+        }
+
+        ret = mmc_block_write(card, data, pos, wsz);
+        if (ret)
+        {
+            LOG_E("read failed - %d", (int)ret);
+            break;
+        }
+
+        twsz += wsz;
+        size -= wsz;
+        data += wsz * geometry->bytes_per_sector;
+        pos += wsz;
+    }
+
+    mmc_card_close(dev_priv->host_id);
+
+    return twsz;
+}
+
+static rt_err_t sdmmc_control(rt_device_t dev, int cmd, void *args)
+{
+    int ret = -RT_ERROR;
+    struct rt_device_blk_geometry *geometry;
+    int flag = 0;
+    if (!dev)
+    {
+        return -EINVAL;
+    }
+
+    struct dev_sdmmc *dev_priv = (struct dev_sdmmc *)dev->user_data;
+    struct mmc_card *card = mmc_card_open(dev_priv->host_id);
+    if (!card)
+    {
+        return ret;
+    }
+
+    switch (cmd)
+    {
+    case BLOCK_DEVICE_CMD_ERASE_ALL:
+        break;
+    case BLOCK_DEVICE_CMD_ERASE_SECTOR:
+        break;
+    case BLOCK_DEVICE_CMD_GET_TOTAL_SIZE:
+        *(uint64_t *)args = card->csd.capacity * 1024ull;
+        ret = 0;
+        break;
+    case BLOCK_DEVICE_CMD_GET_PAGE_SIZE:
+        *(uint32_t *)args = 512;
+        ret = 0;
+        break;
+    case BLOCK_DEVICE_CMD_GET_BLOCK_SIZE:
+        *(uint32_t *)args = 512;
+        ret = 0;
+        break;
+    case RT_DEVICE_CTRL_BLK_GETGEOME:
+        geometry = (struct rt_device_blk_geometry *)args;
+        rt_memset(geometry, 0, sizeof(struct rt_device_blk_geometry));
+        geometry->block_size = 512;
+        geometry->bytes_per_sector = 512;
+        geometry->sector_count = (card->csd.capacity * 1024ull) / geometry->bytes_per_sector;
+        LOG_D("[sdmmc] getgeome: bytes_per_sector:%ld, block_size:%ld, sector_count:%ld",
+              geometry->bytes_per_sector, geometry->block_size, geometry->sector_count);
+        ret = RT_EOK;
+        break;
+
+    default:
+        break;
+    }
+
+    mmc_card_close(dev_priv->host_id);
+    return ret;
+}
+
+static int init_sdmmc_device(rt_device_t device, void *usr_data, char *dev_name)
+{
+    int ret = -1;
+
+    device = rt_device_create(RT_Device_Class_Block, 0);
+    if (!device)
+    {
+        return ret;
+    }
+    device->init = sdmmc_init;
+    device->open = sdmmc_open;
+    device->close = sdmmc_close;
+    device->read = sdmmc_read;
+    device->write = sdmmc_write;
+    device->control = sdmmc_control;
+    device->user_data = usr_data;
+
+    ret = rt_device_register(device, dev_name, RT_DEVICE_FLAG_RDWR);
+    if (ret != RT_EOK)
+    {
+        rt_device_destroy(device);
+        return ret;
+    }
+
+    // int sdmmc_blkpart_init(const char *name);
+    // ret = sdmmc_blkpart_init(dev_name);
+    if (sdmmc_init(device))
+    {
+        LOG_E("sdmmc_init failed!");
+        return -1;
+    }
+
+    /* NOTICE: get block geometry fisrt time here, then you can read/write sdmmc. */
+    struct dev_sdmmc *dev_sdmmc = (struct dev_sdmmc *)device->user_data;
+    if (device->control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &dev_sdmmc->geometry) != RT_EOK)
+    {
+        LOG_E("device get geometry failed!");
+        ret = -ENOSYS;
+    }
+
+    _register_blk_part_device(device, dev_name);
+
+    return ret;
+}
+
+static struct dev_sdmmc dev_sdmmc[SDMMC_CARD_NR];
+
+int driver_sdmmc_init(void)
+{
+    int ret = -1;
+    int i = 0;
+    rt_device_t device[SDMMC_CARD_NR];
+    int32_t used_card_no = 0x01;
+    char name[12];
+
+    ret = esCFG_GetKeyValue("sdcard_global", "used_card_no", (int32_t *)&used_card_no, 1);
+    if (ret)
+    {
+        used_card_no = 0x00;
+        LOG_E("get card no failed, card no: %d", used_card_no);
+        return ret;
+    }
+
+    for (i = 0; i < SDMMC_CARD_NR; ++i)
+    {
+        rt_sprintf(name, "sdmmc%d", i);
+        dev_sdmmc[i].host_id = i;
+        ret = init_sdmmc_device(device[i], (void *)&dev_sdmmc[i], name);
+    }
+    return ret;
+}
+
+void sd_mmc1_init(void)
+{
+    rt_device_t device = NULL;
+    device = rt_device_find("sdmmc1");
+    sdmmc_init(device);
+
+    _register_blk_part_device(device, "sdmmc1");
+}
+
+void sd_mmc1_deinit(void)
+{
+    rt_device_t device = NULL;
+    device = rt_device_find("sdmmc1");
+    sdmmc_deinit(device);
+}
+
+INIT_DEVICE_EXPORT(driver_sdmmc_init);
+
+#endif

bsp/allwinner/libraries/drivers/sdmmc/drv_sdmmc.h

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-11     JasonHu      first version
+ */
+
+#ifndef DRV_SDMMC_H__
+#define DRV_SDMMC_H__
+
+#include <rtdef.h>
+
+#define SDMMC_CARD_NR 2
+
+#define SDMMC_DEV_NAME_DEF "sdmmc0"
+
+struct dev_sdmmc
+{
+    int host_id;                            /* host id for each card device */
+    struct rt_device_blk_geometry geometry; /* block geometry */
+};
+
+void sd_mmc1_init(void);
+void sd_mmc1_deinit(void);
+
+#endif

bsp/allwinner/libraries/drivers/touch/SConscript

@@ -0,0 +1,16 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+LIBS = []
+LIBPATH = [cwd]
+list = os.listdir(GetCurrentDir())
+print(list)
+if 'libtouch_gcc.a' in list:
+    LIBS = ['libtouch_gcc.a']
+    src = []
+
+group = DefineGroup('touch', src, depend = ['BSP_USING_TOUCH'],LIBS = LIBS, LIBPATH = LIBPATH, CPPPATH = CPPPATH)
+
+Return('group')

bsp/allwinner/libraries/drivers/touch/drv_touch.c

@@ -0,0 +1,316 @@
+/*
+ * COPYRIGHT (C) 2012-2022, Shanghai Real-Thread Technology Co., Ltd
+ * All rights reserved.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-02-08     RT-Thread  the first version
+ */
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "drv_touch.h"
+#include "drv_pin.h"
+// #include "lcd_cfg.h"
+
+#ifndef TOUCH_I2C_NAME
+#define TOUCH_I2C_NAME "i2c2"
+#endif
+#define DBG_TAG "TOUCH"
+#define DBG_LVL DBG_LOG
+#include <rtdbg.h>
+
+#define COORD_Y_REVERSE (1 << 0)
+#define COORD_X_REVERSE (1 << 1)
+#define COORD_XY_EXCHANGE (1 << 2)
+
+#ifdef BSP_USING_MANGOPI                             // mango board
+#define TP_INT_PIN GET_PIN(GPIO_PORT_D, GPIO_PIN_22) /* GPIO_PORT_D GPIO_PIN_22 */
+#elif defined(BSP_USING_M7)
+#define TP_INT_PIN GET_PIN(GPIO_PORT_G, GPIO_PIN_14) /* GPIO_PORT_G GPIO_PIN_14 */
+#endif
+
+static rt_slist_t _driver_list;
+static struct rt_i2c_bus_device *i2c_bus = RT_NULL;
+static struct touch_driver *current_driver = RT_NULL;
+static struct rt_touch_device touch_device;
+static rt_timer_t touch_timer = RT_NULL;
+static int tp_convert_flag;
+// static const struct lcd_cfg_panel_info *_panel_info;
+
+void touch_coord_convert(int *x, int *y, int range_x, int range_y, int flag)
+{
+    int xbuf, ybuf;
+
+    if (flag & COORD_XY_EXCHANGE)
+    {
+        xbuf = range_x;
+        range_x = range_y;
+        range_y = xbuf;
+        xbuf = *y;
+        ybuf = *x;
+
+        if (flag & COORD_X_REVERSE)
+        {
+            ybuf = range_y - ybuf;
+        }
+
+        if (flag & COORD_Y_REVERSE)
+        {
+            xbuf = range_x - xbuf;
+        }
+    }
+    else
+    {
+        xbuf = *x;
+        ybuf = *y;
+
+        if (flag & COORD_X_REVERSE)
+        {
+            xbuf = range_x - xbuf;
+        }
+
+        if (flag & COORD_Y_REVERSE)
+        {
+            ybuf = range_y - ybuf;
+        }
+    }
+
+    *x = xbuf;
+    *y = ybuf;
+}
+
+rt_err_t rt_touch_drivers_register(touch_driver_t drv)
+{
+    RT_ASSERT(drv != RT_NULL);
+    RT_ASSERT(drv->ops != RT_NULL);
+    RT_ASSERT(drv->probe != RT_NULL);
+
+    rt_slist_append(&_driver_list, &drv->list);
+
+    return RT_EOK;
+}
+
+int rt_touch_list_init(void)
+{
+    rt_slist_init(&_driver_list);
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_touch_list_init);
+
+static void touch_timeout_handle(void *parameter)
+{
+    rt_touch_t touch = (rt_touch_t)parameter;
+    rt_device_t device = &touch->parent;
+
+    device->control(device, RT_TOUCH_CTRL_ENABLE_INT, RT_NULL); // enable tp irq
+
+    // rt_kprintf("[%s:%d]touch_timeout_handle\n", __FUNCTION__, __LINE__);
+}
+
+static rt_err_t tp_irq_handle(rt_touch_t touch)
+{
+    rt_device_t device;
+    device = &touch->parent;
+
+    device->control(device, RT_TOUCH_CTRL_DISABLE_INT, RT_NULL); // disable tp irq
+
+    return RT_EOK;
+}
+
+int rt_touch_read(rt_uint16_t addr, void *cmd_buf, size_t cmd_len, void *data_buf, size_t data_len)
+{
+    struct rt_i2c_msg msgs[2];
+
+    msgs[0].addr = addr;
+    msgs[0].flags = RT_I2C_WR;
+    msgs[0].buf = cmd_buf;
+    msgs[0].len = cmd_len;
+
+    msgs[1].addr = addr;
+    msgs[1].flags = RT_I2C_RD;
+    msgs[1].buf = data_buf;
+    msgs[1].len = data_len;
+
+    if (rt_i2c_transfer(i2c_bus, msgs, 2) == 2)
+        return 0;
+    else
+        return -1;
+}
+
+int rt_touch_write(rt_uint16_t addr, void *data_buf, size_t data_len)
+{
+    struct rt_i2c_msg msgs[1];
+
+    msgs[0].addr = addr;
+    msgs[0].flags = RT_I2C_WR;
+    msgs[0].buf = data_buf;
+    msgs[0].len = data_len;
+
+    if (rt_i2c_transfer(i2c_bus, msgs, 1) == 1)
+        return 0;
+    else
+        return -1;
+}
+
+static rt_size_t touch_readpoint(struct rt_touch_device *touch, void *buf, rt_size_t touch_num)
+{
+    rt_device_t device;
+    struct rt_touch_data *data = (struct rt_touch_data *)buf;
+    int x, y;
+    device = &touch->parent;
+
+    current_driver->ops->read_point(data, touch_num);
+
+    /* touch up事件是上次转换后的，所以不需要执行转换 */
+    if ((RT_TOUCH_EVENT_NONE != data->event) && (RT_TOUCH_EVENT_UP != data->event))
+    {
+        x = data->x_coordinate;
+        y = data->y_coordinate;
+        // touch_coord_convert(&x, &y, _panel_info->width, _panel_info->height, tp_convert_flag);
+        data->x_coordinate = x;
+        data->y_coordinate = y;
+    }
+
+    if ((touch_timer != RT_NULL) && (current_driver->read_interval != 0))
+    {
+        rt_timer_start(touch_timer);
+    }
+    else if ((TOUCH_INT_MODE == current_driver->check_mode) && (0 != current_driver->read_interval))
+    {
+        device->control(device, RT_TOUCH_CTRL_ENABLE_INT, RT_NULL); // enable tp irq
+    }
+    else
+    {
+    }
+
+    return 1;
+}
+
+static rt_err_t touch_control(struct rt_touch_device *touch, int cmd, void *arg)
+{
+    return RT_EOK;
+}
+
+static struct rt_touch_ops touch_ops =
+    {
+        .touch_readpoint = touch_readpoint,
+        .touch_control = touch_control,
+};
+
+static void touch_poll_entry(void *parameter)
+{
+    rt_tick_t read_interval = current_driver->read_interval;
+
+    if (0 == read_interval)
+    {
+        read_interval = rt_tick_from_millisecond(20);
+    }
+
+    while (1)
+    {
+        rt_thread_delay(read_interval);
+        if (RT_NULL != touch_device.parent.rx_indicate)
+        {
+            /* Notify the application layer to get data */
+            touch_device.parent.rx_indicate(&touch_device.parent, 1);
+        }
+    }
+}
+
+int rt_touch_init(void)
+{
+    rt_slist_t *driver_list = RT_NULL;
+    rt_uint16_t irq_pin = TP_INT_PIN;
+    int range_x, range_y;
+
+    i2c_bus = rt_i2c_bus_device_find(TOUCH_I2C_NAME);
+    RT_ASSERT(i2c_bus);
+
+    if (rt_device_open(&i2c_bus->parent, RT_DEVICE_OFLAG_RDWR) != RT_EOK)
+    {
+        rt_kprintf("[TP] open i2c dvice failed.\n");
+        return -RT_EIO;
+    }
+
+    rt_slist_for_each(driver_list, &_driver_list)
+    {
+        current_driver = (struct touch_driver *)driver_list;
+        if (current_driver->probe(i2c_bus) == RT_TRUE)
+        {
+            break;
+        }
+        current_driver = RT_NULL;
+    }
+
+    if (current_driver == RT_NULL)
+    {
+        rt_kprintf("[TP] No touch pad or driver.\n");
+        rt_device_close((rt_device_t)i2c_bus);
+        return -RT_EIO;
+    }
+
+    if ((TOUCH_INT_MODE == current_driver->check_mode) && (0 != current_driver->read_interval))
+    {
+        touch_timer = rt_timer_create("touch", touch_timeout_handle,
+                                      &touch_device, current_driver->read_interval,
+                                      RT_TIMER_FLAG_ONE_SHOT);
+        if (touch_timer == RT_NULL)
+        {
+            rt_kprintf("[TP] touch timer create failed.\n");
+            rt_device_close((rt_device_t)i2c_bus);
+            return -RT_EIO;
+        }
+    }
+    else if (TOUCH_POLL_MODE == current_driver->check_mode)
+    {
+        rt_thread_t thread;
+        irq_pin = RT_PIN_NONE; // No interrupt pins are used
+        thread = rt_thread_create("touch", touch_poll_entry, RT_NULL, 2048, 16, 20);
+        if (thread == RT_NULL)
+        {
+            rt_kprintf("[TP] touch poll thread create failed.\n");
+            rt_device_close((rt_device_t)i2c_bus);
+            return -RT_ERROR;
+        }
+        rt_thread_startup(thread);
+    }
+
+    /* loading the touchscreen configuration */
+    // _panel_info = load_lcd_config_from_xml();
+    // range_x = _panel_info->width;
+    // range_y = _panel_info->height;
+    // tp_convert_flag = 0;
+    // /* touch screen xy swap */
+    // if (_panel_info->ctp_flag & COORD_XY_EXCHANGE)
+    // {
+    //     tp_convert_flag |= COORD_XY_EXCHANGE;
+    //     touch_coord_convert(&range_x, &range_y, _panel_info->width, _panel_info->height, COORD_XY_EXCHANGE);
+    // }
+
+    // if (_panel_info->ctp_flag & COORD_Y_REVERSE)
+    // {
+    //     tp_convert_flag |= COORD_Y_REVERSE;
+    // }
+
+    // if (_panel_info->ctp_flag & COORD_X_REVERSE)
+    // {
+    //     tp_convert_flag |= COORD_X_REVERSE;
+    // }
+
+    current_driver->ops->init(i2c_bus);
+
+    /* touch infomation */
+    touch_device.info.type = RT_TOUCH_TYPE_CAPACITANCE;
+    touch_device.info.vendor = RT_TOUCH_VENDOR_UNKNOWN;
+    touch_device.info.point_num = 1;
+    touch_device.info.range_x = 480;
+    touch_device.info.range_y = 272;
+    touch_device.config.user_data = RT_NULL;
+    touch_device.ops = &touch_ops;
+    touch_device.irq_handle = tp_irq_handle;
+    touch_device.config.irq_pin.pin = irq_pin;
+    touch_device.config.irq_pin.mode = PIN_MODE_INPUT_PULLUP;
+
+    return rt_hw_touch_register(&touch_device, "touch", RT_DEVICE_FLAG_INT_RX, RT_NULL);
+}
+INIT_ENV_EXPORT(rt_touch_init);