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@@ -51,8 +51,8 @@
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/* Watch Dog registers */
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#define WDT_EN HWREG32(WDT_BASE + 0x00)
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-#define WDT_SET HWREG32(WDT_BASE + 0x04)
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-#define WDT_TIMER HWREG32(WDT_BASE + 0x08)
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+#define WDT_SET HWREG32(WDT_BASE + 0x08)
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+#define WDT_TIMER HWREG32(WDT_BASE + 0x04)
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#define PLL_FREQ HWREG32(0xbfe78030)
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#define PLL_DIV_PARAM HWREG32(0xbfe78034)
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