更新rk3568 bsp 支持PSCI、amp模式

bsp/rockchip/rk3568/Kconfig

@@ -25,6 +25,7 @@ config SOC_RK3568
     select RT_USING_CACHE
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
+    select ARCH_ARM_BOOTWITH_FLUSH_CACHE
     default y
 
 source "$BSP_DIR/driver/Kconfig"

bsp/rockchip/rk3568/driver/Kconfig

@@ -51,8 +51,9 @@ menu "Hardware Drivers Config"
         bool
         default y
 
-        config BSP_USING_GICV3
-            bool
-            default y
+    config BSP_USING_GICV3
+        bool
+        default y
 
+    select ARCH_ARM_CORTEX_A55
 endmenu

bsp/rockchip/rk3568/driver/board.c

@@ -17,17 +17,29 @@
 #include <gtimer.h>
 #include <cpuport.h>
 #include <interrupt.h>
+#include <ioremap.h>
+#include <psci_api.h>
 
 #include <board.h>
 #include <drv_uart.h>
 
+#include "mm_page.h"
+
+#define PLATFORM_MEM_TALBE(va, size) va, ((unsigned long)va + size - 1)
+
 struct mem_desc platform_mem_desc[] =
 {
-    {0x200000, 0x80000000, 0x200000, NORMAL_MEM},
-    {UART0_MMIO_BASE, UART0_MMIO_BASE + 0x10000, UART0_MMIO_BASE, DEVICE_MEM},
-    {UART1_MMIO_BASE, UART1_MMIO_BASE + 0x90000, UART1_MMIO_BASE, DEVICE_MEM},
-    {GIC_PL600_DISTRIBUTOR_PPTR, GIC_PL600_DISTRIBUTOR_PPTR + 0x10000, GIC_PL600_DISTRIBUTOR_PPTR, DEVICE_MEM},
-    {GIC_PL600_REDISTRIBUTOR_PPTR, GIC_PL600_REDISTRIBUTOR_PPTR + 0xc0000, GIC_PL600_REDISTRIBUTOR_PPTR, DEVICE_MEM},
+    {PLATFORM_MEM_TALBE(0x20000000,                    0x10000000), 0x20000000,                   NORMAL_MEM},
+    {PLATFORM_MEM_TALBE(GRF_PMU_BASE,                  0x10000),    GRF_PMU_BASE,                 DEVICE_MEM},
+    {PLATFORM_MEM_TALBE(GRF_SYS_BASE,                  0x10000),    GRF_SYS_BASE,                 DEVICE_MEM},
+    {PLATFORM_MEM_TALBE(CRU_BASE,                      0x10000),    CRU_BASE,                     DEVICE_MEM},
+    {PLATFORM_MEM_TALBE(UART0_MMIO_BASE,               0x10000),    UART0_MMIO_BASE,              DEVICE_MEM},
+    {PLATFORM_MEM_TALBE(UART1_MMIO_BASE,               0x90000),    UART1_MMIO_BASE,              DEVICE_MEM},
+    {PLATFORM_MEM_TALBE(GIC_PL600_DISTRIBUTOR_PPTR,    0x10000),    GIC_PL600_DISTRIBUTOR_PPTR,   DEVICE_MEM},
+    {PLATFORM_MEM_TALBE(GIC_PL600_REDISTRIBUTOR_PPTR,  0xc0000),    GIC_PL600_REDISTRIBUTOR_PPTR, DEVICE_MEM},
+#ifdef PKG_USING_RT_OPENAMP
+    {PLATFORM_MEM_TALBE(AMP_SHARE_MEMORY_ADDRESS, AMP_SHARE_MEMORY_SIZE), AMP_SHARE_MEMORY_ADDRESS, NORMAL_MEM},
+#endif /* PKG_USING_RT_OPENAMP */
 };
 
 const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
@@ -39,20 +51,30 @@ void idle_wfi(void)
 
 void rt_hw_board_init(void)
 {
-    extern void *MMUTable;
-    rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x80000000, 0x10000000, MMUTable, 0);
+    extern unsigned long MMUTable[512];
+    rt_region_t init_page_region;
+
+    rt_hw_mmu_map_init(&rt_kernel_space, (void *) 0x20000000, 0xE0000000 - 1, MMUTable, 0);
+
+    init_page_region.start = RT_HW_PAGE_START;
+    init_page_region.end = RT_HW_PAGE_END;
+    rt_page_init(init_page_region);
+
     rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size);
 
     /* initialize hardware interrupt */
     rt_hw_interrupt_init();
+
     /* initialize uart */
     rt_hw_uart_init();
+
     /* initialize timer for os tick */
     rt_hw_gtimer_init();
 
     rt_thread_idle_sethook(idle_wfi);
 
     // TODO porting to FDT-driven PSCI: arm_psci_init(PSCI_METHOD_SMC, RT_NULL, RT_NULL);
+    psci_init();
 
 #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
     /* set console device */
@@ -79,18 +101,60 @@ void rt_hw_board_init(void)
 void reboot(void)
 {
     // TODO poring to FDT to use new PSCI: arm_psci_system_reboot();
+    if (psci_ops.system_reset)
+    {
+        psci_ops.system_reset();
+    }
+    else
+    {
+        void *cur_base = rt_ioremap((void *) CRU_BASE, 0x100);
+        HWREG32(cur_base + 0x00D4) = 0xfdb9;
+        HWREG32(cur_base + 0x00D8) = 0xeca8;
+    }
 }
 MSH_CMD_EXPORT(reboot, reboot...);
 
-#ifdef RT_USING_SMP
+static void print_cpu_id(int argc, char *argv[])
+{
+    rt_kprintf("rt_hw_cpu_id:%d\n", rt_hw_cpu_id());
+}
+MSH_CMD_EXPORT_ALIAS(print_cpu_id, cpuid, print_cpu_id);
+
+#ifdef RT_USING_AMP
+void start_cpu(int argc, char *argv[])
+{
+    rt_uint32_t status;
+    if (psci_ops.cpu_on)
+    {
+        status = psci_ops.cpu_on(0x3, (rt_uint64_t) 0x7A000000);
+        rt_kprintf("arm_psci_cpu_on 0x%X\n", status);
+    }
+}
+MSH_CMD_EXPORT(start_cpu, start_cpu);
+
+#ifdef RT_AMP_SLAVE
+void rt_hw_cpu_shutdown()
+{
+    if (psci_ops.cpu_off)
+    {
+        psci_ops.cpu_off(0);
+    }
+}
+#endif /* RT_AMP_SLAVE */
+#endif /* RT_USING_AMP */
+
+#if defined(RT_USING_SMP) || defined(RT_USING_AMP)
 rt_uint64_t rt_cpu_mpidr_early[] =
 {
-    [0] = 0x81000000,
-    [1] = 0x81000100,
-    [2] = 0x81000200,
-    [3] = 0x81000300,
+    [0] = 0x80000000,
+    [1] = 0x80000100,
+    [2] = 0x80000200,
+    [3] = 0x80000300,
+    [RT_CPUS_NR] = 0
 };
+#endif
 
+#ifdef RT_USING_SMP
 void rt_hw_secondary_cpu_up(void)
 {
     int i;
@@ -98,7 +162,7 @@ void rt_hw_secondary_cpu_up(void)
 
     for (i = 1; i < RT_CPUS_NR; ++i)
     {
-        arm_psci_cpu_on(rt_cpu_mpidr_early[i], (rt_uint64_t)secondary_cpu_start);
+        arm_psci_cpu_on(rt_cpu_mpidr_early[i], (rt_uint64_t) secondary_cpu_start);
     }
 }
 

bsp/rockchip/rk3568/driver/board.h

@@ -16,13 +16,11 @@
 extern unsigned char __bss_start;
 extern unsigned char __bss_end;
 
-#define RT_HW_HEAP_BEGIN    (void *)&__bss_end
-#define RT_HW_HEAP_END      (void *)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
+#define RT_HW_PAGE_START    RT_ALIGN((unsigned long)&__bss_end, 0x1000)
+#define RT_HW_PAGE_END      (RT_HW_PAGE_START + 0x100000)
 
-#ifndef RT_USING_SMART
-#define PV_OFFSET 0
-#define KERNEL_VADDR_START 0
-#endif
+#define RT_HW_HEAP_BEGIN    (void *)(RT_HW_PAGE_END)
+#define RT_HW_HEAP_END      (void *)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
 
 void rt_hw_board_init(void);
 

bsp/rockchip/rk3568/driver/drv_uart.c

@@ -302,10 +302,12 @@ static void rt_hw_uart_isr(int irqno, void *param)
 
 int rt_hw_uart_init(void)
 {
-    struct hw_uart_device *uart;
+    rt_uint32_t value;
+    struct hw_uart_device* uart;
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    RT_UNUSED(value);
 
-    config.baud_rate = 1500000;
+    config.baud_rate = 115200;
 
 #define BSP_INSTALL_UART_DEVICE(no)     \
     uart = &_uart##no##_device;         \
@@ -331,6 +333,12 @@ int rt_hw_uart_init(void)
 #endif
 
 #ifdef RT_USING_UART4
+    HWREG32(CRU_BASE + 0x370) = 0xFFFF0000 | (0x600) |(HWREG32(CRU_BASE + 0x370) & 0xF0FF);
+    value = HWREG32(0xFDC60000 + 0x48);
+    value &= ~((7 << 8) | (7 << 4));
+    value |= 0xFFFF0000 | (4 << 8) | (4 << 4);
+    HWREG32(0xFDC60000 + 0x48) = value;
+    HWREG32(0xFDC60000 + 0x30C) = 0xFFFF0000 | (1 << 14) | HWREG32(0xFDC60000 + 0x30C);
     BSP_INSTALL_UART_DEVICE(4);
 #endif
 

bsp/rockchip/rk3568/driver/rk3568.h

@@ -13,7 +13,11 @@
 
 #include <rtthread.h>
 
-/* UART */
+#define GRF_PMU_BASE    0xFDC20000
+#define GRF_SYS_BASE    0xFDC60000
+#define CRU_BASE        0xFDD20000
+
+ /* UART */
 #define UART_MMIO_BASE  0xfe650000
 #define UART0_MMIO_BASE 0xfdd50000
 #define UART1_MMIO_BASE (UART_MMIO_BASE + 0)

bsp/rockchip/rk3568/link.lds

@@ -13,7 +13,7 @@ OUTPUT_ARCH(aarch64)
 
 SECTIONS
 {
-    . = 0x208000;
+    . = 0x20000000;
     . = ALIGN(4096);
     .text :
     {

bsp/rockchip/rk3568/rtconfig.h

@@ -238,5 +238,5 @@
 #define RT_USING_UART2
 #define BSP_USING_GIC
 #define BSP_USING_GICV3
-
+#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
 #endif