[BSP] Enable rt-smart feature on raspi4-32 BSP.

bsp/raspberry-pi/raspi4-32/.config

@@ -8,6 +8,7 @@
 #
 CONFIG_RT_NAME_MAX=8
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+CONFIG_RT_USING_SMART=y
 # CONFIG_RT_USING_SMP is not set
 CONFIG_RT_ALIGN_SIZE=4
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
@@ -19,12 +20,12 @@ CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
-CONFIG_IDLE_THREAD_STACK_SIZE=2048
+CONFIG_IDLE_THREAD_STACK_SIZE=4096
 CONFIG_RT_USING_TIMER_SOFT=y
 CONFIG_RT_TIMER_THREAD_PRIO=4
-CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
 CONFIG_RT_DEBUG=y
-# CONFIG_RT_DEBUG_COLOR is not set
+CONFIG_RT_DEBUG_COLOR=y
 # CONFIG_RT_DEBUG_INIT_CONFIG is not set
 # CONFIG_RT_DEBUG_THREAD_CONFIG is not set
 # CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
@@ -50,10 +51,11 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
 # Memory Management
 #
 CONFIG_RT_USING_MEMPOOL=y
-# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_MEMHEAP=y
 # CONFIG_RT_USING_NOHEAP is not set
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
 # CONFIG_RT_USING_MEMTRACE is not set
 CONFIG_RT_USING_HEAP=y
 
@@ -62,14 +64,23 @@ CONFIG_RT_USING_HEAP=y
 #
 CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_DEVICE_OPS is not set
-# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_INTERRUPT_INFO=y
 CONFIG_RT_USING_CONSOLE=y
-CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLEBUF_SIZE=512
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
 CONFIG_RT_VER_NUM=0x40003
+CONFIG_ARCH_ARM=y
 # CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_ARM_MMU=y
+CONFIG_RT_USING_USERSPACE=y
+CONFIG_KERNEL_VADDR_START=0xc0000000
+CONFIG_PV_OFFSET=0x40100000
+CONFIG_RT_IOREMAP_LATE=y
+CONFIG_ARCH_ARM_CORTEX_A=y
+# CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set
 CONFIG_ARCH_ARMV8=y
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+CONFIG_RT_USING_CACHE=y
 
 #
 # RT-Thread Components
@@ -100,7 +111,7 @@ CONFIG_FINSH_CMD_SIZE=80
 # CONFIG_FINSH_USING_AUTH is not set
 CONFIG_FINSH_USING_MSH=y
 CONFIG_FINSH_USING_MSH_DEFAULT=y
-# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_USING_MSH_ONLY=y
 CONFIG_FINSH_ARG_MAX=10
 
 #
@@ -108,8 +119,8 @@ CONFIG_FINSH_ARG_MAX=10
 #
 CONFIG_RT_USING_DFS=y
 CONFIG_DFS_USING_WORKDIR=y
-CONFIG_DFS_FILESYSTEMS_MAX=2
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
 CONFIG_DFS_FD_MAX=16
 # CONFIG_RT_USING_DFS_MNTTABLE is not set
 CONFIG_RT_USING_DFS_ELMFAT=y
@@ -130,7 +141,8 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
 # CONFIG_RT_DFS_ELM_USE_ERASE is not set
 CONFIG_RT_DFS_ELM_REENTRANT=y
 CONFIG_RT_USING_DFS_DEVFS=y
-# CONFIG_RT_USING_DFS_ROMFS is not set
+CONFIG_RT_USING_DFS_ROMFS=y
+# CONFIG_RT_USING_DFS_CROMFS is not set
 # CONFIG_RT_USING_DFS_RAMFS is not set
 # CONFIG_RT_USING_DFS_UFFS is not set
 # CONFIG_RT_USING_DFS_JFFS2 is not set
@@ -141,22 +153,29 @@ CONFIG_RT_USING_DFS_DEVFS=y
 #
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
-# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
 CONFIG_RT_USING_SERIAL=y
-CONFIG_RT_SERIAL_USING_DMA=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
-# CONFIG_RT_USING_HWTIMER is not set
+CONFIG_RT_USING_HWTIMER=y
 # CONFIG_RT_USING_CPUTIME is not set
-# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_I2C_DEBUG is not set
+CONFIG_RT_USING_I2C_BITOPS=y
+# CONFIG_RT_I2C_BITOPS_DEBUG is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
-# CONFIG_RT_USING_PWM is not set
+CONFIG_RT_USING_PWM=y
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
-# CONFIG_RT_USING_RTC is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+CONFIG_RT_USING_SOFT_RTC=y
 CONFIG_RT_USING_SDIO=y
 CONFIG_RT_SDIO_STACK_SIZE=512
 CONFIG_RT_SDIO_THREAD_PRIORITY=15
@@ -189,12 +208,15 @@ CONFIG_RT_USING_WDT=y
 # POSIX layer and C standard library
 #
 CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_NEWLIB is not set
+CONFIG_RT_USING_MUSL=y
+# CONFIG_RT_USING_MUSL_LIBC is not set
 # CONFIG_RT_USING_PTHREADS is not set
 CONFIG_RT_USING_POSIX=y
-# CONFIG_RT_USING_POSIX_MMAP is not set
-# CONFIG_RT_USING_POSIX_TERMIOS is not set
+CONFIG_RT_USING_POSIX_MMAP=y
+CONFIG_RT_USING_POSIX_TERMIOS=y
 # CONFIG_RT_USING_POSIX_GETLINE is not set
-# CONFIG_RT_USING_POSIX_AIO is not set
+CONFIG_RT_USING_POSIX_AIO=y
 # CONFIG_RT_USING_MODULE is not set
 
 #
@@ -204,7 +226,13 @@ CONFIG_RT_USING_POSIX=y
 #
 # Socket abstraction layer
 #
-# CONFIG_RT_USING_SAL is not set
+CONFIG_RT_USING_SAL=y
+
+#
+# protocol stack implement
+#
+CONFIG_SAL_USING_LWIP=y
+CONFIG_SAL_USING_POSIX=y
 
 #
 # Network interface device
@@ -239,8 +267,8 @@ CONFIG_IP_SOF_BROADCAST_RECV=1
 #
 # Static IPv4 Address
 #
-CONFIG_RT_LWIP_IPADDR="192.168.1.30"
-CONFIG_RT_LWIP_GWADDR="192.168.1.1"
+CONFIG_RT_LWIP_IPADDR="192.168.137.100"
+CONFIG_RT_LWIP_GWADDR="192.168.137.1"
 CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
 CONFIG_RT_LWIP_UDP=y
 CONFIG_RT_LWIP_TCP=y
@@ -256,11 +284,11 @@ CONFIG_RT_LWIP_TCP_SND_BUF=8196
 CONFIG_RT_LWIP_TCP_WND=8196
 CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
 CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
-CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
+CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=4096
 # CONFIG_LWIP_NO_RX_THREAD is not set
 # CONFIG_LWIP_NO_TX_THREAD is not set
 CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
-CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
+CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=4096
 CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
 # CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
 CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
@@ -294,6 +322,13 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
+CONFIG_RT_USING_LWP=y
+CONFIG_RT_LWP_MAX_NR=30
+# CONFIG_RT_USING_GDBSERVER is not set
+CONFIG_RT_CH_MSG_MAX_NR=1024
+CONFIG_RT_LWP_SHM_MAX_NR=64
+CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
+# CONFIG_LWP_USING_CORE_DUMP is not set
 
 #
 # RT-Thread online packages
@@ -376,6 +411,7 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_AGILE_JSMN is not set
 # CONFIG_PKG_USING_PDULIB is not set
 # CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
 
 #
 # security packages
@@ -428,6 +464,7 @@ CONFIG_RT_LWIP_USING_PING=y
 # system packages
 #
 # CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_LWEXT4 is not set
@@ -539,6 +576,7 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_ELAPACK is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
 # CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_TETRIS is not set
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_CRCLIB is not set
@@ -604,10 +642,7 @@ CONFIG_BSP_USING_GIC=y
 CONFIG_BSP_USING_GIC400=y
 # CONFIG_BSP_USING_GIC500 is not set
 CONFIG_BSP_USING_PIN=y
-CONFIG_BSP_USING_SPI=y
-CONFIG_BSP_USING_SPI0_BUS=y
-CONFIG_BSP_USING_SPI0_DEVICE0=y
-# CONFIG_BSP_USING_SPI0_DEVICE1 is not set
+# CONFIG_BSP_USING_SPI is not set
 CONFIG_BSP_USING_CORETIMER=y
 # CONFIG_BSP_USING_SYSTIMER is not set
 CONFIG_BSP_USING_WDT=y
@@ -619,4 +654,4 @@ CONFIG_BSP_USING_SDIO0=y
 # Board Peripheral Drivers
 #
 CONFIG_BSP_USING_HDMI=y
-CONFIG_BSP_USING_HDMI_DISPLAY=y
+# CONFIG_BSP_USING_HDMI_DISPLAY is not set

bsp/raspberry-pi/raspi4-32/Kconfig

@@ -21,6 +21,9 @@ source "$PKGS_DIR/Kconfig"
 config BCM2711_SOC
     bool
     select ARCH_ARMV8
+    select ARCH_ARM_CORTEX_A
+    select RT_USING_CACHE
+    select ARCH_ARM_MMU
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
     default y

bsp/raspberry-pi/raspi4-32/SConstruct

@@ -2,7 +2,10 @@ import os
 import sys
 import rtconfig
 
-from rtconfig import RTT_ROOT
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.join(os.getcwd(), '..', '..', '..')
 
 sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
 from building import *
@@ -11,20 +14,20 @@ TARGET = 'rtthread.' + rtconfig.TARGET_EXT
 
 DefaultEnvironment(tools=[])
 env = Environment(tools = ['mingw'],
-    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
-    AR = rtconfig.AR, ARFLAGS = '-rc',
+    AS   = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC   = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    CXX  = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR   = rtconfig.AR, ARFLAGS = '-rc',
     LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
 env['ASCOM'] = env['ASPPCOM']
+env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group'
 
 Export('RTT_ROOT')
 Export('rtconfig')
 
 # prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+objs = PrepareBuilding(env, RTT_ROOT)
 
 # make a building
 DoBuilding(TARGET, objs)
-

bsp/raspberry-pi/raspi4-32/applications/main.c

@@ -4,28 +4,15 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author         Notes
- * 2020-04-16     bigmagic       first version
+ * Date           Author       Notes
+ * 2017-5-30     bernard       the first version
  */
 
-#include <rtthread.h>
-#include <rtdevice.h>
-#include <board.h>
-
-#define     ACTLED      (42)
+#include <stdio.h>
 
 int main(int argc, char** argv)
-{
-    rt_kprintf("Hi, this is RT-Thread!!\n");
-    
-    rt_pin_mode(ACTLED, PIN_MODE_OUTPUT);
+{   
+    rt_kprintf("hello rt-thread!\n");
 
-    while(1)
-    {
-        rt_pin_write(ACTLED, PIN_HIGH);
-        rt_thread_mdelay(1000);
-        rt_pin_write(ACTLED, PIN_LOW);
-        rt_thread_mdelay(1000);
-    }
-    return RT_EOK;
+    return 0;
 }

bsp/raspberry-pi/raspi4-32/driver/board.c

@@ -16,15 +16,52 @@
 
 #include "cp15.h"
 #include "mmu.h"
+#include "mbox.h"
 
+#ifdef RT_USING_USERSPACE
+#include <page.h>
+#include <lwp_arch.h>
+#endif
+
+rt_mmu_info mmu_info;
+extern size_t MMUTable[];
+
+size_t gpio_base_addr = GPIO_BASE_ADDR;
+
+size_t uart_base_addr = UART_BASE;
+
+size_t gic_base_addr = GIC_V2_BASE;
+
+size_t arm_timer_base = ARM_TIMER_BASE;
+
+size_t pactl_cs_base = PACTL_CS_ADDR;
+
+size_t stimer_base_addr = STIMER_BASE;
+
+size_t mmc2_base_addr   = MMC2_BASE_ADDR;
+
+size_t videocore_mbox = VIDEOCORE_MBOX;
+
+size_t mbox_addr = MBOX_ADDR;
+
+size_t wdt_base_addr = WDT_BASE;
+
+void* mac_reg_base_addr = (void *)MAC_REG;
+
+void* eth_send_no_cache = (void *)SEND_DATA_NO_CACHE;
+void* eth_recv_no_cache = (void *)RECV_DATA_NO_CACHE;
+
+#ifdef RT_USING_USERSPACE
+struct mem_desc platform_mem_desc[] = {
+    {KERNEL_VADDR_START, KERNEL_VADDR_START + 0x0fffffff, KERNEL_VADDR_START + PV_OFFSET, NORMAL_MEM}
+};
+#else
 struct mem_desc platform_mem_desc[] = {
     {0x0, 0x6400000, 0x0, NORMAL_MEM},
-    {0x8000000, 0x8800000, 0x8000000, DEVICE_MEM},    //mbox msg
-    {0x0EA00000, 0x0EE00000, 0x0EA00000, DEVICE_MEM}, //framebuffer
-    {0xFD500000, 0xFDA00000, 0xFD500000, DEVICE_MEM}, //gmac
-    {0xFE000000, 0xFE400000, 0xFE000000, DEVICE_MEM}, //peripheral
-    {0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM}  //gic
+    {0xFE000000, 0xFE400000, 0xFE000000, DEVICE_MEM},//uart gpio
+    {0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM} //gic
 };
+#endif
 
 const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]);
 
@@ -58,31 +95,119 @@ void idle_wfi(void)
     asm volatile ("wfi");
 }
 
+#ifdef RT_USING_USERSPACE
+rt_region_t init_page_region = {
+    (uint32_t)(KERNEL_VADDR_START + 32 * 1024 * 1024),
+    (uint32_t)(KERNEL_VADDR_START + 64 * 1024 * 1024),
+};
+#endif
+
 /**
  *  Initialize the Hardware related stuffs. Called from rtthread_startup() 
  *  after interrupt disabled.
  */
 void rt_hw_board_init(void)
 {
+    /* io device remap */
+#ifdef RT_USING_USERSPACE
+    rt_hw_mmu_map_init(&mmu_info, (void*)0xf0000000, 0x10000000, MMUTable, PV_OFFSET);
+
+    rt_page_init(init_page_region);
+    rt_hw_mmu_ioremap_init(&mmu_info, (void*)0xf0000000, 0x10000000);
+
+    arch_kuser_init(&mmu_info, (void*)0xffff0000);
+#else
+    rt_hw_mmu_map_init(&mmu_info, (void*)GPIO_BASE_ADDR, 0x10000000, MMUTable, 0);
+#endif
+
+    //gpio
+    gpio_base_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)GPIO_BASE_ADDR, 0x1000);
+    //uart
+    //uart_base_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)UART_BASE, 0x1000);
+    //aux
+    //aux_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)AUX_BASE_ADDR, 0x1000);
+    //timer
+    arm_timer_base = (size_t)rt_hw_kernel_phys_to_virt((void*)ARM_TIMER_BASE, 0x1000);
+    //gic
+    //gic_base_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)GIC_V2_BASE, 0x10000);
+    //pactl
+    pactl_cs_base = (size_t)rt_hw_kernel_phys_to_virt((void*)PACTL_CS_ADDR, 0x1000);
+
+    //stimer
+    stimer_base_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)STIMER_BASE, 0x1000);
+
+    //mmc2_base_addr 
+    mmc2_base_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)MMC2_BASE_ADDR, 0x1000);
+
+    //mbox
+    videocore_mbox = (size_t)rt_hw_kernel_phys_to_virt((void*)VIDEOCORE_MBOX, 0x1000);
+
+    //mbox msg
+    mbox_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)MBOX_ADDR, 0x1000);
+    mbox = (volatile unsigned int *)mbox_addr;
+
+    //wdt
+    wdt_base_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)WDT_BASE, 0x1000);
+
+    //mac
+    mac_reg_base_addr = (void *)rt_hw_kernel_phys_to_virt((void*)MAC_REG, 0x80000);
+
+    //eth data
+    eth_send_no_cache = (void *)rt_hw_kernel_phys_to_virt((void*)SEND_DATA_NO_CACHE, 0x200000);
+    eth_recv_no_cache = (void *)rt_hw_kernel_phys_to_virt((void*)RECV_DATA_NO_CACHE, 0x200000);
+
     /* initialize hardware interrupt */
     rt_hw_interrupt_init();
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
     /* initialize uart */
-    rt_hw_uart_init();      // driver/drv_uart.c
+    rt_hw_uart_init();
+
 #ifdef RT_USING_CONSOLE
     /* set console device */
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif /* RT_USING_CONSOLE */
 
-#ifdef RT_USING_HEAP
-    /* initialize memory system */
-    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
-    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
-#endif
-        /* initialize timer for os tick */
+    /* initialize timer for os tick */
     rt_hw_timer_init();
     rt_thread_idle_sethook(idle_wfi);
 
+    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
+
+}
+
+#ifdef RT_USING_GDBSERVER
+
+#include <dfs_posix.h>
+
+#define GDB_CONNECT_DEVICE "/dev/uart4"
+
+/* for gdb */
+int gdb_com_open(void)
+{
+    return open(GDB_CONNECT_DEVICE, O_RDWR);
+}
+
+void gdb_com_close(int fd)
+{
+    close(fd);
 }
+
+ssize_t gdb_com_read(int fd, void *buff, size_t len)
+{
+    return read(fd, buff, len);
+}
+
+ssize_t gdb_com_write(int fd, void *buff, size_t len)
+{
+    return write(fd, buff, len);
+}
+
+#endif

bsp/raspberry-pi/raspi4-32/driver/board.h

@@ -13,6 +13,7 @@
 
 #include <stdint.h>
 #include "raspi4.h"
+#include "mmu.h"
 
 extern unsigned char __bss_start;
 extern unsigned char __bss_end;
@@ -22,4 +23,6 @@ extern unsigned char __bss_end;
 
 void rt_hw_board_init(void);
 
+extern rt_mmu_info mmu_info;
+
 #endif

bsp/raspberry-pi/raspi4-32/driver/drv_eth.c

@@ -19,13 +19,18 @@
 #include "raspi4.h"
 #include "drv_eth.h"
 
+#define DBG_LEVEL   DBG_LOG
+#include <rtdbg.h>
+#define LOG_TAG                "drv.eth"
+
+static int link_speed = 0;
+static int link_flag = 0;
+
 #define RECV_CACHE_BUF          (1024)
-#define SEND_DATA_NO_CACHE      (0x08200000)
-#define RECV_DATA_NO_CACHE      (0x08400000)
 #define DMA_DISC_ADDR_SIZE      (4 * 1024 *1024)
 
-#define RX_DESC_BASE            (MAC_REG + GENET_RX_OFF)
-#define TX_DESC_BASE            (MAC_REG + GENET_TX_OFF)
+#define RX_DESC_BASE            (mac_reg_base_addr + GENET_RX_OFF)
+#define TX_DESC_BASE            (mac_reg_base_addr + GENET_TX_OFF)
 
 #define MAX_ADDR_LEN            (6)
 
@@ -34,6 +39,11 @@
 
 #define BIT(nr)                 (1UL << (nr))
 
+static rt_thread_t link_thread_tid = RT_NULL;
+#define LINK_THREAD_STACK_SIZE   (1024)
+#define LINK_THREAD_PRIORITY     (20)
+#define LINK_THREAD_TIMESLICE    (10)
+
 static rt_uint32_t tx_index = 0;
 static rt_uint32_t rx_index = 0;
 static rt_uint32_t index_flag = 0;
@@ -54,6 +64,7 @@ struct rt_eth_dev
 };
 static struct rt_eth_dev eth_dev;
 static struct rt_semaphore sem_lock;
+static struct rt_semaphore link_ack;
 
 static inline rt_uint32_t read32(void *addr)
 {
@@ -77,10 +88,10 @@ static int bcmgenet_interface_set(void)
     switch (phy_mode) {
     case PHY_INTERFACE_MODE_RGMII:
     case PHY_INTERFACE_MODE_RGMII_RXID:
-        write32(MAC_REG + SYS_PORT_CTRL,PORT_MODE_EXT_GPHY);
+        write32(mac_reg_base_addr + SYS_PORT_CTRL,PORT_MODE_EXT_GPHY);
         break;
     default:
-        rt_kprintf("unknown phy mode: %d\n", MAC_REG);
+        rt_kprintf("unknown phy mode: %d\n", mac_reg_base_addr);
         return -1;
     }
     return 0;
@@ -89,44 +100,44 @@ static int bcmgenet_interface_set(void)
 static void bcmgenet_umac_reset(void)
 {
     rt_uint32_t reg;
-    reg = read32(MAC_REG + SYS_RBUF_FLUSH_CTRL);
+    reg = read32(mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL);
     reg |= BIT(1);
-    write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), reg);
+    write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), reg);
 
     reg &= ~BIT(1);
-    write32((MAC_REG + SYS_RBUF_FLUSH_CTRL),reg);
+    write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL),reg);
 
     DELAY_MICROS(10);
-    write32((MAC_REG + SYS_RBUF_FLUSH_CTRL),0);
+    write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL),0);
     DELAY_MICROS(10);
-    write32(MAC_REG + UMAC_CMD, 0);
-    write32(MAC_REG + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN));
+    write32(mac_reg_base_addr + UMAC_CMD, 0);
+    write32(mac_reg_base_addr + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN));
     DELAY_MICROS(2);
-    write32(MAC_REG + UMAC_CMD, 0);
+    write32(mac_reg_base_addr + UMAC_CMD, 0);
     /* clear tx/rx counter */
-    write32(MAC_REG + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT);
-    write32(MAC_REG + UMAC_MIB_CTRL, 0);
-    write32(MAC_REG + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE);
+    write32(mac_reg_base_addr + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT);
+    write32(mac_reg_base_addr + UMAC_MIB_CTRL, 0);
+    write32(mac_reg_base_addr + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE);
     /* init rx registers, enable ip header optimization */
-    reg = read32(MAC_REG + RBUF_CTRL);
+    reg = read32(mac_reg_base_addr + RBUF_CTRL);
     reg |= RBUF_ALIGN_2B;
-    write32(MAC_REG + RBUF_CTRL, reg);
-    write32(MAC_REG + RBUF_TBUF_SIZE_CTRL, 1);
+    write32(mac_reg_base_addr + RBUF_CTRL, reg);
+    write32(mac_reg_base_addr + RBUF_TBUF_SIZE_CTRL, 1);
 }
 
 static void bcmgenet_disable_dma(void)
 {
     rt_uint32_t tdma_reg = 0, rdma_reg = 0;
 
-    tdma_reg = read32(MAC_REG + TDMA_REG_BASE + DMA_CTRL);
+    tdma_reg = read32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL);
     tdma_reg &= ~(1UL << DMA_EN);
-    write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, tdma_reg);
-    rdma_reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL);
+    write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL, tdma_reg);
+    rdma_reg = read32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL);
     rdma_reg &= ~(1UL << DMA_EN);
-    write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, rdma_reg);
-    write32(MAC_REG + UMAC_TX_FLUSH, 1);
+    write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL, rdma_reg);
+    write32(mac_reg_base_addr + UMAC_TX_FLUSH, 1);
     DELAY_MICROS(100);
-    write32(MAC_REG + UMAC_TX_FLUSH, 0);
+    write32(mac_reg_base_addr + UMAC_TX_FLUSH, 0);
 }
 
 static void bcmgenet_enable_dma(void)
@@ -135,10 +146,10 @@ static void bcmgenet_enable_dma(void)
     rt_uint32_t dma_ctrl = 0;
 
     dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN;
-    write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, dma_ctrl);
+    write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL, dma_ctrl);
 
-    reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL);
-    write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg);
+    reg = read32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL);
+    write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg);
 }
 
 static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t value)
@@ -146,16 +157,16 @@ static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t va
     int count = 10000;
     rt_uint32_t val;
     val = MDIO_WR | (addr << MDIO_PMD_SHIFT) |(reg << MDIO_REG_SHIFT) | (0xffff & value);
-    write32(MAC_REG + MDIO_CMD, val);
+    write32(mac_reg_base_addr + MDIO_CMD, val);
 
-    rt_uint32_t reg_val = read32(MAC_REG + MDIO_CMD);
+    rt_uint32_t reg_val = read32(mac_reg_base_addr + MDIO_CMD);
     reg_val = reg_val | MDIO_START_BUSY;
-    write32(MAC_REG + MDIO_CMD, reg_val);
+    write32(mac_reg_base_addr + MDIO_CMD, reg_val);
 
-    while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count))
+    while ((read32(mac_reg_base_addr + MDIO_CMD) & MDIO_START_BUSY) && (--count))
         DELAY_MICROS(1);
 
-    reg_val = read32(MAC_REG + MDIO_CMD);
+    reg_val = read32(mac_reg_base_addr + MDIO_CMD);
 
     return reg_val & 0xffff;
     
@@ -168,16 +179,16 @@ static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg)
     rt_uint32_t reg_val = 0;
 
     val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
-    write32(MAC_REG + MDIO_CMD, val);
+    write32(mac_reg_base_addr + MDIO_CMD, val);
 
-    reg_val = read32(MAC_REG + MDIO_CMD);
+    reg_val = read32(mac_reg_base_addr + MDIO_CMD);
     reg_val = reg_val | MDIO_START_BUSY;
-    write32(MAC_REG + MDIO_CMD, reg_val);
+    write32(mac_reg_base_addr + MDIO_CMD, reg_val);
 
-    while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count))
+    while ((read32(mac_reg_base_addr + MDIO_CMD) & MDIO_START_BUSY) && (--count))
         DELAY_MICROS(1);
 
-    reg_val = read32(MAC_REG + MDIO_CMD);
+    reg_val = read32(mac_reg_base_addr + MDIO_CMD);
 
     return reg_val & 0xffff;    
 }
@@ -190,10 +201,10 @@ static int bcmgenet_gmac_write_hwaddr(void)
     bcm271x_mbox_hardware_get_mac_address(&addr[0]);
 
     reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
-    write32(MAC_REG + UMAC_MAC0, reg);
+    write32(mac_reg_base_addr + UMAC_MAC0, reg);
 
     reg = addr[4] << 8 | addr[5];
-    write32(MAC_REG + UMAC_MAC1, reg);
+    write32(mac_reg_base_addr + UMAC_MAC1, reg);
     return 0;
 }
 
@@ -209,7 +220,7 @@ static int get_ethernet_uid(void)
 
     if(BCM54213PE_VERSION_B1 == uid)
     {
-        rt_kprintf("version is B1\n");
+        LOG_I("version is B1\n");
     }
     return uid;
 }
@@ -236,45 +247,47 @@ static void bcmgenet_mdio_init(void)
     /* read status reg */
     bcmgenet_mdio_read(1, BCM54213PE_IEEE_EXTENDED_STATUS);
     bcmgenet_mdio_read(1, BCM54213PE_AUTO_NEGOTIATION_ADV);
+
     bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS);
     bcmgenet_mdio_read(1, BCM54213PE_CONTROL);
     /* half full duplex capability */
     bcmgenet_mdio_write(1, BCM54213PE_CONTROL, (CONTROL_HALF_DUPLEX_CAPABILITY | CONTROL_FULL_DUPLEX_CAPABILITY));
     bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL);
+
     /* set mii control */
     bcmgenet_mdio_write(1,BCM54213PE_MII_CONTROL,(MII_CONTROL_AUTO_NEGOTIATION_ENABLED | MII_CONTROL_AUTO_NEGOTIATION_RESTART| MII_CONTROL_PHY_FULL_DUPLEX| MII_CONTROL_SPEED_SELECTION));
 }
 
 static void rx_ring_init(void)
 {
-    write32(MAC_REG + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
-    write32(MAC_REG + RDMA_RING_REG_BASE + DMA_START_ADDR,0x0 );
-    write32(MAC_REG + RDMA_READ_PTR, 0x0);
-    write32(MAC_REG + RDMA_WRITE_PTR, 0x0);
-    write32(MAC_REG + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1);
-
-    write32(MAC_REG + RDMA_PROD_INDEX, 0x0);
-    write32(MAC_REG + RDMA_CONS_INDEX, 0x0);
-    write32(MAC_REG + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
-    write32(MAC_REG + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE);
-    write32(MAC_REG + RDMA_REG_BASE + DMA_RING_CFG,1 << DEFAULT_Q);
+    write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
+    write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_START_ADDR,0x0 );
+    write32(mac_reg_base_addr + RDMA_READ_PTR, 0x0);
+    write32(mac_reg_base_addr + RDMA_WRITE_PTR, 0x0);
+    write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1);
+
+    write32(mac_reg_base_addr + RDMA_PROD_INDEX, 0x0);
+    write32(mac_reg_base_addr + RDMA_CONS_INDEX, 0x0);
+    write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
+    write32(mac_reg_base_addr + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE);
+    write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_RING_CFG,1 << DEFAULT_Q);
 }
 
 static void tx_ring_init(void)
 {
-    write32(MAC_REG + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
-    write32(MAC_REG + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0);
-    write32(MAC_REG + TDMA_READ_PTR, 0x0);
-    write32(MAC_REG + TDMA_READ_PTR, 0x0);
-    write32(MAC_REG + TDMA_READ_PTR, 0x0);
-    write32(MAC_REG + TDMA_WRITE_PTR, 0x0);
-    write32(MAC_REG + TDMA_RING_REG_BASE + DMA_END_ADDR,TX_DESCS * DMA_DESC_SIZE / 4 - 1);
-    write32(MAC_REG + TDMA_PROD_INDEX, 0x0);
-    write32(MAC_REG + TDMA_CONS_INDEX, 0x0);
-    write32(MAC_REG + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH,0x1);
-    write32(MAC_REG + TDMA_FLOW_PERIOD,0x0);
-    write32(MAC_REG + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
-    write32(MAC_REG + TDMA_REG_BASE + DMA_RING_CFG,1 << DEFAULT_Q);
+    write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
+    write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0);
+    write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0);
+    write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0);
+    write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0);
+    write32(mac_reg_base_addr + TDMA_WRITE_PTR, 0x0);
+    write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_END_ADDR,TX_DESCS * DMA_DESC_SIZE / 4 - 1);
+    write32(mac_reg_base_addr + TDMA_PROD_INDEX, 0x0);
+    write32(mac_reg_base_addr + TDMA_CONS_INDEX, 0x0);
+    write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH,0x1);
+    write32(mac_reg_base_addr + TDMA_FLOW_PERIOD,0x0);
+    write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
+    write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_RING_CFG,1 << DEFAULT_Q);
 }
 
 static void rx_descs_init(void)
@@ -291,46 +304,10 @@ static void rx_descs_init(void)
     }
 }
 
-static int phy_startup(void)
-{
-    int count = 1000000;
-    while ((bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS) & MII_STATUS_LINK_UP) && (--count))
-    DELAY_MICROS(1);
-    if(count > 0)
-    {
-        rt_kprintf("bcmgenet: PHY startup ok!\n");
-    }
-    else
-    {
-        rt_kprintf("bcmgenet: PHY startup err!\n");
-        return 1;
-    }
-
-    if(bcmgenet_mdio_read(1, BCM54213PE_STATUS) == 0)
-    {
-        //todo
-    }
-    else
-    {
-        rt_kprintf("bcmgenet: BCM54213PE_STATUS err!\n");
-    }
-
-    if(bcmgenet_mdio_read(1, BCM54213PE_CONTROL) == (CONTROL_FULL_DUPLEX_CAPABILITY| CONTROL_HALF_DUPLEX_CAPABILITY))
-    {
-        //todo
-    }
-    else
-    {
-        rt_kprintf("bcmgenet: BCM54213PE_CONTROL err!\n");
-    }
-
-    return 0;
-}
-
 static int bcmgenet_adjust_link(void)
 {
     rt_uint32_t speed;
-    rt_uint32_t phy_dev_speed = SPEED_100;
+    rt_uint32_t phy_dev_speed = link_speed;
     
     switch (phy_dev_speed) {
     case SPEED_1000:
@@ -347,17 +324,25 @@ static int bcmgenet_adjust_link(void)
         return -1;
     }
 
-    rt_uint32_t reg1 = read32(MAC_REG + EXT_RGMII_OOB_CTRL);
+    rt_uint32_t reg1 = read32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL);
     //reg1 &= ~(1UL << OOB_DISABLE);
 
     //rt_kprintf("OOB_DISABLE is %d\n", OOB_DISABLE);
     reg1 |= (RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS);
-    write32(MAC_REG + EXT_RGMII_OOB_CTRL, reg1);
+    write32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL, reg1);
     DELAY_MICROS(1000);
-    write32(MAC_REG + UMAC_CMD, speed << CMD_SPEED_SHIFT);
+    write32(mac_reg_base_addr + UMAC_CMD, speed << CMD_SPEED_SHIFT);
     return 0;
 }
 
+void link_irq(void *param)
+{
+    if((bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS) & MII_STATUS_LINK_UP) != 0)
+    {
+        rt_sem_release(&link_ack);
+    }
+}
+
 static int bcmgenet_gmac_eth_start(void)
 {
     rt_uint32_t ret;
@@ -375,13 +360,6 @@ static int bcmgenet_gmac_eth_start(void)
     /* Enable RX/TX DMA */
     bcmgenet_enable_dma();
 
-    /* read PHY properties over the wire from generic PHY set-up */
-    ret = phy_startup();
-    if (ret) {
-        rt_kprintf("bcmgenet: PHY startup failed: %d\n", ret);
-        return ret;
-    }
-
     /* Update MAC registers based on PHY property */
     ret = bcmgenet_adjust_link();
     if (ret) {
@@ -390,26 +368,26 @@ static int bcmgenet_gmac_eth_start(void)
     }
 
     /* wait tx index clear */
-    while ((read32(MAC_REG + TDMA_CONS_INDEX) != 0) && (--count))
+    while ((read32(mac_reg_base_addr + TDMA_CONS_INDEX) != 0) && (--count))
     DELAY_MICROS(1);
 
-    tx_index = read32(MAC_REG + TDMA_CONS_INDEX);
-    write32(MAC_REG + TDMA_PROD_INDEX, tx_index);
+    tx_index = read32(mac_reg_base_addr + TDMA_CONS_INDEX);
+    write32(mac_reg_base_addr + TDMA_PROD_INDEX, tx_index);
 
-    index_flag = read32(MAC_REG + RDMA_PROD_INDEX);
+    index_flag = read32(mac_reg_base_addr + RDMA_PROD_INDEX);
 
     rx_index = index_flag % 256;
 
-    write32(MAC_REG + RDMA_CONS_INDEX, index_flag);
-    write32(MAC_REG + RDMA_PROD_INDEX, index_flag);
+    write32(mac_reg_base_addr + RDMA_CONS_INDEX, index_flag);
+    write32(mac_reg_base_addr + RDMA_PROD_INDEX, index_flag);
 
     /* Enable Rx/Tx */
     rt_uint32_t rx_tx_en;
-    rx_tx_en = read32(MAC_REG + UMAC_CMD);
+    rx_tx_en = read32(mac_reg_base_addr + UMAC_CMD);
 
     rx_tx_en |= (CMD_TX_EN | CMD_RX_EN);
 
-    write32(MAC_REG + UMAC_CMD, rx_tx_en);
+    write32(mac_reg_base_addr + UMAC_CMD, rx_tx_en);
     return 0;
 }
 
@@ -419,7 +397,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
 {
     void* desc_base;
     rt_uint32_t length = 0, addr = 0;
-    rt_uint32_t prod_index = read32(MAC_REG + RDMA_PROD_INDEX);
+    rt_uint32_t prod_index = read32(mac_reg_base_addr + RDMA_PROD_INDEX);
     //get next
     if(prod_index == index_flag)
     {
@@ -449,7 +427,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
         {
             rx_index = 0;
         }
-        write32(MAC_REG + RDMA_CONS_INDEX, cur_recv_cnt);
+        write32(mac_reg_base_addr + RDMA_CONS_INDEX, cur_recv_cnt);
 
         cur_recv_cnt = cur_recv_cnt + 1;
         prev_recv_cnt = cur_recv_cnt;
@@ -466,7 +444,7 @@ static int bcmgenet_gmac_eth_send(void *packet, int length)
     rt_uint32_t prod_index, cons;
     rt_uint32_t tries = 100;
     
-    prod_index = read32(MAC_REG + TDMA_PROD_INDEX);
+    prod_index = read32(mac_reg_base_addr + TDMA_PROD_INDEX);
 
     len_stat |= 0x3F << DMA_TX_QTAG_SHIFT;
     len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP;
@@ -481,10 +459,10 @@ static int bcmgenet_gmac_eth_send(void *packet, int length)
     }
     prod_index++;
     /* Start Transmisson */
-    write32(MAC_REG + TDMA_PROD_INDEX,prod_index);
+    write32(mac_reg_base_addr + TDMA_PROD_INDEX,prod_index);
 
     do {
-        cons = read32(MAC_REG + TDMA_CONS_INDEX);
+        cons = read32(mac_reg_base_addr + TDMA_CONS_INDEX);
     } while ((cons & 0xffff) < prod_index && --tries);
     if (!tries)
     {
@@ -493,17 +471,67 @@ static int bcmgenet_gmac_eth_send(void *packet, int length)
     return 0;
 }
 
+static void link_task_entry(void *param)
+{   
+    struct eth_device *eth_device = (struct eth_device *)param;
+    RT_ASSERT(eth_device != RT_NULL);
+    struct rt_eth_dev *dev = &eth_dev;
+    //start mdio
+    bcmgenet_mdio_init();
+    //start timer link
+    rt_timer_init(&dev->link_timer, "link_timer",
+                  link_irq,
+                  NULL,
+                  100,
+                  RT_TIMER_FLAG_PERIODIC);
+    rt_timer_start(&dev->link_timer);
+
+    //link wait forever
+    rt_sem_take(&link_ack, RT_WAITING_FOREVER);
+    eth_device_linkchange(&eth_dev.parent, RT_TRUE);//link up
+    rt_timer_stop(&dev->link_timer);
+
+    //set mac
+    bcmgenet_gmac_write_hwaddr();
+    bcmgenet_gmac_write_hwaddr();
+
+    //check link speed
+    if((bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 10)) || (bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 11)))
+    {
+        link_speed = 1000;
+        rt_kprintf("Support link mode Speed 1000M\n");
+    }
+    else if((bcmgenet_mdio_read(1, 0x05) & (1 << 7)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 8))  || (bcmgenet_mdio_read(1, 0x05) & (1 << 9)))
+    {
+        link_speed = 100;
+        rt_kprintf("Support link mode Speed 100M\n");
+    }
+    else
+    {
+        link_speed = 10;
+        rt_kprintf("Support link mode Speed 10M\n");
+    }
+
+    bcmgenet_gmac_eth_start();
+    //irq or poll
+    rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer",
+                  eth_rx_irq,
+                  NULL,
+                  1,
+                  RT_TIMER_FLAG_PERIODIC);
+
+    rt_timer_start(&dev->rx_poll_timer);
+    link_flag = 1;
+}
+
 static rt_err_t bcmgenet_eth_init(rt_device_t device)
 {
-    struct eth_device *eth_device = (struct eth_device *)device;
-    RT_ASSERT(eth_device != RT_NULL);
     rt_uint32_t ret = 0;
     rt_uint32_t hw_reg = 0;
-    struct rt_eth_dev *dev = &eth_dev;
-    
+
     /* Read GENET HW version */
     rt_uint8_t major = 0;
-    hw_reg = read32(MAC_REG + SYS_REV_CTRL);
+    hw_reg = read32(mac_reg_base_addr + SYS_REV_CTRL);
     major = (hw_reg >> 24) & 0x0f;
     if (major != 6) {
         if (major == 5)
@@ -514,7 +542,6 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device)
         rt_kprintf("Uns upported GENETv%d.%d\n", major, (hw_reg >> 16) & 0x0f);
         return RT_ERROR;
     }
-
     /* set interface */
     ret = bcmgenet_interface_set();
     if (ret)
@@ -523,28 +550,18 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device)
     }    
 
     /* rbuf clear */
-    write32(MAC_REG + SYS_RBUF_FLUSH_CTRL, 0);
+    write32(mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL, 0);
 
     /* disable MAC while updating its registers */
-    write32(MAC_REG + UMAC_CMD, 0);
+    write32(mac_reg_base_addr + UMAC_CMD, 0);
     /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
-    write32(MAC_REG + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN);
+    write32(mac_reg_base_addr + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN);
 
-    bcmgenet_mdio_init();
-
-    bcmgenet_gmac_write_hwaddr();
-    bcmgenet_gmac_write_hwaddr();
-
-    bcmgenet_gmac_eth_start();
-
-    //irq or poll
-    rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer",
-                  eth_rx_irq,
-                  NULL,
-                  1,
-                  RT_TIMER_FLAG_PERIODIC);
-
-    rt_timer_start(&dev->rx_poll_timer);
+    link_thread_tid = rt_thread_create("link",link_task_entry, (void *)device,
+                            LINK_THREAD_STACK_SIZE,
+                            LINK_THREAD_PRIORITY, LINK_THREAD_TIMESLICE);
+    if (link_thread_tid != RT_NULL)
+        rt_thread_startup(link_thread_tid);
 
     return RT_EOK;
 }
@@ -565,15 +582,17 @@ static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args)
 
 rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p)
 {
-    rt_uint32_t sendbuf = SEND_DATA_NO_CACHE;
+    rt_uint32_t sendbuf = (rt_uint32_t)eth_send_no_cache;
     /* lock eth device */
-    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
-    //struct rt_eth_dev *dev = (struct rt_eth_dev *) device;
-    pbuf_copy_partial(p, (void *)&send_cache_pbuf[0], p->tot_len, 0);
-    rt_memcpy((void *)sendbuf, send_cache_pbuf, p->tot_len);
+    if(link_flag == 1)
+    {
+        rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+        pbuf_copy_partial(p, (void *)&send_cache_pbuf[0], p->tot_len, 0);
+        rt_memcpy((void *)sendbuf, send_cache_pbuf, p->tot_len);
 
-    bcmgenet_gmac_eth_send((void *)sendbuf, p->tot_len);
-    rt_sem_release(&sem_lock);
+        bcmgenet_gmac_eth_send((void *)sendbuf, p->tot_len);
+        rt_sem_release(&sem_lock);
+    }
     return RT_EOK;
 }
 
@@ -583,16 +602,19 @@ struct pbuf *rt_eth_rx(rt_device_t device)
     int recv_len = 0;
     rt_uint32_t addr_point[8];
     struct pbuf *pbuf = RT_NULL;
-    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
-
-    recv_len = bcmgenet_gmac_eth_recv((rt_uint8_t **)&addr_point[0]);
-
-    if(recv_len > 0)
+    if(link_flag == 1)
     {
-        pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM);
-        rt_memcpy(pbuf->payload, (char *)addr_point[0], recv_len);
+        rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+        recv_len = bcmgenet_gmac_eth_recv((rt_uint8_t **)&addr_point[0]);
+        if(recv_len > 0)
+        {
+            pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM);
+            //calc offset
+            addr_point[0] = (rt_uint32_t)(addr_point[0] + (eth_recv_no_cache - RECV_DATA_NO_CACHE));
+            rt_memcpy(pbuf->payload, (char *)addr_point[0], recv_len);
+        }
+        rt_sem_release(&sem_lock);
     }
-    rt_sem_release(&sem_lock);
     return pbuf;
 }
 
@@ -601,14 +623,14 @@ int rt_hw_eth_init(void)
     rt_uint8_t mac_addr[6];
     
     rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
+    rt_sem_init(&link_ack, "link_ack", 0, RT_IPC_FLAG_FIFO);
 
     memset(&eth_dev, 0, sizeof(eth_dev));
-    memset((void *)SEND_DATA_NO_CACHE, 0, sizeof(DMA_DISC_ADDR_SIZE));
-    memset((void *)RECV_DATA_NO_CACHE, 0, sizeof(DMA_DISC_ADDR_SIZE));
-
+    memset((void *)eth_send_no_cache, 0, sizeof(DMA_DISC_ADDR_SIZE));
+    memset((void *)eth_recv_no_cache, 0, sizeof(DMA_DISC_ADDR_SIZE));
     bcm271x_mbox_hardware_get_mac_address(&mac_addr[0]);
 
-    eth_dev.iobase = MAC_REG;
+    eth_dev.iobase = mac_reg_base_addr;
     eth_dev.name = "e0";
     eth_dev.dev_addr[0] = mac_addr[0];
     eth_dev.dev_addr[1] = mac_addr[1];
@@ -629,9 +651,8 @@ int rt_hw_eth_init(void)
     eth_dev.parent.eth_tx            = rt_eth_tx;
     eth_dev.parent.eth_rx            = rt_eth_rx;
 
-
     eth_device_init(&(eth_dev.parent), "e0");
-    eth_device_linkchange(&eth_dev.parent, RT_TRUE);   //linkup the e0 for lwip to check
+    eth_device_linkchange(&eth_dev.parent, RT_FALSE);   //link down
     return 0;
 }
 INIT_COMPONENT_EXPORT(rt_hw_eth_init);

bsp/raspberry-pi/raspi4-32/driver/drv_eth.h

@@ -12,7 +12,6 @@
 #ifndef __DRV_ETH_H__
 #define __DRV_ETH_H__
 
-#define MAC_REG                     (void *)(0xfd580000)
 
 //#define BIT(nr)                     (1UL << (nr))
 

bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c

@@ -23,26 +23,26 @@ static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_IRQ_NUM];
 uint32_t raspi_get_pin_state(uint32_t fselnum)
 {
     uint32_t gpfsel = 0;
-
+    
     switch (fselnum)
     {
     case 0:
-        gpfsel = GPIO_REG_GPFSEL0(GPIO_BASE);
+        gpfsel = GPIO_REG_GPFSEL0(gpio_base_addr);
         break;
     case 1:
-        gpfsel = GPIO_REG_GPFSEL1(GPIO_BASE);
+        gpfsel = GPIO_REG_GPFSEL1(gpio_base_addr);
         break;
     case 2:
-        gpfsel = GPIO_REG_GPFSEL2(GPIO_BASE);
+        gpfsel = GPIO_REG_GPFSEL2(gpio_base_addr);
         break;
     case 3:
-        gpfsel = GPIO_REG_GPFSEL3(GPIO_BASE);
+        gpfsel = GPIO_REG_GPFSEL3(gpio_base_addr);
         break;
     case 4:
-        gpfsel = GPIO_REG_GPFSEL4(GPIO_BASE);
+        gpfsel = GPIO_REG_GPFSEL4(gpio_base_addr);
         break;
     case 5:
-        gpfsel = GPIO_REG_GPFSEL5(GPIO_BASE);
+        gpfsel = GPIO_REG_GPFSEL5(gpio_base_addr);
         break;
     default:
         break;
@@ -55,22 +55,22 @@ void raspi_set_pin_state(uint32_t fselnum, uint32_t gpfsel)
     switch (fselnum)
     {
     case 0:
-        GPIO_REG_GPFSEL0(GPIO_BASE) = gpfsel;
+        GPIO_REG_GPFSEL0(gpio_base_addr) = gpfsel;
         break;
     case 1:
-        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+        GPIO_REG_GPFSEL1(gpio_base_addr) = gpfsel;
         break;
     case 2:
-        GPIO_REG_GPFSEL2(GPIO_BASE) = gpfsel;
+        GPIO_REG_GPFSEL2(gpio_base_addr) = gpfsel;
         break;
     case 3:
-        GPIO_REG_GPFSEL3(GPIO_BASE) = gpfsel;
+        GPIO_REG_GPFSEL3(gpio_base_addr) = gpfsel;
         break;
     case 4:
-        GPIO_REG_GPFSEL4(GPIO_BASE) = gpfsel;
+        GPIO_REG_GPFSEL4(gpio_base_addr) = gpfsel;
         break;
     case 5:
-        GPIO_REG_GPFSEL5(GPIO_BASE) = gpfsel;
+        GPIO_REG_GPFSEL5(gpio_base_addr) = gpfsel;
         break;
     default:
         break;
@@ -86,22 +86,22 @@ static void gpio_set_pud(GPIO_PIN pin, GPIO_PUPD_FUNC mode)
     switch (fselnum)
     {
     case 0:
-        reg_value = GPIO_PUP_PDN_CNTRL_REG0(GPIO_BASE);
-        GPIO_PUP_PDN_CNTRL_REG0(GPIO_BASE) = (reg_value | (mode << (fselrest*2)));
+        reg_value = GPIO_PUP_PDN_CNTRL_REG0(gpio_base_addr);
+        GPIO_PUP_PDN_CNTRL_REG0(gpio_base_addr) = (reg_value | (mode << (fselrest*2)));
         break;
     case 1:
-        reg_value = GPIO_PUP_PDN_CNTRL_REG1(GPIO_BASE);
-        GPIO_PUP_PDN_CNTRL_REG1(GPIO_BASE) = (reg_value | (mode << (fselrest*2)));
+        reg_value = GPIO_PUP_PDN_CNTRL_REG1(gpio_base_addr);
+        GPIO_PUP_PDN_CNTRL_REG1(gpio_base_addr) = (reg_value | (mode << (fselrest*2)));
         break;
 
     case 2:
-        reg_value = GPIO_PUP_PDN_CNTRL_REG2(GPIO_BASE);
-        GPIO_PUP_PDN_CNTRL_REG2(GPIO_BASE) = (reg_value | (mode << (fselrest*2)));
+        reg_value = GPIO_PUP_PDN_CNTRL_REG2(gpio_base_addr);
+        GPIO_PUP_PDN_CNTRL_REG2(gpio_base_addr) = (reg_value | (mode << (fselrest*2)));
         break;
 
     case 3:
-        reg_value = GPIO_PUP_PDN_CNTRL_REG3(GPIO_BASE);
-        GPIO_PUP_PDN_CNTRL_REG3(GPIO_BASE) = (reg_value | (mode << (fselrest*2)));
+        reg_value = GPIO_PUP_PDN_CNTRL_REG3(gpio_base_addr);
+        GPIO_PUP_PDN_CNTRL_REG3(gpio_base_addr) = (reg_value | (mode << (fselrest*2)));
         break;    
     default:
         break;
@@ -128,23 +128,24 @@ void prev_raspi_pin_write(GPIO_PIN pin, int pin_value)
     {
         if(pin_value == 1)
         {
-            GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32);
+            GPIO_REG_GPSET0(gpio_base_addr) = 1 << (pin % 32);
         }
         else
         {
-            GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32);
+            GPIO_REG_GPCLR0(gpio_base_addr) = 1 << (pin % 32);
         }
     }
     else
     {
         if(pin_value == 1)
         {
-            GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32);
+            GPIO_REG_GPSET1(gpio_base_addr) = 1 << (pin % 32);
         }
         else
         {
-            GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32);
+            GPIO_REG_GPCLR1(gpio_base_addr) = 1 << (pin % 32);
         }
+        
     }
 }
 
@@ -187,7 +188,7 @@ static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
 
     if(num == 0)
     {
-        if(GPIO_REG_GPLEV0(GPIO_BASE) & (1 << pin))
+        if(GPIO_REG_GPLEV0(gpio_base_addr) & (1 << pin))
         {
             pin_level = 1;
         }
@@ -199,7 +200,7 @@ static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
     }
     else
     {
-        if(GPIO_REG_GPLEV1(GPIO_BASE) & (1 << pin))
+        if(GPIO_REG_GPLEV1(gpio_base_addr) & (1 << pin))
         {
             pin_level = 1;
         }
@@ -235,65 +236,65 @@ static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, r
     case PIN_IRQ_MODE_RISING:
         if(pin_num == 0)
         {
-            reg_value = GPIO_REG_GPREN0(GPIO_BASE);
-            GPIO_REG_GPREN0(GPIO_BASE) = (reg_value & ~ mask) | (mask);
+            reg_value = GPIO_REG_GPREN0(gpio_base_addr);
+            GPIO_REG_GPREN0(gpio_base_addr) = (reg_value & ~ mask) | (mask);
         }
         else
         {
-            reg_value = GPIO_REG_GPREN1(GPIO_BASE);
-            GPIO_REG_GPREN1(GPIO_BASE) = (reg_value & ~ mask) | (mask);
+            reg_value = GPIO_REG_GPREN1(gpio_base_addr);
+            GPIO_REG_GPREN1(gpio_base_addr) = (reg_value & ~ mask) | (mask);
         }
         break;
     case PIN_IRQ_MODE_FALLING:
         if(pin_num == 0)
         {
-            reg_value = GPIO_REG_GPFEN0(GPIO_BASE);
-            GPIO_REG_GPFEN0(GPIO_BASE) = (reg_value & ~ mask) | (mask);
+            reg_value = GPIO_REG_GPFEN0(gpio_base_addr);
+            GPIO_REG_GPFEN0(gpio_base_addr) = (reg_value & ~ mask) | (mask);
         }
         else
         {
-            reg_value = GPIO_REG_GPFEN1(GPIO_BASE);
-            GPIO_REG_GPFEN1(GPIO_BASE) = (reg_value & ~ mask) | (mask);
+            reg_value = GPIO_REG_GPFEN1(gpio_base_addr);
+            GPIO_REG_GPFEN1(gpio_base_addr) = (reg_value & ~ mask) | (mask);
         }
         break;
     case PIN_IRQ_MODE_RISING_FALLING:
         if(pin_num == 0)
         {
-            reg_value = GPIO_REG_GPAREN0(GPIO_BASE);
-            GPIO_REG_GPAREN0(GPIO_BASE) = (reg_value & ~ mask) | (mask);
-            reg_value = GPIO_REG_GPFEN0(GPIO_BASE);
-            GPIO_REG_GPFEN0(GPIO_BASE) = (reg_value & ~ mask) | (mask);
+            reg_value = GPIO_REG_GPAREN0(gpio_base_addr);
+            GPIO_REG_GPAREN0(gpio_base_addr) = (reg_value & ~ mask) | (mask);
+            reg_value = GPIO_REG_GPFEN0(gpio_base_addr);
+            GPIO_REG_GPFEN0(gpio_base_addr) = (reg_value & ~ mask) | (mask);
         }
         else
         {
-            reg_value = GPIO_REG_GPAREN1(GPIO_BASE);
-            GPIO_REG_GPAREN1(GPIO_BASE) = (reg_value & ~ mask) | (mask);
-            reg_value = GPIO_REG_GPFEN1(GPIO_BASE);
-            GPIO_REG_GPFEN1(GPIO_BASE) = (reg_value & ~ mask) | (mask);
+            reg_value = GPIO_REG_GPAREN1(gpio_base_addr);
+            GPIO_REG_GPAREN1(gpio_base_addr) = (reg_value & ~ mask) | (mask);
+            reg_value = GPIO_REG_GPFEN1(gpio_base_addr);
+            GPIO_REG_GPFEN1(gpio_base_addr) = (reg_value & ~ mask) | (mask);
         }
         break;
     case PIN_IRQ_MODE_HIGH_LEVEL:
         if(pin_num == 0)
         {
-            reg_value = GPIO_REG_GPHEN0(GPIO_BASE);
-            GPIO_REG_GPHEN0(GPIO_BASE) = (reg_value & ~ mask) | (mask);
+            reg_value = GPIO_REG_GPHEN0(gpio_base_addr);
+            GPIO_REG_GPHEN0(gpio_base_addr) = (reg_value & ~ mask) | (mask);
         }
         else
         {
-            reg_value = GPIO_REG_GPHEN1(GPIO_BASE);
-            GPIO_REG_GPHEN1(GPIO_BASE) = (reg_value & ~ mask) | ( mask);
+            reg_value = GPIO_REG_GPHEN1(gpio_base_addr);
+            GPIO_REG_GPHEN1(gpio_base_addr) = (reg_value & ~ mask) | ( mask);
         }
         break;
     case PIN_IRQ_MODE_LOW_LEVEL:
         if(pin_num == 0)
         {
-            reg_value = GPIO_REG_GPLEN0(GPIO_BASE);
-            GPIO_REG_GPLEN0(GPIO_BASE) = (reg_value & ~ mask) | (mask);
+            reg_value = GPIO_REG_GPLEN0(gpio_base_addr);
+            GPIO_REG_GPLEN0(gpio_base_addr) = (reg_value & ~ mask) | (mask);
         }
         else
         {
-            reg_value = GPIO_REG_GPLEN1(GPIO_BASE);
-            GPIO_REG_GPLEN1(GPIO_BASE) = (reg_value & ~ mask) | (mask);
+            reg_value = GPIO_REG_GPLEN1(gpio_base_addr);
+            GPIO_REG_GPLEN1(gpio_base_addr) = (reg_value & ~ mask) | (mask);
         }
         break;
     }
@@ -357,30 +358,30 @@ static void gpio_irq_handler(int irq, void *param)
     if(irq == IRQ_GPIO0)
     {
         /* 0~27 */
-        value = GPIO_REG_GPEDS0(GPIO_BASE);
+        value = GPIO_REG_GPEDS0(gpio_base_addr);
         value &= 0x0fffffff;
         pin = 0;
-        GPIO_REG_GPEDS0(GPIO_BASE) = value;
+        GPIO_REG_GPEDS0(gpio_base_addr) = value;
     }
     else if(irq == IRQ_GPIO1)
     {
         /* 28-45 */
-        tmpvalue = GPIO_REG_GPEDS0(GPIO_BASE);
+        tmpvalue = GPIO_REG_GPEDS0(gpio_base_addr);
         tmpvalue &= (~0x0fffffff);
-        GPIO_REG_GPEDS0(GPIO_BASE) = tmpvalue;
+        GPIO_REG_GPEDS0(gpio_base_addr) = tmpvalue;
 
-        value = GPIO_REG_GPEDS1(GPIO_BASE);
+        value = GPIO_REG_GPEDS1(gpio_base_addr);
         value &= 0x3fff;
-        GPIO_REG_GPEDS1(GPIO_BASE) = value;
+        GPIO_REG_GPEDS1(gpio_base_addr) = value;
         value = (value) | tmpvalue;
         pin = 28;
     }
     else if (irq == IRQ_GPIO2)
     {
         /* 46-53 */
-        value = GPIO_REG_GPEDS1(GPIO_BASE);
+        value = GPIO_REG_GPEDS1(gpio_base_addr);
         value &= (~0x3fff);
-        GPIO_REG_GPEDS1(GPIO_BASE) = value;
+        GPIO_REG_GPEDS1(gpio_base_addr) = value;
         pin = 46;
     }
 
@@ -405,23 +406,23 @@ int rt_hw_gpio_init(void)
     rt_device_pin_register("gpio", &ops, RT_NULL);
 
     //disable all intr
-    GPIO_REG_GPEDS0(GPIO_BASE) = 0xffffffff;
-    GPIO_REG_GPEDS1(GPIO_BASE) = 0xffffffff;
+    GPIO_REG_GPEDS0(gpio_base_addr) = 0xffffffff;
+    GPIO_REG_GPEDS1(gpio_base_addr) = 0xffffffff;
 
-    GPIO_REG_GPREN0(GPIO_BASE) = 0x0;
-    GPIO_REG_GPREN1(GPIO_BASE) = 0x0;
+    GPIO_REG_GPREN0(gpio_base_addr) = 0x0;
+    GPIO_REG_GPREN1(gpio_base_addr) = 0x0;
 
-    GPIO_REG_GPFEN0(GPIO_BASE) = 0x0;
-    GPIO_REG_GPFEN1(GPIO_BASE) = 0x0;
+    GPIO_REG_GPFEN0(gpio_base_addr) = 0x0;
+    GPIO_REG_GPFEN1(gpio_base_addr) = 0x0;
 
-    GPIO_REG_GPHEN0(GPIO_BASE) = 0x0;
-    GPIO_REG_GPHEN1(GPIO_BASE) = 0x0;
+    GPIO_REG_GPHEN0(gpio_base_addr) = 0x0;
+    GPIO_REG_GPHEN1(gpio_base_addr) = 0x0;
 
-    GPIO_REG_GPAREN0(GPIO_BASE) = 0x0;
-    GPIO_REG_GPAREN1(GPIO_BASE) = 0x0;
+    GPIO_REG_GPAREN0(gpio_base_addr) = 0x0;
+    GPIO_REG_GPAREN1(gpio_base_addr) = 0x0;
 
-    GPIO_REG_GPAFEN0(GPIO_BASE) = 0x0;
-    GPIO_REG_GPAFEN0(GPIO_BASE) = 0x0;
+    GPIO_REG_GPAFEN0(gpio_base_addr) = 0x0;
+    GPIO_REG_GPAFEN0(gpio_base_addr) = 0x0;
     
     rt_hw_interrupt_install(IRQ_GPIO0, gpio_irq_handler, &_g_gpio_irq_tbl[0], "gpio0_irq");
     rt_hw_interrupt_umask(IRQ_GPIO0);

bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c

@@ -103,8 +103,8 @@ rt_err_t sd_int(struct sdhci_pdata_t * pdat, rt_uint32_t mask)
     {
         write32(pdat->virt + EMMC_INTERRUPT, r);
         //qemu maybe can not use sdcard
-        //rt_kprintf("send cmd/data timeout wait for %x int: %x, status: %x\n",mask, r, read32(pdat->virt + EMMC_STATUS));
-        //return -RT_ETIMEOUT;
+        rt_kprintf("send cmd/data timeout wait for %x int: %x, status: %x\n",mask, r, read32(pdat->virt + EMMC_STATUS));
+        return -RT_ETIMEOUT;
     }
     else if (r & INT_ERROR_MASK)
     {
@@ -552,7 +552,6 @@ static rt_err_t reset_emmc(struct sdhci_pdata_t * pdat)
 
     // Clear control2
     write32(pdat->virt + EMMC_CONTROL2, 0);
-
     // Get the base clock rate
     mmc_base_clock = bcm271x_mbox_clock_get_rate(12);
     if(mmc_base_clock == 0)
@@ -590,7 +589,6 @@ int raspi_sdmmc_init(void)
     struct rt_mmcsd_host * host = RT_NULL;
     struct sdhci_pdata_t * pdat = RT_NULL;
     struct sdhci_t * sdhci = RT_NULL;
-
 #ifdef BSP_USING_SDIO0
     host = mmcsd_alloc_host();
     if (!host)
@@ -598,7 +596,6 @@ int raspi_sdmmc_init(void)
         rt_kprintf("alloc host failed");
         goto err;
     }
-
     sdhci = rt_malloc(sizeof(struct sdhci_t));
     if (!sdhci)
     {
@@ -607,18 +604,16 @@ int raspi_sdmmc_init(void)
     }
     rt_memset(sdhci, 0, sizeof(struct sdhci_t));
 
-    virt = MMC2_BASE_ADDR;
-
+    virt = mmc2_base_addr;
     pdat = (struct sdhci_pdata_t *)rt_malloc(sizeof(struct sdhci_pdata_t));
     RT_ASSERT(pdat != RT_NULL);
 
     pdat->virt = (rt_uint32_t)virt;
     reset_emmc(pdat);
-
     sdhci->name = "sd0";
     sdhci->voltages = VDD_33_34;
     sdhci->width = MMCSD_BUSWIDTH_4;
-    sdhci->clock = 250 * 1000 * 1000;
+    sdhci->clock = 1000 * 1000 * 1000;
     sdhci->removeable = RT_TRUE;
 
     sdhci->detect = sdhci_detect;
@@ -634,10 +629,9 @@ int raspi_sdmmc_init(void)
     host->max_seg_size = 2048;
     host->max_dma_segs = 10;
     host->max_blk_size = 512;
-    host->max_blk_count = 4096;
+    host->max_blk_count = 1;
 
     host->private_data = sdhci;
-
     write32((pdat->virt + EMMC_IRPT_EN),0xffffffff);
     write32((pdat->virt + EMMC_IRPT_MASK),0xffffffff);
 #ifdef RT_MMCSD_DBG

bsp/raspberry-pi/raspi4-32/driver/drv_spi.c

@@ -14,7 +14,7 @@
 #include "raspi4.h"
 #include "drv_spi.h"
 
-#ifdef RT_USING_SPI
+#ifdef BSP_USING_SPI
 
 #define RPI_CORE_CLK_HZ        (250000000)
 #define BSP_SPI_MAX_HZ         (30* 1000 *1000)

bsp/raspberry-pi/raspi4-32/driver/drv_uart.c

@@ -16,6 +16,12 @@
 #include "board.h"
 #include "drv_uart.h"
 #include "drv_gpio.h"
+#include <mmu.h>
+
+size_t uart0_addr = 0;
+size_t uart3_addr = 0;
+size_t uart4_addr = 0;
+size_t uart5_addr = 0;
 
 #ifdef RT_USING_UART0
 static struct rt_serial_device _serial0;
@@ -68,25 +74,25 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
         return RT_EOK;
     }
 
-    if(uart->hw_base == UART0_BASE)
+    if(uart->hw_base == uart0_addr)
     {
         prev_raspi_pin_mode(GPIO_PIN_14, ALT0);
         prev_raspi_pin_mode(GPIO_PIN_15, ALT0);
     }
 
-    if(uart->hw_base == UART3_BASE)
+    if(uart->hw_base == uart3_addr)
     {
         prev_raspi_pin_mode(GPIO_PIN_4, ALT4);
         prev_raspi_pin_mode(GPIO_PIN_5, ALT4);
     }
 
-    if(uart->hw_base == UART4_BASE)
+    if(uart->hw_base == uart4_addr)
     {
         prev_raspi_pin_mode(GPIO_PIN_8, ALT4);
         prev_raspi_pin_mode(GPIO_PIN_9, ALT4);
     }
 
-    if(uart->hw_base == UART5_BASE)
+    if(uart->hw_base == uart5_addr)
     {
         prev_raspi_pin_mode(GPIO_PIN_12, ALT4);
         prev_raspi_pin_mode(GPIO_PIN_13, ALT4);
@@ -108,7 +114,6 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg
 
     RT_ASSERT(serial != RT_NULL);
     uart = (struct hw_uart_device *)serial->parent.user_data;
-
     switch (cmd)
     {
     case RT_DEVICE_CTRL_CLR_INT:
@@ -143,7 +148,6 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg
 static int uart_putc(struct rt_serial_device *serial, char c)
 {
     struct hw_uart_device *uart;
-
     RT_ASSERT(serial != RT_NULL);
     uart = (struct hw_uart_device *)serial->parent.user_data;
     if(uart->hw_base == AUX_BASE)
@@ -208,7 +212,7 @@ static void rt_hw_uart_isr(int irqno, void *param)
     {   
         PACTL_CS &=  ~(IRQ_UART0);
         rt_hw_serial_isr(&_serial0, RT_SERIAL_EVENT_RX_IND);
-        PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE;
+        PL011_REG_ICR(uart0_addr) = PL011_INTERRUPT_RECEIVE;
     }
 #endif
 
@@ -217,7 +221,7 @@ static void rt_hw_uart_isr(int irqno, void *param)
     {
         PACTL_CS &=  ~(IRQ_UART3);
         rt_hw_serial_isr(&_serial3, RT_SERIAL_EVENT_RX_IND);
-        PL011_REG_ICR(UART3_BASE) = PL011_INTERRUPT_RECEIVE;
+        PL011_REG_ICR(uart3_addr) = PL011_INTERRUPT_RECEIVE;
     }
 #endif
 
@@ -226,7 +230,7 @@ static void rt_hw_uart_isr(int irqno, void *param)
     {
         PACTL_CS &=  ~(IRQ_UART4);
         rt_hw_serial_isr(&_serial4, RT_SERIAL_EVENT_RX_IND);
-        PL011_REG_ICR(UART4_BASE) = PL011_INTERRUPT_RECEIVE;
+        PL011_REG_ICR(uart4_addr) = PL011_INTERRUPT_RECEIVE;
     }
 #endif
 
@@ -235,7 +239,7 @@ static void rt_hw_uart_isr(int irqno, void *param)
     {
         PACTL_CS &=  ~(IRQ_UART5);
         rt_hw_serial_isr(&_serial5, RT_SERIAL_EVENT_RX_IND);
-        PL011_REG_ICR(UART5_BASE) = PL011_INTERRUPT_RECEIVE;
+        PL011_REG_ICR(uart5_addr) = PL011_INTERRUPT_RECEIVE;
     }
 #endif
 }
@@ -292,11 +296,16 @@ int rt_hw_uart_init(void)
     _serial0.ops    = &_uart_ops;
     _serial0.config = config;
 
+    uart0_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)UART0_BASE, 0x1000);
+    uart0->hw_base = uart0_addr;
+
+    
     /* register UART0 device */
     rt_hw_serial_register(&_serial0, "uart0",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart0);
     rt_hw_interrupt_install(uart0->irqno, rt_hw_uart_isr, &_serial0, "uart0");
+    
 #endif
 
 #ifdef RT_USING_UART1
@@ -305,6 +314,8 @@ int rt_hw_uart_init(void)
 
     _serial1.ops    = &_uart_ops;
     _serial1.config = config;
+    
+    uart1->hw_base = (size_t)rt_hw_kernel_phys_to_virt((void*)AUX_BASE, 0x1000);
 
     /* register UART1 device */
     rt_hw_serial_register(&_serial1, "uart1",
@@ -320,6 +331,9 @@ int rt_hw_uart_init(void)
     _serial3.ops    = &_uart_ops;
     _serial3.config = config;
 
+    uart3_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)UART3_BASE, 0x1000);
+    uart3->hw_base = uart3_addr;
+
     /* register UART3 device */
     rt_hw_serial_register(&_serial3, "uart3",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
@@ -334,6 +348,9 @@ int rt_hw_uart_init(void)
     _serial4.ops    = &_uart_ops;
     _serial4.config = config;
 
+    uart4_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)UART4_BASE, 0x1000);
+    uart4->hw_base = uart4_addr;
+
     /* register UART4 device */
     rt_hw_serial_register(&_serial4, "uart4",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
@@ -348,6 +365,9 @@ int rt_hw_uart_init(void)
     _serial5.ops    = &_uart_ops;
     _serial5.config = config;
 
+    uart5_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)UART5_BASE, 0x1000);
+    uart5->hw_base = uart5_addr;
+
     /* register UART5 device */
     rt_hw_serial_register(&_serial5, "uart5",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
@@ -356,3 +376,4 @@ int rt_hw_uart_init(void)
 #endif
     return 0;
 }
+

bsp/raspberry-pi/raspi4-32/driver/mbox.c

@@ -11,18 +11,20 @@
  */
 
 /* mailbox message buffer */
+#include <rthw.h>
 #include "mbox.h"
 #include "mmu.h"
 //volatile unsigned int  __attribute__((aligned(16))) mbox[36];
-volatile unsigned int *mbox = (volatile unsigned int *) MBOX_ADDR;
+
 #define BUS_ADDRESS(phys)	(((phys) & ~0xC0000000)  |  0xC0000000)
+volatile unsigned int *mbox;
 
 /**
  * Make a mailbox call. Returns 0 on failure, non-zero on success
  */
 int mbox_call(unsigned char ch, int mmu_enable)
 {
-    unsigned int r = (((MBOX_ADDR)&~0xF) | (ch&0xF));
+    unsigned int r = ((((rt_uint32_t)MBOX_ADDR)&~0xF) | (ch&0xF));
     if(mmu_enable)
         r = BUS_ADDRESS(r);
     /* wait until we can write to the mailbox */

bsp/raspberry-pi/raspi4-32/driver/mbox.h

@@ -40,12 +40,13 @@ extern volatile unsigned int* mbox;
 
 #define MMIO_BASE       0xFE000000
 #define VIDEOCORE_MBOX  (MMIO_BASE+0x0000B880)
-#define MBOX_READ       ((volatile unsigned int*)(VIDEOCORE_MBOX+0x0))
-#define MBOX_POLL       ((volatile unsigned int*)(VIDEOCORE_MBOX+0x10))
-#define MBOX_SENDER     ((volatile unsigned int*)(VIDEOCORE_MBOX+0x14))
-#define MBOX_STATUS     ((volatile unsigned int*)(VIDEOCORE_MBOX+0x18))
-#define MBOX_CONFIG     ((volatile unsigned int*)(VIDEOCORE_MBOX+0x1C))
-#define MBOX_WRITE      ((volatile unsigned int*)(VIDEOCORE_MBOX+0x20))
+extern uint32_t videocore_mbox;
+#define MBOX_READ       ((volatile unsigned int*)(videocore_mbox+0x0))
+#define MBOX_POLL       ((volatile unsigned int*)(videocore_mbox+0x10))
+#define MBOX_SENDER     ((volatile unsigned int*)(videocore_mbox+0x14))
+#define MBOX_STATUS     ((volatile unsigned int*)(videocore_mbox+0x18))
+#define MBOX_CONFIG     ((volatile unsigned int*)(videocore_mbox+0x1C))
+#define MBOX_WRITE      ((volatile unsigned int*)(videocore_mbox+0x20))
 #define MBOX_RESPONSE   0x80000000
 #define MBOX_FULL       0x80000000
 #define MBOX_EMPTY      0x40000000
@@ -133,6 +134,8 @@ enum {
 #define MBOX_TAG_NOTIFY_XHCI_RESET     0x00030058
 
 #define MBOX_ADDR 0x08000000
+extern uint32_t mbox_addr;
+
 
 int mbox_call(unsigned char ch, int mmu_enable);
 int bcm271x_notify_reboot(void);

bsp/raspberry-pi/raspi4-32/driver/raspi4.h

@@ -14,6 +14,8 @@
 //gpio offset
 #define GPIO_BASE_OFFSET            (0x00200000)
 
+
+#define PL011_UART_BASE_OFFSET      (0x00201000)
 //pl011 offset
 #define PL011_UART0_BASE_OFFSET     (0x00201000)
 #define PL011_UART2_BASE_OFFSET     (0x00201400)
@@ -28,7 +30,9 @@
 #define AUX_BASE_OFFSET             (0x00215000)
 
 /* GPIO */
-#define GPIO_BASE                   (PER_BASE + GPIO_BASE_OFFSET)
+#define GPIO_BASE_ADDR              (PER_BASE + GPIO_BASE_OFFSET)
+extern uint32_t gpio_base_addr;
+#define GPIO_BASE                   (gpio_base_addr)
 #define GPIO_IRQ_NUM                (3)   //40 pin mode
 #define IRQ_GPIO0                   (96 + 49) //bank0 (0 to 27)
 #define IRQ_GPIO1                   (96 + 50) //bank1 (28 to 45)
@@ -37,44 +41,41 @@
 
 /* Timer (ARM side) */
 #define ARM_TIMER_IRQ       (64)
+extern uint32_t arm_timer_base;
 #define ARM_TIMER_BASE      (PER_BASE + 0xB000)
-#define ARM_TIMER_LOAD      HWREG32(ARM_TIMER_BASE + 0x400)
-#define ARM_TIMER_VALUE     HWREG32(ARM_TIMER_BASE + 0x404)
-#define ARM_TIMER_CTRL      HWREG32(ARM_TIMER_BASE + 0x408)
-#define ARM_TIMER_IRQCLR    HWREG32(ARM_TIMER_BASE + 0x40C)
-#define ARM_TIMER_RAWIRQ    HWREG32(ARM_TIMER_BASE + 0x410)
-#define ARM_TIMER_MASKIRQ   HWREG32(ARM_TIMER_BASE + 0x414)
-#define ARM_TIMER_RELOAD    HWREG32(ARM_TIMER_BASE + 0x418)
-#define ARM_TIMER_PREDIV    HWREG32(ARM_TIMER_BASE + 0x41C)
-#define ARM_TIMER_CNTR      HWREG32(ARM_TIMER_BASE + 0x420)
+#define ARM_TIMER_LOAD      HWREG32(arm_timer_base + 0x400)
+#define ARM_TIMER_VALUE     HWREG32(arm_timer_base + 0x404)
+#define ARM_TIMER_CTRL      HWREG32(arm_timer_base + 0x408)
+#define ARM_TIMER_IRQCLR    HWREG32(arm_timer_base + 0x40C)
+#define ARM_TIMER_RAWIRQ    HWREG32(arm_timer_base + 0x410)
+#define ARM_TIMER_MASKIRQ   HWREG32(arm_timer_base + 0x414)
+#define ARM_TIMER_RELOAD    HWREG32(arm_timer_base + 0x418)
+#define ARM_TIMER_PREDIV    HWREG32(arm_timer_base + 0x41C)
+#define ARM_TIMER_CNTR      HWREG32(arm_timer_base + 0x420)
 
 /* UART PL011 */
-#define UART0_BASE                  (PER_BASE + PL011_UART0_BASE_OFFSET)
-#define UART2_BASE                  (PER_BASE + PL011_UART2_BASE_OFFSET)
-#define UART3_BASE                  (PER_BASE + PL011_UART3_BASE_OFFSET)
-#define UART4_BASE                  (PER_BASE + PL011_UART4_BASE_OFFSET)
-#define UART5_BASE                  (PER_BASE + PL011_UART5_BASE_OFFSET)
+#define UART_BASE                   (PER_BASE + PL011_UART_BASE_OFFSET)
+//extern uint32_t uart_base_addr;
+#define UART0_BASE                  (UART_BASE + 0x0)
+#define UART2_BASE                  (UART_BASE + 0x400)
+#define UART3_BASE                  (UART_BASE + 0x600)
+#define UART4_BASE                  (UART_BASE + 0x800)
+#define UART5_BASE                  (UART_BASE + 0xA00)
 #define IRQ_AUX_UART                (96 + 29)
 #define UART_REFERENCE_CLOCK        (48000000)
 
 /* AUX */
+//#define AUX_BASE_ADDR               (PER_BASE + AUX_BASE_OFFSET)
+//extern uint32_t aux_addr;
+//#define AUX_BASE                    (aux_addr + 0x0)
+
 #define AUX_BASE                    (PER_BASE + AUX_BASE_OFFSET)
 #define IRQ_PL011                   (96 + 57)
 
-/* SPI */
-#define SPI_0_BASE_OFFSET     (0x00204000)
-#define SPI_3_BASE_OFFSET     (0x00204600)
-#define SPI_4_BASE_OFFSET     (0x00204800)
-#define SPI_5_BASE_OFFSET     (0x00204A00)
-#define SPI_6_BASE_OFFSET     (0x00204C00)
-
-#define SPI_0_BASE            (PER_BASE + SPI_0_BASE_OFFSET)
-#define SPI_3_BASE            (PER_BASE + SPI_3_BASE_OFFSET)
-#define SPI_4_BASE            (PER_BASE + SPI_4_BASE_OFFSET)
-#define SPI_5_BASE            (PER_BASE + SPI_5_BASE_OFFSET)
-#define SPI_6_BASE            (PER_BASE + SPI_6_BASE_OFFSET)
 /* Peripheral IRQ OR-ing */
-#define PACTL_CS                    HWREG32((PER_BASE + PACTL_CS_OFFSET))
+#define PACTL_CS_ADDR               (PER_BASE + PACTL_CS_OFFSET)
+extern uint32_t     pactl_cs_base;
+#define PACTL_CS                    HWREG32(pactl_cs_base)
 typedef enum {
     IRQ_SPI0 = 0x00000000,
     IRQ_SPI1 = 0x00000002,
@@ -107,10 +108,12 @@ typedef enum {
 #define INTC_BASE                   (0xff800000)
 #define ARM_GIC_NR_IRQS             (512)
 #define ARM_GIC_MAX_NR              (512)
-#define GIC_V2_DISTRIBUTOR_BASE     (INTC_BASE + 0x00041000)
-#define GIC_V2_CPU_INTERFACE_BASE   (INTC_BASE + 0x00042000)
-#define GIC_V2_HYPERVISOR_BASE      (INTC_BASE + 0x00044000)
-#define GIC_V2_VIRTUAL_CPU_BASE     (INTC_BASE + 0x00046000)
+#define GIC_V2_BASE                 (INTC_BASE + 0x00040000)
+extern uint32_t gic_base_addr;
+#define GIC_V2_DISTRIBUTOR_BASE     (gic_base_addr + 0x1000)
+#define GIC_V2_CPU_INTERFACE_BASE   (gic_base_addr + 0x2000)
+#define GIC_V2_HYPERVISOR_BASE      (gic_base_addr + 0x4000)
+#define GIC_V2_VIRTUAL_CPU_BASE     (gic_base_addr + 0x6000)
 
 #define GIC_PL400_DISTRIBUTOR_PPTR  GIC_V2_DISTRIBUTOR_BASE
 #define GIC_PL400_CONTROLLER_PPTR   GIC_V2_CPU_INTERFACE_BASE
@@ -119,10 +122,13 @@ typedef enum {
 
 #define GIC_ACK_INTID_MASK  0x000003ff
 
+
 //watchdog
-#define PM_RSTC         HWREG32(PER_BASE + 0x0010001c)
-#define PM_RSTS         HWREG32(PER_BASE + 0x00100020)
-#define PM_WDOG         HWREG32(PER_BASE + 0x00100024)
+#define WDT_BASE        (PER_BASE + 0x00100000)
+extern uint32_t         wdt_base_addr;
+#define PM_RSTC         HWREG32(wdt_base_addr + 0x1c)
+#define PM_RSTS         HWREG32(wdt_base_addr + 0x20)
+#define PM_WDOG         HWREG32(wdt_base_addr + 0x24)
 
 #define PM_PASSWORD                 (0x5A000000)
 #define PM_WDOG_TIME_SET            (0x000fffff)
@@ -134,13 +140,14 @@ typedef enum {
 //timer
 #define ST_BASE_OFFSET     (0x003000)
 #define STIMER_BASE  (PER_BASE  + ST_BASE_OFFSET)
-#define STIMER_CS    __REG32(STIMER_BASE + 0x0000)
-#define STIMER_CLO   __REG32(STIMER_BASE + 0x0004)
-#define STIMER_CHI   __REG32(STIMER_BASE + 0x0008)
-#define STIMER_C0    __REG32(STIMER_BASE + 0x000C)
-#define STIMER_C1    __REG32(STIMER_BASE + 0x0010)
-#define STIMER_C2    __REG32(STIMER_BASE + 0x0014)
-#define STIMER_C3    __REG32(STIMER_BASE + 0x0018)
+extern uint32_t stimer_base_addr;
+#define STIMER_CS    __REG32(stimer_base_addr + 0x0000)
+#define STIMER_CLO   __REG32(stimer_base_addr + 0x0004)
+#define STIMER_CHI   __REG32(stimer_base_addr + 0x0008)
+#define STIMER_C0    __REG32(stimer_base_addr + 0x000C)
+#define STIMER_C1    __REG32(stimer_base_addr + 0x0010)
+#define STIMER_C2    __REG32(stimer_base_addr + 0x0014)
+#define STIMER_C3    __REG32(stimer_base_addr + 0x0018)
 
 #define DELAY_MICROS(micros) \
     do{ \
@@ -149,8 +156,20 @@ typedef enum {
     } while (0) \
 
 //External Mass Media Controller (SD Card)
-#define MMC0_BASE_ADDR		(PER_BASE+0x300000)   
-#define MMC2_BASE_ADDR		(PER_BASE+0x340000)  
+#define MMC0_BASE_ADDR    (PER_BASE+0x300000)
+extern uint32_t mmc0_base_addr; 
+#define MMC2_BASE_ADDR    (PER_BASE+0x340000)
+extern uint32_t mmc2_base_addr;
+
+//mac
+#define MAC_REG                 (void *)(0xfd580000)
+extern void *                   mac_reg_base_addr;
+
+#define SEND_DATA_NO_CACHE      (0x08200000)
+extern void *                   eth_send_no_cache;
+
+#define RECV_DATA_NO_CACHE      (0x08400000)
+extern void *                   eth_recv_no_cache;
 
 /* the basic constants and interfaces needed by gic */
 rt_inline rt_uint32_t platform_get_gic_dist_base(void)
@@ -167,5 +186,5 @@ static inline  void __DSB(void)
 {
     __asm__ volatile ("dsb 0xF":::"memory");
 }
-
 #endif
+

bsp/raspberry-pi/raspi4-32/link.lds

@@ -24,7 +24,7 @@
 
 SECTIONS
 {
-    . = 0x8000;
+    . = 0xc0000000;
     . = ALIGN(4096);
     .text :
     {
@@ -63,6 +63,12 @@ SECTIONS
         _etext = .;
     }
 
+    .ARM.exidx : {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    }
+
     .eh_frame_hdr :
     {
          *(.eh_frame_hdr)

bsp/raspberry-pi/raspi4-32/rtconfig.h

@@ -7,6 +7,7 @@
 /* RT-Thread Kernel */
 
 #define RT_NAME_MAX 8
+#define RT_USING_SMART
 #define RT_ALIGN_SIZE 4
 #define RT_THREAD_PRIORITY_32
 #define RT_THREAD_PRIORITY_MAX 32
@@ -15,11 +16,12 @@
 #define RT_USING_HOOK
 #define RT_USING_IDLE_HOOK
 #define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 2048
+#define IDLE_THREAD_STACK_SIZE 4096
 #define RT_USING_TIMER_SOFT
 #define RT_TIMER_THREAD_PRIO 4
-#define RT_TIMER_THREAD_STACK_SIZE 2048
+#define RT_TIMER_THREAD_STACK_SIZE 512
 #define RT_DEBUG
+#define RT_DEBUG_COLOR
 
 /* Inter-Thread communication */
 
@@ -32,17 +34,27 @@
 /* Memory Management */
 
 #define RT_USING_MEMPOOL
+#define RT_USING_MEMHEAP
 #define RT_USING_SMALL_MEM
 #define RT_USING_HEAP
 
 /* Kernel Device Object */
 
 #define RT_USING_DEVICE
+#define RT_USING_INTERRUPT_INFO
 #define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLEBUF_SIZE 512
 #define RT_CONSOLE_DEVICE_NAME "uart0"
 #define RT_VER_NUM 0x40003
+#define ARCH_ARM
+#define ARCH_ARM_MMU
+#define RT_USING_USERSPACE
+#define KERNEL_VADDR_START 0xc0000000
+#define PV_OFFSET 0x40100000
+#define RT_IOREMAP_LATE
+#define ARCH_ARM_CORTEX_A
 #define ARCH_ARMV8
+#define RT_USING_CACHE
 
 /* RT-Thread Components */
 
@@ -67,14 +79,15 @@
 #define FINSH_CMD_SIZE 80
 #define FINSH_USING_MSH
 #define FINSH_USING_MSH_DEFAULT
+#define FINSH_USING_MSH_ONLY
 #define FINSH_ARG_MAX 10
 
 /* Device virtual file system */
 
 #define RT_USING_DFS
 #define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 2
-#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
 #define DFS_FD_MAX 16
 #define RT_USING_DFS_ELMFAT
 
@@ -89,15 +102,24 @@
 #define RT_DFS_ELM_MAX_SECTOR_SIZE 512
 #define RT_DFS_ELM_REENTRANT
 #define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_ROMFS
 
 /* Device Drivers */
 
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
 #define RT_USING_SERIAL
-#define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_HWTIMER
+#define RT_USING_I2C
+#define RT_USING_I2C_BITOPS
 #define RT_USING_PIN
+#define RT_USING_PWM
+#define RT_USING_RTC
+#define RT_USING_SOFT_RTC
 #define RT_USING_SDIO
 #define RT_SDIO_STACK_SIZE 512
 #define RT_SDIO_THREAD_PRIORITY 15
@@ -113,12 +135,22 @@
 /* POSIX layer and C standard library */
 
 #define RT_USING_LIBC
+#define RT_USING_MUSL
 #define RT_USING_POSIX
+#define RT_USING_POSIX_MMAP
+#define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_AIO
 
 /* Network */
 
 /* Socket abstraction layer */
 
+#define RT_USING_SAL
+
+/* protocol stack implement */
+
+#define SAL_USING_LWIP
+#define SAL_USING_POSIX
 
 /* Network interface device */
 
@@ -144,8 +176,8 @@
 
 /* Static IPv4 Address */
 
-#define RT_LWIP_IPADDR "192.168.1.30"
-#define RT_LWIP_GWADDR "192.168.1.1"
+#define RT_LWIP_IPADDR "192.168.137.100"
+#define RT_LWIP_GWADDR "192.168.137.1"
 #define RT_LWIP_MSKADDR "255.255.255.0"
 #define RT_LWIP_UDP
 #define RT_LWIP_TCP
@@ -160,9 +192,9 @@
 #define RT_LWIP_TCP_WND 8196
 #define RT_LWIP_TCPTHREAD_PRIORITY 10
 #define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
-#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
 #define RT_LWIP_ETHTHREAD_PRIORITY 12
-#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
+#define RT_LWIP_ETHTHREAD_STACKSIZE 4096
 #define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
 #define LWIP_NETIF_STATUS_CALLBACK 1
 #define LWIP_NETIF_LINK_CALLBACK 1
@@ -182,6 +214,11 @@
 
 /* Utilities */
 
+#define RT_USING_LWP
+#define RT_LWP_MAX_NR 30
+#define RT_CH_MSG_MAX_NR 1024
+#define RT_LWP_SHM_MAX_NR 64
+#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
 
 /* RT-Thread online packages */
 
@@ -241,9 +278,6 @@
 #define BSP_USING_GIC
 #define BSP_USING_GIC400
 #define BSP_USING_PIN
-#define BSP_USING_SPI
-#define BSP_USING_SPI0_BUS
-#define BSP_USING_SPI0_DEVICE0
 #define BSP_USING_CORETIMER
 #define BSP_USING_WDT
 #define BSP_USING_SDIO
@@ -252,6 +286,5 @@
 /* Board Peripheral Drivers */
 
 #define BSP_USING_HDMI
-#define BSP_USING_HDMI_DISPLAY
 
 #endif

bsp/raspberry-pi/raspi4-32/rtconfig.py

@@ -14,7 +14,7 @@ if os.getenv('RTT_CC'):
     CROSS_TOOL = os.getenv('RTT_CC')
 
 PLATFORM    = 'gcc'
-EXEC_PATH   = r'/usr/bin'  
+EXEC_PATH   = r'/opt/gcc-arm-none-eabi-5_4-2016q3/bin/'
 
 BUILD = 'debug'
 
@@ -24,7 +24,7 @@ if os.getenv('RTT_EXEC_PATH'):
 if PLATFORM == 'gcc':
     # toolchains
     # PREFIX = 'arm-none-eabi-'
-    PREFIX = 'arm-none-eabi-'
+    PREFIX  = os.getenv('RTT_CC_PREFIX') or 'arm-none-eabi-'
     CC      = PREFIX + 'gcc'
     CXX     = PREFIX + 'g++'
     AS      = PREFIX + 'gcc'
@@ -35,20 +35,22 @@ if PLATFORM == 'gcc':
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY  = PREFIX + 'objcopy'
 
-    DEVICE = ' -march=armv8-a -mtune=cortex-a72'
-    CFLAGS = DEVICE + ' -Wall'
+    DEVICE = ' -march=armv8-a -mtune=cortex-a72 -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing'
+    CXXFLAGS= DEVICE + ' -Wall'
+    CFLAGS = DEVICE + ' -Wall  -std=gnu99'
     AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
-    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds ' + ' -lsupc++ -lgcc '
     CPATH   = ''
     LPATH   = ''
 
     if BUILD == 'debug':
-        CFLAGS += ' -O0 -gdwarf-2'
-        AFLAGS += ' -gdwarf-2'
+        CFLAGS   += ' -O0 -gdwarf-2'
+        CXXFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS   += ' -gdwarf-2'
     else:
-        CFLAGS += ' -O2'
-
-    CXXFLAGS = CFLAGS
+        CFLAGS   += ' -Os'
+        CXXFLAGS += ' -Os'
+    CXXFLAGS += ' -Woverloaded-virtual -fno-exceptions -fno-rtti'
 
 DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
 POST_ACTION = OBJCPY + ' -O binary $TARGET kernel7.img\n' + SIZE + ' $TARGET \n'