git-svn-id: https://rt-thread.googlecode.com/svn/trunk@76 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/stm32_radio/board.c

@@ -1,110 +1,110 @@
-/*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-08-23     Bernard      first implementation
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "stm32f10x.h"
-#include "board.h"
-
-static void rt_hw_console_init(void);
-
-/**
- * @addtogroup STM32
- */
-
-/*@{*/
-
-/*******************************************************************************
- * Function Name  : RCC_Configuration
- * Description    : Configures the different system clocks.
- * Input          : None
- * Output         : None
- * Return         : None
- *******************************************************************************/
-void RCC_Configuration(void)
-{
-	ErrorStatus HSEStartUpStatus;
-
-	/* RCC system reset(for debug purpose) */
-	RCC_DeInit();
-
-	/* Enable HSE */
-	RCC_HSEConfig(RCC_HSE_ON);
-
-	/* Wait till HSE is ready */
-	HSEStartUpStatus = RCC_WaitForHSEStartUp();
-
-    if (HSEStartUpStatus == SUCCESS)
-	{
-		/* HCLK = SYSCLK */
-		RCC_HCLKConfig(RCC_SYSCLK_Div1);
-
-		/* PCLK2 = HCLK */
-		RCC_PCLK2Config(RCC_HCLK_Div1);
-		/* PCLK1 = HCLK/2 */
-		RCC_PCLK1Config(RCC_HCLK_Div2);
-
-		/* Flash 2 wait state */
-		FLASH_SetLatency(FLASH_Latency_2);
-		/* Enable Prefetch Buffer */
-		FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
-
-		/* PLLCLK = 8MHz * 9 = 72 MHz */
-		RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
-
-		/* Enable PLL */
-		RCC_PLLCmd(ENABLE);
-
-		/* Wait till PLL is ready */
-        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) ;
-
-		/* Select PLL as system clock source */
-		RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-		/* Wait till PLL is used as system clock source */
-        while (RCC_GetSYSCLKSource() != 0x08) ;
-	}
-}
-
-/*******************************************************************************
-* Function Name  : NVIC_Configuration
-* Description    : Configures Vector Table base location.
-* Input          : None
-* Output         : None
-* Return         : None
-*******************************************************************************/
-void NVIC_Configuration(void)
-{
-#ifdef  VECT_TAB_RAM
-	/* Set the Vector Table base location at 0x20000000 */
-	NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
-#else  /* VECT_TAB_FLASH  */
-	/* Set the Vector Table base location at 0x08000000 */
-	NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
-#endif
-}
-
-/*******************************************************************************
- * Function Name  : SysTick_Configuration
- * Description    : Configures the SysTick for OS tick.
- * Input          : None
- * Output         : None
- * Return         : None
- *******************************************************************************/
-void  SysTick_Configuration(void)
-{
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-08-23     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "stm32f10x.h"
+#include "board.h"
+
+static void rt_hw_console_init(void);
+
+/**
+ * @addtogroup STM32
+ */
+
+/*@{*/
+
+/*******************************************************************************
+ * Function Name  : RCC_Configuration
+ * Description    : Configures the different system clocks.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void RCC_Configuration(void)
+{
+    ErrorStatus HSEStartUpStatus;
+
+    /* RCC system reset(for debug purpose) */
+    RCC_DeInit();
+
+    /* Enable HSE */
+    RCC_HSEConfig(RCC_HSE_ON);
+
+    /* Wait till HSE is ready */
+    HSEStartUpStatus = RCC_WaitForHSEStartUp();
+
+    if (HSEStartUpStatus == SUCCESS)
+    {
+        /* HCLK = SYSCLK */
+        RCC_HCLKConfig(RCC_SYSCLK_Div1);
+
+        /* PCLK2 = HCLK */
+        RCC_PCLK2Config(RCC_HCLK_Div1);
+        /* PCLK1 = HCLK/2 */
+        RCC_PCLK1Config(RCC_HCLK_Div2);
+
+        /* Flash 2 wait state */
+        FLASH_SetLatency(FLASH_Latency_2);
+        /* Enable Prefetch Buffer */
+        FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
+
+        /* PLLCLK = 8MHz * 9 = 72 MHz */
+        RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
+
+        /* Enable PLL */
+        RCC_PLLCmd(ENABLE);
+
+        /* Wait till PLL is ready */
+        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) ;
+
+        /* Select PLL as system clock source */
+        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+        /* Wait till PLL is used as system clock source */
+        while (RCC_GetSYSCLKSource() != 0x08) ;
+    }
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_Configuration
+* Description    : Configures Vector Table base location.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+#ifdef  VECT_TAB_RAM
+    /* Set the Vector Table base location at 0x20000000 */
+    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else  /* VECT_TAB_FLASH  */
+    /* Set the Vector Table base location at 0x08000000 */
+    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+}
+
+/*******************************************************************************
+ * Function Name  : SysTick_Configuration
+ * Description    : Configures the SysTick for OS tick.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SysTick_Configuration(void)
+{
     RCC_ClocksTypeDef  rcc_clocks;
     rt_uint32_t         cnts;
 
@@ -114,146 +114,147 @@ void  SysTick_Configuration(void)
 
     SysTick_Config(cnts);
     SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
-}
-
-extern void rt_hw_interrupt_thread_switch(void);
-/**
- * This is the timer interrupt service routine.
- *
- */
-void rt_hw_timer_handler(void)
-{
-	/* enter interrupt */
-	rt_interrupt_enter();
-
-	rt_tick_increase();
-
-	/* leave interrupt */
-	rt_interrupt_leave();
-}
-
-/* NAND Flash */
-#include "fsmc_nand.h"
-
-/**
- * This function will initial STM32 Radio board.
- */
-void rt_hw_board_init()
-{
-	NAND_IDTypeDef NAND_ID;
-
-	/* Configure the system clocks */
-	RCC_Configuration();
-
-	/* NVIC Configuration */
-	NVIC_Configuration();
-
-	/* Configure the SysTick */
-	SysTick_Configuration();
-
-	/* Console Initialization*/
-	rt_hw_console_init();
-
-    /* FSMC Initialization */
-    FSMC_NAND_Init();
-
-    /* NAND read ID command */
-    FSMC_NAND_ReadID(&NAND_ID);
-    rt_kprintf("Read the NAND ID:%02X%02X%02X%02X\n",NAND_ID.Maker_ID,NAND_ID.Device_ID,NAND_ID.Third_ID,NAND_ID.Fourth_ID);
-
-    /* SRAM init */
-    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
-	FSMC_SRAM_Init();
-
-	{
-		/* PC6 for SDCard Rst */
+}
+
+extern void rt_hw_interrupt_thread_switch(void);
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void rt_hw_timer_handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/* NAND Flash */
+#include "fsmc_nand.h"
+
+/**
+ * This function will initial STM32 Radio board.
+ */
+ extern void FSMC_SRAM_Init(void);
+void rt_hw_board_init()
+{
+    NAND_IDTypeDef NAND_ID;
+
+    /* Configure the system clocks */
+    RCC_Configuration();
+
+    /* NVIC Configuration */
+    NVIC_Configuration();
+
+    /* Configure the SysTick */
+    SysTick_Configuration();
+
+    /* Console Initialization*/
+    rt_hw_console_init();
+
+    /* FSMC Initialization */
+    FSMC_NAND_Init();
+
+    /* NAND read ID command */
+    FSMC_NAND_ReadID(&NAND_ID);
+    rt_kprintf("Read the NAND ID:%02X%02X%02X%02X\n",NAND_ID.Maker_ID,NAND_ID.Device_ID,NAND_ID.Third_ID,NAND_ID.Fourth_ID);
+
+    /* SRAM init */
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
+    FSMC_SRAM_Init();
+
+    {
+        /* PC6 for SDCard Rst */
         GPIO_InitTypeDef GPIO_InitStructure;
-
+
         GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
         GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
         GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
         GPIO_Init(GPIOC,&GPIO_InitStructure);
         GPIO_SetBits(GPIOC,GPIO_Pin_6);
-	}
-}
-
-/* init console to support rt_kprintf */
-static void rt_hw_console_init()
-{
-	/* Enable USART1 and GPIOA clocks */
-    RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1
-                           | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC
-                           | RCC_APB2Periph_GPIOF, ENABLE);
-
-	/* GPIO configuration */
-	{
-        GPIO_InitTypeDef GPIO_InitStructure;
-
-        /* Configure USART1 Tx (PA.09) as alternate function push-pull */
-        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
-        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-        GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-        /* Configure USART1 Rx (PA.10) as input floating */
-        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
-        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-        GPIO_Init(GPIOA, &GPIO_InitStructure);
-	}
-
-	/* USART configuration */
-	{
-        USART_InitTypeDef USART_InitStructure;
-
-        /* USART1 configured as follow:
-            - BaudRate = 115200 baud
-            - Word Length = 8 Bits
-            - One Stop Bit
-            - No parity
-            - Hardware flow control disabled (RTS and CTS signals)
-            - Receive and transmit enabled
-            - USART Clock disabled
-            - USART CPOL: Clock is active low
-            - USART CPHA: Data is captured on the middle
-            - USART LastBit: The clock pulse of the last data bit is not output to
-              the SCLK pin
-        */
-        USART_InitStructure.USART_BaudRate = 115200;
-        USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-        USART_InitStructure.USART_StopBits = USART_StopBits_1;
-        USART_InitStructure.USART_Parity = USART_Parity_No;
-        USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-        USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-        USART_Init(USART1, &USART_InitStructure);
-        /* Enable USART1 */
-        USART_Cmd(USART1, ENABLE);
-	}
-}
-
-/* write one character to serial, must not trigger interrupt */
-static void rt_hw_console_putc(const char c)
-{
-	/*
-		to be polite with serial console add a line feed
-		to the carriage return character
-	*/
-	if (c=='\n')rt_hw_console_putc('\r');
-
-	while (!(USART1->SR & USART_FLAG_TXE));
-	USART1->DR = (c & 0x1FF);
-}
-
-/**
- * This function is used by rt_kprintf to display a string on console.
- *
- * @param str the displayed string
- */
-void rt_hw_console_output(const char* str)
-{
-	while (*str)
-	{
-		rt_hw_console_putc (*str++);
-	}
-}
-
-/*@}*/
+    }
+}
+
+/* init console to support rt_kprintf */
+static void rt_hw_console_init()
+{
+    /* Enable USART1 and GPIOA clocks */
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1
+                           | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC
+                           | RCC_APB2Periph_GPIOF, ENABLE);
+
+    /* GPIO configuration */
+    {
+        GPIO_InitTypeDef GPIO_InitStructure;
+
+        /* Configure USART1 Tx (PA.09) as alternate function push-pull */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+        /* Configure USART1 Rx (PA.10) as input floating */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+        GPIO_Init(GPIOA, &GPIO_InitStructure);
+    }
+
+    /* USART configuration */
+    {
+        USART_InitTypeDef USART_InitStructure;
+
+        /* USART1 configured as follow:
+            - BaudRate = 115200 baud
+            - Word Length = 8 Bits
+            - One Stop Bit
+            - No parity
+            - Hardware flow control disabled (RTS and CTS signals)
+            - Receive and transmit enabled
+            - USART Clock disabled
+            - USART CPOL: Clock is active low
+            - USART CPHA: Data is captured on the middle
+            - USART LastBit: The clock pulse of the last data bit is not output to
+              the SCLK pin
+        */
+        USART_InitStructure.USART_BaudRate = 115200;
+        USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+        USART_InitStructure.USART_StopBits = USART_StopBits_1;
+        USART_InitStructure.USART_Parity = USART_Parity_No;
+        USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+        USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+        USART_Init(USART1, &USART_InitStructure);
+        /* Enable USART1 */
+        USART_Cmd(USART1, ENABLE);
+    }
+}
+
+/* write one character to serial, must not trigger interrupt */
+static void rt_hw_console_putc(const char c)
+{
+    /*
+    	to be polite with serial console add a line feed
+    	to the carriage return character
+    */
+    if (c=='\n')rt_hw_console_putc('\r');
+
+    while (!(USART1->SR & USART_FLAG_TXE));
+    USART1->DR = (c & 0x1FF);
+}
+
+/**
+ * This function is used by rt_kprintf to display a string on console.
+ *
+ * @param str the displayed string
+ */
+void rt_hw_console_output(const char* str)
+{
+    while (*str)
+    {
+        rt_hw_console_putc (*str++);
+    }
+}
+
+/*@}*/

bsp/stm32_radio/cortexm3_macro.s

@@ -1,279 +0,0 @@
-;******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
-;* File Name          : cortexm3_macro.s
-;* Author             : MCD Application Team
-;* Version            : V1.1
-;* Date               : 11/26/2007
-;* Description        : Instruction wrappers for special Cortex-M3 instructions.
-;*******************************************************************************
-; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
-    
-  THUMB
-  REQUIRE8
-  PRESERVE8
-    
-  AREA |.text|, CODE, READONLY, ALIGN=2
-
-  ; Exported functions
-  EXPORT __WFI
-  EXPORT __WFE
-  EXPORT __SEV
-  EXPORT __ISB
-  EXPORT __DSB
-  EXPORT __DMB
-  EXPORT __SVC
-  EXPORT __MRS_CONTROL
-  EXPORT __MSR_CONTROL
-  EXPORT __MRS_PSP
-  EXPORT __MSR_PSP
-  EXPORT __MRS_MSP
-  EXPORT __MSR_MSP   
-  EXPORT __SETPRIMASK
-  EXPORT __RESETPRIMASK
-  EXPORT __SETFAULTMASK
-  EXPORT __RESETFAULTMASK
-  EXPORT __BASEPRICONFIG
-  EXPORT __GetBASEPRI
-  EXPORT __REV_HalfWord
-  EXPORT __REV_Word
-
-;*******************************************************************************
-; Function Name  : __WFI
-; Description    : Assembler function for the WFI instruction.
-; Input          : None
-; Return         : None
-;*******************************************************************************
-__WFI 
- 
-    WFI
-    BX r14
-
-;*******************************************************************************
-; Function Name  : __WFE
-; Description    : Assembler function for the WFE instruction.
-; Input          : None
-; Return         : None
-;*******************************************************************************
-__WFE
-
-    WFE
-    BX r14
-
-;*******************************************************************************
-; Function Name  : __SEV
-; Description    : Assembler function for the SEV instruction.
-; Input          : None
-; Return         : None
-;*******************************************************************************
-__SEV
-
-    SEV
-    BX r14
-
-;*******************************************************************************
-; Function Name  : __ISB
-; Description    : Assembler function for the ISB instruction.
-; Input          : None
-; Return         : None
-;*******************************************************************************
-__ISB
-
-    ISB
-    BX r14
-
-;*******************************************************************************
-; Function Name  : __DSB
-; Description    : Assembler function for the DSB instruction.
-; Input          : None
-; Return         : None
-;*******************************************************************************
-__DSB
-
-    DSB
-    BX r14
-
-;*******************************************************************************
-; Function Name  : __DMB
-; Description    : Assembler function for the DMB instruction.
-; Input          : None
-; Return         : None
-;*******************************************************************************
-__DMB
-
-    DMB
-    BX r14
-
-;*******************************************************************************
-; Function Name  : __SVC
-; Description    : Assembler function for the SVC instruction.
-; Input          : None
-; Return         : None
-;*******************************************************************************
-__SVC
-
-    SVC 0x01
-    BX r14
-
-;*******************************************************************************
-; Function Name  : __MRS_CONTROL
-; Description    : Assembler function for the MRS instruction.
-; Input          : None
-; Return         : - r0 : Cortex-M3 CONTROL register value.
-;*******************************************************************************
-__MRS_CONTROL
-
-  MRS r0, CONTROL
-  BX r14
-
-;*******************************************************************************
-; Function Name  : __MSR_CONTROL
-; Description    : Assembler function for the MSR instruction.
-; Input          : - r0 : Cortex-M3 CONTROL register new value.  
-; Return         : None
-;*******************************************************************************
-__MSR_CONTROL
-
-  MSR CONTROL, r0
-  ISB
-  BX r14
-
-;*******************************************************************************
-; Function Name  : __MRS_PSP
-; Description    : Assembler function for the MRS instruction.
-; Input          : None
-; Return         : - r0 : Process Stack value.
-;*******************************************************************************
-__MRS_PSP
-
-  MRS r0, PSP
-  BX r14
-
-;*******************************************************************************
-; Function Name  : __MSR_PSP
-; Description    : Assembler function for the MSR instruction.
-; Input          : - r0 : Process Stack new value.  
-; Return         : None
-;*******************************************************************************
-__MSR_PSP 
- 
-    MSR PSP, r0 ; set Process Stack value
-    BX r14
-
-;*******************************************************************************
-; Function Name  : __MRS_MSP
-; Description    : Assembler function for the MRS instruction.
-; Input          : None
-; Return         : - r0 : Main Stack value.
-;*******************************************************************************
-__MRS_MSP
-
-  MRS r0, MSP
-  BX r14
-
-;*******************************************************************************
-; Function Name  : __MSR_MSP
-; Description    : Assembler function for the MSR instruction.
-; Input          : - r0 : Main Stack new value.  
-; Return         : None
-;*******************************************************************************
-__MSR_MSP 
- 
-    MSR MSP, r0 ; set Main Stack value
-    BX r14
-
-;*******************************************************************************
-; Function Name  : __SETPRIMASK
-; Description    : Assembler function to set the PRIMASK.
-; Input          : None 
-; Return         : None
-;*******************************************************************************
-__SETPRIMASK
-
-  CPSID i
-  BX r14
-
-;*******************************************************************************
-; Function Name  : __RESETPRIMASK
-; Description    : Assembler function to reset the PRIMASK.
-; Input          : None 
-; Return         : None
-;*******************************************************************************
-__RESETPRIMASK
-
-  CPSIE i
-  BX r14
-
-;*******************************************************************************
-; Function Name  : __SETFAULTMASK
-; Description    : Assembler function to set the FAULTMASK.
-; Input          : None 
-; Return         : None
-;*******************************************************************************
-__SETFAULTMASK
-
-  CPSID f
-  BX r14
-
-;*******************************************************************************
-; Function Name  : __RESETFAULTMASK
-; Description    : Assembler function to reset the FAULTMASK.
-; Input          : None 
-; Return         : None
-;*******************************************************************************
-__RESETFAULTMASK
-
-  CPSIE f
-  BX r14
-
-;*******************************************************************************
-; Function Name  : __BASEPRICONFIG
-; Description    : Assembler function to set the Base Priority.
-; Input          : - r0 : Base Priority new value  
-; Return         : None
-;*******************************************************************************
-__BASEPRICONFIG
-
-  MSR BASEPRI, r0
-  BX r14
-
-;*******************************************************************************
-; Function Name  : __GetBASEPRI
-; Description    : Assembler function to get the Base Priority value.
-; Input          : None 
-; Return         : - r0 : Base Priority value 
-;*******************************************************************************
-__GetBASEPRI
-
-  MRS r0, BASEPRI_MAX
-  BX r14
-
-;*******************************************************************************
-; Function Name  : __REV_HalfWord
-; Description    : Reverses the byte order in HalfWord(16-bit) input variable.
-; Input          : - r0 : specifies the input variable
-; Return         : - r0 : holds tve variable value after byte reversing.
-;*******************************************************************************
-__REV_HalfWord 
- 
-  REV16 r0, r0
-  BX r14
-
-;*******************************************************************************
-; Function Name  : __REV_Word
-; Description    : Reverses the byte order in Word(32-bit) input variable.
-; Input          : - r0 : specifies the input variable
-; Return         : - r0 : holds tve variable value after byte reversing.
-;*******************************************************************************
-__REV_Word 
- 
-  REV r0, r0
-  BX r14
-    
-  END
-  
-;******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE*****

bsp/stm32_radio/dm9000.c

@@ -31,14 +31,14 @@ enum DM9000_TYPE
 
 struct rt_dm9000_eth
 {
-	/* inherit from ethernet device */
-	struct eth_device parent;
+    /* inherit from ethernet device */
+    struct eth_device parent;
 
     enum DM9000_TYPE type;
     rt_uint8_t imr_all;
 
-	/* interface address info. */
-	rt_uint8_t  dev_addr[MAX_ADDR_LEN];			/* hw address	*/
+    /* interface address info. */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];			/* hw address	*/
 };
 static struct rt_dm9000_eth dm9000_device;
 static struct rt_semaphore sem_ack, sem_lock;
@@ -47,9 +47,9 @@ void rt_dm9000_isr(void);
 
 static void delay_ms(rt_uint32_t ms)
 {
-	rt_uint32_t len;
-	for (;ms > 0; ms --)
-		for (len = 0; len < 100; len++ );
+    rt_uint32_t len;
+    for (;ms > 0; ms --)
+        for (len = 0; len < 100; len++ );
 }
 
 /* Read a byte from I/O port */
@@ -69,76 +69,76 @@ rt_inline void dm9000_io_write(rt_uint16_t reg, rt_uint16_t value)
 /* Read a word from phyxcer */
 rt_inline rt_uint16_t phy_read(rt_uint16_t reg)
 {
-	rt_uint16_t val;
+    rt_uint16_t val;
 
-	/* Fill the phyxcer register into REG_0C */
-	dm9000_io_write(DM9000_EPAR, DM9000_PHY | reg);
-	dm9000_io_write(DM9000_EPCR, 0xc);	/* Issue phyxcer read command */
+    /* Fill the phyxcer register into REG_0C */
+    dm9000_io_write(DM9000_EPAR, DM9000_PHY | reg);
+    dm9000_io_write(DM9000_EPCR, 0xc);	/* Issue phyxcer read command */
 
-	delay_ms(100);		/* Wait read complete */
+    delay_ms(100);		/* Wait read complete */
 
-	dm9000_io_write(DM9000_EPCR, 0x0);	/* Clear phyxcer read command */
-	val = (dm9000_io_read(DM9000_EPDRH) << 8) | dm9000_io_read(DM9000_EPDRL);
+    dm9000_io_write(DM9000_EPCR, 0x0);	/* Clear phyxcer read command */
+    val = (dm9000_io_read(DM9000_EPDRH) << 8) | dm9000_io_read(DM9000_EPDRL);
 
-	return val;
+    return val;
 }
 
 /* Write a word to phyxcer */
 rt_inline void phy_write(rt_uint16_t reg, rt_uint16_t value)
 {
-	/* Fill the phyxcer register into REG_0C */
-	dm9000_io_write(DM9000_EPAR, DM9000_PHY | reg);
+    /* Fill the phyxcer register into REG_0C */
+    dm9000_io_write(DM9000_EPAR, DM9000_PHY | reg);
 
-	/* Fill the written data into REG_0D & REG_0E */
-	dm9000_io_write(DM9000_EPDRL, (value & 0xff));
-	dm9000_io_write(DM9000_EPDRH, ((value >> 8) & 0xff));
-	dm9000_io_write(DM9000_EPCR, 0xa);	/* Issue phyxcer write command */
+    /* Fill the written data into REG_0D & REG_0E */
+    dm9000_io_write(DM9000_EPDRL, (value & 0xff));
+    dm9000_io_write(DM9000_EPDRH, ((value >> 8) & 0xff));
+    dm9000_io_write(DM9000_EPCR, 0xa);	/* Issue phyxcer write command */
 
-	delay_ms(500);		/* Wait write complete */
+    delay_ms(500);		/* Wait write complete */
 
-	dm9000_io_write(DM9000_EPCR, 0x0);	/* Clear phyxcer write command */
+    dm9000_io_write(DM9000_EPCR, 0x0);	/* Clear phyxcer write command */
 }
 
 /* Set PHY operationg mode */
 rt_inline void phy_mode_set(rt_uint32_t media_mode)
 {
-	rt_uint16_t phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
-	if (!(media_mode & DM9000_AUTO))
-	{
-		switch (media_mode)
-		{
-		case DM9000_10MHD:
-			phy_reg4 = 0x21;
-			phy_reg0 = 0x0000;
-			break;
-		case DM9000_10MFD:
-			phy_reg4 = 0x41;
-			phy_reg0 = 0x1100;
-			break;
-		case DM9000_100MHD:
-			phy_reg4 = 0x81;
-			phy_reg0 = 0x2000;
-			break;
-		case DM9000_100MFD:
-			phy_reg4 = 0x101;
-			phy_reg0 = 0x3100;
-			break;
-		}
-		phy_write(4, phy_reg4);	/* Set PHY media mode */
-		phy_write(0, phy_reg0);	/*  Tmp */
-	}
-
-	dm9000_io_write(DM9000_GPCR, 0x01);	/* Let GPIO0 output */
-	dm9000_io_write(DM9000_GPR, 0x00);	/* Enable PHY */
+    rt_uint16_t phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
+    if (!(media_mode & DM9000_AUTO))
+    {
+        switch (media_mode)
+        {
+        case DM9000_10MHD:
+            phy_reg4 = 0x21;
+            phy_reg0 = 0x0000;
+            break;
+        case DM9000_10MFD:
+            phy_reg4 = 0x41;
+            phy_reg0 = 0x1100;
+            break;
+        case DM9000_100MHD:
+            phy_reg4 = 0x81;
+            phy_reg0 = 0x2000;
+            break;
+        case DM9000_100MFD:
+            phy_reg4 = 0x101;
+            phy_reg0 = 0x3100;
+            break;
+        }
+        phy_write(4, phy_reg4);	/* Set PHY media mode */
+        phy_write(0, phy_reg0);	/*  Tmp */
+    }
+
+    dm9000_io_write(DM9000_GPCR, 0x01);	/* Let GPIO0 output */
+    dm9000_io_write(DM9000_GPR, 0x00);	/* Enable PHY */
 }
 
 /* interrupt service routine */
 void rt_dm9000_isr()
 {
     rt_uint32_t int_status;
-	rt_uint32_t last_io;
+    rt_uint32_t last_io;
 
-	last_io = DM9000_IO;
+    last_io = DM9000_IO;
 
     /* Disable all interrupts */
     dm9000_io_write(DM9000_IMR, IMR_PAR);
@@ -147,16 +147,16 @@ void rt_dm9000_isr()
     int_status = dm9000_io_read(DM9000_ISR);               /* Got ISR */
     dm9000_io_write(DM9000_ISR, int_status);    /* Clear ISR status */
 
-	/* receive overflow */
-	if (int_status & ISR_ROS)
-	{
-		rt_kprintf("overflow\n");
-	}
+    /* receive overflow */
+    if (int_status & ISR_ROS)
+    {
+        rt_kprintf("overflow\n");
+    }
 
-	if (int_status & ISR_ROOS)
-	{
-		rt_kprintf("overflow counter overflow\n");
-	}
+    if (int_status & ISR_ROOS)
+    {
+        rt_kprintf("overflow counter overflow\n");
+    }
 
     /* Received the coming packet */
     if (int_status & ISR_PRS)
@@ -165,7 +165,7 @@ void rt_dm9000_isr()
 
         /* a frame has been received */
         result = eth_device_ready(&(dm9000_device.parent));
-		if (result != RT_EOK) rt_kprintf("eth notification failed\n");
+        if (result != RT_EOK) rt_kprintf("eth notification failed\n");
         RT_ASSERT(result == RT_EOK);
     }
 
@@ -178,223 +178,225 @@ void rt_dm9000_isr()
         if (tx_status & (NSR_TX2END | NSR_TX1END))
         {
             /* One packet sent complete */
-			rt_sem_release(&sem_ack);
+            rt_sem_release(&sem_ack);
         }
     }
 
     /* Re-enable interrupt mask */
     dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
 
-	DM9000_IO = last_io;
+    DM9000_IO = last_io;
 }
 
 /* RT-Thread Device Interface */
 /* initialize the interface */
 static rt_err_t rt_dm9000_init(rt_device_t dev)
 {
-	int i, oft, lnk;
-	rt_uint32_t value;
+    int i, oft, lnk;
+    rt_uint32_t value;
 
-	/* RESET device */
-	dm9000_io_write(DM9000_NCR, NCR_RST);
-	delay_ms(100);		/* delay 1ms */
+    /* RESET device */
+    dm9000_io_write(DM9000_NCR, NCR_RST);
+    delay_ms(100);		/* delay 1ms */
 
     /* identfy DM9000 */
-	value  = dm9000_io_read(DM9000_VIDL);
-	value |= dm9000_io_read(DM9000_VIDH) << 8;
-	value |= dm9000_io_read(DM9000_PIDL) << 16;
-	value |= dm9000_io_read(DM9000_PIDH) << 24;
-	if (value == DM9000_ID)
-	{
-		rt_kprintf("dm9000 id: 0x%x\n", value);
+    value  = dm9000_io_read(DM9000_VIDL);
+    value |= dm9000_io_read(DM9000_VIDH) << 8;
+    value |= dm9000_io_read(DM9000_PIDL) << 16;
+    value |= dm9000_io_read(DM9000_PIDH) << 24;
+    if (value == DM9000_ID)
+    {
+        rt_kprintf("dm9000 id: 0x%x\n", value);
     }
     else
     {
         return -RT_ERROR;
     }
 
-	/* GPIO0 on pre-activate PHY */
-	dm9000_io_write(DM9000_GPR, 0x00);	            /* REG_1F bit0 activate phyxcer */
-	// dm9000_io_write(DM9000_GPCR, GPCR_GEP_CNTL);    /* Let GPIO0 output */
+    /* GPIO0 on pre-activate PHY */
+    dm9000_io_write(DM9000_GPR, 0x00);	            /* REG_1F bit0 activate phyxcer */
+    // dm9000_io_write(DM9000_GPCR, GPCR_GEP_CNTL);    /* Let GPIO0 output */
     // dm9000_io_write(DM9000_GPR, 0x00);                 /* Enable PHY */
 
-	/* Set PHY */
-	phy_mode_set(DM9000_AUTO);
-
-	/* Program operating register */
-	dm9000_io_write(DM9000_NCR, 0x0);	/* only intern phy supported by now */
-	dm9000_io_write(DM9000_TCR, 0);	    /* TX Polling clear */
-	dm9000_io_write(DM9000_BPTR, 0x3f);	/* Less 3Kb, 200us */
-	dm9000_io_write(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));	/* Flow Control : High/Low Water */
-	dm9000_io_write(DM9000_FCR, 0x0);	/* SH FIXME: This looks strange! Flow Control */
-	dm9000_io_write(DM9000_SMCR, 0);	/* Special Mode */
-	dm9000_io_write(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);	/* clear TX status */
-	dm9000_io_write(DM9000_ISR, 0x0f);	/* Clear interrupt status */
-	dm9000_io_write(DM9000_TCR2, 0x90);	/* Switch LED to mode 1 and one packet mode */
-
-	/* set mac address */
-	for (i = 0, oft = 0x10; i < 6; i++, oft++)
-		dm9000_io_write(oft, dm9000_device.dev_addr[i]);
-	/* set multicast address */
-	for (i = 0, oft = 0x16; i < 8; i++, oft++)
-		dm9000_io_write(oft, 0xff);
-
-	/* Activate DM9000 */
-	dm9000_io_write(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);	/* RX enable */
-	dm9000_io_write(DM9000_IMR, IMR_PAR);
-
-	i = 0;
-	while (!(phy_read(1) & 0x20))
-	{
+    /* Set PHY */
+    phy_mode_set(DM9000_AUTO);
+
+    /* Program operating register */
+    dm9000_io_write(DM9000_NCR, 0x0);	/* only intern phy supported by now */
+    dm9000_io_write(DM9000_TCR, 0);	    /* TX Polling clear */
+    dm9000_io_write(DM9000_BPTR, 0x3f);	/* Less 3Kb, 200us */
+    dm9000_io_write(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));	/* Flow Control : High/Low Water */
+    dm9000_io_write(DM9000_FCR, 0x0);	/* SH FIXME: This looks strange! Flow Control */
+    dm9000_io_write(DM9000_SMCR, 0);	/* Special Mode */
+    dm9000_io_write(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);	/* clear TX status */
+    dm9000_io_write(DM9000_ISR, 0x0f);	/* Clear interrupt status */
+    dm9000_io_write(DM9000_TCR2, 0x90);	/* Switch LED to mode 1 and one packet mode */
+
+    /* set mac address */
+    for (i = 0, oft = 0x10; i < 6; i++, oft++)
+        dm9000_io_write(oft, dm9000_device.dev_addr[i]);
+    /* set multicast address */
+    for (i = 0, oft = 0x16; i < 8; i++, oft++)
+        dm9000_io_write(oft, 0xff);
+
+    /* Activate DM9000 */
+    dm9000_io_write(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);	/* RX enable */
+    dm9000_io_write(DM9000_IMR, IMR_PAR);
+
+    i = 0;
+    while (!(phy_read(1) & 0x20))
+    {
         /* autonegation complete bit */
-		delay_ms(100);
-		i++;
-		if (i == 100000)
-		{
-			rt_kprintf("could not establish link\n");
-			return 0;
-		}
-	}
-
-	/* see what we've got */
-	lnk = phy_read(17) >> 12;
-	rt_kprintf("operating at ");
-	switch (lnk) {
-	case 1:
-		rt_kprintf("10M half duplex ");
-		break;
-	case 2:
-		rt_kprintf("10M full duplex ");
-		break;
-	case 4:
-		rt_kprintf("100M half duplex ");
-		break;
-	case 8:
-		rt_kprintf("100M full duplex ");
-		break;
-	default:
-		rt_kprintf("unknown: %d ", lnk);
-		break;
-	}
-	rt_kprintf("mode\n");
-
-	dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);	/* Enable TX/RX interrupt mask */
+        delay_ms(100);
+        i++;
+        if (i == 100000)
+        {
+            rt_kprintf("could not establish link\n");
+            return 0;
+        }
+    }
+
+    /* see what we've got */
+    lnk = phy_read(17) >> 12;
+    rt_kprintf("operating at ");
+    switch (lnk)
+    {
+    case 1:
+        rt_kprintf("10M half duplex ");
+        break;
+    case 2:
+        rt_kprintf("10M full duplex ");
+        break;
+    case 4:
+        rt_kprintf("100M half duplex ");
+        break;
+    case 8:
+        rt_kprintf("100M full duplex ");
+        break;
+    default:
+        rt_kprintf("unknown: %d ", lnk);
+        break;
+    }
+    rt_kprintf("mode\n");
+
+    dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);	/* Enable TX/RX interrupt mask */
 
     return RT_EOK;
 }
 
 static rt_err_t rt_dm9000_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_dm9000_close(rt_device_t dev)
 {
-	/* RESET devie */
-	phy_write(0, 0x8000);	/* PHY RESET */
-	dm9000_io_write(DM9000_GPR, 0x01);	/* Power-Down PHY */
-	dm9000_io_write(DM9000_IMR, 0x80);	/* Disable all interrupt */
-	dm9000_io_write(DM9000_RCR, 0x00);	/* Disable RX */
+    /* RESET devie */
+    phy_write(0, 0x8000);	/* PHY RESET */
+    dm9000_io_write(DM9000_GPR, 0x01);	/* Power-Down PHY */
+    dm9000_io_write(DM9000_IMR, 0x80);	/* Disable all interrupt */
+    dm9000_io_write(DM9000_RCR, 0x00);	/* Disable RX */
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_dm9000_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_size_t rt_dm9000_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_err_t rt_dm9000_control(rt_device_t dev, rt_uint8_t cmd, void *args)
 {
-	switch(cmd)
-	{
-	case NIOCTL_GADDR:
-		/* get mac address */
-		if(args) rt_memcpy(args, dm9000_device.dev_addr, 6);
-		else return -RT_ERROR;
-		break;
-
-	default :
-		break;
-	}
-
-	return RT_EOK;
+    switch (cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if (args) rt_memcpy(args, dm9000_device.dev_addr, 6);
+        else return -RT_ERROR;
+        break;
+
+    default :
+        break;
+    }
+
+    return RT_EOK;
 }
 
 /* ethernet device interface */
 /* transmit packet. */
 rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
 {
-	struct pbuf* q;
-	rt_int32_t len;
-	rt_uint16_t* ptr;
+    struct pbuf* q;
+    rt_int32_t len;
+    rt_uint16_t* ptr;
 
-	/* lock DM9000 device */
-	rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+    /* lock DM9000 device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
 
     /* Move data to DM9000 TX RAM */
-	DM9000_outb(DM9000_IO_BASE, DM9000_MWCMD);
+    DM9000_outb(DM9000_IO_BASE, DM9000_MWCMD);
 
-	for (q = p; q != NULL; q = q->next)
-	{
-		len = q->len;
-		ptr = q->payload;
+    for (q = p; q != NULL; q = q->next)
+    {
+        len = q->len;
+        ptr = q->payload;
 
         /* use 16bit mode to write data to DM9000 RAM */
         while (len > 0)
         {
-			DM9000_outw(DM9000_DATA_BASE, *ptr);
-            ptr ++; len -= 2;
+            DM9000_outw(DM9000_DATA_BASE, *ptr);
+            ptr ++;
+            len -= 2;
         }
-	}
+    }
 
     /* Set TX length to DM9000 */
     dm9000_io_write(DM9000_TXPLL, p->tot_len & 0xff);
     dm9000_io_write(DM9000_TXPLH, (p->tot_len >> 8) & 0xff);
 
-	/* Issue TX polling command */
-	dm9000_io_write(DM9000_TCR, TCR_TXREQ);	/* Cleared after TX complete */
+    /* Issue TX polling command */
+    dm9000_io_write(DM9000_TCR, TCR_TXREQ);	/* Cleared after TX complete */
 
-	/* unlock DM9000 device */
-	rt_sem_release(&sem_lock);
+    /* unlock DM9000 device */
+    rt_sem_release(&sem_lock);
 
-	rt_sem_take(&sem_ack, RT_WAITING_FOREVER);
+    rt_sem_take(&sem_ack, RT_WAITING_FOREVER);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /* reception packet. */
 struct pbuf *rt_dm9000_rx(rt_device_t dev)
 {
     struct pbuf* p;
-	rt_uint32_t rxbyte;
+    rt_uint32_t rxbyte;
 
     /* init p pointer */
     p = RT_NULL;
 
-	/* lock DM9000 device */
-	rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+    /* lock DM9000 device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
 
-	/* Check packet ready or not */
-	dm9000_io_read(DM9000_MRCMDX);	    /* Dummy read */
-	rxbyte = DM9000_inb(DM9000_DATA_BASE);		/* Got most updated data */
-	if (rxbyte)
+    /* Check packet ready or not */
+    dm9000_io_read(DM9000_MRCMDX);	    /* Dummy read */
+    rxbyte = DM9000_inb(DM9000_DATA_BASE);		/* Got most updated data */
+    if (rxbyte)
     {
         rt_uint16_t rx_status, rx_len;
         rt_uint16_t* data;
 
-		if (rxbyte > 1)
-		{
-		dm9000_io_write(DM9000_RCR, 0x00);	/* Stop Device */
-		dm9000_io_write(DM9000_ISR, 0x80);	/* Stop INT request */
-		}
+        if (rxbyte > 1)
+        {
+            dm9000_io_write(DM9000_RCR, 0x00);	/* Stop Device */
+            dm9000_io_write(DM9000_ISR, 0x80);	/* Stop INT request */
+        }
 
         /* A packet ready now  & Get status/length */
         DM9000_outb(DM9000_IO_BASE, DM9000_MRCMD);
@@ -407,7 +409,7 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
         if (p != RT_NULL)
         {
             struct pbuf* q;
-			rt_int32_t len;
+            rt_int32_t len;
 
             for (q = p; q != RT_NULL; q= q->next)
             {
@@ -417,7 +419,8 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
                 while (len > 0)
                 {
                     *data = DM9000_inw(DM9000_DATA_BASE);
-                    data ++; len -= 2;
+                    data ++;
+                    len -= 2;
                 }
             }
         }
@@ -435,13 +438,14 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
         }
 
         if ((rx_status & 0xbf00) || (rx_len < 0x40)
-            || (rx_len > DM9000_PKT_MAX))
+                || (rx_len > DM9000_PKT_MAX))
         {
             if (rx_status & 0x100)
             {
                 rt_kprintf("rx fifo error\n");
             }
-            if (rx_status & 0x200) {
+            if (rx_status & 0x200)
+            {
                 rt_kprintf("rx crc error\n");
             }
             if (rx_status & 0x8000)
@@ -452,9 +456,9 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
             {
                 rt_kprintf("rx length too big\n");
 
-				/* RESET device */
-				dm9000_io_write(DM9000_NCR, NCR_RST);
-				rt_thread_delay(1); /* delay 5ms */
+                /* RESET device */
+                dm9000_io_write(DM9000_NCR, NCR_RST);
+                rt_thread_delay(1); /* delay 5ms */
             }
 
             /* it issues an error, release pbuf */
@@ -468,8 +472,8 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
         dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
     }
 
-	/* unlock DM9000 device */
-	rt_sem_release(&sem_lock);
+    /* unlock DM9000 device */
+    rt_sem_release(&sem_lock);
 
     return p;
 }
@@ -489,7 +493,7 @@ static void NVIC_Configuration(void)
     NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
 
     /* Enable the EXTI0 Interrupt */
-    NVIC_InitStructure.NVIC_IRQChannel = EXTI15_10_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn;
     NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
     NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
     NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
@@ -498,7 +502,7 @@ static void NVIC_Configuration(void)
 
 static void GPIO_Configuration()
 {
-	GPIO_InitTypeDef GPIO_InitStructure;
+    GPIO_InitTypeDef GPIO_InitStructure;
     EXTI_InitTypeDef EXTI_InitStructure;
 
     /* configure PF6 as eth RST */
@@ -509,11 +513,11 @@ static void GPIO_Configuration()
     GPIO_ResetBits(GPIOF,GPIO_Pin_6);
     RST_1();
 
-	/* configure PF7 as external interrupt */
-	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
+    /* configure PF7 as external interrupt */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
     GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
-	GPIO_Init(GPIOF, &GPIO_InitStructure);
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
+    GPIO_Init(GPIOF, &GPIO_InitStructure);
 
     /* Connect DM9000 EXTI Line to GPIOF Pin 7 */
     GPIO_EXTILineConfig(GPIO_PortSourceGPIOF, GPIO_PinSource7);
@@ -525,79 +529,79 @@ static void GPIO_Configuration()
     EXTI_InitStructure.EXTI_LineCmd = ENABLE;
     EXTI_Init(&EXTI_InitStructure);
 
-	/* Clear the Key Button EXTI line pending bit */
-	EXTI_ClearITPendingBit(EXTI_Line7);
+    /* Clear the Key Button EXTI line pending bit */
+    EXTI_ClearITPendingBit(EXTI_Line7);
 }
 
 void rt_hw_dm9000_init()
 {
-	RCC_Configuration();
-	NVIC_Configuration();
-	GPIO_Configuration();
+    RCC_Configuration();
+    NVIC_Configuration();
+    GPIO_Configuration();
 
-	rt_sem_init(&sem_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO);
-	rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
+    rt_sem_init(&sem_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO);
+    rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
 
     dm9000_device.type    = TYPE_DM9000A;
-	/*
-	 * SRAM Tx/Rx pointer automatically return to start address,
-	 * Packet Transmitted, Packet Received
-	 */
+    /*
+     * SRAM Tx/Rx pointer automatically return to start address,
+     * Packet Transmitted, Packet Received
+     */
     dm9000_device.imr_all = IMR_PAR | IMR_ROOM | IMR_ROM | IMR_PTM | IMR_PRM;
 
-	dm9000_device.dev_addr[0] = 0x01;
-	dm9000_device.dev_addr[1] = 0x60;
-	dm9000_device.dev_addr[2] = 0x6E;
-	dm9000_device.dev_addr[3] = 0x11;
-	dm9000_device.dev_addr[4] = 0x02;
-	dm9000_device.dev_addr[5] = 0x0F;
-
-	dm9000_device.parent.parent.init       = rt_dm9000_init;
-	dm9000_device.parent.parent.open       = rt_dm9000_open;
-	dm9000_device.parent.parent.close      = rt_dm9000_close;
-	dm9000_device.parent.parent.read       = rt_dm9000_read;
-	dm9000_device.parent.parent.write      = rt_dm9000_write;
-	dm9000_device.parent.parent.control    = rt_dm9000_control;
-	dm9000_device.parent.parent.private    = RT_NULL;
-
-	dm9000_device.parent.eth_rx     = rt_dm9000_rx;
-	dm9000_device.parent.eth_tx     = rt_dm9000_tx;
-
-	eth_device_init(&(dm9000_device.parent), "e0");
+    dm9000_device.dev_addr[0] = 0x01;
+    dm9000_device.dev_addr[1] = 0x60;
+    dm9000_device.dev_addr[2] = 0x6E;
+    dm9000_device.dev_addr[3] = 0x11;
+    dm9000_device.dev_addr[4] = 0x02;
+    dm9000_device.dev_addr[5] = 0x0F;
+
+    dm9000_device.parent.parent.init       = rt_dm9000_init;
+    dm9000_device.parent.parent.open       = rt_dm9000_open;
+    dm9000_device.parent.parent.close      = rt_dm9000_close;
+    dm9000_device.parent.parent.read       = rt_dm9000_read;
+    dm9000_device.parent.parent.write      = rt_dm9000_write;
+    dm9000_device.parent.parent.control    = rt_dm9000_control;
+    dm9000_device.parent.parent.private    = RT_NULL;
+
+    dm9000_device.parent.eth_rx     = rt_dm9000_rx;
+    dm9000_device.parent.eth_tx     = rt_dm9000_tx;
+
+    eth_device_init(&(dm9000_device.parent), "e0");
 }
 
 #ifdef RT_USING_FINSH
 #include <finsh.h>
 void dm9000(void)
 {
-	rt_kprintf("\n");
-	rt_kprintf("NCR   (0x00): %02x\n", dm9000_io_read(DM9000_NCR));
-	rt_kprintf("NSR   (0x01): %02x\n", dm9000_io_read(DM9000_NSR));
-	rt_kprintf("TCR   (0x02): %02x\n", dm9000_io_read(DM9000_TCR));
-	rt_kprintf("TSRI  (0x03): %02x\n", dm9000_io_read(DM9000_TSR1));
-	rt_kprintf("TSRII (0x04): %02x\n", dm9000_io_read(DM9000_TSR2));
-	rt_kprintf("RCR   (0x05): %02x\n", dm9000_io_read(DM9000_RCR));
-	rt_kprintf("RSR   (0x06): %02x\n", dm9000_io_read(DM9000_RSR));
-	rt_kprintf("ORCR  (0x07): %02x\n", dm9000_io_read(DM9000_ROCR));
-	rt_kprintf("CRR   (0x2C): %02x\n", dm9000_io_read(DM9000_CHIPR));
-	rt_kprintf("CSCR  (0x31): %02x\n", dm9000_io_read(DM9000_CSCR));
-	rt_kprintf("RCSSR (0x32): %02x\n", dm9000_io_read(DM9000_RCSSR));
-	rt_kprintf("ISR   (0xFE): %02x\n", dm9000_io_read(DM9000_ISR));
-	rt_kprintf("IMR   (0xFF): %02x\n", dm9000_io_read(DM9000_IMR));
-	rt_kprintf("\n");
+    rt_kprintf("\n");
+    rt_kprintf("NCR   (0x00): %02x\n", dm9000_io_read(DM9000_NCR));
+    rt_kprintf("NSR   (0x01): %02x\n", dm9000_io_read(DM9000_NSR));
+    rt_kprintf("TCR   (0x02): %02x\n", dm9000_io_read(DM9000_TCR));
+    rt_kprintf("TSRI  (0x03): %02x\n", dm9000_io_read(DM9000_TSR1));
+    rt_kprintf("TSRII (0x04): %02x\n", dm9000_io_read(DM9000_TSR2));
+    rt_kprintf("RCR   (0x05): %02x\n", dm9000_io_read(DM9000_RCR));
+    rt_kprintf("RSR   (0x06): %02x\n", dm9000_io_read(DM9000_RSR));
+    rt_kprintf("ORCR  (0x07): %02x\n", dm9000_io_read(DM9000_ROCR));
+    rt_kprintf("CRR   (0x2C): %02x\n", dm9000_io_read(DM9000_CHIPR));
+    rt_kprintf("CSCR  (0x31): %02x\n", dm9000_io_read(DM9000_CSCR));
+    rt_kprintf("RCSSR (0x32): %02x\n", dm9000_io_read(DM9000_RCSSR));
+    rt_kprintf("ISR   (0xFE): %02x\n", dm9000_io_read(DM9000_ISR));
+    rt_kprintf("IMR   (0xFF): %02x\n", dm9000_io_read(DM9000_IMR));
+    rt_kprintf("\n");
 }
 FINSH_FUNCTION_EXPORT(dm9000, dm9000 register dump);
 
 void rx(void)
 {
-	rt_err_t result;
+    rt_err_t result;
 
     dm9000_io_write(DM9000_ISR, ISR_PRS);		/* Clear rx status */
 
-	/* a frame has been received */
-	result = eth_device_ready(&(dm9000_device.parent));
-	if (result != RT_EOK) rt_kprintf("eth notification failed\n");
-	RT_ASSERT(result == RT_EOK);
+    /* a frame has been received */
+    result = eth_device_ready(&(dm9000_device.parent));
+    if (result != RT_EOK) rt_kprintf("eth notification failed\n");
+    RT_ASSERT(result == RT_EOK);
 }
 FINSH_FUNCTION_EXPORT(rx, notify packet rx);
 

bsp/stm32_radio/project.Opt

@@ -21,150 +21,149 @@ GRPOPT 7,(Filesystem),0,0,0
 GRPOPT 8,(LwIP),0,0,0
 GRPOPT 9,(mp3),0,0,0
 
-OPTFFF 1,1,1,1,0,0,0,0,<.\application.c><application.c> 
-OPTFFF 1,2,1,0,0,100,115,0,<.\board.c><board.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,44,0,0,0,58,0,0,0,8,4,0,0,183,1,0,0 }
+OPTFFF 1,1,1,0,0,0,0,0,<.\application.c><application.c> 
+OPTFFF 1,2,1,83886083,0,151,167,0,<.\board.c><board.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,44,0,0,0,58,0,0,0,8,4,0,0,183,1,0,0 }
 OPTFFF 1,3,1,0,0,0,0,0,<.\startup.c><startup.c> 
-OPTFFF 1,4,2,0,0,0,0,0,<.\cortexm3_macro.s><cortexm3_macro.s> 
-OPTFFF 1,5,1,385875968,0,347,356,0,<.\stm32f10x_it.c><stm32f10x_it.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,110,0,0,0,145,0,0,0,74,4,0,0,14,2,0,0 }
-OPTFFF 1,6,5,0,0,30,44,0,<.\stm32f10x_conf.h><stm32f10x_conf.h> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,132,0,0,0,174,0,0,0,96,4,0,0,43,2,0,0 }
-OPTFFF 1,7,5,268435456,0,0,0,0,<.\rtconfig.h><rtconfig.h> 
-OPTFFF 1,8,1,822083584,0,169,172,0,<.\usart.c><usart.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,132,0,0,0,174,0,0,0,96,4,0,0,43,2,0,0 }
-OPTFFF 1,9,1,2,0,2990,2999,0,<.\sdcard.c><sdcard.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,0,0,0,0,0,0,0,0,220,3,0,0,125,1,0,0 }
-OPTFFF 1,10,1,0,0,0,0,0,<.\rtc.c><rtc.c> 
-OPTFFF 1,11,1,0,0,0,0,0,<.\mp3.c><mp3.c> 
-OPTFFF 1,12,1,939524096,0,102,118,0,<.\wm8753.c><wm8753.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,22,0,0,0,29,0,0,0,242,3,0,0,154,1,0,0 }
-OPTFFF 1,13,1,0,0,0,0,0,<.\wav.c><wav.c> 
-OPTFFF 1,14,1,922746880,0,483,492,0,<.\dm9000.c><dm9000.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,44,0,0,0,58,0,0,0,8,4,0,0,183,1,0,0 }
-OPTFFF 1,15,1,0,0,0,0,0,<.\fsmc_nand.c><fsmc_nand.c> 
-OPTFFF 1,16,1,0,0,0,0,0,<.\fsmc_sram.c><fsmc_sram.c> 
-OPTFFF 1,17,1,0,0,0,0,0,<.\fmt0371\fmt0371.c><fmt0371.c> 
-OPTFFF 2,18,1,0,0,0,0,0,<..\..\src\clock.c><clock.c> 
-OPTFFF 2,19,1,0,0,0,0,0,<..\..\src\idle.c><idle.c> 
-OPTFFF 2,20,1,0,0,0,0,0,<..\..\src\ipc.c><ipc.c> 
-OPTFFF 2,21,1,0,0,0,0,0,<..\..\src\mempool.c><mempool.c> 
-OPTFFF 2,22,1,0,0,0,0,0,<..\..\src\mem.c><mem.c> 
-OPTFFF 2,23,1,0,0,0,0,0,<..\..\src\object.c><object.c> 
-OPTFFF 2,24,1,0,0,0,0,0,<..\..\src\scheduler.c><scheduler.c> 
-OPTFFF 2,25,1,0,0,0,0,0,<..\..\src\thread.c><thread.c> 
-OPTFFF 2,26,1,0,0,0,0,0,<..\..\src\timer.c><timer.c> 
-OPTFFF 2,27,1,0,0,0,0,0,<..\..\src\irq.c><irq.c> 
-OPTFFF 2,28,1,0,0,0,0,0,<..\..\src\kservice.c><kservice.c> 
-OPTFFF 2,29,1,0,0,0,0,0,<..\..\src\device.c><device.c> 
-OPTFFF 2,30,1,0,0,0,0,0,<..\..\src\slab.c><slab.c> 
-OPTFFF 3,31,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\stack.c><stack.c> 
-OPTFFF 3,32,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\interrupt.c><interrupt.c> 
-OPTFFF 3,33,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\cpu.c><cpu.c> 
-OPTFFF 3,34,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\serial.c><serial.c> 
-OPTFFF 3,35,2,0,0,0,0,0,<..\..\libcpu\arm\stm32\context_rvds.S><context_rvds.S> 
-OPTFFF 3,36,2,0,0,0,0,0,<..\..\libcpu\arm\stm32\start_rvds.s><start_rvds.s> 
-OPTFFF 3,37,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\fault.c><fault.c> 
-OPTFFF 3,38,2,0,0,0,0,0,<..\..\libcpu\arm\stm32\fault_rvds.S><fault_rvds.S> 
-OPTFFF 4,39,1,218103808,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c><misc.c> 
-OPTFFF 4,40,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c><stm32f10x_adc.c> 
-OPTFFF 4,41,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c><stm32f10x_bkp.c> 
-OPTFFF 4,42,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c><stm32f10x_can.c> 
-OPTFFF 4,43,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c><stm32f10x_crc.c> 
-OPTFFF 4,44,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c><stm32f10x_dac.c> 
-OPTFFF 4,45,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c><stm32f10x_dbgmcu.c> 
-OPTFFF 4,46,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c><stm32f10x_dma.c> 
-OPTFFF 4,47,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c><stm32f10x_exti.c> 
-OPTFFF 4,48,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c><stm32f10x_flash.c> 
-OPTFFF 4,49,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c><stm32f10x_fsmc.c> 
-OPTFFF 4,50,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c><stm32f10x_gpio.c> 
-OPTFFF 4,51,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c><stm32f10x_i2c.c> 
-OPTFFF 4,52,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c><stm32f10x_iwdg.c> 
-OPTFFF 4,53,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c><stm32f10x_pwr.c> 
-OPTFFF 4,54,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c><stm32f10x_rcc.c> 
-OPTFFF 4,55,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rtc.c><stm32f10x_rtc.c> 
-OPTFFF 4,56,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c><stm32f10x_sdio.c> 
-OPTFFF 4,57,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c><stm32f10x_spi.c> 
-OPTFFF 4,58,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c><stm32f10x_tim.c> 
-OPTFFF 4,59,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c><stm32f10x_usart.c> 
-OPTFFF 4,60,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c><stm32f10x_wwdg.c> 
-OPTFFF 5,61,1,0,0,0,0,0,<.\Libraries\CMSIS\Core\CM3\core_cm3.c><core_cm3.c> 
-OPTFFF 5,62,1,167772160,0,0,0,0,<.\Libraries\CMSIS\Core\CM3\system_stm32f10x.c><system_stm32f10x.c> 
-OPTFFF 6,63,1,0,0,0,0,0,<..\..\finsh\finsh_compiler.c><finsh_compiler.c> 
-OPTFFF 6,64,1,0,0,0,0,0,<..\..\finsh\finsh_error.c><finsh_error.c> 
-OPTFFF 6,65,1,0,0,0,0,0,<..\..\finsh\finsh_heap.c><finsh_heap.c> 
-OPTFFF 6,66,1,0,0,0,0,0,<..\..\finsh\finsh_init.c><finsh_init.c> 
-OPTFFF 6,67,1,0,0,0,0,0,<..\..\finsh\finsh_node.c><finsh_node.c> 
-OPTFFF 6,68,1,0,0,0,0,0,<..\..\finsh\finsh_ops.c><finsh_ops.c> 
-OPTFFF 6,69,1,0,0,0,0,0,<..\..\finsh\finsh_parser.c><finsh_parser.c> 
-OPTFFF 6,70,1,0,0,0,0,0,<..\..\finsh\finsh_token.c><finsh_token.c> 
-OPTFFF 6,71,1,0,0,0,0,0,<..\..\finsh\finsh_var.c><finsh_var.c> 
-OPTFFF 6,72,1,0,0,0,0,0,<..\..\finsh\finsh_vm.c><finsh_vm.c> 
-OPTFFF 6,73,1,0,0,0,0,0,<..\..\finsh\shell.c><shell.c> 
-OPTFFF 6,74,1,0,0,0,0,0,<..\..\finsh\symbol.c><symbol.c> 
-OPTFFF 6,75,1,0,0,0,0,0,<..\..\finsh\cmd.c><cmd.c> 
-OPTFFF 7,76,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_init.c><dfs_init.c> 
-OPTFFF 7,77,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_fs.c><dfs_fs.c> 
-OPTFFF 7,78,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_raw.c><dfs_raw.c> 
-OPTFFF 7,79,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_util.c><dfs_util.c> 
-OPTFFF 7,80,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_cache.c><dfs_cache.c> 
-OPTFFF 7,81,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_posix.c><dfs_posix.c> 
-OPTFFF 7,82,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\efs.c><efs.c> 
-OPTFFF 7,83,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\extract.c><extract.c> 
-OPTFFF 7,84,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\partition.c><partition.c> 
-OPTFFF 7,85,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\plibc.c><plibc.c> 
-OPTFFF 7,86,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\dir.c><dir.c> 
-OPTFFF 7,87,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fat.c><fat.c> 
-OPTFFF 7,88,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\file.c><file.c> 
-OPTFFF 7,89,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fs.c><fs.c> 
-OPTFFF 7,90,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ls.c><ls.c> 
-OPTFFF 7,91,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\time.c><time.c> 
-OPTFFF 7,92,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ui.c><ui.c> 
-OPTFFF 8,93,1,0,0,0,0,0,<..\..\net\lwip\src\core\dhcp.c><dhcp.c> 
-OPTFFF 8,94,1,0,0,0,0,0,<..\..\net\lwip\src\core\dns.c><dns.c> 
-OPTFFF 8,95,1,0,0,0,0,0,<..\..\net\lwip\src\core\init.c><init.c> 
-OPTFFF 8,96,1,0,0,0,0,0,<..\..\net\lwip\src\core\netif.c><netif.c> 
-OPTFFF 8,97,1,0,0,0,0,0,<..\..\net\lwip\src\core\pbuf.c><pbuf.c> 
-OPTFFF 8,98,1,0,0,0,0,0,<..\..\net\lwip\src\core\raw.c><raw.c> 
-OPTFFF 8,99,1,0,0,0,0,0,<..\..\net\lwip\src\core\stats.c><stats.c> 
-OPTFFF 8,100,1,0,0,0,0,0,<..\..\net\lwip\src\core\sys.c><sys.c> 
-OPTFFF 8,101,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp.c><tcp.c> 
-OPTFFF 8,102,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp_in.c><tcp_in.c> 
-OPTFFF 8,103,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp_out.c><tcp_out.c> 
-OPTFFF 8,104,1,0,0,0,0,0,<..\..\net\lwip\src\core\udp.c><udp.c> 
-OPTFFF 8,105,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\autoip.c><autoip.c> 
-OPTFFF 8,106,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\icmp.c><icmp.c> 
-OPTFFF 8,107,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\igmp.c><igmp.c> 
-OPTFFF 8,108,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet.c><inet.c> 
-OPTFFF 8,109,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet_chksum.c><inet_chksum.c> 
-OPTFFF 8,110,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip.c><ip.c> 
-OPTFFF 8,111,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_addr.c><ip_addr.c> 
-OPTFFF 8,112,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_frag.c><ip_frag.c> 
-OPTFFF 8,113,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\msg_in.c><msg_in.c> 
-OPTFFF 8,114,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\msg_out.c><msg_out.c> 
-OPTFFF 8,115,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_lib.c><api_lib.c> 
-OPTFFF 8,116,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_msg.c><api_msg.c> 
-OPTFFF 8,117,1,0,0,0,0,0,<..\..\net\lwip\src\api\err.c><err.c> 
-OPTFFF 8,118,1,0,0,0,0,0,<..\..\net\lwip\src\api\netbuf.c><netbuf.c> 
-OPTFFF 8,119,1,0,0,0,0,0,<..\..\net\lwip\src\api\netdb.c><netdb.c> 
-OPTFFF 8,120,1,0,0,0,0,0,<..\..\net\lwip\src\api\netifapi.c><netifapi.c> 
-OPTFFF 8,121,1,0,0,0,0,0,<..\..\net\lwip\src\api\tcpip.c><tcpip.c> 
-OPTFFF 8,122,1,0,0,0,0,0,<..\..\net\lwip\src\netif\etharp.c><etharp.c> 
-OPTFFF 8,123,1,0,0,0,0,0,<..\..\net\lwip\src\netif\ethernetif.c><ethernetif.c> 
-OPTFFF 8,124,1,0,0,0,0,0,<..\..\net\lwip\src\netif\loopif.c><loopif.c> 
-OPTFFF 8,125,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch_init.c><sys_arch_init.c> 
-OPTFFF 8,126,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch.c><sys_arch.c> 
-OPTFFF 8,127,1,0,0,0,0,0,<..\..\net\lwip\src\api\sockets.c><sockets.c> 
-OPTFFF 8,128,1,0,0,0,0,0,<..\..\net\lwip\src\core\memp_tiny.c><memp_tiny.c> 
-OPTFFF 9,129,1,0,0,0,0,0,<.\mp3\mp3dec.c><mp3dec.c> 
-OPTFFF 9,130,1,0,0,0,0,0,<.\mp3\mp3tabs.c><mp3tabs.c> 
-OPTFFF 9,131,1,0,0,0,0,0,<.\mp3\real\bitstream.c><bitstream.c> 
-OPTFFF 9,132,1,0,0,0,0,0,<.\mp3\real\buffers.c><buffers.c> 
-OPTFFF 9,133,1,0,0,0,0,0,<.\mp3\real\dct32.c><dct32.c> 
-OPTFFF 9,134,1,0,0,0,0,0,<.\mp3\real\dequant.c><dequant.c> 
-OPTFFF 9,135,1,0,0,0,0,0,<.\mp3\real\dqchan.c><dqchan.c> 
-OPTFFF 9,136,1,0,0,0,0,0,<.\mp3\real\huffman.c><huffman.c> 
-OPTFFF 9,137,1,0,0,0,0,0,<.\mp3\real\hufftabs.c><hufftabs.c> 
-OPTFFF 9,138,1,0,0,0,0,0,<.\mp3\real\imdct.c><imdct.c> 
-OPTFFF 9,139,1,0,0,0,0,0,<.\mp3\real\scalfact.c><scalfact.c> 
-OPTFFF 9,140,1,0,0,0,0,0,<.\mp3\real\stproc.c><stproc.c> 
-OPTFFF 9,141,1,0,0,0,0,0,<.\mp3\real\subband.c><subband.c> 
-OPTFFF 9,142,1,0,0,0,0,0,<.\mp3\real\trigtabs.c><trigtabs.c> 
-OPTFFF 9,143,2,0,0,0,0,0,<.\mp3\real\arm\asmpoly_thumb2.s><asmpoly_thumb2.s> 
-OPTFFF 9,144,2,0,0,0,0,0,<.\mp3\real\arm\asmmisc.s><asmmisc.s> 
+OPTFFF 1,4,1,385875968,0,0,0,0,<.\stm32f10x_it.c><stm32f10x_it.c> 
+OPTFFF 1,5,5,0,0,0,0,0,<.\stm32f10x_conf.h><stm32f10x_conf.h> 
+OPTFFF 1,6,5,268435456,0,0,0,0,<.\rtconfig.h><rtconfig.h> 
+OPTFFF 1,7,1,822083584,0,0,0,0,<.\usart.c><usart.c> 
+OPTFFF 1,8,1,0,0,0,0,0,<.\sdcard.c><sdcard.c> 
+OPTFFF 1,9,1,0,0,0,0,0,<.\rtc.c><rtc.c> 
+OPTFFF 1,10,1,0,0,0,0,0,<.\mp3.c><mp3.c> 
+OPTFFF 1,11,1,939524096,0,0,0,0,<.\wm8753.c><wm8753.c> 
+OPTFFF 1,12,1,0,0,0,0,0,<.\wav.c><wav.c> 
+OPTFFF 1,13,1,922746880,0,0,0,0,<.\dm9000.c><dm9000.c> 
+OPTFFF 1,14,1,0,0,0,0,0,<.\fsmc_nand.c><fsmc_nand.c> 
+OPTFFF 1,15,1,486539264,0,0,0,0,<.\fsmc_sram.c><fsmc_sram.c> 
+OPTFFF 1,16,1,0,0,0,0,0,<.\fmt0371\fmt0371.c><fmt0371.c> 
+OPTFFF 2,17,1,0,0,0,0,0,<..\..\src\clock.c><clock.c> 
+OPTFFF 2,18,1,0,0,0,0,0,<..\..\src\idle.c><idle.c> 
+OPTFFF 2,19,1,0,0,0,0,0,<..\..\src\ipc.c><ipc.c> 
+OPTFFF 2,20,1,0,0,0,0,0,<..\..\src\mempool.c><mempool.c> 
+OPTFFF 2,21,1,0,0,0,0,0,<..\..\src\mem.c><mem.c> 
+OPTFFF 2,22,1,0,0,0,0,0,<..\..\src\object.c><object.c> 
+OPTFFF 2,23,1,0,0,0,0,0,<..\..\src\scheduler.c><scheduler.c> 
+OPTFFF 2,24,1,0,0,0,0,0,<..\..\src\thread.c><thread.c> 
+OPTFFF 2,25,1,0,0,0,0,0,<..\..\src\timer.c><timer.c> 
+OPTFFF 2,26,1,0,0,0,0,0,<..\..\src\irq.c><irq.c> 
+OPTFFF 2,27,1,0,0,0,0,0,<..\..\src\kservice.c><kservice.c> 
+OPTFFF 2,28,1,0,0,0,0,0,<..\..\src\device.c><device.c> 
+OPTFFF 2,29,1,0,0,0,0,0,<..\..\src\slab.c><slab.c> 
+OPTFFF 3,30,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\stack.c><stack.c> 
+OPTFFF 3,31,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\interrupt.c><interrupt.c> 
+OPTFFF 3,32,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\cpu.c><cpu.c> 
+OPTFFF 3,33,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\serial.c><serial.c> 
+OPTFFF 3,34,2,0,0,0,0,0,<..\..\libcpu\arm\stm32\context_rvds.S><context_rvds.S> 
+OPTFFF 3,35,2,0,0,0,0,0,<..\..\libcpu\arm\stm32\start_rvds.s><start_rvds.s> 
+OPTFFF 3,36,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\fault.c><fault.c> 
+OPTFFF 3,37,2,0,0,0,0,0,<..\..\libcpu\arm\stm32\fault_rvds.S><fault_rvds.S> 
+OPTFFF 4,38,1,218103808,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c><misc.c> 
+OPTFFF 4,39,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c><stm32f10x_adc.c> 
+OPTFFF 4,40,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c><stm32f10x_bkp.c> 
+OPTFFF 4,41,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c><stm32f10x_can.c> 
+OPTFFF 4,42,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c><stm32f10x_crc.c> 
+OPTFFF 4,43,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c><stm32f10x_dac.c> 
+OPTFFF 4,44,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c><stm32f10x_dbgmcu.c> 
+OPTFFF 4,45,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c><stm32f10x_dma.c> 
+OPTFFF 4,46,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c><stm32f10x_exti.c> 
+OPTFFF 4,47,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c><stm32f10x_flash.c> 
+OPTFFF 4,48,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c><stm32f10x_fsmc.c> 
+OPTFFF 4,49,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c><stm32f10x_gpio.c> 
+OPTFFF 4,50,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c><stm32f10x_i2c.c> 
+OPTFFF 4,51,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c><stm32f10x_iwdg.c> 
+OPTFFF 4,52,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c><stm32f10x_pwr.c> 
+OPTFFF 4,53,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c><stm32f10x_rcc.c> 
+OPTFFF 4,54,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rtc.c><stm32f10x_rtc.c> 
+OPTFFF 4,55,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c><stm32f10x_sdio.c> 
+OPTFFF 4,56,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c><stm32f10x_spi.c> 
+OPTFFF 4,57,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c><stm32f10x_tim.c> 
+OPTFFF 4,58,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c><stm32f10x_usart.c> 
+OPTFFF 4,59,1,0,0,0,0,0,<.\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c><stm32f10x_wwdg.c> 
+OPTFFF 5,60,1,0,0,0,0,0,<.\Libraries\CMSIS\Core\CM3\core_cm3.c><core_cm3.c> 
+OPTFFF 5,61,1,167772160,0,0,0,0,<.\Libraries\CMSIS\Core\CM3\system_stm32f10x.c><system_stm32f10x.c> 
+OPTFFF 6,62,1,0,0,0,0,0,<..\..\finsh\finsh_compiler.c><finsh_compiler.c> 
+OPTFFF 6,63,1,0,0,0,0,0,<..\..\finsh\finsh_error.c><finsh_error.c> 
+OPTFFF 6,64,1,0,0,0,0,0,<..\..\finsh\finsh_heap.c><finsh_heap.c> 
+OPTFFF 6,65,1,0,0,0,0,0,<..\..\finsh\finsh_init.c><finsh_init.c> 
+OPTFFF 6,66,1,0,0,0,0,0,<..\..\finsh\finsh_node.c><finsh_node.c> 
+OPTFFF 6,67,1,0,0,0,0,0,<..\..\finsh\finsh_ops.c><finsh_ops.c> 
+OPTFFF 6,68,1,0,0,0,0,0,<..\..\finsh\finsh_parser.c><finsh_parser.c> 
+OPTFFF 6,69,1,0,0,0,0,0,<..\..\finsh\finsh_token.c><finsh_token.c> 
+OPTFFF 6,70,1,0,0,0,0,0,<..\..\finsh\finsh_var.c><finsh_var.c> 
+OPTFFF 6,71,1,0,0,0,0,0,<..\..\finsh\finsh_vm.c><finsh_vm.c> 
+OPTFFF 6,72,1,0,0,0,0,0,<..\..\finsh\shell.c><shell.c> 
+OPTFFF 6,73,1,0,0,0,0,0,<..\..\finsh\symbol.c><symbol.c> 
+OPTFFF 6,74,1,0,0,0,0,0,<..\..\finsh\cmd.c><cmd.c> 
+OPTFFF 7,75,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_init.c><dfs_init.c> 
+OPTFFF 7,76,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_fs.c><dfs_fs.c> 
+OPTFFF 7,77,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_raw.c><dfs_raw.c> 
+OPTFFF 7,78,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_util.c><dfs_util.c> 
+OPTFFF 7,79,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_cache.c><dfs_cache.c> 
+OPTFFF 7,80,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_posix.c><dfs_posix.c> 
+OPTFFF 7,81,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\efs.c><efs.c> 
+OPTFFF 7,82,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\extract.c><extract.c> 
+OPTFFF 7,83,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\partition.c><partition.c> 
+OPTFFF 7,84,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\plibc.c><plibc.c> 
+OPTFFF 7,85,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\dir.c><dir.c> 
+OPTFFF 7,86,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fat.c><fat.c> 
+OPTFFF 7,87,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\file.c><file.c> 
+OPTFFF 7,88,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fs.c><fs.c> 
+OPTFFF 7,89,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ls.c><ls.c> 
+OPTFFF 7,90,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\time.c><time.c> 
+OPTFFF 7,91,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ui.c><ui.c> 
+OPTFFF 8,92,1,0,0,0,0,0,<..\..\net\lwip\src\core\dhcp.c><dhcp.c> 
+OPTFFF 8,93,1,0,0,0,0,0,<..\..\net\lwip\src\core\dns.c><dns.c> 
+OPTFFF 8,94,1,0,0,0,0,0,<..\..\net\lwip\src\core\init.c><init.c> 
+OPTFFF 8,95,1,0,0,0,0,0,<..\..\net\lwip\src\core\netif.c><netif.c> 
+OPTFFF 8,96,1,0,0,0,0,0,<..\..\net\lwip\src\core\pbuf.c><pbuf.c> 
+OPTFFF 8,97,1,0,0,0,0,0,<..\..\net\lwip\src\core\raw.c><raw.c> 
+OPTFFF 8,98,1,0,0,0,0,0,<..\..\net\lwip\src\core\stats.c><stats.c> 
+OPTFFF 8,99,1,0,0,0,0,0,<..\..\net\lwip\src\core\sys.c><sys.c> 
+OPTFFF 8,100,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp.c><tcp.c> 
+OPTFFF 8,101,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp_in.c><tcp_in.c> 
+OPTFFF 8,102,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp_out.c><tcp_out.c> 
+OPTFFF 8,103,1,0,0,0,0,0,<..\..\net\lwip\src\core\udp.c><udp.c> 
+OPTFFF 8,104,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\autoip.c><autoip.c> 
+OPTFFF 8,105,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\icmp.c><icmp.c> 
+OPTFFF 8,106,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\igmp.c><igmp.c> 
+OPTFFF 8,107,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet.c><inet.c> 
+OPTFFF 8,108,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet_chksum.c><inet_chksum.c> 
+OPTFFF 8,109,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip.c><ip.c> 
+OPTFFF 8,110,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_addr.c><ip_addr.c> 
+OPTFFF 8,111,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_frag.c><ip_frag.c> 
+OPTFFF 8,112,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\msg_in.c><msg_in.c> 
+OPTFFF 8,113,1,0,0,0,0,0,<..\..\net\lwip\src\core\snmp\msg_out.c><msg_out.c> 
+OPTFFF 8,114,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_lib.c><api_lib.c> 
+OPTFFF 8,115,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_msg.c><api_msg.c> 
+OPTFFF 8,116,1,0,0,0,0,0,<..\..\net\lwip\src\api\err.c><err.c> 
+OPTFFF 8,117,1,0,0,0,0,0,<..\..\net\lwip\src\api\netbuf.c><netbuf.c> 
+OPTFFF 8,118,1,0,0,0,0,0,<..\..\net\lwip\src\api\netdb.c><netdb.c> 
+OPTFFF 8,119,1,0,0,0,0,0,<..\..\net\lwip\src\api\netifapi.c><netifapi.c> 
+OPTFFF 8,120,1,0,0,0,0,0,<..\..\net\lwip\src\api\tcpip.c><tcpip.c> 
+OPTFFF 8,121,1,0,0,0,0,0,<..\..\net\lwip\src\netif\etharp.c><etharp.c> 
+OPTFFF 8,122,1,0,0,0,0,0,<..\..\net\lwip\src\netif\ethernetif.c><ethernetif.c> 
+OPTFFF 8,123,1,0,0,0,0,0,<..\..\net\lwip\src\netif\loopif.c><loopif.c> 
+OPTFFF 8,124,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch_init.c><sys_arch_init.c> 
+OPTFFF 8,125,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch.c><sys_arch.c> 
+OPTFFF 8,126,1,0,0,0,0,0,<..\..\net\lwip\src\api\sockets.c><sockets.c> 
+OPTFFF 8,127,1,0,0,0,0,0,<..\..\net\lwip\src\core\memp_tiny.c><memp_tiny.c> 
+OPTFFF 9,128,1,0,0,0,0,0,<.\mp3\mp3dec.c><mp3dec.c> 
+OPTFFF 9,129,1,0,0,0,0,0,<.\mp3\mp3tabs.c><mp3tabs.c> 
+OPTFFF 9,130,1,0,0,0,0,0,<.\mp3\real\bitstream.c><bitstream.c> 
+OPTFFF 9,131,1,0,0,0,0,0,<.\mp3\real\buffers.c><buffers.c> 
+OPTFFF 9,132,1,0,0,0,0,0,<.\mp3\real\dct32.c><dct32.c> 
+OPTFFF 9,133,1,0,0,0,0,0,<.\mp3\real\dequant.c><dequant.c> 
+OPTFFF 9,134,1,0,0,0,0,0,<.\mp3\real\dqchan.c><dqchan.c> 
+OPTFFF 9,135,1,0,0,0,0,0,<.\mp3\real\huffman.c><huffman.c> 
+OPTFFF 9,136,1,0,0,0,0,0,<.\mp3\real\hufftabs.c><hufftabs.c> 
+OPTFFF 9,137,1,0,0,0,0,0,<.\mp3\real\imdct.c><imdct.c> 
+OPTFFF 9,138,1,0,0,0,0,0,<.\mp3\real\scalfact.c><scalfact.c> 
+OPTFFF 9,139,1,0,0,0,0,0,<.\mp3\real\stproc.c><stproc.c> 
+OPTFFF 9,140,1,16777216,0,0,0,0,<.\mp3\real\subband.c><subband.c> 
+OPTFFF 9,141,1,0,0,0,0,0,<.\mp3\real\trigtabs.c><trigtabs.c> 
+OPTFFF 9,142,2,0,0,0,0,0,<.\mp3\real\arm\asmpoly_thumb2.s><asmpoly_thumb2.s> 
+OPTFFF 9,143,2,0,0,0,0,0,<.\mp3\real\arm\asmmisc.s><asmmisc.s> 
 
 
 TARGOPT 1, (RT-Thread STM32 Radio)

bsp/stm32_radio/project.Uv2

@@ -16,7 +16,6 @@ Group (mp3)
 File 1,1,<.\application.c><application.c>
 File 1,1,<.\board.c><board.c>
 File 1,1,<.\startup.c><startup.c>
-File 1,2,<.\cortexm3_macro.s><cortexm3_macro.s>
 File 1,1,<.\stm32f10x_it.c><stm32f10x_it.c>
 File 1,5,<.\stm32f10x_conf.h><stm32f10x_conf.h>
 File 1,5,<.\rtconfig.h><rtconfig.h>
@@ -213,7 +212,7 @@ Options 1,0,0  // Target 'RT-Thread STM32 Radio'
  OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
  OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,8,0,0,8,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 }
  RV_STAVEC ()
- ADSCCFLG { 5,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSCCFLG { 5,32,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
  ADSCMISC ()
  ADSCDEFN (USE_STDPERIPH_DRIVER, STM32F10X_HD,)
  ADSCUDEF ()

bsp/stm32_radio/wm8753.c

@@ -5,7 +5,7 @@
 /*
  * WM8753 Driver
  */
-	
+
 /* WM8753 register definitions */
 #define WM8753_DAC		0x01
 #define WM8753_ADC		0x02
@@ -84,63 +84,63 @@ CSB   PA4  SPI1_NSS
 /* data node for Tx Mode */
 struct wm8753_data_node
 {
-	rt_uint16_t *data_ptr;
-	rt_size_t  data_size;
+    rt_uint16_t *data_ptr;
+    rt_size_t  data_size;
 };
 
 struct wm8753_device
 {
-	/* inherit from rt_device */
-	struct rt_device parent;
+    /* inherit from rt_device */
+    struct rt_device parent;
 
-	/* pcm data list */
-	struct wm8753_data_node data_list[DATA_NODE_MAX];
-	rt_uint16_t read_index, put_index;
+    /* pcm data list */
+    struct wm8753_data_node data_list[DATA_NODE_MAX];
+    rt_uint16_t read_index, put_index;
 
-	/* transmitted offset of current data node */
-	rt_size_t offset;
+    /* transmitted offset of current data node */
+    rt_size_t offset;
 };
 struct wm8753_device wm8753;
 
 static void NVIC_Configuration(void)
 {
-	NVIC_InitTypeDef NVIC_InitStructure;
-	NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
-	
-	/* SPI2 IRQ Channel configuration */
-	NVIC_InitStructure.NVIC_IRQChannel = SPI2_IRQn;
-	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
-	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-	NVIC_Init(&NVIC_InitStructure);
-
-	/* DMA1 IRQ Channel configuration */
-	NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel5_IRQn;
-	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
-	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-	NVIC_Init(&NVIC_InitStructure);
+    NVIC_InitTypeDef NVIC_InitStructure;
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
+
+    /* SPI2 IRQ Channel configuration */
+    NVIC_InitStructure.NVIC_IRQChannel = SPI2_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+
+    /* DMA1 IRQ Channel configuration */
+    NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel5_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
 }
 
 static void GPIO_Configuration(void)
 {
     GPIO_InitTypeDef GPIO_InitStructure;
 
-	/* Disable the JTAG interface and enable the SWJ interface */
-	GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
-	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+    /* Disable the JTAG interface and enable the SWJ interface */
+    GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
 
-	/* Configure GPIOA 2, 3, 7 */
-	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_7;
+    /* Configure GPIOA 2, 3, 7 */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_7;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
     GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
     GPIO_Init(GPIOA,&GPIO_InitStructure);
 
-	/* Configure SPI2 pins: CK, WS and SD */
-	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_15;
-	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-	GPIO_Init(GPIOB, &GPIO_InitStructure);
+    /* Configure SPI2 pins: CK, WS and SD */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_15;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
 
     /*    MCO    configure */
     GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
@@ -154,45 +154,45 @@ static void GPIO_Configuration(void)
 #define SPI2_DR_Address  0x4000380C
 static void DMA_Configuration(rt_uint32_t addr, rt_size_t size)
 {
-	DMA_InitTypeDef    DMA_InitStructure;
-
-	/* DMA1 Channel2 configuration ----------------------------------------------*/
-	DMA_Cmd(DMA1_Channel5, DISABLE);
-	DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)SPI2_DR_Address;
-	DMA_InitStructure.DMA_MemoryBaseAddr = (u32)addr;
-	DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
-	DMA_InitStructure.DMA_BufferSize = size;
-	DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-	DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-	DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
-	DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
-	DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
-	DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-	DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-	DMA_Init(DMA1_Channel5, &DMA_InitStructure);
-	
-	/* Enable SPI2 DMA Tx request */
-	SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
-	
-	DMA_ITConfig(DMA1_Channel5, DMA_IT_TC, ENABLE);
-	DMA_Cmd(DMA1_Channel5, ENABLE);
+    DMA_InitTypeDef    DMA_InitStructure;
+
+    /* DMA1 Channel2 configuration ----------------------------------------------*/
+    DMA_Cmd(DMA1_Channel5, DISABLE);
+    DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)SPI2_DR_Address;
+    DMA_InitStructure.DMA_MemoryBaseAddr = (u32)addr;
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+    DMA_InitStructure.DMA_BufferSize = size;
+    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
+    DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
+    DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
+    DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+    DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+    DMA_Init(DMA1_Channel5, &DMA_InitStructure);
+
+    /* Enable SPI2 DMA Tx request */
+    SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
+
+    DMA_ITConfig(DMA1_Channel5, DMA_IT_TC, ENABLE);
+    DMA_Cmd(DMA1_Channel5, ENABLE);
 }
 
 static void I2S_Configuration(void)
 {
-	I2S_InitTypeDef I2S_InitStructure;
-
-	/* I2S peripheral configuration */
-	I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips;
-	I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
-	I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-	I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq_44k;
-	I2S_InitStructure.I2S_CPOL = I2S_CPOL_High;// I2S_CPOL_Low
-
-	/* I2S2 Master Transmitter to I2S3 Slave Receiver communication -----------*/
-	/* I2S2 configuration */
-	I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;//I2S_Mode_MasterTx  I2S_Mode_SlaveTx
-	I2S_Init(SPI2, &I2S_InitStructure);
+    I2S_InitTypeDef I2S_InitStructure;
+
+    /* I2S peripheral configuration */
+    I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips;
+    I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
+    I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+    I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq_44k;
+    I2S_InitStructure.I2S_CPOL = I2S_CPOL_High;// I2S_CPOL_Low
+
+    /* I2S2 Master Transmitter to I2S3 Slave Receiver communication -----------*/
+    /* I2S2 configuration */
+    I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;//I2S_Mode_MasterTx  I2S_Mode_SlaveTx
+    I2S_Init(SPI2, &I2S_InitStructure);
 }
 
 void wm8753_send(rt_uint16_t s_data)
@@ -200,9 +200,9 @@ void wm8753_send(rt_uint16_t s_data)
     u8 i;
     wm_sclk_0;
 
-    for(i=0;i<16;i++)
+    for (i=0;i<16;i++)
     {
-        if(s_data & 0x8000)
+        if (s_data & 0x8000)
         {
             wm_sdin_1;
         }
@@ -221,171 +221,171 @@ void wm8753_send(rt_uint16_t s_data)
 
 static rt_err_t wm8753_init (rt_device_t dev)
 {
-	wm8753_send(31<<9 | 0); // reset
-	
-	wm8753_send(20<<9 | (1<<7) | 1<<6 | 1<<3 | 1<<2 );      // 打开电源 处理部分
-	//wm8753_send(21<<9 | 0x1FF);
-	wm8753_send(22<<9 | 1<<3 | 1<<7 | 1<<8 | 1<<5 | 1<<6 ); // 电源管理 功率输出部分
-	wm8753_send(23<<9 | 1<<1 | 1 ); // 打开左右调音台电源
-	
-	/*  设置时钟及PLL　 */
-	#define MCLK1DIV2 0
-	#define pll1_N    11
-	#define pll1_K    0x1288CE
-	
-	#if pll1_K > 0x3FFFFF
-	#warning MAX bit(21:0)
-	#endif
-	
-	wm8753_send(53<<9 | 1<<5 | MCLK1DIV2<<3 | 1<<2 | 1<<1 | 1 );
-	wm8753_send(54<<9 | pll1_N<<5 | (pll1_K>>18) );
-	wm8753_send(55<<9 | ( (pll1_K>>9)&0x1FF ) );
-	wm8753_send(56<<9 | ( (pll1_K)&0x1FF ) );
-	
-	wm8753_send(52<<9 | 1<<4 | 0<<1 | 0 ); // 打开CLK输出 测试用 可以不设置
-	/*  设置时钟及PLL　 */
-	
-	/* 设置IIS及DAC */
-	// wm8753_send(6<<9 | 0<<1 | 0 ); // 48K
-	wm8753_send(7<<9 | 3<<3 ); // BCLK = MCLK / 8	   0:0 1:2 2:4 3:8 4:16
-	wm8753_send(6<<9 | 16<<1 | 0 ); // 44.1K
-	wm8753_send(5<<9 | 0x01<<4 | 0x01<<5 | 0x02<<2 | 0x02<<2 | 0x01<<1 | 1); //
-	wm8753_send(4<<9 | 0<<6 | 2 ); // 6.master IIS
-	wm8753_send(1<<9 | 0 ); // 关闭DAC静音
-	/* 设置IIS及DAC */
-
-	/* 设置模拟通道及功放输出部分 */
-	wm8753_send(34<<9 | 1<<8 | 1<<7 | 4<<4 );  // DAC LINE
-	wm8753_send(36<<9 | 1<<8 | 1<<7 | 4<<4 );  // DAC LINE
-	
-	wm8753_send(40<<9 | 0<<8 | 1<<7 | 100);    // 耳机音量
-	wm8753_send(41<<9 | 1<<8 | 1<<7 | 100);    // 耳机音量
-	
-	wm8753_send(45<<9 | 1<<2); // 设置ROUT反向
-	wm8753_send(42<<9 | 1<<8 | 1<<7 | 105 ); //喇叭音量
-	wm8753_send(43<<9 | 1<<8 | 1<<7 | 105 ); //喇叭音量
-	/* 设置IIS及DAC */
-
-	return RT_EOK;
+    wm8753_send(31<<9 | 0); // reset
+
+    wm8753_send(20<<9 | (1<<7) | 1<<6 | 1<<3 | 1<<2 );      // 打开电源 处理部分
+    //wm8753_send(21<<9 | 0x1FF);
+    wm8753_send(22<<9 | 1<<3 | 1<<7 | 1<<8 | 1<<5 | 1<<6 ); // 电源管理 功率输出部分
+    wm8753_send(23<<9 | 1<<1 | 1 ); // 打开左右调音台电源
+
+    /*  设置时钟及PLL　 */
+#define MCLK1DIV2 0
+#define pll1_N    11
+#define pll1_K    0x1288CE
+
+#if pll1_K > 0x3FFFFF
+#warning MAX bit(21:0)
+#endif
+
+    wm8753_send(53<<9 | 1<<5 | MCLK1DIV2<<3 | 1<<2 | 1<<1 | 1 );
+    wm8753_send(54<<9 | pll1_N<<5 | (pll1_K>>18) );
+    wm8753_send(55<<9 | ( (pll1_K>>9)&0x1FF ) );
+    wm8753_send(56<<9 | ( (pll1_K)&0x1FF ) );
+
+    wm8753_send(52<<9 | 1<<4 | 0<<1 | 0 ); // 打开CLK输出 测试用 可以不设置
+    /*  设置时钟及PLL　 */
+
+    /* 设置IIS及DAC */
+    // wm8753_send(6<<9 | 0<<1 | 0 ); // 48K
+    wm8753_send(7<<9 | 3<<3 ); // BCLK = MCLK / 8	   0:0 1:2 2:4 3:8 4:16
+    wm8753_send(6<<9 | 16<<1 | 0 ); // 44.1K
+    wm8753_send(5<<9 | 0x01<<4 | 0x01<<5 | 0x02<<2 | 0x02<<2 | 0x01<<1 | 1); //
+    wm8753_send(4<<9 | 0<<6 | 2 ); // 6.master IIS
+    wm8753_send(1<<9 | 0 ); // 关闭DAC静音
+    /* 设置IIS及DAC */
+
+    /* 设置模拟通道及功放输出部分 */
+    wm8753_send(34<<9 | 1<<8 | 1<<7 | 4<<4 );  // DAC LINE
+    wm8753_send(36<<9 | 1<<8 | 1<<7 | 4<<4 );  // DAC LINE
+
+    wm8753_send(40<<9 | 0<<8 | 1<<7 | 100);    // 耳机音量
+    wm8753_send(41<<9 | 1<<8 | 1<<7 | 100);    // 耳机音量
+
+    wm8753_send(45<<9 | 1<<2); // 设置ROUT反向
+    wm8753_send(42<<9 | 1<<8 | 1<<7 | 105 ); //喇叭音量
+    wm8753_send(43<<9 | 1<<8 | 1<<7 | 105 ); //喇叭音量
+    /* 设置IIS及DAC */
+
+    return RT_EOK;
 }
 
 #include <finsh.h>
 void vol(int v)
 {
-	wm8753_send(40<<9 | 0<<8 | 1<<7 | v);    // 耳机音量
-	wm8753_send(41<<9 | 1<<8 | 1<<7 | v);    // 耳机音量
+    wm8753_send(40<<9 | 0<<8 | 1<<7 | v);    // 耳机音量
+    wm8753_send(41<<9 | 1<<8 | 1<<7 | v);    // 耳机音量
 
-	wm8753_send(42<<9 | 0<<8 | 1<<7 | v);    // 耳机音量
-	wm8753_send(43<<9 | 1<<8 | 1<<7 | v);    // 耳机音量
+    wm8753_send(42<<9 | 0<<8 | 1<<7 | v);    // 耳机音量
+    wm8753_send(43<<9 | 1<<8 | 1<<7 | v);    // 耳机音量
 }
 FINSH_FUNCTION_EXPORT(vol, set volume)
 
 static rt_err_t wm8753_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	/* enable I2S */
-	I2S_Cmd(SPI2, ENABLE);
+    /* enable I2S */
+    I2S_Cmd(SPI2, ENABLE);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t wm8753_close(rt_device_t dev)
 {
-	/* interrupt mode */
-	if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-	{
-		/* Disable the I2S2 */
-		I2S_Cmd(SPI2, DISABLE);
-	}
-
-	/* remove all data node */
-	
-	return RT_EOK;
+    /* interrupt mode */
+    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+    {
+        /* Disable the I2S2 */
+        I2S_Cmd(SPI2, DISABLE);
+    }
+
+    /* remove all data node */
+
+    return RT_EOK;
 }
 
 static rt_err_t wm8753_control(rt_device_t dev, rt_uint8_t cmd, void *args)
 {
-	/* rate control */
-	return RT_EOK;
+    /* rate control */
+    return RT_EOK;
 }
 
 static rt_size_t wm8753_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	struct wm8753_device* device;
-	struct wm8753_data_node* node;
-	rt_uint32_t level;
-	rt_uint16_t next_index;
-	
-	device = (struct wm8753_device*)dev;
-	RT_ASSERT(device != RT_NULL);
-	
-	next_index = device->put_index + 1;
-	if (next_index >= DATA_NODE_MAX) next_index = 0;
-
-	/* check data_list full */
-	if (next_index == device->read_index)
-	{
-		rt_set_errno(-RT_EFULL);
-		return 0;
-	}
-	
-	level = rt_hw_interrupt_disable();
-	node = &device->data_list[device->put_index];
-	device->put_index = next_index;
-
-	// rt_kprintf("+\n");
-	/* set node attribute */
-	node->data_ptr = (rt_uint16_t*)buffer;
-	node->data_size = size >> 1; /* size is byte unit, convert to half word unit */
-
-	next_index = device->read_index + 1;
-	if (next_index >= DATA_NODE_MAX) next_index = 0;
-	
-	/* check data list whether is empty */
-	if (next_index == device->put_index)
-	{
-		if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-		{
-			device->offset = 0;
-			/* enable I2S interrupt */
-			SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, ENABLE);
-		}
-		else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
-		{
-			DMA_Configuration((rt_uint32_t)node->data_ptr, node->data_size);
-		}
-	}
-	rt_hw_interrupt_enable(level);
-
-	return size;
+    struct wm8753_device* device;
+    struct wm8753_data_node* node;
+    rt_uint32_t level;
+    rt_uint16_t next_index;
+
+    device = (struct wm8753_device*)dev;
+    RT_ASSERT(device != RT_NULL);
+
+    next_index = device->put_index + 1;
+    if (next_index >= DATA_NODE_MAX) next_index = 0;
+
+    /* check data_list full */
+    if (next_index == device->read_index)
+    {
+        rt_set_errno(-RT_EFULL);
+        return 0;
+    }
+
+    level = rt_hw_interrupt_disable();
+    node = &device->data_list[device->put_index];
+    device->put_index = next_index;
+
+    // rt_kprintf("+\n");
+    /* set node attribute */
+    node->data_ptr = (rt_uint16_t*)buffer;
+    node->data_size = size >> 1; /* size is byte unit, convert to half word unit */
+
+    next_index = device->read_index + 1;
+    if (next_index >= DATA_NODE_MAX) next_index = 0;
+
+    /* check data list whether is empty */
+    if (next_index == device->put_index)
+    {
+        if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+        {
+            device->offset = 0;
+            /* enable I2S interrupt */
+            SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, ENABLE);
+        }
+        else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+        {
+            DMA_Configuration((rt_uint32_t)node->data_ptr, node->data_size);
+        }
+    }
+    rt_hw_interrupt_enable(level);
+
+    return size;
 }
 
 rt_err_t wm8753_hw_init(void)
 {
-	rt_device_t dev;
-	
+    rt_device_t dev;
+
     RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB, ENABLE);
-	RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
-	RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
-	
-	NVIC_Configuration();
-	GPIO_Configuration();
-	I2S_Configuration();
-
-	dev = (rt_device_t)&wm8753;
-	dev->type			= RT_Device_Class_Unknown;
-	dev->rx_indicate 	= RT_NULL;
-	dev->tx_complete 	= RT_NULL;
-	dev->init 			= wm8753_init;
-	dev->open			= wm8753_open;
-	dev->close			= wm8753_close;
-	dev->read 			= RT_NULL;
-	dev->write 			= wm8753_write;
-	dev->control 		= wm8753_control;
-	dev->private		= RT_NULL;
-
-	/* set read_index and put index to 0 */
-	wm8753.read_index	= 0;
-	wm8753.put_index 	= 0;
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
+
+    NVIC_Configuration();
+    GPIO_Configuration();
+    I2S_Configuration();
+
+    dev = (rt_device_t)&wm8753;
+    dev->type			= RT_Device_Class_Unknown;
+    dev->rx_indicate 	= RT_NULL;
+    dev->tx_complete 	= RT_NULL;
+    dev->init 			= wm8753_init;
+    dev->open			= wm8753_open;
+    dev->close			= wm8753_close;
+    dev->read 			= RT_NULL;
+    dev->write 			= wm8753_write;
+    dev->control 		= wm8753_control;
+    dev->private		= RT_NULL;
+
+    /* set read_index and put index to 0 */
+    wm8753.read_index	= 0;
+    wm8753.put_index 	= 0;
 
     wm_sclk_0;
     wm_sclk_1;
@@ -398,77 +398,77 @@ rt_err_t wm8753_hw_init(void)
     wm_csb_0;
     wm_csb_1;
 
-	/* register the device */
-	return rt_device_register(&wm8753.parent, "snd", 
-		RT_DEVICE_FLAG_WRONLY | RT_DEVICE_FLAG_DMA_TX);
+    /* register the device */
+    return rt_device_register(&wm8753.parent, "snd",
+                              RT_DEVICE_FLAG_WRONLY | RT_DEVICE_FLAG_DMA_TX);
 }
 
 void wm8753_isr()
 {
-	struct wm8753_data_node* node;
-	node = &wm8753.data_list[wm8753.read_index]; /* get current data node */
-	
-	if (SPI_I2S_GetITStatus(SPI2, SPI_I2S_IT_TXE) == SET)
-	{
-		SPI_I2S_SendData(SPI2, node->data_ptr[wm8753.offset++]);
-	}
-
-	if (wm8753.offset == node->data_size)
-	{
-		/* move to next node */
-		rt_uint16_t next_index;
-		
-		next_index = wm8753.read_index + 1;
-		if (next_index >= DATA_NODE_MAX) next_index = 0;
-
-		/* notify transmitted complete. */
-		if (wm8753.parent.tx_complete != RT_NULL)
-		{
-			wm8753.parent.tx_complete (&wm8753.parent, wm8753.data_list[wm8753.read_index].data_ptr);
-			rt_kprintf("-\n");
-		}
-
-		wm8753.offset = 0;
-		wm8753.read_index = next_index;
-		if (next_index == wm8753.put_index)
-		{
-			/* no data on the list, disable I2S interrupt */
-			SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, DISABLE);
-			
-			rt_kprintf("*\n");
-		}
-	}
+    struct wm8753_data_node* node;
+    node = &wm8753.data_list[wm8753.read_index]; /* get current data node */
+
+    if (SPI_I2S_GetITStatus(SPI2, SPI_I2S_IT_TXE) == SET)
+    {
+        SPI_I2S_SendData(SPI2, node->data_ptr[wm8753.offset++]);
+    }
+
+    if (wm8753.offset == node->data_size)
+    {
+        /* move to next node */
+        rt_uint16_t next_index;
+
+        next_index = wm8753.read_index + 1;
+        if (next_index >= DATA_NODE_MAX) next_index = 0;
+
+        /* notify transmitted complete. */
+        if (wm8753.parent.tx_complete != RT_NULL)
+        {
+            wm8753.parent.tx_complete (&wm8753.parent, wm8753.data_list[wm8753.read_index].data_ptr);
+            rt_kprintf("-\n");
+        }
+
+        wm8753.offset = 0;
+        wm8753.read_index = next_index;
+        if (next_index == wm8753.put_index)
+        {
+            /* no data on the list, disable I2S interrupt */
+            SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, DISABLE);
+
+            rt_kprintf("*\n");
+        }
+    }
 }
 
 void wm8753_dma_isr()
 {
-	/* switch to next buffer */
-	rt_uint16_t next_index;
-	void* data_ptr;
-	
-	next_index = wm8753.read_index + 1;
-	if (next_index >= DATA_NODE_MAX) next_index = 0;
-
-	/* save current data pointer */
-	data_ptr = wm8753.data_list[wm8753.read_index].data_ptr;
-
-	wm8753.read_index = next_index;
-	if (next_index != wm8753.put_index)
-	{
-		/* enable next dma request */
-		DMA_Configuration((rt_uint32_t)wm8753.data_list[wm8753.read_index].data_ptr, 
-			wm8753.data_list[wm8753.read_index].data_size);
-	}
-	else
-	{
-		rt_kprintf("*\n");
-	}
-
-	/* notify transmitted complete. */
-	if (wm8753.parent.tx_complete != RT_NULL)
-	{
-		wm8753.parent.tx_complete (&wm8753.parent, data_ptr);
-		// rt_kprintf("-\n");
-	}
+    /* switch to next buffer */
+    rt_uint16_t next_index;
+    void* data_ptr;
+
+    next_index = wm8753.read_index + 1;
+    if (next_index >= DATA_NODE_MAX) next_index = 0;
+
+    /* save current data pointer */
+    data_ptr = wm8753.data_list[wm8753.read_index].data_ptr;
+
+    wm8753.read_index = next_index;
+    if (next_index != wm8753.put_index)
+    {
+        /* enable next dma request */
+        DMA_Configuration((rt_uint32_t)wm8753.data_list[wm8753.read_index].data_ptr,
+                          wm8753.data_list[wm8753.read_index].data_size);
+    }
+    else
+    {
+        rt_kprintf("*\n");
+    }
+
+    /* notify transmitted complete. */
+    if (wm8753.parent.tx_complete != RT_NULL)
+    {
+        wm8753.parent.tx_complete (&wm8753.parent, data_ptr);
+        // rt_kprintf("-\n");
+    }
 }