本次PR涉及①BSP驱动新增②F103库更新③GCC、IAR适配及MDK更新④README文件及由更新驱动引起的脚本改动。 (#5638)

* 本次提交包括①BSP驱动新增②F103库更新③GCC、IAR适配及MDK更新④README文件及由更新驱动引起的脚本改动。
详情如下：
一、BSP驱动新增
这是本次PR的主要目的，现新增了如下BSP驱动：
ADC、DAC、RTC、PWM、HWTIMER、I2C、SPI和WDT等八个驱动文件。
二、F103库更新：
本次提交使用2022年3月初极海官网发布的最新F103库，主要增加了版权声明、USB驱动及其他代码调整。
三、编译器适配：
1、新增GCC编译支持，在ENV工具下编译能成功且输出的bin文件能够使开发板闪灯。
2、新增IAR工程支持。
3、由F103的SDK更新，MDK的工程也进行了相应更新。
四、其他
1、README文件做了修改，加入了scons编译后的jlink下载说明和官网链接。
2、Kconfig、SConscript脚本根据驱动更新做了修改。

* 格式化代码（AStyle + Formatting）

* 增加BSP APM版权声明

* 在ci添加当前bsp的路径，以能够验证gcc能否正常编译

* 路径的“\”改为“/”

.github/workflows/action.yml

@@ -31,6 +31,7 @@ jobs:
        legs:
          - {RTT_BSP: "acm32f0x0-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "apm32/apm32f103xe-minibroard", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"}

bsp/Copyright_Notice.md

@@ -20,6 +20,33 @@ Path:
 
 - bsp/acm32f0x0-nucleo/libraries
 
+### apm32
+
+bsp 列表：
+- apm32f103xe-minibroard
+
+------
+
+License: GEEHY SOFTWARE PACKAGE LICENSE
+
+Copyright: Copyright (C) 2020-2022 Geehy Semiconductor
+
+Path:
+
+- bsp\apm32\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver
+- bsp\apm32\libraries\APM32F10x_Library\Device
+- bsp\apm32\libraries\APM32F10x_Library\USB_Device_Lib
+
+------
+
+License: bsd-new
+
+Copyright (c) 2009-2018 Arm Limited
+
+Path:
+
+- bsp\apm32\libraries\APM32F10x_Library\CMSIS\Include
+
 ### apollo2
 
 License:  bsd-new

bsp/apm32/apm32f103xe-minibroard/README.md

@@ -17,17 +17,18 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO
 
 ![board](figures/APM32F103ZE.png)
 
+- 有关开发板和芯片的详情可至极海官网查阅。[官网开发板链接 ](https://www.geehy.com/support/apm32?id=192)
 
 
 该开发板常用 **板载资源** 如下：
 
-- MCU：APM32F103C8T6，主频 96MHz，512KB FLASH ，128KB RAM
+- MCU：APM32F103ZET6，主频 96MHz，512KB FLASH ，128KB RAM
 - 外部 RAM：无
 - 外部 FLASH：无
 - 常用外设
   - LED：2个，（黄色，PE5/PE6）
   - 按键：2个，K1（兼具唤醒功能，PA0），K2（PC13）
-- 常用接口：RS232转串口、、USB SLAVE
+- 常用接口：RS232转串口、USB SLAVE
 - 调试接口：标准 JTAG/SWD
 
 
@@ -42,6 +43,14 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO
 | **片上外设** | **支持情况** | **备注**                              |
 | GPIO         |     支持     | PA0, PA1... PG15 ---> PIN: 0, 1...143 |
 | UART         |     支持     | UART1/2                               |
+| ADC          |     支持     | ADC1/2/3                              |
+| DAC          |     支持     | DAC1                                  |
+| RTC          |     支持     |                                   |
+| TMR          |     支持     | TMR1/2/3/4/5/6/7/8                |
+| PWM          |     支持     | TMR3 ->CH1/2                      |
+| I2C          |     支持     | 软件I2C                           |
+| SPI          |     支持     | SPI1/2/3                          |
+| WDT          |     支持     | IWDT                              |
 
 ## 使用说明
 
@@ -57,11 +66,28 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO
 使用数据线连接开发板到 PC，打开电源开关。
 
 #### 编译下载
+- 方式一：MDK
 
-双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+   双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
 
 > 工程默认配置使用 J-Link 仿真器下载程序，在通过 J-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
 
+- 方式二：J-Flash下载
+
+  通过ENV工具的scons指令或MDK编译出bin文件后，再使用J-Flash工具将bin文件下载至开发板即可，大致步骤如下：
+
+##### 1、建立J-Flash工程
+
+![board](figures/JFlash_leader_01.png)
+
+##### 2、连接开发板
+
+![board](figures/JFlash_leader_02.png)
+##### 3、将bin文件拖至工程，起始地址设为0x8000000
+![board](figures/JFlash_leader_03.png)
+##### 4、点击下载
+![board](figures/JFlash_leader_04.png)
+
 #### 运行结果
 
 下载程序成功之后，系统会自动运行，LED 闪烁
@@ -71,7 +97,7 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO
 ```bash
  \ | /
 - RT -     Thread Operating System
- / | \     4.0.4 build Aug 20 2021
+ / | \     4.1.0 build Aug 20 2021
  2006 - 2021 Copyright by rt-thread team
 msh >
 ```
@@ -81,4 +107,6 @@ msh >
 
 ## 联系人信息
 
--[abbbcc ](https://gitee.com/abbbcc)
+-[abbbcc ](https://gitee.com/abbbcc)
+
+-[stevetong459 ](https://github.com/stevetong459)

bsp/apm32/apm32f103xe-minibroard/board/Kconfig

@@ -24,6 +24,155 @@ menu "On-chip Peripheral Drivers"
                 default y
 
         endif
+
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            config BSP_USING_ADC1
+                bool "Enable ADC1"
+                default n
+            config BSP_USING_ADC2
+                bool "Enable ADC2"
+                default n
+            config BSP_USING_ADC3
+                bool "Enable ADC3"
+                default n
+        endif
+
+    menuconfig BSP_USING_DAC
+        bool "Enable DAC"
+        default n
+        select RT_USING_DAC
+        if BSP_USING_DAC
+            config BSP_USING_DAC1
+                bool "Enable DAC1"
+                default n
+        endif
+
+    menuconfig BSP_USING_ONCHIP_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+        if BSP_USING_ONCHIP_RTC
+            choice
+                prompt "Select clock source"
+                default BSP_RTC_USING_LSE
+
+                config BSP_RTC_USING_LSE
+                    bool "RTC USING LSE"
+
+                config BSP_RTC_USING_LSI
+                    bool "RTC USING LSI"
+            endchoice
+        endif
+
+    menuconfig BSP_USING_I2C1
+        bool "Enable I2C1 BUS (software simulation)"
+        default n
+        select RT_USING_I2C
+        select RT_USING_I2C_BITOPS
+        select RT_USING_PIN
+        if BSP_USING_I2C1
+            config BSP_I2C1_SCL_PIN
+                int "i2c1 scl pin number"
+                range 0 63
+                default 22
+            config BSP_I2C1_SDA_PIN
+                int "I2C1 sda pin number"
+                range 0 63
+                default 23
+        endif
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI"
+        default n
+        select RT_USING_SPI
+        if BSP_USING_SPI
+            config BSP_USING_SPI1
+                bool "Enable SPI1"
+                default n
+
+            config BSP_USING_SPI2
+                bool "Enable SPI2"
+                default n
+
+            config BSP_USING_SPI3
+                bool "Enable SPI3"
+                default n
+        endif
+
+    menuconfig BSP_USING_TMR
+        bool "Enable Timer"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_TMR
+            config BSP_USING_TMR1
+                bool "Enable TMR1"
+                default n
+
+            config BSP_USING_TMR2
+                bool "Enable TMR2"
+                default n
+
+            config BSP_USING_TMR3
+                bool "Enable TMR3"
+                default n
+
+            config BSP_USING_TMR4
+                bool "Enable TMR4"
+                default n
+
+            config BSP_USING_TMR5
+                bool "Enable TMR5"
+                default n
+
+            config BSP_USING_TMR6
+                bool "Enable TMR6"
+                default n
+
+            config BSP_USING_TMR7
+                bool "Enable TMR7"
+                default n
+
+            config BSP_USING_TMR8
+                bool "Enable TMR8"
+                default n
+        endif
+
+    menuconfig BSP_USING_PWM
+        bool "Enable PWM"
+        default n
+        select RT_USING_PWM
+        if BSP_USING_PWM
+        menuconfig BSP_USING_PWM3
+            bool "Enable timer3 output pwm"
+            default n
+            if BSP_USING_PWM3
+                config BSP_USING_PWM3_CH1
+                    bool "Enable PWM3 channel1"
+                    default n
+
+                config BSP_USING_PWM3_CH2
+                    bool "Enable PWM3 channel2"
+                    default n
+
+                config BSP_USING_PWM3_CH3
+                    bool "Enable PWM3 channel3"
+                    default n
+
+                config BSP_USING_PWM3_CH4
+                    bool "Enable PWM3 channel4"
+                    default n
+            endif
+        endif
+
+    config BSP_USING_WDT
+        bool "Enable Watchdog Timer"
+        select RT_USING_WDT
+        default n
+
 endmenu
 
 endmenu

bsp/apm32/apm32f103xe-minibroard/board/SConscript

@@ -16,9 +16,15 @@ path =  [cwd]
 startup_path_prefix = SDK_LIB
 
 if rtconfig.CROSS_TOOL == 'keil':
-    src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s']
+    src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_hd.s']
+
+if rtconfig.CROSS_TOOL == 'iar':
+    src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s']
+
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s']
 
 # You can select chips from the list above
-CPPDEFINES = ['APM32F103xE']
+CPPDEFINES = ['APM32F10X_HD']
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
 Return('group')

bsp/apm32/apm32f103xe-minibroard/board/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2022, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -13,15 +13,15 @@
 void apm32_usart_init(void)
 {
     GPIO_Config_T GPIO_ConfigStruct;
-    
+
 #ifdef BSP_USING_UART1
     RCM_EnableAPB2PeriphClock((RCM_APB2_PERIPH_T)(RCM_APB2_PERIPH_GPIOA | RCM_APB2_PERIPH_USART1));
-    
+
     GPIO_ConfigStruct.mode = GPIO_MODE_AF_PP;
     GPIO_ConfigStruct.pin = GPIO_PIN_9;
     GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
     GPIO_Config(GPIOA, &GPIO_ConfigStruct);
-    
+
     GPIO_ConfigStruct.mode = GPIO_MODE_IN_PU;
     GPIO_ConfigStruct.pin = GPIO_PIN_10;
     GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
@@ -31,12 +31,12 @@ void apm32_usart_init(void)
 #ifdef BSP_USING_UART2
     RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA);
     RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_USART2);
-    
+
     GPIO_ConfigStruct.mode = GPIO_MODE_AF_PP;
     GPIO_ConfigStruct.pin = GPIO_PIN_2;
     GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
     GPIO_Config(GPIOA, &GPIO_ConfigStruct);
-    
+
     GPIO_ConfigStruct.mode = GPIO_MODE_IN_PU;
     GPIO_ConfigStruct.pin = GPIO_PIN_3;
     GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;

bsp/apm32/apm32f103xe-minibroard/board/board.h

@@ -1,11 +1,12 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2022, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       Notes
- * 2020-08-20     Abbcc        first version
+ * Date           Author         Notes
+ * 2020-08-20     Abbcc          first version
+ * 2022-03-04     stevetong459   Add head file of new driver
  */
 
 #ifndef __BOARD_H__
@@ -21,6 +22,27 @@
 #include "apm32f10x_eint.h"
 #include "apm32f10x_usart.h"
 
+#if defined(RT_USING_ADC)
+    #include "apm32f10x_adc.h"
+#endif
+#if defined(RT_USING_DAC)
+    #include "apm32f10x_dac.h"
+#endif
+#if defined(RT_USING_RTC)
+    #include "apm32f10x_rtc.h"
+    #include "apm32f10x_pmu.h"
+#endif
+#if defined(RT_USING_SPI)
+    #include "apm32f10x_spi.h"
+#endif
+#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM)
+    #include "apm32f10x_tmr.h"
+#endif
+#if defined(RT_USING_WDT)
+    #include "apm32f10x_iwdt.h"
+    #include "apm32f10x_wwdt.h"
+#endif
+
 #include "drv_common.h"
 #include "drv_gpio.h"
 

bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.icf

@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2001FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0400;
+define symbol __ICFEDIT_size_heap__   = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, last block CSTACK};

bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds

@@ -0,0 +1,141 @@
+/*
+ * linker script for APM32F10x with GNU ld
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */
+    DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack : 
+    {
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/apm32/apm32f103xe-minibroard/project.ewp

@@ -0,0 +1,2346 @@
+<project>
+  <fileVersion>3</fileVersion>
+  <configuration>
+    <name>rt-thread</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>31</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>rt-thread\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>rt-thread\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>rt-thread\List</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Automatic choice of formatter, without multibyte support.</state>
+        </option>
+        <option>
+          <name>Output description</name>
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+          <state />
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state />
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state />
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state />
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state />
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state />
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state />
+        </option>
+        <option>
+          <name>AsmNoLiteralPool</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>3</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state />
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions />
+        <cmdline />
+        <hasPrio>0</hasPrio>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data />
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild />
+        <postbuild />
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>###Unitialized###</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>lnk0t.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state />
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state />
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkThreadsSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogCallGraph</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile_AltDefault</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkEncInput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkEncOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkEncOutputBom</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkHeapSelect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLocaleSelect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkTrustzoneImportLibraryOut</name>
+          <state>###Unitialized###</state>
+        </option>
+        <option>
+          <name>OILinkExtraOption</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile2</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol2</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment2</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign2</name>
+          <state />
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state />
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data />
+    </settings>
+  </configuration>
+  <group>
+    <name>Applications</name>
+    <file>
+      <name>$PROJ_DIR$\applications\main.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Compiler</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\time.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\common\stdlib.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c</name>
+    </file>
+  </group>
+  <group>
+    <name>CPU</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3\cpuport.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3\context_iar.S</name>
+    </file>
+  </group>
+  <group>
+    <name>DeviceDrivers</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\misc\pin.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\serial\serial.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\completion.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\pipe.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Drivers</name>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\iar\startup_apm32f10x_hd.s</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\board\board.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\Drivers\drv_gpio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\Drivers\drv_usart.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\Drivers\drv_common.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Finsh</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\finsh\shell.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\finsh\msh.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\components\finsh\cmd.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Kernel</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\scheduler.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\mem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\components.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\mempool.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\kservice.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\ipc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\clock.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\object.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\timer.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\irq.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\idle.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\device.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\src\thread.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Libraries</name>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\system_apm32f10x.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_rcm.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_misc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_usart.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_eint.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_gpio.c</name>
+    </file>
+  </group>
+  <group>
+    <name>POSIX</name>
+  </group>
+  <group>
+    <name>utestcases</name>
+  </group>
+</project>

bsp/apm32/apm32f103xe-minibroard/project.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/apm32/apm32f103xe-minibroard/project.uvoptx

@@ -0,0 +1,805 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
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+      <bShared>0</bShared>
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+    <File>
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+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\ipc.c</PathWithFileName>
+      <FilenameWithoutPath>ipc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
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+      <tvExp>0</tvExp>
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+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\idle.c</PathWithFileName>
+      <FilenameWithoutPath>idle.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Libraries</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
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+      <tvExp>0</tvExp>
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+      <bDave2>0</bDave2>
+      <PathWithFileName>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\system_apm32f10x.c</PathWithFileName>
+      <FilenameWithoutPath>system_apm32f10x.c</FilenameWithoutPath>
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+      <tvExp>0</tvExp>
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+      <PathWithFileName>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_rcm.c</PathWithFileName>
+      <FilenameWithoutPath>apm32f10x_rcm.c</FilenameWithoutPath>
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+      <tvExpOptDlg>0</tvExpOptDlg>
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+      <PathWithFileName>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_gpio.c</PathWithFileName>
+      <FilenameWithoutPath>apm32f10x_gpio.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+</ProjectOpt>

bsp/apm32/apm32f103xe-minibroard/project.uvprojx

@@ -13,7 +13,7 @@
         <TargetCommonOption>
           <Device>APM32F103ZE</Device>
           <Vendor>Geehy</Vendor>
-          <PackID>Geehy.APM32F1xx_DFP.1.0.7</PackID>
+          <PackID>Geehy.APM32F1xx_DFP.1.0.8</PackID>
           <PackURL>https://www.geehy.com/uploads/tool/</PackURL>
           <Cpu>IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
           <FlashUtilSpec />
@@ -182,7 +182,6 @@
             <uocXRam>0</uocXRam>
             <RvdsVP>0</RvdsVP>
             <RvdsMve>0</RvdsMve>
-            <RvdsCdeCp>0</RvdsCdeCp>
             <hadIRAM2>0</hadIRAM2>
             <hadIROM2>0</hadIROM2>
             <StupSel>8</StupSel>
@@ -334,9 +333,9 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls />
-              <Define>USE_STDPERIPH_DRIVER, __RTTHREAD__, APM32F103xE, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND</Define>
+              <Define>USE_STDPERIPH_DRIVER, APM32F10X_HD, __RTTHREAD__, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND</Define>
               <Undefine />
-              <IncludePath>applications;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\extension;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc;..\..\..\examples\utest\testcases\kernel</IncludePath>
+              <IncludePath>applications;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\nogcc;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\examples\utest\testcases\kernel</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -349,7 +348,7 @@
             <NoWarn>0</NoWarn>
             <uSurpInc>0</uSurpInc>
             <useXO>0</useXO>
-            <ClangAsOpt>4</ClangAsOpt>
+            <uClangAs>0</uClangAs>
             <VariousControls>
               <MiscControls />
               <Define />
@@ -391,9 +390,9 @@
           <GroupName>Compiler</GroupName>
           <Files>
             <File>
-              <FileName>syscalls.c</FileName>
+              <FileName>libc_syms.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
+              <FilePath>..\..\..\components\libc\compilers\armlibc\libc_syms.c</FilePath>
             </File>
           </Files>
           <Files>
@@ -405,9 +404,9 @@
           </Files>
           <Files>
             <File>
-              <FileName>stdlib.c</FileName>
+              <FileName>syscalls.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\libc\compilers\common\stdlib.c</FilePath>
+              <FilePath>..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
             </File>
           </Files>
           <Files>
@@ -417,6 +416,13 @@
               <FilePath>..\..\..\components\libc\compilers\common\time.c</FilePath>
             </File>
           </Files>
+          <Files>
+            <File>
+              <FileName>stdlib.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\libc\compilers\common\stdlib.c</FilePath>
+            </File>
+          </Files>
         </Group>
         <Group>
           <GroupName>CPU</GroupName>
@@ -429,16 +435,16 @@
           </Files>
           <Files>
             <File>
-              <FileName>div0.c</FileName>
+              <FileName>backtrace.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
+              <FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>backtrace.c</FileName>
+              <FileName>div0.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
+              <FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
             </File>
           </Files>
           <Files>
@@ -460,65 +466,65 @@
           <GroupName>DeviceDrivers</GroupName>
           <Files>
             <File>
-              <FileName>completion.c</FileName>
+              <FileName>pin.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\ipc\completion.c</FilePath>
+              <FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>ringbuffer.c</FileName>
+              <FileName>serial.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
+              <FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>waitqueue.c</FileName>
+              <FileName>ringbuffer.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
+              <FilePath>..\..\..\components\drivers\src\ringbuffer.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>dataqueue.c</FileName>
+              <FileName>pipe.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
+              <FilePath>..\..\..\components\drivers\src\pipe.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>pipe.c</FileName>
+              <FileName>ringblk_buf.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
+              <FilePath>..\..\..\components\drivers\src\ringblk_buf.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>workqueue.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\ipc\workqueue.c</FilePath>
+              <FilePath>..\..\..\components\drivers\src\workqueue.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>ringblk_buf.c</FileName>
+              <FileName>dataqueue.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
+              <FilePath>..\..\..\components\drivers\src\dataqueue.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>pin.c</FileName>
+              <FileName>waitqueue.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
+              <FilePath>..\..\..\components\drivers\src\waitqueue.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>serial.c</FileName>
+              <FileName>completion.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
+              <FilePath>..\..\..\components\drivers\src\completion.c</FilePath>
             </File>
           </Files>
         </Group>
@@ -526,16 +532,16 @@
           <GroupName>Drivers</GroupName>
           <Files>
             <File>
-              <FileName>startup_apm32f10x_hd.s</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\ARM\startup_apm32f10x_hd.s</FilePath>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\board.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>board.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>board\board.c</FilePath>
+              <FileName>startup_apm32f10x_hd.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\arm\startup_apm32f10x_hd.s</FilePath>
             </File>
           </Files>
           <Files>
@@ -588,93 +594,93 @@
           <GroupName>Kernel</GroupName>
           <Files>
             <File>
-              <FileName>clock.c</FileName>
+              <FileName>thread.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\src\clock.c</FilePath>
+              <FilePath>..\..\..\src\thread.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>kservice.c</FileName>
+              <FileName>mempool.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\src\kservice.c</FilePath>
+              <FilePath>..\..\..\src\mempool.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>scheduler.c</FileName>
+              <FileName>timer.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\src\scheduler.c</FilePath>
+              <FilePath>..\..\..\src\timer.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>ipc.c</FileName>
+              <FileName>object.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\src\ipc.c</FilePath>
+              <FilePath>..\..\..\src\object.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>mem.c</FileName>
+              <FileName>clock.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\src\mem.c</FilePath>
+              <FilePath>..\..\..\src\clock.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>device.c</FileName>
+              <FileName>scheduler.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\src\device.c</FilePath>
+              <FilePath>..\..\..\src\scheduler.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>mempool.c</FileName>
+              <FileName>ipc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\src\mempool.c</FilePath>
+              <FilePath>..\..\..\src\ipc.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>components.c</FileName>
+              <FileName>mem.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\src\components.c</FilePath>
+              <FilePath>..\..\..\src\mem.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>thread.c</FileName>
+              <FileName>device.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\src\thread.c</FilePath>
+              <FilePath>..\..\..\src\device.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>object.c</FileName>
+              <FileName>kservice.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\src\object.c</FilePath>
+              <FilePath>..\..\..\src\kservice.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>idle.c</FileName>
+              <FileName>irq.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\src\idle.c</FilePath>
+              <FilePath>..\..\..\src\irq.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>timer.c</FileName>
+              <FileName>components.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\src\timer.c</FilePath>
+              <FilePath>..\..\..\src\components.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>irq.c</FileName>
+              <FileName>idle.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\src\irq.c</FilePath>
+              <FilePath>..\..\..\src\idle.c</FilePath>
             </File>
           </Files>
         </Group>

bsp/apm32/apm32f103xe-minibroard/template.ewp

@@ -0,0 +1,2114 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>rt-thread</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>General</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>31</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>ExePath</name>
+                    <state>rt-thread\Exe</state>
+                </option>
+                <option>
+                    <name>ObjPath</name>
+                    <state>rt-thread\Obj</state>
+                </option>
+                <option>
+                    <name>ListPath</name>
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+                    <state>.text</state>
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+                    <name>IccCppInlineSemantics</name>
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+                    <name>IccCmsis</name>
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+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoFill</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FillerByte</name>
+                    <state>0xFF</state>
+                </option>
+                <option>
+                    <name>FillerStart</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>FillerEnd</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>CrcSize</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcAlign</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcPoly</name>
+                    <state>0x11021</state>
+                </option>
+                <option>
+                    <name>CrcCompl</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcBitOrder</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkBufferedTerminalOutput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkStdoutInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIElfToolPostProcess</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptInline</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsAllow</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsForce</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptUseVfe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptForceVfe</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackAnalysisEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackControlFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkStackCallGraphFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkThreadsSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLocaleSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkTrustzoneImportLibraryOut</name>
+                    <state>###Unitialized###</state>
+                </option>
+                <option>
+                    <name>OILinkExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign2</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IARCHIVE</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>BILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+    </configuration>
+    <configuration>
+        <name>Release</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>0</debug>
+        <settings>
+            <name>General</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>31</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>ExePath</name>
+                    <state>Release\Exe</state>
+                </option>
+                <option>
+                    <name>ObjPath</name>
+                    <state>Release\Obj</state>
+                </option>
+                <option>
+                    <name>ListPath</name>
+                    <state>Release\List</state>
+                </option>
+                <option>
+                    <name>GEndianMode</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>Input description</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>Output description</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GOutputBinary</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGCoreOrChip</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelect</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelectSlave</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RTDescription</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OGProductVersion</name>
+                    <state>8.50.4.26131</state>
+                </option>
+                <option>
+                    <name>OGLastSavedByProductVersion</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GeneralEnableMisra</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVerbose</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGChipSelectEditMenu</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GenLowLevelInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GEndianModeBE</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGBufferedTerminalOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenStdoutInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules04</name>
+                    <version>0</version>
+                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+                </option>
+                <option>
+                    <name>RTConfigPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GBECoreSlave</name>
+                    <version>28</version>
+                    <state>38</state>
+                </option>
+                <option>
+                    <name>OGUseCmsis</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGUseCmsisDspLib</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibThreads</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CoreVariant</name>
+                    <version>28</version>
+                    <state>38</state>
+                </option>
+                <option>
+                    <name>GFPUDeviceSlave</name>
+                    <state>-</state>
+                </option>
+                <option>
+                    <name>FPU2</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>NrRegs</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>NEON</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GFPUCoreSlave2</name>
+                    <version>28</version>
+                    <state>38</state>
+                </option>
+                <option>
+                    <name>OGCMSISPackSelectDevice</name>
+                </option>
+                <option>
+                    <name>OgLibHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGLibAdditionalLocale</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenLocaleTags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GenLocaleDisplayOnly</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DSPExtension</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZone</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZoneModes</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ICCARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>36</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CCDefines</name>
+                    <state>NDEBUG</state>
+                </option>
+                <option>
+                    <name>CCPreprocFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocComments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocLine</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCListCFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMnemonics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMessages</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagSuppress</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagRemark</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagWarning</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagError</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCAllowList</name>
+                    <version>1</version>
+                    <state>11111110</state>
+                </option>
+                <option>
+                    <name>CCDebugInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IEndianMode</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLangConformance</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSignedPlainChar</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRequirePrototypes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagWarnAreErr</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCompilerRuntimeInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OutputFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLibConfigHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CompilerMisraOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIncludePath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCStdIncCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCodeSection</name>
+                    <state>.text</state>
+                </option>
+                <option>
+                    <name>IProcessorMode2</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptLevel</name>
+                    <state>3</state>
+                </option>
+                <option>
+                    <name>CCOptStrategy</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptLevelSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CompilerMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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+                    <state>0</state>
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+                <option>
+                    <name>CCPosIndRwpi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndNoDynInit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccLang</name>
+                    <state>0</state>
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+                <option>
+                    <name>IccCDialect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccAllowVLA</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccStaticDestr</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccCppInlineSemantics</name>
+                    <state>0</state>
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+                <option>
+                    <name>IccCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccFloatSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptimizationNoSizeConstraints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptStrategySlave</name>
+                    <version>0</version>
+                    <state>0</state>
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+                <option>
+                    <name>CCGuardCalls</name>
+                    <state>1</state>
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+                <option>
+                    <name>CCEncSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutput</name>
+                    <state>0</state>
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+                <option>
+                    <name>CCEncOutputBom</name>
+                    <state>1</state>
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+                <option>
+                    <name>CCEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccExceptions2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccRTTI2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OICompilerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCStackProtection</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>AARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>10</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
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+                    <state>1</state>
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+                    <name>AEndian</name>
+                    <state>1</state>
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+                    <state>1</state>
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+                <option>
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+                    <version>0</version>
+                    <state>0</state>
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+                <option>
+                    <name>AWarnEnable</name>
+                    <state>0</state>
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+                <option>
+                    <name>AWarnWhat</name>
+                    <state>0</state>
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+                <option>
+                    <name>AWarnOne</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ADebug</name>
+                    <state>0</state>
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+                <option>
+                    <name>AltRegisterNames</name>
+                    <state>0</state>
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+                <option>
+                    <name>ADefines</name>
+                    <state></state>
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+                <option>
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+                    <state>0</state>
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+                <option>
+                    <name>AListHeader</name>
+                    <state>1</state>
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+                <option>
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+                    <state>1</state>
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+                <option>
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+                <option>
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+                    <state>1</state>
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+                    <state>0</state>
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+                <option>
+                    <name>PageLength</name>
+                    <state>80</state>
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+                    <state>8</state>
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+                    <state>0</state>
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+                <option>
+                    <name>AXRefDual</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AOutputFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ALimitErrorsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsEdit</name>
+                    <state>100</state>
+                </option>
+                <option>
+                    <name>AIgnoreStdInclude</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AUserIncludes</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AExtraOptionsCheckV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AExtraOptionsV2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AsmNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>OBJCOPY</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OOCOutputFormat</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCOutputOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OOCOutputFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OOCCommandLineProducer</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCObjCopyEnable</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CUSTOM</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <extensions></extensions>
+                <cmdline></cmdline>
+                <hasPrio>0</hasPrio>
+            </data>
+        </settings>
+        <settings>
+            <name>BICOMP</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>1</archiveVersion>
+            <data>
+                <prebuild></prebuild>
+                <postbuild></postbuild>
+            </data>
+        </settings>
+        <settings>
+            <name>ILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>23</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>IlinkLibIOConfig</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>XLinkMisraHandler</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkInputFileSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOutputFile</name>
+                    <state>###Unitialized###</state>
+                </option>
+                <option>
+                    <name>IlinkDebugInfoEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkKeepSymbols</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkConfigDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkMapFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInitialization</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogModule</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogSection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogVeneer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile</name>
+                    <state>lnk0t.icf</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFileSlave</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkSuppressDiags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsRem</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsWarn</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsErr</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkWarningsAreErrors</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkUseExtraOptions</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkLowLevelInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAutoLibEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAdditionalLibs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkOverrideProgramEntryLabel</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabelSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoFill</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FillerByte</name>
+                    <state>0xFF</state>
+                </option>
+                <option>
+                    <name>FillerStart</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>FillerEnd</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>CrcSize</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcAlign</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcPoly</name>
+                    <state>0x11021</state>
+                </option>
+                <option>
+                    <name>CrcCompl</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcBitOrder</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkBufferedTerminalOutput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkStdoutInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIElfToolPostProcess</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptInline</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsAllow</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsForce</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptUseVfe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptForceVfe</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackAnalysisEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackControlFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkStackCallGraphFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkThreadsSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLocaleSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkTrustzoneImportLibraryOut</name>
+                    <state>###Unitialized###</state>
+                </option>
+                <option>
+                    <name>OILinkExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign2</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IARCHIVE</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>BILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+    </configuration>
+</project>

bsp/apm32/apm32f103xe-minibroard/template.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\template.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/apm32/apm32f103xe-minibroard/template.uvoptx

@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>0</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>4</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>Segger\JL2CM3.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U59701291 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512.FLM -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Source Group 1</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+  </Group>
+
+</ProjectOpt>

bsp/apm32/apm32f103xe-minibroard/template.uvprojx

@@ -16,7 +16,7 @@
         <TargetCommonOption>
           <Device>APM32F103ZE</Device>
           <Vendor>Geehy</Vendor>
-          <PackID>Geehy.APM32F1xx_DFP.1.0.7</PackID>
+          <PackID>Geehy.APM32F1xx_DFP.1.0.8</PackID>
           <PackURL>https://www.geehy.com/uploads/tool/</PackURL>
           <Cpu>IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
@@ -185,7 +185,6 @@
             <uocXRam>0</uocXRam>
             <RvdsVP>0</RvdsVP>
             <RvdsMve>0</RvdsMve>
-            <RvdsCdeCp>0</RvdsCdeCp>
             <hadIRAM2>0</hadIRAM2>
             <hadIROM2>0</hadIROM2>
             <StupSel>8</StupSel>
@@ -352,7 +351,7 @@
             <NoWarn>0</NoWarn>
             <uSurpInc>0</uSurpInc>
             <useXO>0</useXO>
-            <ClangAsOpt>4</ClangAsOpt>
+            <uClangAs>0</uClangAs>
             <VariousControls>
               <MiscControls></MiscControls>
               <Define></Define>

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h

@@ -3,21 +3,35 @@
  *
  * @brief       This file contains all the functions prototypes for the ADC firmware library
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_ADC_H
 #define __APM32F10X_ADC_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
-  extern "C" {
+extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -62,7 +76,7 @@ typedef enum
     ADC_EXT_TRIG_CONV_None            = ((uint32_t)0x000E0000),
 
     ADC_EXT_TRIG_CONV_TMR3_CC1        = ((uint32_t)0x00000000),
-    ADC_EXT_TRIG_CONV_TMR2_CC3        = ((uint32_t)0x00030000),
+    ADC_EXT_TRIG_CONV_TMR2_CC3        = ((uint32_t)0x00020000),
     ADC_EXT_TRIG_CONV_TMR8_CC1        = ((uint32_t)0x00060000),
     ADC_EXT_TRIG_CONV_TMR8_TRGO       = ((uint32_t)0x00080000),
     ADC_EXT_TRIG_CONV_TMR5_CC1        = ((uint32_t)0x000A0000),
@@ -110,15 +124,15 @@ typedef enum
  */
 typedef enum
 {
-    ADC_SAMPLE_TIME_1_5   = ((uint8_t)0x00),
-    ADC_SAMPLE_TIME_7_5   = ((uint8_t)0x01),
-    ADC_SAMPLE_TIME_13_5  = ((uint8_t)0x02),
-    ADC_SAMPLE_TIME_28_5  = ((uint8_t)0x03),
-    ADC_SAMPLE_TIME_41_5  = ((uint8_t)0x04),
-    ADC_SAMPLE_TIME_55_5  = ((uint8_t)0x05),
-    ADC_SAMPLE_TIME_71_5  = ((uint8_t)0x06),
-    ADC_SAMPLE_TIME_239_5 = ((uint8_t)0x07)
-} ADC_SAMPLE_TIME_T;
+    ADC_SAMPLETIME_1CYCLES5   = ((uint8_t)0x00),
+    ADC_SAMPLETIME_7CYCLES5   = ((uint8_t)0x01),
+    ADC_SAMPLETIME_13CYCLES5  = ((uint8_t)0x02),
+    ADC_SAMPLETIME_28CYCLES5  = ((uint8_t)0x03),
+    ADC_SAMPLETIME_41CYCLES5  = ((uint8_t)0x04),
+    ADC_SAMPLETIME_55CYCLES5  = ((uint8_t)0x05),
+    ADC_SAMPLETIME_71CYCLES5  = ((uint8_t)0x06),
+    ADC_SAMPLETIME_239CYCLES5 = ((uint8_t)0x07)
+} ADC_SAMPLETIME_T;
 
 /**
  * @brief    ADC external trigger sources for injected channels conversion
@@ -246,80 +260,80 @@ typedef struct
 */
 
 /** ADC reset and common configuration */
-void ADC_Reset(ADC_T* adc);
-void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig);
-void ADC_ConfigStructInit(ADC_Config_T* adcConfig);
-void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime);
-void ADC_Enable(ADC_T* adc);
-void ADC_Disable(ADC_T* adc);
+void ADC_Reset(ADC_T *adc);
+void ADC_Config(ADC_T *adc, ADC_Config_T *adcConfig);
+void ADC_ConfigStructInit(ADC_Config_T *adcConfig);
+void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
+void ADC_Enable(ADC_T *adc);
+void ADC_Disable(ADC_T *adc);
 
 /** ADC for DMA */
-void ADC_EnableDMA(ADC_T* adc);
-void ADC_DisableDMA(ADC_T* adc);
+void ADC_EnableDMA(ADC_T *adc);
+void ADC_DisableDMA(ADC_T *adc);
 
 /** ADC Calibration */
-void ADC_ResetCalibration(ADC_T* adc);
-uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc);
-void ADC_StartCalibration(ADC_T* adc);
-uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc);
+void ADC_ResetCalibration(ADC_T *adc);
+uint8_t ADC_ReadResetCalibrationStatus(ADC_T *adc);
+void ADC_StartCalibration(ADC_T *adc);
+uint8_t ADC_ReadCalibrationStartFlag(ADC_T *adc);
 
 /** ADC software start conversion */
-void ADC_EnableSoftwareStartConv(ADC_T* adc);
-void ADC_DisableSoftwareStartConv(ADC_T* adc);
-uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc);
+void ADC_EnableSoftwareStartConv(ADC_T *adc);
+void ADC_DisableSoftwareStartConv(ADC_T *adc);
+uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T *adc);
 
 /** ADC Discontinuous mode */
-void ADC_ConfigDiscModeChannel(ADC_T* adc, uint8_t number);
-void ADC_EnableDiscMode(ADC_T* adc);
-void ADC_DisableDiscMode(ADC_T* adc);
+void ADC_ConfigDiscMode(ADC_T *adc, uint8_t number);
+void ADC_EnableDiscMode(ADC_T *adc);
+void ADC_DisableDiscMode(ADC_T *adc);
 
 /** ADC External trigger conversion */
-void ADC_EnableExternalTrigConv(ADC_T* adc);
-void ADC_DisableExternalTrigConv(ADC_T* adc);
+void ADC_EnableExternalTrigConv(ADC_T *adc);
+void ADC_DisableExternalTrigConv(ADC_T *adc);
 
 /** ADC Conversion result */
-uint16_t ADC_ReadConversionValue(ADC_T* adc);
-uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc);
+uint16_t ADC_ReadConversionValue(ADC_T *adc);
+uint32_t ADC_ReadDualModeConversionValue(ADC_T *adc);
 
 /** ADC Automatic injected group */
-void ADC_EnableInjectedConv(ADC_T* adc);
-void ADC_DisableInjectedConv(ADC_T* adc);
-void ADC_EnableInjectedDiscMode(ADC_T* adc);
-void ADC_DisableInjectedDiscMode(ADC_T* adc);
+void ADC_EnableAutoInjectedConv(ADC_T *adc);
+void ADC_DisableAutoInjectedConv(ADC_T *adc);
+void ADC_EnableInjectedDiscMode(ADC_T *adc);
+void ADC_DisableInjectedDiscMode(ADC_T *adc);
 
 /** ADC External trigger for injected channels conversion */
-void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv);
-void ADC_EnableExternalTrigInjectedConv(ADC_T* adc);
-void ADC_DisableExternalTrigInjectedConv(ADC_T* adc);
+void ADC_ConfigExternalTrigInjectedConv(ADC_T *adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv);
+void ADC_EnableExternalTrigInjectedConv(ADC_T *adc);
+void ADC_DisableExternalTrigInjectedConv(ADC_T *adc);
 
 /** ADC Start of the injected channels conversion */
-void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc);
-void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc);
-uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc);
+void ADC_EnableSoftwareStartInjectedConv(ADC_T *adc);
+void ADC_DisableSoftwareStartInjectedConv(ADC_T *adc);
+uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T *adc);
 
 /** ADC injected channel */
-void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
-void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length);
-void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet);
-uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel);
+void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
+void ADC_ConfigInjectedSequencerLength(ADC_T *adc, uint8_t length);
+void ADC_ConfigInjectedOffset(ADC_T *adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet);
+uint16_t ADC_ReadInjectedConversionValue(ADC_T *adc, ADC_INJEC_CHANNEL_T channel);
 
 /** ADC analog watchdog */
-void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog);
-void ADC_DisableAnalogWatchdog(ADC_T* adc);
-void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold);
-void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel);
+void ADC_EnableAnalogWatchdog(ADC_T *adc, uint32_t analogWatchdog);
+void ADC_DisableAnalogWatchdog(ADC_T *adc);
+void ADC_ConfigAnalogWatchdogThresholds(ADC_T *adc, uint16_t highThreshold, uint16_t lowThreshold);
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T *adc, uint8_t channel);
 
 /** ADC temperature sensor */
-void ADC_EnableTempSensorVrefint(ADC_T* adc);
-void ADC_DisableTempSensorVrefint(ADC_T* adc);
+void ADC_EnableTempSensorVrefint(ADC_T *adc);
+void ADC_DisableTempSensorVrefint(ADC_T *adc);
 
 /** Interrupt and flag */
-void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt);
-void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt);
-uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag);
-void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag);
-uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T interrupt);
-void ADC_ClearIntFlag(ADC_T* adc, uint16_t interrupt);
+void ADC_EnableInterrupt(ADC_T *adc, uint16_t interrupt);
+void ADC_DisableInterrupt(ADC_T *adc, uint16_t interrupt);
+uint8_t ADC_ReadStatusFlag(ADC_T *adc, ADC_FLAG_T flag);
+void ADC_ClearStatusFlag(ADC_T *adc, uint8_t flag);
+uint8_t ADC_ReadIntFlag(ADC_T *adc, ADC_INT_T flag);
+void ADC_ClearIntFlag(ADC_T *adc, uint16_t flag);
 
 /**@} end of group ADC_Fuctions*/
 /**@} end of group ADC_Driver*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h

@@ -3,21 +3,35 @@
  *
  * @brief       This file contains all the functions prototypes for the BAKPR firmware library.
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_BAKPR_H
 #define __APM32F10X_BAKPR_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -125,7 +139,7 @@ uint8_t BAKPR_ReadIntFlag(void);
 void BAKPR_ClearIntFlag(void);
 
 /**@} end of group BAKPR_Fuctions*/
-/**@} end of group BAKPR_Driver */
+/**@} end of group BAKPR_Driver*/
 /**@} end of group Peripherals_Library*/
 
 #ifdef __cplusplus

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h

@@ -1,23 +1,37 @@
 /*!
- * @file       apm32f10x_can.h
+ * @file        apm32f10x_can.h
  *
- * @brief      This file contains all the functions prototypes for the CAN firmware library
+ * @brief       This file contains all the functions prototypes for the CAN firmware library
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_CAN_H
 #define __APM32F10X_CAN_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -35,10 +49,10 @@ extern "C" {
  */
 typedef enum
 {
-    CAN_MODE_NORMAL          = ((uint8_t)00),  //!< normal mode
-    CAN_MODE_LOOPBACK        = ((uint8_t)01),  //!< loopback mode
-    CAN_MODE_SILENT          = ((uint8_t)02),  //!< silent mode
-    CAN_MODE_SILENT_LOOPBACK = ((uint8_t)03),  //!< loopback combined with silent mode
+    CAN_MODE_NORMAL          = ((uint8_t)0x00),  //!< normal mode
+    CAN_MODE_LOOPBACK        = ((uint8_t)0x01),  //!< loopback mode
+    CAN_MODE_SILENT          = ((uint8_t)0x02),  //!< silent mode
+    CAN_MODE_SILENT_LOOPBACK = ((uint8_t)0x03)   //!< loopback combined with silent mode
 } CAN_MODE_T;
 
 /**
@@ -46,10 +60,10 @@ typedef enum
  */
 typedef enum
 {
-    CAN_SJW_1 = ((uint8_t)00),  //!< 1 time quantum
-    CAN_SJW_2 = ((uint8_t)01),  //!< 2 time quantum
-    CAN_SJW_3 = ((uint8_t)02),  //!< 3 time quantum
-    CAN_SJW_4 = ((uint8_t)03)   //!< 4 time quantum
+    CAN_SJW_1 = ((uint8_t)0x00),  //!< 1 time quantum
+    CAN_SJW_2 = ((uint8_t)0x01),  //!< 2 time quantum
+    CAN_SJW_3 = ((uint8_t)0x02),  //!< 3 time quantum
+    CAN_SJW_4 = ((uint8_t)0x03)   //!< 4 time quantum
 } CAN_SJW_T;
 
 /**
@@ -87,7 +101,7 @@ typedef enum
     CAN_TIME_SEGMENT2_5 = (uint8_t)0x04,     //!< 5  time quanta
     CAN_TIME_SEGMENT2_6 = (uint8_t)0x05,     //!< 6  time quanta
     CAN_TIME_SEGMENT2_7 = (uint8_t)0x06,     //!< 7  time quanta
-    CAN_TIME_SEGMENT2_8 = (uint8_t)0x07,     //!< 8  time quanta
+    CAN_TIME_SEGMENT2_8 = (uint8_t)0x07      //!< 8  time quanta
 } CAN_TIME_SEGMENT2_T;
 
 /**
@@ -96,7 +110,7 @@ typedef enum
 typedef enum
 {
     CAN_FILTER_FIFO_0 = ((uint8_t)0x00),     //!< filter FIFO 0
-    CAN_FILTER_FIFO_1 = ((uint8_t)0x01),     //!< filter FIFO 1
+    CAN_FILTER_FIFO_1 = ((uint8_t)0x01)      //!< filter FIFO 1
 } CAN_FILTER_FIFO_T;
 
 /**
@@ -104,8 +118,8 @@ typedef enum
  */
 typedef enum
 {
-    CAN_FILTER_MODE_IDMASK = ((uint8_t)00),  //!< identifier/mask mode
-    CAN_FILTER_MODE_IDLIST = ((uint8_t)01)   //!< identifier list mode
+    CAN_FILTER_MODE_IDMASK = ((uint8_t)0x00),//!< identifier/mask mode
+    CAN_FILTER_MODE_IDLIST = ((uint8_t)0x01) //!< identifier list mode
 } CAN_FILTER_MODE_T;
 
 /**
@@ -114,7 +128,7 @@ typedef enum
 typedef enum
 {
     CAN_FILTER_SCALE_16BIT = ((uint8_t)0x00), //!< Two 16-bit filters
-    CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01), //!< One 32-bit filter
+    CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01)  //!< One 32-bit filter
 } CAN_FILTER_SCALE_T;
 
 /**
@@ -142,7 +156,7 @@ typedef enum
 {
     CAN_TX_MAILBIX_0 = ((uint8_t)0x00), //!< Tx mailbox0
     CAN_TX_MAILBIX_1 = ((uint8_t)0x01), //!< Tx mailbox1
-    CAN_TX_MAILBIX_2 = ((uint8_t)0x02), //!< Tx mailbox2
+    CAN_TX_MAILBIX_2 = ((uint8_t)0x02)  //!< Tx mailbox2
 } CAN_TX_MAILBIX_T;
 
 /**
@@ -151,7 +165,7 @@ typedef enum
 typedef enum
 {
     CAN_RX_FIFO_0 = ((uint8_t)0x00), //!< receive FIFO 0
-    CAN_RX_FIFO_1 = ((uint8_t)0x01), //!< receive FIFO 1
+    CAN_RX_FIFO_1 = ((uint8_t)0x01)  //!< receive FIFO 1
 } CAN_RX_FIFO_T;
 
 /**
@@ -159,9 +173,9 @@ typedef enum
  */
 typedef enum
 {
-    CAN_OPERATING_MODE_INIT   = ((uint8_t)00), //!< Initialization mode
-    CAN_OPERATING_MODE_NORMAL = ((uint8_t)01), //!< Normal mode
-    CAN_OPERATING_MODE_SLEEP  = ((uint8_t)02), //!< sleep mode
+    CAN_OPERATING_MODE_INIT   = ((uint8_t)0x00), //!< Initialization mode
+    CAN_OPERATING_MODE_NORMAL = ((uint8_t)0x01), //!< Normal mode
+    CAN_OPERATING_MODE_SLEEP  = ((uint8_t)0x02)  //!< sleep mode
 } CAN_OPERATING_MODE_T;
 
 /**
@@ -223,7 +237,6 @@ typedef enum
  */
 typedef struct
 {
-    uint8_t      timeTrigComMode;     //!< Enable or disable the time triggered communication mode.
     uint8_t      autoBusOffManage;    //!< Enable or disable the automatic bus-off management.
     uint8_t      autoWakeUpMode;      //!< Enable or disable the automatic wake-up mode.
     uint8_t      nonAutoRetran;       //!< Enable or disable the non-automatic retransmission mode.
@@ -249,7 +262,7 @@ typedef struct
     CAN_RTXR_T          remoteTxReq;
     uint8_t             dataLengthCode;//!< Specifies the data length code.       It can be 0 to 8.
     uint8_t             data[8];       //!< Specifies the data to be transmitted. It can be 0 to 0xFF.
-} CAN_TX_MESSAGE_T;
+} CAN_TxMessage_T;
 
 /**
  * @brief  CAN Rx message structure definition
@@ -263,7 +276,7 @@ typedef struct
     uint8_t             dataLengthCode;  //!< Specifies the data length code.       It can be 0 to 8.
     uint8_t             data[8];         //!< Specifies the data to be transmitted. It can be 0 to 0xFF.
     uint8_t             filterMatchIndex;//!< Specifies the filter match index.     It can be 0 to 0xFF.
-} CAN_RX_MESSAGE_T;
+} CAN_RxMessage_T;
 
 /**
  * @brief     CAN filter config structure definition
@@ -279,7 +292,7 @@ typedef struct
     CAN_FILTER_FIFO_T   filterFIFO;
     CAN_FILTER_MODE_T   filterMode;
     CAN_FILTER_SCALE_T  filterScale;
-} CAN_FILTER_CONFIG_T;
+} CAN_FilterConfig_T;
 
 /**@} end of group CAN_Structure*/
 
@@ -289,45 +302,44 @@ typedef struct
 */
 
 /** CAN reset and configuration */
-void CAN_Reset(CAN_T* can);
-uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig);
-void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig);
-void CAN_ConfigStructInit(CAN_Config_T* canConfig);
-void CAN_EnableDBGFreeze(CAN_T* can);
-void CAN_DisableDBGFreeze(CAN_T* can);
-void CAN_EnableTTCComMode(CAN_T* can);
-void CAN_DisableTTCComMode(CAN_T* can);
+void CAN_Reset(CAN_T *can);
+uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig);
+void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig);
+void CAN_ConfigStructInit(CAN_Config_T *canConfig);
+void CAN_EnableDBGFreeze(CAN_T *can);
+void CAN_DisableDBGFreeze(CAN_T *can);
+void CAN_SlaveStartBank(CAN_T *can, uint8_t bankNum);
 
 /** CAN frames transmit */
-uint8_t CAN_TxMessage(CAN_T* can, CAN_TX_MESSAGE_T* TxMessage);
-uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox);
-void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox);
+uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage);
+uint8_t CAN_TxMessageStatus(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox);
+void CAN_CancelTxMailbox(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox);
 
 /** CAN frames receive */
-void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RX_MESSAGE_T* RxMessage);
-void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber);
-uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber);
+void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMessage);
+void CAN_ReleaseFIFO(CAN_T *can, CAN_RX_FIFO_T FIFONumber);
+uint8_t CAN_PendingMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber);
 
 /** CAN operation modes */
-uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode);
-uint8_t CAN_SleepMode(CAN_T* can);
-uint8_t CAN_WakeUpMode(CAN_T* can);
+uint8_t CAN_OperatingMode(CAN_T *can, CAN_OPERATING_MODE_T operatingMode);
+uint8_t CAN_SleepMode(CAN_T *can);
+uint8_t CAN_WakeUpMode(CAN_T *can);
 
 /** CAN bus error management */
-uint8_t CAN_ReadLastErrorCode(CAN_T* can);
-uint8_t CAN_ReadRxErrorCounter(CAN_T* can);
-uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can);
+uint8_t CAN_ReadLastErrorCode(CAN_T *can);
+uint8_t CAN_ReadRxErrorCounter(CAN_T *can);
+uint8_t CAN_ReadLSBTxErrorCounter(CAN_T *can);
 
 /** CAN interrupt and flag */
-void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupt);
-void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupt);
-uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag);
-void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag);
-uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag);
-void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag);
+void CAN_EnableInterrupt(CAN_T *can, uint32_t interrupt);
+void CAN_DisableInterrupt(CAN_T *can, uint32_t interrupt);
+uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag);
+void CAN_ClearStatusFlag(CAN_T *can, CAN_FLAG_T flag);
+uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag);
+void CAN_ClearIntFlag(CAN_T *can, CAN_INT_T flag);
 
 /**@} end of group CAN_Fuctions*/
-/**@} end of group CAN_Driver */
+/**@} end of group CAN_Driver*/
 /**@} end of group Peripherals_Library*/
 
 #ifdef __cplusplus

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h

@@ -1,23 +1,37 @@
 /*!
- * @file       apm32f10x_crc.h
+ * @file        apm32f10x_crc.h
  *
- * @brief      This file contains all the functions prototypes for the CRC firmware library
+ * @brief       This file contains all the functions prototypes for the CRC firmware library
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_CRC_H
 #define __APM32F10X_CRC_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -41,7 +55,7 @@ void CRC_WriteIDRegister(uint8_t inData);
 uint8_t CRC_ReadIDRegister(void);
 
 /**@} end of group CRC_Fuctions*/
-/**@} end of group CRC_Driver */
+/**@} end of group CRC_Driver*/
 /**@} end of group Peripherals_Library*/
 
 #ifdef __cplusplus

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h

@@ -3,21 +3,35 @@
  *
  * @brief       This file contains all the functions prototypes for the DAC firmware library
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_DAC_H
 #define __APM32F10X_DAC_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -37,7 +51,7 @@ typedef enum
 {
     DAC_CHANNEL_1 = 0x00000000,
     DAC_CHANNEL_2 = 0x00000010
-}DAC_CHANNEL_T;
+} DAC_CHANNEL_T;
 
 /**
  * @brief    DAC trigger selection
@@ -53,7 +67,7 @@ typedef enum
     DAC_TRIGGER_TMR4_TRGO  = 0x0000002C,
     DAC_TRIGGER_EINT9      = 0x00000034,
     DAC_TRIGGER_SOFT       = 0x0000003C
-}DAC_TRIGGER_T;
+} DAC_TRIGGER_T;
 
 /**
  * @brief    DAC wave generation
@@ -63,7 +77,7 @@ typedef enum
     DAC_WAVE_GENERATION_NONE     = 0x00000000,
     DAC_WAVE_GENERATION_NOISE    = 0x00000040,
     DAC_WAVE_GENERATION_TRIANGLE = 0x00000080
-}DAC_WAVE_GENERATION_T;
+} DAC_WAVE_GENERATION_T;
 
 /**
  * @brief    DAC channelx mask/amplitude selector
@@ -71,31 +85,31 @@ typedef enum
 typedef enum
 {
     DAC_LFSR_MASK_BIT11_1  = 0x00000000, //!< Mask bit[11:1] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_2  = 0x00001000, //!< Mask bit[11:2] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_3  = 0x00002000, //!< Mask bit[11:3] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_4  = 0x00003000, //!< Mask bit[11:4] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_5  = 0x00004000, //!< Mask bit[11:5] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_6  = 0x00005000, //!< Mask bit[11:6] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_7  = 0x00006000, //!< Mask bit[11:7] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_8  = 0x00007000, //!< Mask bit[11:8] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_9  = 0x00008000, //!< Mask bit[11:9] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_10 = 0x00009000, //!< Mask bit[11:10] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11    = 0x0000A000, //!< Mask bit11 of LFSR for noise wave generation
-    DAC_LFSR_MASK_NONE     = 0x0000B000, //!< Mask none bit of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_2  = 0x00000100, //!< Mask bit[11:2] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_3  = 0x00000200, //!< Mask bit[11:3] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_4  = 0x00000300, //!< Mask bit[11:4] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_5  = 0x00000400, //!< Mask bit[11:5] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_6  = 0x00000500, //!< Mask bit[11:6] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_7  = 0x00000600, //!< Mask bit[11:7] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_8  = 0x00000700, //!< Mask bit[11:8] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_9  = 0x00000800, //!< Mask bit[11:9] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_10 = 0x00000900, //!< Mask bit[11:10] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11    = 0x00000A00, //!< Mask bit11 of LFSR for noise wave generation
+    DAC_LFSR_MASK_NONE     = 0x00000B00, //!< Mask none bit of LFSR for noise wave generation
 
     DAC_TRIANGLE_AMPLITUDE_1    = 0x00000000, //!< Triangle amplitude equal to 1
-    DAC_TRIANGLE_AMPLITUDE_3    = 0x00001000, //!< Triangle amplitude equal to 3
-    DAC_TRIANGLE_AMPLITUDE_7    = 0x00002000, //!< Triangle amplitude equal to 7
-    DAC_TRIANGLE_AMPLITUDE_15   = 0x00003000, //!< Triangle amplitude equal to 15
-    DAC_TRIANGLE_AMPLITUDE_31   = 0x00004000, //!< Triangle amplitude equal to 31
-    DAC_TRIANGLE_AMPLITUDE_63   = 0x00005000, //!< Triangle amplitude equal to 63
-    DAC_TRIANGLE_AMPLITUDE_127  = 0x00006000, //!< Triangle amplitude equal to 127
-    DAC_TRIANGLE_AMPLITUDE_255  = 0x00007000, //!< Triangle amplitude equal to 255
-    DAC_TRIANGLE_AMPLITUDE_511  = 0x00008000, //!< Triangle amplitude equal to 511
-    DAC_TRIANGLE_AMPLITUDE_1023 = 0x00009000, //!< Triangle amplitude equal to 1023
-    DAC_TRIANGLE_AMPLITUDE_2047 = 0x0000A000, //!< Triangle amplitude equal to 2047
-    DAC_TRIANGLE_AMPLITUDE_4095 = 0x0000B000  //!< Triangle amplitude equal to 4095
-}DAC_MASK_AMPLITUDE_SEL_T;
+    DAC_TRIANGLE_AMPLITUDE_3    = 0x00000100, //!< Triangle amplitude equal to 3
+    DAC_TRIANGLE_AMPLITUDE_7    = 0x00000200, //!< Triangle amplitude equal to 7
+    DAC_TRIANGLE_AMPLITUDE_15   = 0x00000300, //!< Triangle amplitude equal to 15
+    DAC_TRIANGLE_AMPLITUDE_31   = 0x00000400, //!< Triangle amplitude equal to 31
+    DAC_TRIANGLE_AMPLITUDE_63   = 0x00000500, //!< Triangle amplitude equal to 63
+    DAC_TRIANGLE_AMPLITUDE_127  = 0x00000600, //!< Triangle amplitude equal to 127
+    DAC_TRIANGLE_AMPLITUDE_255  = 0x00000700, //!< Triangle amplitude equal to 255
+    DAC_TRIANGLE_AMPLITUDE_511  = 0x00000800, //!< Triangle amplitude equal to 511
+    DAC_TRIANGLE_AMPLITUDE_1023 = 0x00000900, //!< Triangle amplitude equal to 1023
+    DAC_TRIANGLE_AMPLITUDE_2047 = 0x00000A00, //!< Triangle amplitude equal to 2047
+    DAC_TRIANGLE_AMPLITUDE_4095 = 0x00000B00  //!< Triangle amplitude equal to 4095
+} DAC_MASK_AMPLITUDE_SEL_T;
 
 /**
  * @brief    DAC output buffer
@@ -104,7 +118,7 @@ typedef enum
 {
     DAC_OUTPUT_BUFFER_ENBALE  = 0x00000000,
     DAC_OUTPUT_BUFFER_DISABLE = 0x00000002
-}DAC_OUTPUT_BUFFER_T;
+} DAC_OUTPUT_BUFFER_T;
 
 /**
  * @brief    DAC data align
@@ -114,7 +128,7 @@ typedef enum
     DAC_ALIGN_12BIT_R = 0x00000000,
     DAC_ALIGN_12BIT_L = 0x00000004,
     DAC_ALIGN_8BIT_R  = 0x00000008
-}DAC_ALIGN_T;
+} DAC_ALIGN_T;
 
 /**@} end of group DAC_Enumerations*/
 
@@ -132,7 +146,7 @@ typedef struct
     DAC_OUTPUT_BUFFER_T         outputBuffer;
     DAC_WAVE_GENERATION_T       waveGeneration;
     DAC_MASK_AMPLITUDE_SEL_T    maskAmplitudeSelect;
-}DAC_ConfigStruct_T;
+} DAC_Config_T;
 
 /**@} end of group DAC_Structure*/
 
@@ -143,8 +157,8 @@ typedef struct
 
 /** DAC Reset and Configuration */
 void DAC_Reset(void);
-void DAC_Config(uint32_t channel, DAC_ConfigStruct_T* configStruct);
-void DAC_ConfigStructInit(DAC_ConfigStruct_T* configStruct);
+void DAC_Config(uint32_t channel, DAC_Config_T *dacConfig);
+void DAC_ConfigStructInit(DAC_Config_T *dacConfig);
 void DAC_Enable(DAC_CHANNEL_T channel);
 void DAC_Disable(DAC_CHANNEL_T channel);
 
@@ -171,7 +185,7 @@ void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1
 uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel);
 
 /**@} end of group DAC_Fuctions*/
-/**@} end of group DAC_Driver */
+/**@} end of group DAC_Driver*/
 /**@} end of group Peripherals_Library*/
 
 #ifdef __cplusplus

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h

@@ -3,21 +3,35 @@
  *
  * @brief       This file contains all the functions prototypes for the DBUGMCU firmware library
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_DBGMCU_H
 #define __APM32F10X_DBGMCU_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -73,7 +87,7 @@ void DBGMCU_Enable(uint32_t periph);
 void DBGMCU_Disable(uint32_t periph);
 
 /**@} end of group DBGMCU_Fuctions*/
-/**@} end of group DBGMCU_Driver */
+/**@} end of group DBGMCU_Driver*/
 /**@} end of group Peripherals_Library*/
 
 #ifdef __cplusplus

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h

@@ -1,23 +1,37 @@
 /*!
- * @file       apm32f10x_dma.h
+ * @file        apm32f10x_dma.h
  *
- * @brief      This file contains all the functions prototypes for the DMA firmware library
+ * @brief       This file contains all the functions prototypes for the DMA firmware library
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_DMA_H
 #define __APM32F10X_DMA_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -173,7 +187,7 @@ typedef enum
 } DMA_FLAG_T;
 
 /**
- * @brief   DMA Flag
+ * @brief DMA Interrupt Flag
  */
 typedef enum
 {
@@ -262,8 +276,8 @@ typedef struct
 
 /** Reset and configuration */
 void DMA_Reset(DMA_Channel_T *channel);
-void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig);
-void DMA_ConfigStructInit( DMA_Config_T* dmaConfig);
+void DMA_Config(DMA_Channel_T *channel, DMA_Config_T *dmaConfig);
+void DMA_ConfigStructInit(DMA_Config_T *dmaConfig);
 void DMA_Enable(DMA_Channel_T *channel);
 void DMA_Disable(DMA_Channel_T *channel);
 
@@ -280,7 +294,7 @@ uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag);
 void DMA_ClearIntFlag(uint32_t flag);
 
 /**@} end of group DMA_Fuctions*/
-/**@} end of group DMA_Driver */
+/**@} end of group DMA_Driver*/
 /**@} end of group Peripherals_Library*/
 
 #ifdef __cplusplus

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h

@@ -3,20 +3,35 @@
  *
  * @brief       This file contains all the prototypes,enumeration and macros for the DMC peripheral
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
+
 #ifndef __APM32F10X_DMC_H
 #define __APM32F10X_DMC_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -37,7 +52,7 @@ typedef enum
 {
     DMC_BANK_WIDTH_1,
     DMC_BANK_WIDTH_2
-}DMC_BANK_WIDTH_T;
+} DMC_BANK_WIDTH_T;
 
 /**
  * @brief   Row Address Width
@@ -50,7 +65,7 @@ typedef enum
     DMC_ROW_WIDTH_14,
     DMC_ROW_WIDTH_15,
     DMC_ROW_WIDTH_16
-}DMC_ROW_WIDTH_T;
+} DMC_ROW_WIDTH_T;
 
 /**
  * @brief   Column Address Width
@@ -65,7 +80,7 @@ typedef enum
     DMC_COL_WIDTH_13,
     DMC_COL_WIDTH_14,
     DMC_COL_WIDTH_15
-}DMC_COL_WIDTH_T;
+} DMC_COL_WIDTH_T;
 
 /**
  * @brief   CAS Latency Select
@@ -76,7 +91,7 @@ typedef enum
     DMC_CAS_LATENCY_2,
     DMC_CAS_LATENCY_3,
     DMC_CAS_LATENCY_4
-}DMC_CAS_LATENCY_T;
+} DMC_CAS_LATENCY_T;
 
 /**
  * @brief   RAS Minimun Time Select
@@ -99,7 +114,7 @@ typedef enum
     DMC_RAS_MINIMUM_14,
     DMC_RAS_MINIMUM_15,
     DMC_RAS_MINIMUM_16
-}DMC_RAS_MINIMUM_T;
+} DMC_RAS_MINIMUM_T;
 
 /**
  * @brief   RAS To CAS Delay Time Select
@@ -114,7 +129,7 @@ typedef enum
     DMC_DELAY_TIME_6,
     DMC_DELAY_TIME_7,
     DMC_DELAY_TIME_8
-}DMC_DELAY_TIME_T;
+} DMC_DELAY_TIME_T;
 
 /**
  * @brief   Precharge Period Select
@@ -129,10 +144,10 @@ typedef enum
     DMC_PRECHARGE_6,
     DMC_PRECHARGE_7,
     DMC_PRECHARGE_8
-}DMC_PRECHARGE_T;
+} DMC_PRECHARGE_T;
 
 /**
- * @brief   Last Data Next Precharge For Write Time Select 
+ * @brief   Last Data Next Precharge For Write Time Select
  */
 typedef enum
 {
@@ -140,7 +155,7 @@ typedef enum
     DMC_NEXT_PRECHARGE_2,
     DMC_NEXT_PRECHARGE_3,
     DMC_NEXT_PRECHARGE_4
-}DMC_NEXT_PRECHARGE_T;
+} DMC_NEXT_PRECHARGE_T;
 
 /**
  * @brief   Auto-Refresh Period Select
@@ -163,7 +178,7 @@ typedef enum
     DMC_AUTO_REFRESH_14,
     DMC_AUTO_REFRESH_15,
     DMC_AUTO_REFRESH_16,
-}DMC_AUTO_REFRESH_T;
+} DMC_AUTO_REFRESH_T;
 
 /**
  * @brief   Active-to-active Command Period Select
@@ -186,7 +201,7 @@ typedef enum
     DMC_ATA_CMD_14,
     DMC_ATA_CMD_15,
     DMC_ATA_CMD_16,
-}DMC_ATA_CMD_T;
+} DMC_ATA_CMD_T;
 
 /**
  * @brief   Clock PHASE
@@ -195,7 +210,7 @@ typedef enum
 {
     DMC_CLK_PHASE_NORMAL,
     DMC_CLK_PHASE_REVERSE
-}DMC_CLK_PHASE_T;
+} DMC_CLK_PHASE_T;
 
 /**
  * @brief   DMC Memory Size
@@ -216,10 +231,10 @@ typedef enum
     DMC_MEMORY_SIZE_64MB,
     DMC_MEMORY_SIZE_128MB,
     DMC_MEMORY_SIZE_256MB,
-}DMC_MEMORY_SIZE_T;
+} DMC_MEMORY_SIZE_T;
 
 /**
- * @brief    Open Banks Of Number 
+ * @brief    Open Banks Of Number
  */
 typedef enum
 {
@@ -239,7 +254,7 @@ typedef enum
     DMC_BANK_NUMBER_14,
     DMC_BANK_NUMBER_15,
     DMC_BANK_NUMBER_16,
-}DMC_BANK_NUMBER_T;
+} DMC_BANK_NUMBER_T;
 
 /**
  * @brief   Full refresh type
@@ -248,7 +263,7 @@ typedef enum
 {
     DMC_REFRESH_ROW_ONE,        //!< Refresh one row
     DMC_REFRESH_ROW_ALL,        //!< Refresh all row
-}DMC_REFRESH_T;
+} DMC_REFRESH_T;
 
 /**
  * @brief   Precharge type
@@ -257,8 +272,16 @@ typedef enum
 {
     DMC_PRECHARGE_IM,        //!< Immediate precharge
     DMC_PRECHARGE_DELAY,     //!< Delayed precharge
-}DMC_PRECHARE_T;
+} DMC_PRECHARE_T;
 
+/**
+ * @brief WRAP Burst Type
+ */
+typedef enum
+{
+    DMC_WRAPB_4,
+    DMC_WRAPB_8,
+} DMC_WRPB_T;
 
 /**@} end of group DMC_Enumerations*/
 
@@ -281,7 +304,7 @@ typedef struct
     uint32_t    tCMD        : 4;       //!< DMC_ATA_CMD_T
     uint32_t    tXSR        : 9;       //!< auto-refresh commands, can be 0x000 to 0x1FF
     uint16_t    tRFP        : 16;      //!< Refresh period, can be 0x0000 to 0xFFFF
-}DMC_TimingConfig_T;
+} DMC_TimingConfig_T;
 
 /**
  * @brief   Config struct definition
@@ -294,7 +317,7 @@ typedef struct
     DMC_COL_WIDTH_T         colWidth;      //!< Number of col address bits
     DMC_CLK_PHASE_T         clkPhase;      //!< Clock phase
     DMC_TimingConfig_T      timing;        //!< Timing
-}DMC_Config_T;
+} DMC_Config_T;
 
 /**@} end of group DMC_Structure*/
 
@@ -303,7 +326,7 @@ typedef struct
   @{
 */
 
- /** Enable / Disable */
+/** Enable / Disable */
 void DMC_Enable(void);
 void DMC_Disable(void);
 void DMC_EnableInit(void);
@@ -327,6 +350,10 @@ void DMC_ConfigRefreshPeriod(uint16_t period);
 void DMC_EixtSlefRefreshMode(void);
 void DMC_EnterSlefRefreshMode(void);
 
+/** Accelerate Module */
+void DMC_EnableAccelerateModule(void);
+void DMC_DisableAccelerateModule(void);
+
 /** Config */
 void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num);
 void DMC_EnableUpdateMode(void);
@@ -336,6 +363,7 @@ void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh);
 void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge);
 void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize);
 void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase);
+void DMC_ConfigWRAPB(DMC_WRPB_T burst);
 
 /** read flag */
 uint8_t DMC_ReadSelfRefreshStatus(void);

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h

@@ -1,23 +1,37 @@
 /*!
- * @file       apm32f10x_eint.h
+ * @file        apm32f10x_eint.h
  *
- * @brief      This file contains all the functions prototypes for the EINT firmware library
+ * @brief       This file contains all the functions prototypes for the EINT firmware library
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_EINT_H
 #define __APM32F10X_EINT_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -51,6 +65,7 @@ typedef enum
 
 typedef enum
 {
+    EINT_LINENONE = 0x00000,  //!<No interrupt selected >
     EINT_LINE_0   = 0x00001,  //!< External interrupt line 0
     EINT_LINE_1   = 0x00002,  //!< External interrupt line 1
     EINT_LINE_2   = 0x00004,  //!< External interrupt line 2
@@ -99,7 +114,8 @@ typedef struct
 
 /** Reset and configuration */
 void EINT_Reset(void);
-void EINT_Config( EINT_Config_T* eintConfig);
+void EINT_Config(EINT_Config_T *eintConfig);
+void EINT_ConfigStructInit(EINT_Config_T *eintConfig);
 
 /** Interrupt and flag */
 void EINT_SelectSWInterrupt(uint32_t line);
@@ -109,11 +125,11 @@ uint8_t EINT_ReadIntFlag(EINT_LINE_T line);
 void EINT_ClearIntFlag(uint32_t line);
 
 /**@} end of group EINT_Fuctions*/
-/**@} end of group EINT_Driver */
+/**@} end of group EINT_Driver*/
 /**@} end of group Peripherals_Library*/
 
-#ifdef __APM32F10X_cplusplus
+#ifdef __cplusplus
 }
 #endif
 
-#endif /* __EINT_H */
+#endif /* __APM32F10XEINT_H */

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h

@@ -1,23 +1,37 @@
 /*!
- * @file       apm32f10x_emmc.h
+ * @file        apm32f10x_emmc.h
  *
- * @brief      This file contains all the functions prototypes for the EMMC firmware library
+ * @brief       This file contains all the functions prototypes for the EMMC firmware library
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_EMMC_H
 #define __APM32F10X_EMMC_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -66,7 +80,7 @@ typedef enum
 typedef enum
 {
     EMMC_MEMORY_TYPE_SRAM  = 0x00000000,
-    EMMC_MEMORY_TYPE_PARAM = 0x00000004,
+    EMMC_MEMORY_TYPE_PSRAM = 0x00000004,
     EMMC_MEMORY_TYPE_NOR   = 0x00000008
 } EMMC_MEMORY_TYPE_T;
 
@@ -262,8 +276,8 @@ typedef struct
     EMMC_WAITE_SIGNAL_T         waiteSignal;
     EMMC_EXTENDEN_MODE_T        extendedMode;
     EMMC_WRITE_BURST_T          writeBurst;
-    EMMC_NORSRAMTimingConfig_T*   readWriteTimingStruct;
-    EMMC_NORSRAMTimingConfig_T*   writeTimingStruct;
+    EMMC_NORSRAMTimingConfig_T   *readWriteTimingStruct;
+    EMMC_NORSRAMTimingConfig_T   *writeTimingStruct;
 } EMMC_NORSRAMConfig_T;
 
 /**
@@ -289,8 +303,8 @@ typedef struct
     EMMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize;
     uint32_t                  TCLRSetupTime;
     uint32_t                  TARSetupTime;
-    EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
-    EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
+    EMMC_NAND_PCCARDTimingConfig_T *commonSpaceTimingStruct;
+    EMMC_NAND_PCCARDTimingConfig_T *attributeSpaceTimingStruct;
 } EMMC_NANDConfig_T;
 
 /**
@@ -301,9 +315,9 @@ typedef struct
     EMMC_WAIT_FEATURE_T waitFeature;
     uint32_t            TCLRSetupTime;
     uint32_t            TARSetupTime;
-    EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
-    EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
-    EMMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct;
+    EMMC_NAND_PCCARDTimingConfig_T *commonSpaceTimingStruct;
+    EMMC_NAND_PCCARDTimingConfig_T *attributeSpaceTimingStruct;
+    EMMC_NAND_PCCARDTimingConfig_T *IOSpaceTimingStruct;
 } EMMC_PCCARDConfig_T;
 
 /**@} end of group EMMC_Structure*/
@@ -318,12 +332,12 @@ void EMMC_ResetNAND(EMMC_BANK_NAND_T bank);
 void EMMC_ResetPCCard(void);
 
 /** EMMC Configuration */
-void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
-void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig);
-void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig);
-void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
-void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig);
-void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig);
+void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig);
+void EMMC_ConfigNAND(EMMC_NANDConfig_T *emmcNANDConfig);
+void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T *emmcPCCardConfig);
+void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig);
+void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T *emmcNANDConfig);
+void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T *emmcPCCardConfig);
 
 /** EMMC bank control */
 void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank);
@@ -345,7 +359,7 @@ uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag);
 void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag);
 
 /**@} end of group EMMC_Fuctions*/
-/**@} end of group EMMC_Driver */
+/**@} end of group EMMC_Driver*/
 /**@} end of group Peripherals_Library*/
 
 #ifdef __cplusplus

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h

@@ -1,23 +1,37 @@
 /*!
- * @file       apm32f10x_fmc.h
+ * @file        apm32f10x_fmc.h
  *
- * @brief      This file contains all the functions prototypes for the FMC firmware library
+ * @brief       This file contains all the functions prototypes for the FMC firmware library
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_FMC_H
 #define __APM32F10X_FMC_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -224,7 +238,7 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data);
 FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page);
 FMC_STATUS_T FMC_EnableReadOutProtection(void);
 FMC_STATUS_T FMC_DisableReadOutProtection(void);
-FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig);
+FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T *userConfig);
 uint32_t FMC_ReadUserOptionByte(void);
 uint32_t FMC_ReadOptionByteWriteProtection(void);
 uint8_t FMC_GetReadProtectionStatus(void);
@@ -234,7 +248,7 @@ uint8_t FMC_ReadPrefetchBufferStatus(void);
 void FMC_EnableInterrupt(FMC_INT_T interrupt);
 void FMC_DisableInterrupt(FMC_INT_T interrupt);
 uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag);
-void FMC_ClearStatusFlag(FMC_FLAG_T flag);
+void FMC_ClearStatusFlag(uint32_t flag);
 
 /** Status management */
 FMC_STATUS_T FMC_ReadStatus(void);

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h

@@ -1,23 +1,37 @@
 /*!
- * @file       apm32f10x_gpio.h
+ * @file        apm32f10x_gpio.h
  *
- * @brief      This file contains all the functions prototypes for the GPIO firmware library
+ * @brief       This file contains all the functions prototypes for the GPIO firmware library
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_GPIO_H
 #define __APM32F10X_GPIO_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -35,10 +49,10 @@
  */
 typedef enum
 {
-   GPIO_SPEED_10MHz = 1,
-   GPIO_SPEED_2MHz,
-   GPIO_SPEED_50MHz
-}GPIO_SPEED_T;
+    GPIO_SPEED_10MHz = 1,
+    GPIO_SPEED_20MHz,
+    GPIO_SPEED_50MHz
+} GPIO_SPEED_T;
 
 /**
  * @brief   Configuration Mode enumeration
@@ -53,7 +67,7 @@ typedef enum
     GPIO_MODE_OUT_OD      = 0x84,  //!< General purpose output Open-drain
     GPIO_MODE_AF_PP       = 0x88,  //!< Alternate function output Push-pull
     GPIO_MODE_AF_OD       = 0x8C,  //!< Alternate function output Open-drain
-}GPIO_MODE_T;
+} GPIO_MODE_T;
 
 /**
  * @brief    Definition of the GPIO pins
@@ -84,108 +98,108 @@ typedef enum
  */
 typedef enum
 {
-   GPIO_NO_REMAP_SPI1          = 0x00000010,
-   GPIO_REMAP_SPI1             = 0x00000011,
+    GPIO_NO_REMAP_SPI1          = 0x00000010,
+    GPIO_REMAP_SPI1             = 0x00000011,
 
-   GPIO_NO_REMAP_I2C1          = 0x00000110,
-   GPIO_REMAP_I2C1             = 0x00000111,
+    GPIO_NO_REMAP_I2C1          = 0x00000110,
+    GPIO_REMAP_I2C1             = 0x00000111,
 
-   GPIO_NO_REMAP_USART1        = 0x00000210,
-   GPIO_REMAP_USART1           = 0x00000211,
+    GPIO_NO_REMAP_USART1        = 0x00000210,
+    GPIO_REMAP_USART1           = 0x00000211,
 
-   GPIO_NO_REMAP_USART2        = 0x00000310,
-   GPIO_REMAP_USART2           = 0x00000311,
+    GPIO_NO_REMAP_USART2        = 0x00000310,
+    GPIO_REMAP_USART2           = 0x00000311,
 
-   GPIO_NO_REMAP_USART3        = 0x00000430,
-   GPIO_PARTIAL_REMAP_USART3   = 0x00000431,
-   GPIO_FULL_REMAP_USART3      = 0x00000433,
+    GPIO_NO_REMAP_USART3        = 0x00000430,
+    GPIO_PARTIAL_REMAP_USART3   = 0x00000431,
+    GPIO_FULL_REMAP_USART3      = 0x00000433,
 
-   GPIO_NO_REMAP_TMR1          = 0x00000630,
-   GPIO_PARTIAL_REMAP_TMR1     = 0x00000631,
-   GPIO_FULL_REMAP_TMR1        = 0x00000633,
+    GPIO_NO_REMAP_TMR1          = 0x00000630,
+    GPIO_PARTIAL_REMAP_TMR1     = 0x00000631,
+    GPIO_FULL_REMAP_TMR1        = 0x00000633,
 
-   GPIO_NO_REMAP_TMR2          = 0x00000830,
-   GPIO_PARTIAL_REMAP1_TMR2    = 0x00000831,
-   GPIO_PARTIAL_REMAP2_TMR2    = 0x00000832,
-   GPIO_FULL_REMAP_TMR2        = 0x00000833,
+    GPIO_NO_REMAP_TMR2          = 0x00000830,
+    GPIO_PARTIAL_REMAP1_TMR2    = 0x00000831,
+    GPIO_PARTIAL_REMAP2_TMR2    = 0x00000832,
+    GPIO_FULL_REMAP_TMR2        = 0x00000833,
 
-   GPIO_NO_REMAP_TMR3          = 0x00000A30,
-   GPIO_PARTIAL_REMAP_TMR3     = 0x00000A32,
-   GPIO_FULL_REMAP_TMR3        = 0x00000A33,
+    GPIO_NO_REMAP_TMR3          = 0x00000A30,
+    GPIO_PARTIAL_REMAP_TMR3     = 0x00000A32,
+    GPIO_FULL_REMAP_TMR3        = 0x00000A33,
 
-   GPIO_NO_REMAP_TMR4          = 0x00000C10,
-   GPIO_REMAP_TMR4             = 0x00000C11,
+    GPIO_NO_REMAP_TMR4          = 0x00000C10,
+    GPIO_REMAP_TMR4             = 0x00000C11,
 
-   GPIO_NO_REMAP_CAN1          = 0x00000D30,
-   GPIO_REMAP1_CAN1            = 0x00000D32,
-   GPIO_REMAP2_CAN1            = 0x00000D33,
+    GPIO_NO_REMAP_CAN1          = 0x00000D30,
+    GPIO_REMAP1_CAN1            = 0x00000D32,
+    GPIO_REMAP2_CAN1            = 0x00000D33,
 
-   GPIO_NO_REMAP_PD01          = 0x00000F10,
-   GPIO_REMAP_PD01             = 0x00000F11,
+    GPIO_NO_REMAP_PD01          = 0x00000F10,
+    GPIO_REMAP_PD01             = 0x00000F11,
 
-   GPIO_NO_REMAP_TMR5CH4_LSI   = 0x00001010,
-   GPIO_REMAP_TMR5CH4_LSI      = 0x00001011,
+    GPIO_NO_REMAP_TMR5CH4_LSI   = 0x00001010,
+    GPIO_REMAP_TMR5CH4_LSI      = 0x00001011,
 
-   GPIO_NO_REMAP_ADC1_ETRGINJ  = 0x00001110,
-   GPIO_REMAP_ADC1_ETRGINJ     = 0x00001111,
+    GPIO_NO_REMAP_ADC1_ETRGINJ  = 0x00001110,
+    GPIO_REMAP_ADC1_ETRGINJ     = 0x00001111,
 
-   GPIO_NO_REMAP_ADC1_ETRGREG  = 0x00001210,
-   GPIO_REMAP_ADC1_ETRGREG     = 0x00001211,
+    GPIO_NO_REMAP_ADC1_ETRGREG  = 0x00001210,
+    GPIO_REMAP_ADC1_ETRGREG     = 0x00001211,
 
-   GPIO_NO_REMAP_ADC2_ETRGINJ  = 0x00001310,
-   GPIO_REMAP_ADC2_ETRGINJ     = 0x00001311,
+    GPIO_NO_REMAP_ADC2_ETRGINJ  = 0x00001310,
+    GPIO_REMAP_ADC2_ETRGINJ     = 0x00001311,
 
-   GPIO_NO_REMAP_ADC2_ETRGREG  = 0x00001410,
-   GPIO_REMAP_ADC2_ETRGREG     = 0x00001411,
+    GPIO_NO_REMAP_ADC2_ETRGREG  = 0x00001410,
+    GPIO_REMAP_ADC2_ETRGREG     = 0x00001411,
 
-   GPIO_NO_REMAP_CAN2          = 0x00001610,
-   GPIO_REMAP_CAN2             = 0x00001611,
+    GPIO_NO_REMAP_CAN2          = 0x00001610,
+    GPIO_REMAP_CAN2             = 0x00001611,
 
-   GPIO_NO_REMAP_SWJ           = 0x00001870,
-   GPIO_REMAP_SWJ_NOJTRST      = 0x00001871,
-   GPIO_REMAP_SWJ_JTAGDISABLE  = 0x00001872,
-   GPIO_REMAP_SWJ_DISABLE      = 0x00001874,
+    GPIO_NO_REMAP_SWJ           = 0x00001870,
+    GPIO_REMAP_SWJ_NOJTRST      = 0x00001871,
+    GPIO_REMAP_SWJ_JTAGDISABLE  = 0x00001872,
+    GPIO_REMAP_SWJ_DISABLE      = 0x00001874,
 
-   GPIO_NO_REMAP_EMMC_NADV     = 0x00010A10,
-   GPIO_REMAP_EMMC_NADV        = 0x00010A11,
-}GPIO_REMAP_T;
+    GPIO_NO_REMAP_EMMC_NADV     = 0x00010A10,
+    GPIO_REMAP_EMMC_NADV        = 0x00010A11,
+} GPIO_REMAP_T;
 
 /**
  * @brief   gpio port source define
  */
 typedef enum
 {
-   GPIO_PORT_SOURCE_A,
-   GPIO_PORT_SOURCE_B,
-   GPIO_PORT_SOURCE_C,
-   GPIO_PORT_SOURCE_D,
-   GPIO_PORT_SOURCE_E,
-   GPIO_PORT_SOURCE_F,
-   GPIO_PORT_SOURCE_G,
-}GPIO_PORT_SOURCE_T;
+    GPIO_PORT_SOURCE_A,
+    GPIO_PORT_SOURCE_B,
+    GPIO_PORT_SOURCE_C,
+    GPIO_PORT_SOURCE_D,
+    GPIO_PORT_SOURCE_E,
+    GPIO_PORT_SOURCE_F,
+    GPIO_PORT_SOURCE_G,
+} GPIO_PORT_SOURCE_T;
 
 /**
  * @brief   gpio pin source define
  */
 typedef enum
 {
-   GPIO_PIN_SOURCE_0,
-   GPIO_PIN_SOURCE_1,
-   GPIO_PIN_SOURCE_2,
-   GPIO_PIN_SOURCE_3,
-   GPIO_PIN_SOURCE_4,
-   GPIO_PIN_SOURCE_5,
-   GPIO_PIN_SOURCE_6,
-   GPIO_PIN_SOURCE_7,
-   GPIO_PIN_SOURCE_8,
-   GPIO_PIN_SOURCE_9,
-   GPIO_PIN_SOURCE_10,
-   GPIO_PIN_SOURCE_11,
-   GPIO_PIN_SOURCE_12,
-   GPIO_PIN_SOURCE_13,
-   GPIO_PIN_SOURCE_14,
-   GPIO_PIN_SOURCE_15,
-}GPIO_PIN_SOURCE_T;
+    GPIO_PIN_SOURCE_0,
+    GPIO_PIN_SOURCE_1,
+    GPIO_PIN_SOURCE_2,
+    GPIO_PIN_SOURCE_3,
+    GPIO_PIN_SOURCE_4,
+    GPIO_PIN_SOURCE_5,
+    GPIO_PIN_SOURCE_6,
+    GPIO_PIN_SOURCE_7,
+    GPIO_PIN_SOURCE_8,
+    GPIO_PIN_SOURCE_9,
+    GPIO_PIN_SOURCE_10,
+    GPIO_PIN_SOURCE_11,
+    GPIO_PIN_SOURCE_12,
+    GPIO_PIN_SOURCE_13,
+    GPIO_PIN_SOURCE_14,
+    GPIO_PIN_SOURCE_15,
+} GPIO_PIN_SOURCE_T;
 
 /**@} end of group GPIO_Enumerations*/
 
@@ -199,10 +213,10 @@ typedef enum
  */
 typedef struct
 {
-   uint16_t         pin;
-   GPIO_SPEED_T     speed;
-   GPIO_MODE_T      mode;
-}GPIO_Config_T;
+    uint16_t         pin;
+    GPIO_SPEED_T     speed;
+    GPIO_MODE_T      mode;
+} GPIO_Config_T;
 
 /**@} end of group GPIO_Structure*/
 
@@ -211,25 +225,25 @@ typedef struct
 */
 
 /** Reset and common Configuration */
-void GPIO_Reset(GPIO_T* port);
+void GPIO_Reset(GPIO_T *port);
 void GPIO_AFIOReset(void);
-void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig);
-void GPIO_StructInit(GPIO_Config_T* gpioConfig);
+void GPIO_Config(GPIO_T *port, GPIO_Config_T *gpioConfig);
+void GPIO_ConfigStructInit(GPIO_Config_T *gpioConfig);
 
 /** Read */
-uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin);
-uint16_t GPIO_ReadInputPort(GPIO_T* port);
-uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin);
-uint16_t GPIO_ReadOutputPort(GPIO_T* port);
+uint8_t GPIO_ReadInputBit(GPIO_T *port, uint16_t pin);
+uint16_t GPIO_ReadInputPort(GPIO_T *port);
+uint8_t GPIO_ReadOutputBit(GPIO_T *port, uint16_t pin);
+uint16_t GPIO_ReadOutputPort(GPIO_T *port);
 
 /** Write */
-void GPIO_SetBits(GPIO_T* port, uint16_t pin);
-void GPIO_ResetBits(GPIO_T* port, uint16_t pin);
-void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue);
-void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal);
+void GPIO_SetBit(GPIO_T *port, uint16_t pin);
+void GPIO_ResetBit(GPIO_T *port, uint16_t pin);
+void GPIO_WriteOutputPort(GPIO_T *port, uint16_t portValue);
+void GPIO_WriteBitValue(GPIO_T *port, uint16_t pin, uint8_t bitVal);
 
 /** GPIO Configuration */
-void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin);
+void GPIO_ConfigPinLock(GPIO_T *port, uint16_t pin);
 void GPIO_ConfigEventOutput(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource);
 void GPIO_EnableEventOutput(void);
 void GPIO_DisableEventOutput(void);
@@ -237,7 +251,7 @@ void GPIO_ConfigPinRemap(GPIO_REMAP_T remap);
 void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource);
 
 /**@} end of group GPIO_Fuctions*/
-/**@} end of group GPIO_Driver */
+/**@} end of group GPIO_Driver*/
 /**@} end of group Peripherals_Library*/
 
 #ifdef __cplusplus

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h

@@ -1,23 +1,37 @@
 /*!
- * @file       apm32f10x_i2c.h
+ * @file        apm32f10x_i2c.h
  *
- * @brief      This file contains all the functions prototypes for the I2C firmware library
+ * @brief       This file contains all the functions prototypes for the I2C firmware library
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_I2C_H
 #define __APM32F10X_I2C_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -269,59 +283,59 @@ typedef struct
 */
 
 /** I2C reset and configuration */
-void I2C_Reset(I2C_T* i2c);
-void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig);
-void I2C_ConfigStructInit(I2C_Config_T* i2cConfig);
-void I2C_Enable(I2C_T* i2c);
-void I2C_Disable(I2C_T* i2c);
-void I2C_EnableGenerateStart(I2C_T* i2c);
-void I2C_DisableGenerateStart(I2C_T* i2c);
-void I2C_EnableGenerateStop(I2C_T* i2c);
-void I2C_DisableGenerateStop(I2C_T* i2c);
-void I2C_EnableAcknowledge(I2C_T* i2c);
-void I2C_DisableAcknowledge(I2C_T* i2c);
-void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address);
-void I2C_EnableDualAddress(I2C_T* i2c);
-void I2C_DisableDualAddress(I2C_T* i2c);
-void I2C_EnableGeneralCall(I2C_T* i2c);
-void I2C_DisableGeneralCall(I2C_T* i2c);
+void I2C_Reset(I2C_T *i2c);
+void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig);
+void I2C_ConfigStructInit(I2C_Config_T *i2cConfig);
+void I2C_Enable(I2C_T *i2c);
+void I2C_Disable(I2C_T *i2c);
+void I2C_EnableGenerateStart(I2C_T *i2c);
+void I2C_DisableGenerateStart(I2C_T *i2c);
+void I2C_EnableGenerateStop(I2C_T *i2c);
+void I2C_DisableGenerateStop(I2C_T *i2c);
+void I2C_EnableAcknowledge(I2C_T *i2c);
+void I2C_DisableAcknowledge(I2C_T *i2c);
+void I2C_ConfigOwnAddress2(I2C_T *i2c, uint8_t address);
+void I2C_EnableDualAddress(I2C_T *i2c);
+void I2C_DisableDualAddress(I2C_T *i2c);
+void I2C_EnableGeneralCall(I2C_T *i2c);
+void I2C_DisableGeneralCall(I2C_T *i2c);
 
 /** Transmit Configuration */
-void I2C_TxData(I2C_T* i2c, uint8_t data);
-uint8_t I2C_RxData(I2C_T* i2c);
-void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction);
-uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister);
-void I2C_EnableSoftwareReset(I2C_T* i2c);
-void I2C_DisableSoftwareReset(I2C_T* i2c);
-void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition);
-void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState);
-void I2C_EnablePECTransmit(I2C_T* i2c);
-void I2C_DisablePECTransmit(I2C_T* i2c);
-void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition);
-void I2C_EnablePEC(I2C_T* i2c);
-void I2C_DisablePEC(I2C_T* i2c);
-uint8_t I2C_ReadPEC(I2C_T* i2c);
-void I2C_EnableARP(I2C_T* i2c);
-void I2C_DisableARP(I2C_T* i2c);
-void I2C_EnableStretchClock(I2C_T* i2c);
-void I2C_DisableStretchClock(I2C_T* i2c);
-void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle);
+void I2C_TxData(I2C_T *i2c, uint8_t data);
+uint8_t I2C_RxData(I2C_T *i2c);
+void I2C_Tx7BitAddress(I2C_T *i2c, uint8_t address, I2C_DIRECTION_T direction);
+uint16_t I2C_ReadRegister(I2C_T *i2c, I2C_REGISTER_T i2cRegister);
+void I2C_EnableSoftwareReset(I2C_T *i2c);
+void I2C_DisableSoftwareReset(I2C_T *i2c);
+void I2C_ConfigNACKPosition(I2C_T *i2c, I2C_NACK_POSITION_T NACKPosition);
+void I2C_ConfigSMBusAlert(I2C_T *i2c, I2C_SMBUSALER_T SMBusState);
+void I2C_EnablePECTransmit(I2C_T *i2c);
+void I2C_DisablePECTransmit(I2C_T *i2c);
+void I2C_ConfigPECPosition(I2C_T *i2c, I2C_PEC_POSITION_T PECPosition);
+void I2C_EnablePEC(I2C_T *i2c);
+void I2C_DisablePEC(I2C_T *i2c);
+uint8_t I2C_ReadPEC(I2C_T *i2c);
+void I2C_EnableARP(I2C_T *i2c);
+void I2C_DisableARP(I2C_T *i2c);
+void I2C_EnableStretchClock(I2C_T *i2c);
+void I2C_DisableStretchClock(I2C_T *i2c);
+void I2C_ConfigFastModeDutyCycle(I2C_T *i2c, I2C_DUTYCYCLE_T dutyCycle);
 
 /** DMA */
-void I2C_EnableDMA(I2C_T* i2c);
-void I2C_DisableDMA(I2C_T* i2c);
-void I2C_EnableDMALastTransfer(I2C_T* i2c);
-void I2C_DisableDMALastTransfer(I2C_T* i2c);
+void I2C_EnableDMA(I2C_T *i2c);
+void I2C_DisableDMA(I2C_T *i2c);
+void I2C_EnableDMALastTransfer(I2C_T *i2c);
+void I2C_DisableDMALastTransfer(I2C_T *i2c);
 
 /** Interrupts and flags */
-void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt);
-void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt);
-uint8_t  I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent);
-uint32_t I2C_ReadLastEvent(I2C_T* i2c);
-uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag);
-void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag);
-uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag);
-void I2C_ClearIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag);
+void I2C_EnableInterrupt(I2C_T *i2c, uint16_t interrupt);
+void I2C_DisableInterrupt(I2C_T *i2c, uint16_t interrupt);
+uint8_t  I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent);
+uint32_t I2C_ReadLastEvent(I2C_T *i2c);
+uint8_t I2C_ReadStatusFlag(I2C_T *i2c, I2C_FLAG_T flag);
+void I2C_ClearStatusFlag(I2C_T *i2c, I2C_FLAG_T flag);
+uint8_t I2C_ReadIntFlag(I2C_T *i2c, I2C_INT_FLAG_T flag);
+void I2C_ClearIntFlag(I2C_T *i2c, uint32_t flag);
 
 /**@} end of group I2C_Fuctions*/
 /**@} end of group I2C_Driver*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h

@@ -3,21 +3,35 @@
  *
  * @brief       This file contains all the functions prototypes for the IWDT firmware library
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_IWDT_H
 #define __APM32F10X_IWDT_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -37,7 +51,7 @@ typedef enum
 {
     IWDT_KEYWORD_RELOAD = 0xAAAA,
     IWDT_KEYWORD_ENABLE = 0xCCCC
-}IWDT_KEYWORD_T;
+} IWDT_KEYWORD_T;
 
 /**
  * @brief    IWDT Write Access define
@@ -46,7 +60,7 @@ typedef enum
 {
     IWDT_WRITEACCESS_ENABLE  = 0x5555,
     IWDT_WRITEACCESS_DISABLE = 0x0000
-}IWDT_WRITEACCESS_T;
+} IWDT_WRITEACCESS_T;
 
 /**
  * @brief    IWDT Divider
@@ -60,7 +74,7 @@ typedef enum
     IWDT_DIVIDER_64  = 0x04,
     IWDT_DIVIDER_128 = 0x05,
     IWDT_DIVIDER_256 = 0x06
-}IWDT_DIVIDER_T;
+} IWDT_DIVIDER_T;
 
 /**
  * @brief    IWDT Flag
@@ -69,7 +83,7 @@ typedef enum
 {
     IWDT_FLAG_PSCU = BIT0,
     IWDT_FLAG_CNTU = BIT1
-}IWDT_FLAG_T;
+} IWDT_FLAG_T;
 
 /**@} end of group IWDT_Enumerations*/
 
@@ -98,7 +112,7 @@ void IWDT_DisableWriteAccess(void);
 uint8_t IWDT_ReadStatusFlag(uint16_t flag);
 
 /**@} end of group IWDT_Fuctions*/
-/**@} end of group IWDT_Driver */
+/**@} end of group IWDT_Driver*/
 /**@} end of group Peripherals_Library*/
 
 #ifdef __cplusplus

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h

@@ -1,24 +1,38 @@
 /*!
- * @file       apm32f10x_misc.h
+ * @file        apm32f10x_misc.h
  *
- * @brief      This file provides all the miscellaneous firmware functions.
+ * @brief       This file provides all the miscellaneous firmware functions.
  *             Include NVIC,SystemTick and Power management.
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_MISC_H
 #define __APM32F10X_MISC_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -36,19 +50,19 @@
  */
 typedef enum
 {
-   NVIC_VECT_TAB_RAM   = 0x20000000,
-   NVIC_VECT_TAB_FLASH = 0x08000000,
-}NVIC_VECT_TAB_T;
+    NVIC_VECT_TAB_RAM   = 0x20000000,
+    NVIC_VECT_TAB_FLASH = 0x08000000,
+} NVIC_VECT_TAB_T;
 
 /**
  * @brief   system low power mode
  */
 typedef enum
 {
-   NVIC_LOWPOWER_SEVONPEND   = 0x10,
-   NVIC_LOWPOWER_SLEEPDEEP   = 0x04,
-   NVIC_LOWPOWER_SLEEPONEXIT = 0x02
-}NVIC_LOWPOWER_T;
+    NVIC_LOWPOWER_SEVONPEND   = 0x10,
+    NVIC_LOWPOWER_SLEEPDEEP   = 0x04,
+    NVIC_LOWPOWER_SLEEPONEXIT = 0x02
+} NVIC_LOWPOWER_T;
 
 /**
  * @brief   nvic priority group
@@ -60,16 +74,16 @@ typedef enum
     NVIC_PRIORITY_GROUP_2 = 0x500,  //!< 2 bits for pre-emption priority,2 bits for subpriority
     NVIC_PRIORITY_GROUP_3 = 0x400,  //!< 3 bits for pre-emption priority,1 bits for subpriority
     NVIC_PRIORITY_GROUP_4 = 0x300   //!< 4 bits for pre-emption priority,0 bits for subpriority
-}NVIC_PRIORITY_GROUP_T;
+} NVIC_PRIORITY_GROUP_T;
 
 /**
  * @brief   SysTick Clock source
  */
 typedef enum
 {
-   SYSTICK_CLK_SOURCE_HCLK_DIV8 = 0x00,
-   SYSTICK_CLK_SOURCE_HCLK      = 0x01
-}SYSTICK_CLK_SOURCE_T;
+    SYSTICK_CLK_SOURCE_HCLK_DIV8 = 0x00,
+    SYSTICK_CLK_SOURCE_HCLK      = 0x01
+} SYSTICK_CLK_SOURCE_T;
 
 /**@} end of group MISC_Enumerations*/
 
@@ -93,6 +107,10 @@ void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode);
 /** Systick */
 void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource);
 
+/**@} end of group MISC_Fuctions*/
+/**@} end of group MISC_Driver*/
+/**@} end of group Peripherals_Library*/
+
 #ifdef __cplusplus
 }
 #endif

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h

@@ -1,23 +1,37 @@
 /*!
- * @file       apm32f10x_pmu.h
+ * @file        apm32f10x_pmu.h
  *
- * @brief      This file contains all the functions prototypes for the PMU firmware library.
+ * @brief       This file contains all the functions prototypes for the PMU firmware library.
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_PMU_H
 #define __APM32F10X_PMU_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -30,6 +44,9 @@ extern "C" {
   @{
 */
 
+/**
+ * @brief PMU PVD detection level
+ */
 typedef enum
 {
     PMU_PVD_LEVEL_2V2    = 0x00,    //!< PVD detection level set to 2.2V
@@ -42,18 +59,27 @@ typedef enum
     PMU_PVD_LEVEL_2V9    = 0x07,    //!< PVD detection level set to 2.9V
 } PMU_PVD_LEVEL_T;
 
+/**
+ * @brief PMU Regulator state in STOP mode
+ */
 typedef enum
 {
     PMU_REGULATOR_ON       = 0x00,
     PMU_REGULATOR_LOWPOWER = 0x01
 } PMU_REGULATOR_T;
 
+/**
+ * @brief PMU STOP mode entry
+ */
 typedef enum
 {
     PMU_STOP_ENTRY_WFI     = 0x01,
     PMU_STOP_ENTRY_WFE     = 0x02
 } PMU_STOP_ENTRY_T;
 
+/**
+ * @brief PMU Flag
+ */
 typedef enum
 {
     PMU_FLAG_WUE,
@@ -87,7 +113,7 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag);
 void PMU_ClearStatusFlag(PMU_FLAG_T flag);
 
 /**@} end of group PMU_Fuctions*/
-/**@} end of group PMU_Driver */
+/**@} end of group PMU_Driver*/
 /**@} end of group Peripherals_Library*/
 
 #ifdef __cplusplus

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h

@@ -3,21 +3,35 @@
  *
  * @brief       This file contains all the prototypes,enumeration and macros for the QSPI peripheral
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
- 
+
 #ifndef __APM32F10X_QSPI_H
 #define __APM32F10X_QSPI_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -38,7 +52,7 @@ typedef enum
     QSPI_FRF_STANDARD,              //!< Standard mode
     QSPI_FRF_DUAL,                  //!< Dual SPI
     QSPI_FRF_QUAD                   //!< QUAD SPI
-}QSPI_FRF_T;
+} QSPI_FRF_T;
 
 /**
  * @brief   Transmission mode
@@ -48,8 +62,8 @@ typedef enum
     QSPI_TRANS_MODE_TX_RX,          //!< TX and RX mode
     QSPI_TRANS_MODE_TX,             //!< TX mode only
     QSPI_TRANS_MODE_RX,             //!< RX mode only
-    QSPI_TRANS_MODE_EEPROM_READ,    //!< EEPROM read mode
-}QSPI_TRANS_MODE_T;
+    QSPI_TRANS_MODE_EEPROM_READ     //!< EEPROM read mode
+} QSPI_TRANS_MODE_T;
 
 /**
  * @brief   Clock polarity
@@ -57,8 +71,8 @@ typedef enum
 typedef enum
 {
     QSPI_CLKPOL_LOW,
-    QSPI_CLKPOL_HIGH,
-}QSPI_CLKPOL_T;
+    QSPI_CLKPOL_HIGH
+} QSPI_CLKPOL_T;
 
 /**
  * @brief   Clock phase
@@ -67,7 +81,7 @@ typedef enum
 {
     QSPI_CLKPHA_1EDGE,
     QSPI_CLKPHA_2EDGE
-}QSPI_CLKPHA_T;
+} QSPI_CLKPHA_T;
 
 /**
  * @brief   Data format size
@@ -102,8 +116,8 @@ typedef enum
     QSPI_DFS_29BIT,
     QSPI_DFS_30BIT,
     QSPI_DFS_31BIT,
-    QSPI_DFS_32BIT,
-}QSPI_DFS_T;
+    QSPI_DFS_32BIT
+} QSPI_DFS_T;
 
 /**
  * @brief   QSPI flag
@@ -116,7 +130,7 @@ typedef enum
     QSPI_FLAG_RFNE      = BIT3,     //!< RX FIFO not empty flag
     QSPI_FLAG_RFF       = BIT4,     //!< RX FIFO full flag
     QSPI_FLAG_DCE       = BIT6      //!< Data collision error
-}QSPI_FLAG_T;
+} QSPI_FLAG_T;
 
 /**
  * @brief   QSPI interrupt source
@@ -128,8 +142,8 @@ typedef enum
     QSPI_INT_RFU        = BIT2,     //!< RX FIFO underflow interrupt
     QSPI_INT_RFO        = BIT3,     //!< RX FIFO overflow interrupt
     QSPI_INT_RFF        = BIT4,     //!< RX FIFO full interrupt
-    QSPI_INT_MST        = BIT5,     //!< Master interrupt
-}QSPI_INT_T;
+    QSPI_INT_MST        = BIT5      //!< Master interrupt
+} QSPI_INT_T;
 
 /**
  * @brief   QSPI interrupt flag
@@ -141,8 +155,8 @@ typedef enum
     QSPI_INT_FLAG_RFU   = BIT2,     //!< RX FIFO underflow interrupt flag
     QSPI_INT_FLAG_RFO   = BIT3,     //!< RX FIFO overflow interrupt flag
     QSPI_INT_FLAG_RFF   = BIT4,     //!< RX FIFO full interrupt flag
-    QSPI_INT_FLAG_MST   = BIT5,     //!< Master interrupt flag
-}QSPI_INT_FLAG_T;
+    QSPI_INT_FLAG_MST   = BIT5      //!< Master interrupt flag
+} QSPI_INT_FLAG_T;
 
 /**
  * @brief   Reception sample edge
@@ -151,7 +165,7 @@ typedef enum
 {
     QSPI_RSE_RISING,
     QSPI_RSE_FALLING
-}QSPI_RSE_T;
+} QSPI_RSE_T;
 
 /**
  * @brief   Instruction length
@@ -161,8 +175,8 @@ typedef enum
     QSPI_INST_LEN_0,
     QSPI_INST_LEN_4BIT,
     QSPI_INST_LEN_8BIT,
-    QSPI_INST_LEN_16BIT,
-}QSPI_INST_LEN_T;
+    QSPI_INST_LEN_16BIT
+} QSPI_INST_LEN_T;
 
 /**
  * @brief   QSPI address length
@@ -184,8 +198,8 @@ typedef enum
     QSPI_ADDR_LEN_48BIT,
     QSPI_ADDR_LEN_52BIT,
     QSPI_ADDR_LEN_56BIT,
-    QSPI_ADDR_LEN_60BIT,
-}QSPI_ADDR_LEN_T;
+    QSPI_ADDR_LEN_60BIT
+} QSPI_ADDR_LEN_T;
 
 /**
  * @brief   Instruction and address transmission mode
@@ -194,8 +208,8 @@ typedef enum
 {
     QSPI_INST_ADDR_TYPE_STANDARD,
     QSPI_INST_TYPE_STANDARD,
-    QSPI_INST_ADDR_TYPE_FRF,
-}QSPI_INST_ADDR_TYPE_T;
+    QSPI_INST_ADDR_TYPE_FRF
+} QSPI_INST_ADDR_TYPE_T;
 
 /**
  * @brief   Slave Select Toggle
@@ -203,8 +217,8 @@ typedef enum
 typedef enum
 {
     QSPI_SST_DISABLE,
-    QSPI_SST_ENABLE,
-}QSPI_SST_T;
+    QSPI_SST_ENABLE
+} QSPI_SST_T;
 
 /**@} end of group QSPI_Enumerations*/
 
@@ -255,7 +269,7 @@ typedef struct
     QSPI_CLKPOL_T    clockPolarity;     //!< Clock polarity
     QSPI_CLKPHA_T    clockPhase;        //!< Clock phase
     QSPI_DFS_T       dataFrameSize;     //!< Data frame size
-}QSPI_Config_T;
+} QSPI_Config_T;
 
 /**@} end of group QSPI_Structure*/
 

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h

@@ -1,23 +1,37 @@
 /*!
- * @file       apm32f10x_rcm.h
+ * @file        apm32f10x_rcm.h
  *
- * @brief      This file contains all the functions prototypes for the RCM firmware library
+ * @brief       This file contains all the functions prototypes for the RCM firmware library
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_RCM_H
 #define __APM32F10X_RCM_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -35,9 +49,9 @@ extern "C" {
  */
 typedef enum
 {
-    RCM_HSE_CLOSE,    //!< CLOSE HSE
-    RCM_HSE_OPEN,     //!< OPEN HSE
-    RCM_HSE_BYPASS,   //!< HSE BYPASS
+    RCM_HSE_CLOSE,
+    RCM_HSE_OPEN,
+    RCM_HSE_BYPASS
 } RCM_HSE_T;
 
 /**
@@ -59,7 +73,7 @@ typedef enum
     RCM_PLLMF_13,
     RCM_PLLMF_14,
     RCM_PLLMF_15,
-    RCM_PLLMF_16,
+    RCM_PLLMF_16
 } RCM_PLLMF_T;
 
 /**
@@ -85,7 +99,7 @@ typedef enum
     RCM_AHB_DIV_64,
     RCM_AHB_DIV_128,
     RCM_AHB_DIV_256,
-    RCM_AHB_DIV_512,
+    RCM_AHB_DIV_512
 } RCM_AHB_DIV_T;
 
 /**
@@ -117,7 +131,7 @@ typedef enum
 typedef enum
 {
     RCM_FPU_DIV_1,
-    RCM_FPU_DIV_2,
+    RCM_FPU_DIV_2
 } RCM_FPU_DIV_T;
 
 /**
@@ -128,7 +142,7 @@ typedef enum
     RCM_PCLK2_DIV_2,
     RCM_PCLK2_DIV_4,
     RCM_PCLK2_DIV_6,
-    RCM_PCLK2_DIV_8,
+    RCM_PCLK2_DIV_8
 } RCM_PCLK2_DIV_T;
 
 /**
@@ -160,7 +174,7 @@ typedef enum
     RCM_MCOCLK_SYSCLK,
     RCM_MCOCLK_HSI,
     RCM_MCOCLK_HSE,
-    RCM_MCOCLK_PLLCLK_DIV_2,
+    RCM_MCOCLK_PLLCLK_DIV_2
 } RCM_MCOCLK_T;
 
 /**
@@ -199,7 +213,7 @@ typedef enum
     RCM_AHB_PERIPH_QSPI = BIT5,
     RCM_AHB_PERIPH_CRC  = BIT6,
     RCM_AHB_PERIPH_EMMC = BIT8,
-    RCM_AHB_PERIPH_SDIO = BIT10,
+    RCM_AHB_PERIPH_SDIO = BIT10
 } RCM_AHB_PERIPH_T;
 
 /**
@@ -221,7 +235,7 @@ typedef enum
     RCM_APB2_PERIPH_SPI1    = BIT12,
     RCM_APB2_PERIPH_TMR8    = BIT13,
     RCM_APB2_PERIPH_USART1  = BIT14,
-    RCM_APB2_PERIPH_ADC3    = BIT15,
+    RCM_APB2_PERIPH_ADC3    = BIT15
 } RCM_APB2_PERIPH_T;
 
 /**
@@ -249,7 +263,7 @@ typedef enum
     RCM_APB1_PERIPH_CAN2   = BIT26,
     RCM_APB1_PERIPH_BAKR   = BIT27,
     RCM_APB1_PERIPH_PMU    = BIT28,
-    RCM_APB1_PERIPH_DAC    = BIT29,
+    RCM_APB1_PERIPH_DAC    = BIT29
 } RCM_APB1_PERIPH_T;
 
 /**
@@ -267,7 +281,7 @@ typedef enum
     RCM_FLAG_SWRST   = 0x21C,   //!< Software reset flag
     RCM_FLAG_IWDTRST = 0x21D,   //!< Independent watchdog reset flag
     RCM_FLAG_WWDTRST = 0x21E,   //!< Window watchdog reset flag
-    RCM_FLAG_LPRRST  = 0x21F,   //!< Low-power reset flag
+    RCM_FLAG_LPRRST  = 0x21F    //!< Low-power reset flag
 } RCM_FLAG_T;
 
 /**@} end of group RCM_Enumerations*/
@@ -287,7 +301,7 @@ void RCM_ConfigHSE(RCM_HSE_T state);
 uint8_t RCM_WaitHSEReady(void);
 
 /** HSI clock */
-void RCM_SetHSITrim(uint8_t HSITrim);
+void RCM_ConfigHSITrim(uint8_t HSITrim);
 void RCM_EnableHSI(void);
 void RCM_DisableHSI(void);
 
@@ -325,7 +339,7 @@ void RCM_DisableRTCCLK(void);
 /** Reads the clock frequency */
 uint32_t RCM_ReadSYSCLKFreq(void);
 uint32_t RCM_ReadHCLKFreq(void);
-void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2);
+void RCM_ReadPCLKFreq(uint32_t *PCLK1, uint32_t *PCLK2);
 uint32_t RCM_ReadADCCLKFreq(void);
 
 /** Enable or disable Periph Clock */

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h

@@ -1,23 +1,37 @@
 /*!
- * @file       apm32f10x_rtc.h
+ * @file        apm32f10x_rtc.h
  *
- * @brief      This file contains all the functions prototypes for the RTC firmware library
+ * @brief       This file contains all the functions prototypes for the RTC firmware library
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_RTC_H
 #define __APM32F10X_RTC_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h

@@ -3,21 +3,35 @@
  *
  * @brief       This file contains all the prototypes,enumeration and macros for the SCI2C(I2C3, I2C4) peripheral
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_SCI2C_H
 #define __APM32F10X_SCI2C_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
-  extern "C" {
+extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -38,7 +52,7 @@ typedef enum
     SCI2C_SPEED_STANDARD = 1,
     SCI2C_SPEED_FAST,
     SCI2C_SPEED_HIGH
-}SCI2C_SPEED_T;
+} SCI2C_SPEED_T;
 
 /**
  * @brief   Address mode
@@ -47,7 +61,7 @@ typedef enum
 {
     SCI2C_ADDR_MODE_7BIT,
     SCI2C_ADDR_MODE_10BIT
-}SCI2C_ADDR_MODE_T;
+} SCI2C_ADDR_MODE_T;
 
 /**
  * @brief   SCI2C mode enumeration
@@ -56,7 +70,7 @@ typedef enum
 {
     SCI2C_MODE_MASTER,
     SCI2C_MODE_SLAVE
-}SCI2C_MODE_T;
+} SCI2C_MODE_T;
 
 /**
  * @brief   Restart enable or disable
@@ -65,7 +79,7 @@ typedef enum
 {
     SCI2C_RESTART_DISABLE,
     SCI2C_RESTART_ENABLE
-}SCI2C_RESTART_T;
+} SCI2C_RESTART_T;
 
 /**
  * @brief   Enable or disable generate stop condition
@@ -74,7 +88,7 @@ typedef enum
 {
     SCI2C_STOP_DISABLE,
     SCI2C_STOP_ENABLE
-}SCI2C_STOP_T;
+} SCI2C_STOP_T;
 /**
  * @brief   Data direction
  */
@@ -82,7 +96,7 @@ typedef enum
 {
     SCI2C_DATA_DIR_WRITE,
     SCI2C_DATA_DIR_READ,
-}SCI2C_DATA_DIR_T;
+} SCI2C_DATA_DIR_T;
 
 /**
  * @brief   SCI2C interrupt
@@ -104,7 +118,7 @@ typedef enum
     SCI2C_INT_RSTAD     = BIT12,        //!< Restart detect interrupt
     SCI2C_INT_MOH       = BIT13,        //!< Master on hold interrupt
     SCI2C_INT_ALL       = BIT15         //!< All interrupt
-}SCI2C_INT_T;
+} SCI2C_INT_T;
 
 /**
  * @brief   Flag enumeration
@@ -121,7 +135,7 @@ typedef enum
     SCI2C_FLAG_I2CEN    = BIT8 | BIT0,  //!< I2C enable flag
     SCI2C_FLAG_SDWB     = BIT8 | BIT1,  //!< Slave disable while busy flag
     SCI2C_FLAG_SRDL     = BIT8 | BIT2   //!< Slave receive data lost flag
-}SCI2C_FLAG_T;
+} SCI2C_FLAG_T;
 
 /**
  * @brief   Tx abort source
@@ -144,7 +158,7 @@ typedef enum
     SCI2C_TAS_SRI       = BIT13,        //!< Slave read done
     SCI2C_TAS_USRARB    = BIT14,        //!< User abort
     SCI2C_TAS_FLUCNT    = BIT15         //!< Tx flush counter
-}SCI2C_TAS_T;
+} SCI2C_TAS_T;
 
 /**
  * @brief   DMA Enable
@@ -153,7 +167,7 @@ typedef enum
 {
     SCI2C_DMA_RX = BIT0,
     SCI2C_DMA_TX = BIT1,
-}SCI2C_DMA_T;
+} SCI2C_DMA_T;
 
 /**@} end of group SCI2C_Enumerations*/
 
@@ -213,7 +227,7 @@ typedef struct
     uint8_t             txFifoThreshold;  //!< Tx FIFO threshold
     SCI2C_RESTART_T     restart;          //!< Enable or disable restart
     SCI2C_ADDR_MODE_T   addrMode;         //!< Address mode. 7-bit or 10-bit mode.
-}SCI2C_Config_T;
+} SCI2C_Config_T;
 
 /**@} end of group SCI2C_Structure*/
 

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h

@@ -3,21 +3,35 @@
  *
  * @brief       This file contains all the functions prototypes for the SDIO firmware library
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_SDIO_H
 #define __APM32F10X_SDIO_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -37,7 +51,7 @@ typedef enum
 {
     SDIO_CLOCK_EDGE_RISING        = 0x00000000,
     SDIO_CLOCK_EDGE_FALLING       = 0x00002000
-}SDIO_CLOCK_EDGE_T;
+} SDIO_CLOCK_EDGE_T;
 
 /**
  * @brief    SDIO clock bypass
@@ -46,7 +60,7 @@ typedef enum
 {
     SDIO_CLOCK_BYPASS_DISABLE     = 0x00000000,
     SDIO_CLOCK_BYPASS_ENABLE      = 0x00000400
-}SDIO_CLOCK_BYPASS_T;
+} SDIO_CLOCK_BYPASS_T;
 
 /**
  * @brief    SDIO clock power save
@@ -55,17 +69,17 @@ typedef enum
 {
     SDIO_CLOCK_POWER_SAVE_DISABLE = 0x00000000,
     SDIO_CLOCK_POWER_SAVE_ENABLE  = 0x00000200
-}SDIO_CLOCK_POWER_SAVE_T;
+} SDIO_CLOCK_POWER_SAVE_T;
 
 /**
  * @brief    SDIO bus wide
  */
 typedef enum
 {
-    SDIO_BUSWIDE_1B = 0x00000000,
-    SDIO_BUSWIDE_4B = 0x00000800,
-    SDIO_BUSWIDE_8B = 0x00001000
-}SDIO_BUSWIDE_T;
+    SDIO_BUS_WIDE_1B = 0x00000000,
+    SDIO_BUS_WIDE_4B = 0x00000800,
+    SDIO_BUS_WIDE_8B = 0x00001000
+} SDIO_BUS_WIDE_T;
 
 /**
  * @brief    SDIO hardware flow control
@@ -74,7 +88,7 @@ typedef enum
 {
     SDIO_HARDWARE_FLOW_CONTROL_DISABLE = 0x00000000,
     SDIO_HARDWARE_FLOW_CONTROL_ENABLE  = 0x00004000
-}SDIO_HARDWARE_FLOW_CONTROL_T;
+} SDIO_HARDWARE_FLOW_CONTROL_T;
 
 /**
  * @brief    SDIO power state
@@ -83,7 +97,7 @@ typedef enum
 {
     SDIO_POWER_STATE_OFF = 0x00000000,
     SDIO_POWER_STATE_ON  = 0x00000003
-}SDIO_POWER_STATE_T;
+} SDIO_POWER_STATE_T;
 
 /**
  * @brief    SDIO interrupt sources
@@ -114,7 +128,7 @@ typedef enum
     SDIO_INT_RXDA       = 0x00200000,
     SDIO_INT_SDIOINT    = 0x00400000,
     SDIO_INT_ATAEND     = 0x00800000
-}SDIO_INT_T;
+} SDIO_INT_T;
 
 /**
  * @brief    SDIO response
@@ -124,7 +138,7 @@ typedef enum
     SDIO_RESPONSE_NO    = 0x00000000,
     SDIO_RESPONSE_SHORT = 0x00000040,
     SDIO_RESPONSE_LONG  = 0x000000C0
-}SDIO_RESPONSE_T;
+} SDIO_RESPONSE_T;
 
 /**
  * @brief    SDIO wait interrupt state
@@ -134,7 +148,7 @@ typedef enum
     SDIO_WAIT_NO        = 0x00000000,
     SDIO_WAIT_INT       = 0x00000100,
     SDIO_WAIT_PEND      = 0x00000200
-}SDIO_WAIT_T;
+} SDIO_WAIT_T;
 
 /**
  * @brief    SDIO CPSM state
@@ -143,7 +157,7 @@ typedef enum
 {
     SDIO_CPSM_DISABLE   = 0x00000000,
     SDIO_CPSM_ENABLE    = 0x00000400
-}SDIO_CPSM_T;
+} SDIO_CPSM_T;
 
 /**
  * @brief    SDIO response registers
@@ -154,7 +168,7 @@ typedef enum
     SDIO_RES2 = 0x00000004,
     SDIO_RES3 = 0x00000008,
     SDIO_RES4 = 0x0000000C
-}SDIO_RES_T;
+} SDIO_RES_T;
 
 /**
  * @brief    SDIO data block size
@@ -176,16 +190,16 @@ typedef enum
     SDIO_DATA_BLOCKSIZE_496B   = 0x000000C0,
     SDIO_DATA_BLOCKSIZE_8192B  = 0x000000D0,
     SDIO_DATA_BLOCKSIZE_16384B = 0x000000E0
-}SDIO_DATA_BLOCKSIZE_T;
+} SDIO_DATA_BLOCKSIZE_T;
 
 /**
  * @brief    SDIO transfer direction
  */
 typedef enum
 {
-    SDIO_TRANSFER_DIR_TOCARD   = 0x00000000,
-    SDIO_TRANSFER_DIR_TOSDIO   = 0x00000002
-}SDIO_TRANSFER_DIR_T;
+    SDIO_TRANSFER_DIR_TO_CARD   = 0x00000000,
+    SDIO_TRANSFER_DIR_TO_SDIO   = 0x00000002
+} SDIO_TRANSFER_DIR_T;
 
 /**
  * @brief    SDIO transfer type
@@ -194,7 +208,7 @@ typedef enum
 {
     SDIO_TRANSFER_MODE_BLOCK   = 0x00000000,
     SDIO_TRANSFER_MODE_STREAM  = 0x00000004
-}SDIO_TRANSFER_MODE_T;
+} SDIO_TRANSFER_MODE_T;
 
 /**
  * @brief    SDIO DPSM state
@@ -203,7 +217,7 @@ typedef enum
 {
     SDIO_DPSM_DISABLE          = 0x00000000,
     SDIO_DPSM_ENABLE           = 0x00000001
-}SDIO_DPSM_T;
+} SDIO_DPSM_T;
 
 /**
  * @brief    SDIO flag
@@ -234,7 +248,7 @@ typedef enum
     SDIO_FLAG_RXDA      = 0x00200000,
     SDIO_FLAG_SDIOINT   = 0x00400000,
     SDIO_FLAG_ATAEND    = 0x00800000
-}SDIO_FLAG_T;
+} SDIO_FLAG_T;
 
 /**
  * @brief    SDIO read wait mode
@@ -243,7 +257,7 @@ typedef enum
 {
     SDIO_READ_WAIT_MODE_CLK   = 0x00000001,
     SDIO_READ_WAIT_MODE_DATA2 = 0x00000000
-}SDIO_READ_WAIT_MODE_T;
+} SDIO_READ_WAIT_MODE_T;
 
 /**@} end of group SDIO_Enumerations*/
 
@@ -255,52 +269,52 @@ typedef enum
 /** ------------ SDIO registers bit address in the alias region ----------- */
 #define SDIO_OFFSET                (SDIO_BASE - PERIPH_BASE)
 
-/* --- CLKCTRL Register ---*/
+/** --- CLKCTRL Register ---*/
 
-/* Alias word address of CLKEN bit */
+/** Alias word address of CLKEN bit */
 #define CLKCTRL_OFFSET            (SDIO_OFFSET + 0x04)
 #define CLKEN_BitNumber            0x08
 #define CLKCTRL_CLKEN_BB          (PERIPH_BB_BASE + (CLKCTRL_OFFSET * 32) + (CLKEN_BitNumber * 4))
 
-/* --- CMD Register ---*/
+/** --- CMD Register ---*/
 
-/* Alias word address of SDIOSC bit */
+/** Alias word address of SDIOSC bit */
 #define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
 #define SDIOSC_BitNumber           0x0B
 #define CMD_SDIOSC_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSC_BitNumber * 4))
 
-/* Alias word address of CMDCPEN bit */
+/** Alias word address of CMDCPEN bit */
 #define CMDCPEN_BitNumber          0x0C
 #define CMD_CMDCPEN_BB            (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (CMDCPEN_BitNumber * 4))
 
-/* Alias word address of INTEN bit */
+/** Alias word address of INTEN bit */
 #define INTEN_BitNumber            0x0D
 #define CMD_INTEN_BB              (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (INTEN_BitNumber * 4))
 
-/* Alias word address of ATACMD bit */
+/** Alias word address of ATACMD bit */
 #define ATACMD_BitNumber           0x0E
 #define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
 
-/* --- DCTRL Register ---*/
+/** --- DCTRL Register ---*/
 
-/* Alias word address of DMAEN bit */
+/** Alias word address of DMAEN bit */
 #define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
 #define DMAEN_BitNumber            0x03
 #define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
 
-/* Alias word address of RWSTR bit */
+/** Alias word address of RWSTR bit */
 #define RWSTR_BitNumber            0x08
 #define DCTRL_RWSTR_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTR_BitNumber * 4))
 
-/* Alias word address of RWSTOP bit */
+/** Alias word address of RWSTOP bit */
 #define RWSTOP_BitNumber           0x09
 #define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
 
-/* Alias word address of RDWAIT bit */
+/** Alias word address of RDWAIT bit */
 #define RDWAIT_BitNumber           0x0A
 #define DCTRL_RDWAIT_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RDWAIT_BitNumber * 4))
 
-/* Alias word address of SDIOF bit */
+/** Alias word address of SDIOF bit */
 #define SDIOF_BitNumber            0x0B
 #define DCTRL_SDIOF_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOF_BitNumber * 4))
 
@@ -318,10 +332,10 @@ typedef struct
     SDIO_CLOCK_EDGE_T            clockEdge;
     SDIO_CLOCK_BYPASS_T          clockBypass;
     SDIO_CLOCK_POWER_SAVE_T      clockPowerSave;
-    SDIO_BUSWIDE_T               busWide;
+    SDIO_BUS_WIDE_T              busWide;
     SDIO_HARDWARE_FLOW_CONTROL_T hardwareFlowControl;
     uint8_t                      clockDiv;
-}SDIO_Config_T;
+} SDIO_Config_T;
 
 /**
  * @brief    SDIO CMD Config structure definition
@@ -333,7 +347,7 @@ typedef struct
     SDIO_RESPONSE_T              response;
     SDIO_WAIT_T                  wait;
     SDIO_CPSM_T                  CPSM;
-}SDIO_CMDConfig_T;
+} SDIO_CmdConfig_T;
 
 /**
  * @brief    SDIO Data Config structure definition
@@ -346,7 +360,7 @@ typedef struct
     SDIO_TRANSFER_DIR_T          transferDir;
     SDIO_TRANSFER_MODE_T         transferMode;
     SDIO_DPSM_T                  DPSM;
-}SDIO_DataConfig_T;
+} SDIO_DataConfig_T;
 
 /**@} end of group SDIO_Structure*/
 
@@ -357,8 +371,8 @@ typedef struct
 
 /** SDIO reset and configuration */
 void SDIO_Reset(void);
-void SDIO_Config(SDIO_Config_T* sdioConfig);
-void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig);
+void SDIO_Config(SDIO_Config_T *sdioConfig);
+void SDIO_ConfigStructInit(SDIO_Config_T *sdioConfig);
 void SDIO_EnableClock(void);
 void SDIO_DisableClock(void);
 void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState);
@@ -369,14 +383,14 @@ void SDIO_EnableDMA(void);
 void SDIO_DisableDMA(void);
 
 /** Command */
-void SDIO_TxCommand(SDIO_CMDConfig_T *cmdConfig);
-void SDIO_TxCommandStructInit(SDIO_CMDConfig_T* cmdconfig);
+void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig);
+void SDIO_TxCommandStructInit(SDIO_CmdConfig_T *cmdconfig);
 uint8_t SDIO_ReadCommandResponse(void);
 uint32_t SDIO_ReadResponse(SDIO_RES_T res);
 
 /** SDIO data configuration */
-void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig);
-void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig);
+void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig);
+void SDIO_ConfigDataStructInit(SDIO_DataConfig_T *dataConfig);
 uint32_t SDIO_ReadDataCounter(void);
 void SDIO_WriteData(uint32_t data);
 uint32_t SDIO_ReadData(void);

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h

@@ -3,21 +3,35 @@
  *
  * @brief       This file contains all the functions prototypes for the SPI firmware library
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_SPI_H
 #define __APM32F10X_SPI_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -39,7 +53,7 @@ typedef enum
     SPI_DIRECTION_2LINES_RXONLY     = 0x0400,
     SPI_DIRECTION_1LINE_RX          = 0x8000,
     SPI_DIRECTION_1LINE_TX          = 0xC000
-}SPI_DIRECTION_T;
+} SPI_DIRECTION_T;
 
 /**
  * @brief    SPI mode
@@ -48,7 +62,7 @@ typedef enum
 {
     SPI_MODE_MASTER = 0x0104,
     SPI_MODE_SLAVE  = 0x0000
-}SPI_MODE_T;
+} SPI_MODE_T;
 
 /**
  * @brief    SPI Data length
@@ -57,7 +71,7 @@ typedef enum
 {
     SPI_DATA_LENGTH_16B = 0x0800,
     SPI_DATA_LENGTH_8B  = 0x0000
-}SPI_DATA_LENGTH_T;
+} SPI_DATA_LENGTH_T;
 
 /**
  * @brief    SPI Clock Polarity
@@ -66,7 +80,7 @@ typedef enum
 {
     SPI_CLKPOL_LOW   = 0x0000,
     SPI_CLKPOL_HIGH  = 0x0002
-}SPI_CLKPOL_T;
+} SPI_CLKPOL_T;
 
 /**
  * @brief    SPI Clock Phase
@@ -75,7 +89,7 @@ typedef enum
 {
     SPI_CLKPHA_1EDGE = 0x0000,
     SPI_CLKPHA_2EDGE = 0x0001
-}SPI_CLKPHA_T;
+} SPI_CLKPHA_T;
 
 /**
  * @brief    SPI Slave Select management
@@ -84,7 +98,7 @@ typedef enum
 {
     SPI_NSS_SOFT = 0x0200,
     SPI_NSS_HARD = 0x0000
-}SPI_NSS_T;
+} SPI_NSS_T;
 
 /**
  * @brief    SPI BaudRate Prescaler
@@ -99,7 +113,7 @@ typedef enum
     SPI_BAUDRATE_DIV_64  = 0x0028,
     SPI_BAUDRATE_DIV_128 = 0x0030,
     SPI_BAUDRATE_DIV_256 = 0x0038,
-}SPI_BAUDRATE_DIV_T;
+} SPI_BAUDRATE_DIV_T;
 
 /**
  * @brief    SPI MSB LSB transmission
@@ -108,7 +122,7 @@ typedef enum
 {
     SPI_FIRSTBIT_MSB = 0x0000,
     SPI_FIRSTBIT_LSB = 0x0080
-}SPI_FIRSTBIT_T;
+} SPI_FIRSTBIT_T;
 
 /**
  * @brief    I2S Mode
@@ -119,7 +133,7 @@ typedef enum
     I2S_MODE_SLAVE_RX  = 0x0100,
     I2S_MODE_MASTER_TX = 0x0200,
     I2S_MODE_MASTER_RX = 0x0300
-}I2S_MODE_T;
+} I2S_MODE_T;
 
 /**
  * @brief    I2S Standard
@@ -131,7 +145,7 @@ typedef enum
     I2S_STANDARD_LSB      = 0x0020,
     I2S_STANDARD_PCMSHORT = 0x0030,
     I2S_STANDARD_PCMLONG  = 0x00B0
-}I2S_STANDARD_T;
+} I2S_STANDARD_T;
 
 /**
  * @brief   I2S data length
@@ -151,7 +165,7 @@ typedef enum
 {
     I2S_MCLK_OUTPUT_DISABLE = 0x0000,
     I2S_MCLK_OUTPUT_ENABLE  = 0x0200,
-}I2S_MCLK_OUTPUT_T;
+} I2S_MCLK_OUTPUT_T;
 
 /**
  * @brief    I2S Audio divider
@@ -168,7 +182,7 @@ typedef enum
     I2S_AUDIO_DIV_11K     = 11025,
     I2S_AUDIO_DIV_8K      = 8000,
     I2S_AUDIO_DIV_DEFAULT = 2
-}I2S_AUDIO_DIV_T;
+} I2S_AUDIO_DIV_T;
 
 /**
  * @brief    I2S Clock Polarity
@@ -177,7 +191,7 @@ typedef enum
 {
     I2S_CLKPOL_LOW      = 0x0000,
     I2S_CLKPOL_HIGH     = 0x0008
-}I2S_CLKPOL_T;
+} I2S_CLKPOL_T;
 
 /**
  * @brief    SPI Direction select
@@ -186,7 +200,7 @@ typedef enum
 {
     SPI_DIRECTION_RX    = 0xBFFF,
     SPI_DIRECTION_TX    = 0x4000
-}SPI_DIRECTION_SELECT_T;
+} SPI_DIRECTION_SELECT_T;
 
 /**
  * @brief    SPI interrupts definition
@@ -200,7 +214,7 @@ typedef enum
     SPI_INT_CRCE        = 0x2010,
     SPI_INT_ME          = 0x2020,
     I2S_INT_UDR         = 0x2008
-}SPI_I2S_INT_T;
+} SPI_I2S_INT_T;
 
 /**
  * @brief    SPI flags definition
@@ -215,7 +229,7 @@ typedef enum
     SPI_FLAG_ME         = 0x0020,
     SPI_FLAG_OVR        = 0x0040,
     SPI_FLAG_BSY        = 0x0080
-}SPI_FLAG_T;
+} SPI_FLAG_T;
 
 /**
  * @brief    SPI I2S DMA requests
@@ -224,7 +238,7 @@ typedef enum
 {
     SPI_I2S_DMA_REQ_TX  = 0x0002,
     SPI_I2S_DMA_REQ_RX  = 0x0001
-}SPI_I2S_DMA_REQ_T;
+} SPI_I2S_DMA_REQ_T;
 
 /**@} end of group SPI_Enumerations*/
 
@@ -247,7 +261,7 @@ typedef struct
     SPI_DIRECTION_T     direction;
     SPI_BAUDRATE_DIV_T  baudrateDiv;
     uint16_t            crcPolynomial;
-}SPI_Config_T;
+} SPI_Config_T;
 
 /**
  * @brief    I2S Config structure definition
@@ -260,7 +274,7 @@ typedef struct
     I2S_MCLK_OUTPUT_T   MCLKOutput;
     I2S_AUDIO_DIV_T     audioDiv;
     I2S_CLKPOL_T        polarity;
-}I2S_Config_T;
+} I2S_Config_T;
 
 /**@} end of group SPI_Structure*/
 
@@ -269,44 +283,44 @@ typedef struct
 */
 
 /** Reset and Configuration */
-void SPI_I2S_Reset(SPI_T* spi);
-void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig);
-void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig);
-void SPI_ConfigStructInit(SPI_Config_T* spiConfig);
-void I2S_ConfigStructInit(I2S_Config_T* i2sConfig);
-void SPI_Enable(SPI_T* spi);
-void SPI_Disable(SPI_T* spi);
-void I2S_Enable(SPI_T* spi);
-void I2S_Disable(SPI_T* spi);
-
-void SPI_I2S_TxData(SPI_T* spi, uint16_t data);
-uint16_t SPI_I2S_RxData(SPI_T* spi);
-void SPI_SetSoftwareNSS(SPI_T* spi);
-void SPI_ResetSoftwareNSS(SPI_T* spi);
-void SPI_EnableSSOutput(SPI_T* spi);
-void SPI_DisableSSOutput(SPI_T* spi);
-void SPI_ConfigDataSize(SPI_T* spi, uint16_t dataSize);
+void SPI_I2S_Reset(SPI_T *spi);
+void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig);
+void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig);
+void SPI_ConfigStructInit(SPI_Config_T *spiConfig);
+void I2S_ConfigStructInit(I2S_Config_T *i2sConfig);
+void SPI_Enable(SPI_T *spi);
+void SPI_Disable(SPI_T *spi);
+void I2S_Enable(SPI_T *spi);
+void I2S_Disable(SPI_T *spi);
+
+void SPI_I2S_TxData(SPI_T *spi, uint16_t data);
+uint16_t SPI_I2S_RxData(SPI_T *spi);
+void SPI_SetSoftwareNSS(SPI_T *spi);
+void SPI_ResetSoftwareNSS(SPI_T *spi);
+void SPI_EnableSSOutput(SPI_T *spi);
+void SPI_DisableSSOutput(SPI_T *spi);
+void SPI_ConfigDataSize(SPI_T *spi, SPI_DATA_LENGTH_T length);
 
 /** DMA */
-void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq);
-void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq);
+void SPI_I2S_EnableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq);
+void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq);
 
 /** CRC */
-void SPI_TxCRC(SPI_T* spi);
-void SPI_EnableCRC(SPI_T* spi);
-void SPI_DisableCRC(SPI_T* spi);
-uint16_t SPI_ReadTxCRC(SPI_T* spi);
-uint16_t SPI_ReadRxCRC(SPI_T* spi);
-uint16_t SPI_ReadCRCPolynomial(SPI_T* spi);
-void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction);
+void SPI_TxCRC(SPI_T *spi);
+void SPI_EnableCRC(SPI_T *spi);
+void SPI_DisableCRC(SPI_T *spi);
+uint16_t SPI_ReadTxCRC(SPI_T *spi);
+uint16_t SPI_ReadRxCRC(SPI_T *spi);
+uint16_t SPI_ReadCRCPolynomial(SPI_T *spi);
+void SPI_ConfigBiDirectionalLine(SPI_T *spi, SPI_DIRECTION_SELECT_T direction);
 
 /** Interrupts and flag */
-void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt);
-void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt);
-uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag);
-void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag);
-uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag);
-void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag);
+void SPI_I2S_EnableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt);
+void SPI_I2S_DisableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt);
+uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag);
+void SPI_I2S_ClearStatusFlag(SPI_T *spi, SPI_FLAG_T flag);
+uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag);
+void SPI_I2S_ClearIntFlag(SPI_T *spi, SPI_I2S_INT_T flag);
 
 /**@} end of group SPI_Fuctions*/
 /**@} end of group SPI_Driver*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h

@@ -1,22 +1,36 @@
 /*!
- * @file       apm32f10x_tmr.h
+ * @file        apm32f10x_tmr.h
  *
- * @brief      This file contains all the functions prototypes for the TMR firmware library.
+ * @brief       This file contains all the functions prototypes for the TMR firmware library.
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 #ifndef __APM32F10X_TMR_H
 #define __APM32F10X_TMR_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -63,7 +77,7 @@ typedef enum
     TMR_OC_MODE_LOWLEVEL   = 0x04,
     TMR_OC_MODE_HIGHLEVEL  = 0x05,
     TMR_OC_MODE_PWM1       = 0x06,
-    TMR_OC_MODE_PWM2       = 0x07,
+    TMR_OC_MODE_PWM2       = 0x07
 } TMR_OC_MODE_T;
 
 /**
@@ -353,9 +367,9 @@ typedef enum
  */
 typedef enum
 {
-    TMR_PRESCALER_RELOAD_UPDATA,
-    TMR_PRESCALER_RELOAD_IMMEDIATE
-} TMR_PRESCALER_RELOAD_T;
+    TMR_PSC_RELOAD_UPDATE,
+    TMR_PSC_RELOAD_IMMEDIATE
+} TMR_PSC_RELOAD_T;
 
 /**
  * @brief    TMR Encoder Mode
@@ -444,7 +458,7 @@ typedef enum
     TMR_SLAVE_MODE_RESET     = 0x04,
     TMR_SLAVE_MODE_GATED     = 0x05,
     TMR_SLAVE_MODE_TRIGGER   = 0x06,
-    TMR_SLAVE_MODE_EXTERNALL = 0x07
+    TMR_SLAVE_MODE_EXTERNAL1 = 0x07
 } TMR_SLAVE_MODE_T;
 
 /**
@@ -532,124 +546,124 @@ typedef struct
 */
 
 /** Reset and Configuration */
-void TMR_Reset(TMR_T* tmr);
-void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T *baseConfig);
-void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T *OC1Config);
-void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T *OC2Config);
-void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T *OC3Config);
-void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T *OC4Config);
-void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T *ICConfig);
-void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T *BDTConfig);
+void TMR_Reset(TMR_T *tmr);
+void TMR_ConfigTimeBase(TMR_T *tmr, TMR_BaseConfig_T *baseConfig);
+void TMR_ConfigOC1(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
+void TMR_ConfigOC2(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
+void TMR_ConfigOC3(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
+void TMR_ConfigOC4(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
+void TMR_ConfigIC(TMR_T *tmr, TMR_ICConfig_T *ICConfig);
+void TMR_ConfigBDT(TMR_T *tmr, TMR_BDTConfig_T *BDTConfig);
 void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig);
 void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig);
 void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig);
-void TMR_ConfigBDTStructInit( TMR_BDTConfig_T *BDTConfig);
-void TMR_Enable(TMR_T* tmr);
-void TMR_Disable(TMR_T* tmr);
+void TMR_ConfigBDTStructInit(TMR_BDTConfig_T *BDTConfig);
+void TMR_ConfigSinglePulseMode(TMR_T *tmr, TMR_SPM_T singlePulseMode);
+void TMR_ConfigClockDivision(TMR_T *tmr, TMR_CLOCK_DIV_T clockDivision);
+void TMR_Enable(TMR_T *tmr);
+void TMR_Disable(TMR_T *tmr);
 
-/* PWM Configuration */
-void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T *PWMConfig);
-void TMR_EnablePWMOutputs(TMR_T* tmr);
-void TMR_DisablePWMOutputs(TMR_T* tmr);
+/** PWM Configuration */
+void TMR_ConfigPWM(TMR_T *tmr, TMR_ICConfig_T *PWMConfig);
+void TMR_EnablePWMOutputs(TMR_T *tmr);
+void TMR_DisablePWMOutputs(TMR_T *tmr);
 
 /** DMA */
-void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength);
-void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource);
-void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource);
+void TMR_ConfigDMA(TMR_T *tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength);
+void TMR_EnableDMASoure(TMR_T *tmr, uint16_t dmaSource);
+void TMR_DisableDMASoure(TMR_T *tmr, uint16_t dmaSource);
 
 /** Configuration */
-void TMR_ConfigInternalClock(TMR_T* tmr);
-void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource);
-void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource,
-                                TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter);
-void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
+void TMR_ConfigInternalClock(TMR_T *tmr);
+void TMR_ConfigIntTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource);
+void TMR_ConfigTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource,
+                                 TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter);
+void TMR_ConfigETRClockMode1(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
                              TMR_EXTTRG_POL_T polarity, uint16_t filter);
-void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
+void TMR_ConfigETRClockMode2(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
                              TMR_EXTTRG_POL_T polarity, uint16_t filter);
-void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
+void TMR_ConfigETR(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
                    TMR_EXTTRG_POL_T polarity, uint16_t filter);
-void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PRESCALER_RELOAD_T pscReloadMode);
-void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode);
-void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSouce);
-void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
+void TMR_ConfigPrescaler(TMR_T *tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode);
+void TMR_ConfigCounterMode(TMR_T *tmr, TMR_COUNTER_MODE_T countMode);
+void TMR_SelectInputTrigger(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSouce);
+void TMR_ConfigEncodeInterface(TMR_T *tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
                                TMR_IC_POLARITY_T IC2Polarity);
-void TMR_ConfigForcedOC1(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
-void TMR_ConfigForcedOC2(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
-void TMR_ConfigForcedOC3(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
-void TMR_ConfigForcedOC4(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
-void TMR_EnableAUTOReload(TMR_T* tmr);
-void TMR_DisableAUTOReload(TMR_T* tmr);
-void TMR_EnableSelectCOM(TMR_T* tmr);
-void TMR_DisableSelectCOM(TMR_T* tmr);
-void TMR_EnableCCDMA(TMR_T* tmr);
-void TMR_DisableCCDMA(TMR_T* tmr);
-void TMR_EnableCCPreload(TMR_T* tmr);
-void TMR_DisableCCPreload(TMR_T* tmr);
-void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
-void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
-void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
-void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
-void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
-void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
-void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
-void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
-void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
-void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
-void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
-void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
-void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
-void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
-void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
-void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
-void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
-void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
-void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
-void TMR_EnableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
-void TMR_DisableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
-void TMR_EnableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
-void TMR_DisableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
-void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode);
-void TMR_EnableNoUpdate(TMR_T* tmr);
-void TMR_DisableNoUpdate(TMR_T* tmr);
-void TMR_ConfigUPdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource);
-void TMR_EnableHallSensor(TMR_T* tmr);
-void TMR_DisableHallSensor(TMR_T* tmr);
-void TMR_SelectSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode);
-void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource);
-void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode);
-void TMR_EnableMasterSlaveMode(TMR_T* tmr);
-void TMR_DisableMasterSlaveMode(TMR_T* tmr);
-void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter);
-void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload);
-void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1);
-void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2);
-void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3);
-void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4);
-void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
-void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
-void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
-void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
-void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision);
-uint16_t TMR_ReadCaputer1(TMR_T* tmr);
-uint16_t TMR_ReadCaputer2(TMR_T* tmr);
-uint16_t TMR_ReadCaputer3(TMR_T* tmr);
-uint16_t TMR_ReadCaputer4(TMR_T* tmr);
-uint16_t TMR_ReadCounter(TMR_T* tmr);
-uint16_t TMR_ReadPrescaler(TMR_T* tmr);
+void TMR_ConfigForcedOC1(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
+void TMR_ConfigForcedOC2(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
+void TMR_ConfigForcedOC3(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
+void TMR_ConfigForcedOC4(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
+void TMR_EnableAutoReload(TMR_T *tmr);
+void TMR_DisableAutoReload(TMR_T *tmr);
+void TMR_EnableSelectCOM(TMR_T *tmr);
+void TMR_DisableSelectCOM(TMR_T *tmr);
+void TMR_EnableCCDMA(TMR_T *tmr);
+void TMR_DisableCCDMA(TMR_T *tmr);
+void TMR_EnableCCPreload(TMR_T *tmr);
+void TMR_DisableCCPreload(TMR_T *tmr);
+void TMR_ConfigOC1Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
+void TMR_ConfigOC2Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
+void TMR_ConfigOC3Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
+void TMR_ConfigOC4Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
+void TMR_ConfigOC1Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
+void TMR_ConfigOC2Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
+void TMR_ConfigOC3Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
+void TMR_ConfigOC4Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
+void TMR_ClearOC1Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
+void TMR_ClearOC2Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
+void TMR_ClearOC3Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
+void TMR_ClearOC4Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
+void TMR_ConfigOC1Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
+void TMR_ConfigOC1NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T OCNPolarity);
+void TMR_ConfigOC2Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
+void TMR_ConfigOC2NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T OCNPolarity);
+void TMR_ConfigOC3Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
+void TMR_ConfigOC3NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T OCNPolarity);
+void TMR_ConfigOC4Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
+void TMR_EnableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
+void TMR_DisableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
+void TMR_EnableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
+void TMR_DisableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
+void TMR_SelectOCxMode(TMR_T *tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode);
+void TMR_EnableUpdate(TMR_T *tmr);
+void TMR_DisableUpdate(TMR_T *tmr);
+void TMR_ConfigUpdateRequest(TMR_T *tmr, TMR_UPDATE_SOURCE_T updateSource);
+void TMR_EnableHallSensor(TMR_T *tmr);
+void TMR_DisableHallSensor(TMR_T *tmr);
+void TMR_SelectOutputTrigger(TMR_T *tmr, TMR_TRGO_SOURCE_T TRGOSource);
+void TMR_SelectSlaveMode(TMR_T *tmr, TMR_SLAVE_MODE_T slaveMode);
+void TMR_EnableMasterSlaveMode(TMR_T *tmr);
+void TMR_DisableMasterSlaveMode(TMR_T *tmr);
+void TMR_ConfigCounter(TMR_T *tmr, uint16_t counter);
+void TMR_ConfigAutoreload(TMR_T *tmr, uint16_t autoReload);
+void TMR_ConfigCompare1(TMR_T *tmr, uint16_t compare1);
+void TMR_ConfigCompare2(TMR_T *tmr, uint16_t compare2);
+void TMR_ConfigCompare3(TMR_T *tmr, uint16_t compare3);
+void TMR_ConfigCompare4(TMR_T *tmr, uint16_t compare4);
+void TMR_ConfigIC1Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
+void TMR_ConfigIC2Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
+void TMR_ConfigIC3Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
+void TMR_ConfigIC4Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
+uint16_t TMR_ReadCaputer1(TMR_T *tmr);
+uint16_t TMR_ReadCaputer2(TMR_T *tmr);
+uint16_t TMR_ReadCaputer3(TMR_T *tmr);
+uint16_t TMR_ReadCaputer4(TMR_T *tmr);
+uint16_t TMR_ReadCounter(TMR_T *tmr);
+uint16_t TMR_ReadPrescaler(TMR_T *tmr);
 
 /** Interrupts and Event */
-void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt);
-void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt);
-void TMR_GenerateEvent(TMR_T* tmr,uint16_t eventSources);
+void TMR_EnableInterrupt(TMR_T *tmr, uint16_t interrupt);
+void TMR_DisableInterrupt(TMR_T *tmr, uint16_t interrupt);
+void TMR_GenerateEvent(TMR_T *tmr, uint16_t eventSources);
 
 /** flags */
-uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag);
-void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag);
-uint16_t TMR_ReadIntFlag(TMR_T* tmr,  TMR_INT_T flag);
-void TMR_ClearIntFlag(TMR_T* tmr,  uint16_t flag);
+uint16_t TMR_ReadStatusFlag(TMR_T *tmr, TMR_FLAG_T flag);
+void TMR_ClearStatusFlag(TMR_T *tmr, uint16_t flag);
+uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag);
+void TMR_ClearIntFlag(TMR_T *tmr, uint16_t flag);
 
 /**@} end of group TMR_Fuctions*/
-/**@} end of group TMR_Driver */
+/**@} end of group TMR_Driver*/
 /**@} end of group Peripherals_Library*/
 
 #ifdef __cplusplus

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h

@@ -1,23 +1,37 @@
 /*!
- * @file       apm32f10x_usart.h
+ * @file        apm32f10x_usart.h
  *
- * @brief      This file contains all the functions prototypes for the USART firmware library
+ * @brief       This file contains all the functions prototypes for the USART firmware library
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_USART_H
 #define __APM32F10X_USART_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -226,64 +240,64 @@ typedef struct
 */
 
 /** USART Reset and Configuration */
-void USART_Reset(USART_T* usart);
-void USART_Config(USART_T* uart, USART_Config_T* usartConfig);
-void USART_ConfigStructInit(USART_Config_T* usartConfig);
-void USART_Address(USART_T* usart, uint8_t address);
-void USART_Enable(USART_T* usart);
-void USART_Disable(USART_T* usart);
+void USART_Reset(USART_T *usart);
+void USART_Config(USART_T *uart, USART_Config_T *usartConfig);
+void USART_ConfigStructInit(USART_Config_T *usartConfig);
+void USART_Address(USART_T *usart, uint8_t address);
+void USART_Enable(USART_T *usart);
+void USART_Disable(USART_T *usart);
 
 /** Clock communication */
-void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig);
-void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig);
+void USART_ConfigClock(USART_T *usart, USART_ClockConfig_T *clockConfig);
+void USART_ConfigClockStructInit(USART_ClockConfig_T *clockConfig);
 
 /** DMA mode */
-void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq);
-void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq);
+void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq);
+void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq);
 
 /** Mute mode */
-void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup);
-void USART_EnableMuteMode(USART_T* usart);
-void USART_DisableMuteMode(USART_T* usart);
+void USART_ConfigWakeUp(USART_T *usart, USART_WAKEUP_T wakeup);
+void USART_EnableMuteMode(USART_T *usart);
+void USART_DisableMuteMode(USART_T *usart);
 
 /** LIN mode */
-void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length);
-void USART_EnableLIN(USART_T* usart);
-void USART_DisableLIN(USART_T* usart);
+void USART_ConfigLINBreakDetectLength(USART_T *usart, USART_LBDL_T length);
+void USART_EnableLIN(USART_T *usart);
+void USART_DisableLIN(USART_T *usart);
 
 /** Transmit and receive */
-void USART_EnableTx(USART_T* usart);
-void USART_DisableTx(USART_T* usart);
-void USART_EnableRx(USART_T* usart);
-void USART_DisableRx(USART_T* usart);
-void USART_TxData(USART_T* usart, uint16_t data);
-uint16_t USART_RxData(USART_T* usart);
-void USART_TxBreak(USART_T* usart);
+void USART_EnableTx(USART_T *usart);
+void USART_DisableTx(USART_T *usart);
+void USART_EnableRx(USART_T *usart);
+void USART_DisableRx(USART_T *usart);
+void USART_TxData(USART_T *usart, uint16_t data);
+uint16_t USART_RxData(USART_T *usart);
+void USART_TxBreak(USART_T *usart);
 
 /** Smartcard mode */
-void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime);
-void USART_ConfigPrescaler(USART_T* usart, uint8_t div);
-void USART_EnableSmartCard(USART_T* usart);
-void USART_DisableSmartCard(USART_T* usart);
-void USART_EnableSmartCardNACK(USART_T* usart);
-void USART_DisableSmartCardNACK(USART_T* usart);
+void USART_ConfigGuardTime(USART_T *usart, uint8_t guardTime);
+void USART_ConfigPrescaler(USART_T *usart, uint8_t div);
+void USART_EnableSmartCard(USART_T *usart);
+void USART_DisableSmartCard(USART_T *usart);
+void USART_EnableSmartCardNACK(USART_T *usart);
+void USART_DisableSmartCardNACK(USART_T *usart);
 
 /** Half-duplex mode  */
-void USART_EnableHalfDuplex(USART_T* usart);
-void USART_DisableHalfDuplex(USART_T* usart);
+void USART_EnableHalfDuplex(USART_T *usart);
+void USART_DisableHalfDuplex(USART_T *usart);
 
 /** IrDA mode */
-void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode);
-void USART_EnableIrDA(USART_T* usart);
-void USART_DisableIrDA(USART_T* usart);
+void USART_ConfigIrDA(USART_T *usart, USART_IRDALP_T IrDAMode);
+void USART_EnableIrDA(USART_T *usart);
+void USART_DisableIrDA(USART_T *usart);
 
 /** Interrupt and flag */
-void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt);
-void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt);
-uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag);
-void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag);
-uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag);
-void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag);
+void USART_EnableInterrupt(USART_T *usart, USART_INT_T interrupt);
+void USART_DisableInterrupt(USART_T *usart, USART_INT_T interrupt);
+uint8_t USART_ReadStatusFlag(USART_T *usart, USART_FLAG_T flag);
+void USART_ClearStatusFlag(USART_T *usart, USART_FLAG_T flag);
+uint8_t USART_ReadIntFlag(USART_T *usart, USART_INT_T flag);
+void USART_ClearIntFlag(USART_T *usart, USART_INT_T flag);
 
 /**@} end of group USART_Fuctions*/
 /**@} end of group USART_Driver*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h

@@ -3,21 +3,35 @@
  *
  * @brief       This file contains all the functions prototypes for the WWDT firmware library
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __APM32F10X_WWDT_H
 #define __APM32F10X_WWDT_H
 
-#include "apm32f10x.h"
-
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+#include "apm32f10x.h"
+
 /** @addtogroup Peripherals_Library Standard Peripheral Library
   @{
 */
@@ -39,7 +53,7 @@ typedef enum
     WWDT_TIME_BASE_2 = 0x00000080,
     WWDT_TIME_BASE_4 = 0x00000100,
     WWDT_TIME_BASE_8 = 0x00000180
-}WWDT_TIME_BASE_T;
+} WWDT_TIME_BASE_T;
 
 /**@} end of group WWDT_Enumerations*/
 
@@ -68,7 +82,7 @@ uint8_t WWDT_ReadFlag(void);
 void WWDT_ClearFlag(void);
 
 /**@} end of group WWDT_Fuctions*/
-/**@} end of group WWDT_Driver */
+/**@} end of group WWDT_Driver*/
 /**@} end of group Peripherals_Library*/
 
 #ifdef __cplusplus

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c

@@ -3,10 +3,24 @@
  *
  * @brief       This file provides all the ADC firmware functions
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_adc.h"
@@ -25,22 +39,22 @@
 */
 
 /*!
- * @brief     Reset ADC peripheral registers to their default reset values.
+ * @brief       Reset ADC peripheral registers to their default reset values.
  *
- * @param     adc: Select ADC peripheral.
+ * @param       adc: Select ADC peripheral.
  *
- * @retval    None
+ * @retval      None
  *
- * @note      adc can be ADC1, ADC2 or ADC3.
+ * @note        adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_Reset(ADC_T* adc)
+void ADC_Reset(ADC_T *adc)
 {
-    if(adc == ADC1)
+    if (adc == ADC1)
     {
         RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_ADC1);
         RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_ADC1);
     }
-    else if(adc == ADC2)
+    else if (adc == ADC2)
     {
         RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_ADC2);
         RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_ADC2);
@@ -63,7 +77,7 @@ void ADC_Reset(ADC_T* adc)
  *
  * @note        adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig)
+void ADC_Config(ADC_T *adc, ADC_Config_T *adcConfig)
 {
     uint32_t reg;
 
@@ -74,8 +88,10 @@ void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig)
 
     reg = adc->CTRL2;
     reg &= 0xFFF1F7FD;
-    reg |= (uint32_t)(adcConfig->dataAlign | adcConfig->externalTrigConv |
-                    ((uint32_t)adcConfig->continuosConvMode << 1));
+    reg |= (uint32_t)adcConfig->dataAlign | \
+           (uint32_t)adcConfig->externalTrigConv | \
+           ((uint32_t)adcConfig->continuosConvMode << 1);
+
     adc->CTRL2 = reg;
 
     reg = adc->REGSEQ1;
@@ -91,7 +107,7 @@ void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig)
  *
  * @retval      None
  */
-void ADC_ConfigStructInit(ADC_Config_T* adcConfig)
+void ADC_ConfigStructInit(ADC_Config_T *adcConfig)
 {
     adcConfig->mode = ADC_MODE_INDEPENDENT;
     adcConfig->scanConvMode = DISABLE;
@@ -110,7 +126,7 @@ void ADC_ConfigStructInit(ADC_Config_T* adcConfig)
  *
  * @note        adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_Enable(ADC_T* adc)
+void ADC_Enable(ADC_T *adc)
 {
     adc->CTRL2_B.ADCEN = BIT_SET;
 }
@@ -124,7 +140,7 @@ void ADC_Enable(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_Disable(ADC_T* adc)
+void ADC_Disable(ADC_T *adc)
 {
     adc->CTRL2_B.ADCEN = BIT_RESET;
 }
@@ -138,7 +154,7 @@ void ADC_Disable(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableDMA(ADC_T* adc)
+void ADC_EnableDMA(ADC_T *adc)
 {
     adc->CTRL2_B.DMAEN = BIT_SET;
 }
@@ -152,7 +168,7 @@ void ADC_EnableDMA(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableDMA(ADC_T* adc)
+void ADC_DisableDMA(ADC_T *adc)
 {
     adc->CTRL2_B.DMAEN = BIT_RESET;
 }
@@ -166,7 +182,7 @@ void ADC_DisableDMA(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ResetCalibration(ADC_T* adc)
+void ADC_ResetCalibration(ADC_T *adc)
 {
     adc->CTRL2_B.CALRST = BIT_SET;
 }
@@ -180,7 +196,7 @@ void ADC_ResetCalibration(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc)
+uint8_t ADC_ReadResetCalibrationStatus(ADC_T *adc)
 {
     uint8_t ret;
     ret = (adc->CTRL2_B.CALRST) ? BIT_SET : BIT_RESET;
@@ -196,7 +212,7 @@ uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_StartCalibration(ADC_T* adc)
+void ADC_StartCalibration(ADC_T *adc)
 {
     adc->CTRL2_B.CAL = BIT_SET;
 }
@@ -210,7 +226,7 @@ void ADC_StartCalibration(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc)
+uint8_t ADC_ReadCalibrationStartFlag(ADC_T *adc)
 {
     uint8_t ret;
     ret = (adc->CTRL2_B.CAL) ? BIT_SET : BIT_RESET;
@@ -226,7 +242,7 @@ uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableSoftwareStartConv(ADC_T* adc)
+void ADC_EnableSoftwareStartConv(ADC_T *adc)
 {
     adc->CTRL2 |= 0x00500000;
 }
@@ -240,7 +256,7 @@ void ADC_EnableSoftwareStartConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableSoftwareStartConv(ADC_T* adc)
+void ADC_DisableSoftwareStartConv(ADC_T *adc)
 {
     adc->CTRL2 &= 0xFFAFFFFF;
 }
@@ -254,7 +270,7 @@ void ADC_DisableSoftwareStartConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc)
+uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T *adc)
 {
     uint8_t ret;
     ret = (adc->CTRL2_B.REGSWSC) ? BIT_SET : BIT_RESET;
@@ -273,7 +289,7 @@ uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigDiscModeChannel(ADC_T* adc, uint8_t number)
+void ADC_ConfigDiscMode(ADC_T *adc, uint8_t number)
 {
     adc->CTRL1_B.DISCNUMCFG |= number - 1;
 }
@@ -287,7 +303,7 @@ void ADC_ConfigDiscModeChannel(ADC_T* adc, uint8_t number)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableDiscMode(ADC_T* adc)
+void ADC_EnableDiscMode(ADC_T *adc)
 {
     adc->CTRL1_B.REGDISCEN = BIT_SET;
 }
@@ -301,7 +317,7 @@ void ADC_EnableDiscMode(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableDiscMode(ADC_T* adc)
+void ADC_DisableDiscMode(ADC_T *adc)
 {
     adc->CTRL1_B.REGDISCEN = BIT_RESET;
 }
@@ -337,24 +353,24 @@ void ADC_DisableDiscMode(ADC_T* adc)
  *
  * @param        sampleTime: the specified ADC channel SampleTime
  *                           The parameter can be one of following values:
- *                           @arg ADC_SAMPLE_TIME_1_5:   ADC 1.5 clock cycles
- *                           @arg ADC_SAMPLE_TIME_7_5:   ADC 7.5 clock cycles
- *                           @arg ADC_SAMPLE_TIME_13_5:  ADC 13.5 clock cycles
- *                           @arg ADC_SAMPLE_TIME_28_5:  ADC 28.5 clock cycles
- *                           @arg ADC_SAMPLE_TIME_41_5:  ADC 41.5 clock cycles
- *                           @arg ADC_SAMPLE_TIME_55_5:  ADC 55.5 clock cycles
- *                           @arg ADC_SAMPLE_TIME_71_5:  ADC 71.5 clock cycles
- *                           @arg ADC_SAMPLE_TIME_239_5: ADC 239.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_1CYCLES5:   ADC 1.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_7CYCLES5:   ADC 7.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_13CYCLES5:  ADC 13.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_28CYCLES5:  ADC 28.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_41CYCLES5:  ADC 41.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_55CYCLES5:  ADC 55.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_71CYCLES5:  ADC 71.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_239CYCLES5: ADC 239.5 clock cycles
  *
  * @retval       None
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime)
+void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
 {
     uint32_t temp1 = 0;
     uint32_t temp2 = 0;
-    if(channel > ADC_CHANNEL_9)
+    if (channel > ADC_CHANNEL_9)
     {
         temp1 = adc->SMPTIM1;
         temp2 = SMPCYCCFG_SET_SMPTIM1 << (3 * (channel - 10));
@@ -373,7 +389,7 @@ void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t
         adc->SMPTIM2 = temp1;
     }
 
-    if(rank < 7)
+    if (rank < 7)
     {
         temp1 = adc->REGSEQ3;
         temp2 = REGSEQC_SET_REGSEQ3 << (5 * (rank - 1));
@@ -382,7 +398,7 @@ void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t
         temp1 |= temp2;
         adc->REGSEQ3 = temp1;
     }
-    else if(rank < 13)
+    else if (rank < 13)
     {
         temp1 = adc->REGSEQ2;
         temp2 = REGSEQC_SET_REGSEQ2 << (5 * (rank - 7));
@@ -411,7 +427,7 @@ void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableExternalTrigConv(ADC_T* adc)
+void ADC_EnableExternalTrigConv(ADC_T *adc)
 {
     adc->CTRL2_B.REGEXTTRGEN = BIT_SET;
 }
@@ -425,7 +441,7 @@ void ADC_EnableExternalTrigConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableExternalTrigConv(ADC_T* adc)
+void ADC_DisableExternalTrigConv(ADC_T *adc)
 {
     adc->CTRL2_B.REGEXTTRGEN = BIT_RESET;
 }
@@ -439,7 +455,7 @@ void ADC_DisableExternalTrigConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint16_t ADC_ReadConversionValue(ADC_T* adc)
+uint16_t ADC_ReadConversionValue(ADC_T *adc)
 {
     return (uint16_t) adc->REGDATA;
 }
@@ -453,9 +469,9 @@ uint16_t ADC_ReadConversionValue(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc)
+uint32_t ADC_ReadDualModeConversionValue(ADC_T *adc)
 {
-      return (*(__IOM uint32_t *) RDG_ADDRESS);
+    return (*(__IOM uint32_t *) RDG_ADDRESS);
 }
 
 /*!
@@ -467,7 +483,7 @@ uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableInjectedConv(ADC_T* adc)
+void ADC_EnableAutoInjectedConv(ADC_T *adc)
 {
     adc->CTRL1_B.INJGACEN = BIT_SET;
 }
@@ -481,7 +497,7 @@ void ADC_EnableInjectedConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableInjectedConv(ADC_T* adc)
+void ADC_DisableAutoInjectedConv(ADC_T *adc)
 {
     adc->CTRL1_B.INJGACEN = BIT_RESET;
 }
@@ -495,7 +511,7 @@ void ADC_DisableInjectedConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableInjectedDiscMode(ADC_T* adc)
+void ADC_EnableInjectedDiscMode(ADC_T *adc)
 {
     adc->CTRL1_B.INJDISCEN = BIT_SET;
 }
@@ -509,7 +525,7 @@ void ADC_EnableInjectedDiscMode(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableInjectedDiscMode(ADC_T* adc)
+void ADC_DisableInjectedDiscMode(ADC_T *adc)
 {
     adc->CTRL1_B.INJDISCEN = BIT_RESET;
 }
@@ -542,7 +558,7 @@ void ADC_DisableInjectedDiscMode(ADC_T* adc)
  *
  * @note    adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv)
+void ADC_ConfigExternalTrigInjectedConv(ADC_T *adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv)
 {
     adc->CTRL2_B.INJGEXTTRGSEL = RESET;
     adc->CTRL2_B.INJGEXTTRGSEL |= extTrigInjecConv;
@@ -557,7 +573,7 @@ void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T ex
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableExternalTrigInjectedConv(ADC_T* adc)
+void ADC_EnableExternalTrigInjectedConv(ADC_T *adc)
 {
     adc->CTRL2_B.INJEXTTRGEN = BIT_SET;
 }
@@ -571,7 +587,7 @@ void ADC_EnableExternalTrigInjectedConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableExternalTrigInjectedConv(ADC_T* adc)
+void ADC_DisableExternalTrigInjectedConv(ADC_T *adc)
 {
     adc->CTRL2_B.INJEXTTRGEN = BIT_RESET;
 }
@@ -585,7 +601,7 @@ void ADC_DisableExternalTrigInjectedConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc)
+void ADC_EnableSoftwareStartInjectedConv(ADC_T *adc)
 {
     adc->CTRL2_B.INJEXTTRGEN = BIT_SET;
     adc->CTRL2_B.INJSWSC = BIT_SET;
@@ -600,7 +616,7 @@ void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc)
+void ADC_DisableSoftwareStartInjectedConv(ADC_T *adc)
 {
     adc->CTRL2_B.INJEXTTRGEN = BIT_RESET;
     adc->CTRL2_B.INJSWSC = BIT_RESET;
@@ -615,7 +631,7 @@ void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc)
+uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T *adc)
 {
     uint8_t ret;
     ret = (adc->CTRL2_B.INJSWSC) ? BIT_SET : BIT_RESET;
@@ -653,20 +669,20 @@ uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc)
  *
  * @param        sampleTime: the specified ADC channel SampleTime
  *                           The parameter can be one of following values:
- *                           @arg ADC_SAMPLE_TIME_1_5:   ADC 1.5 clock cycles
- *                           @arg ADC_SAMPLE_TIME_7_5:   ADC 7.5 clock cycles
- *                           @arg ADC_SAMPLE_TIME_13_5:  ADC 13.5 clock cycles
- *                           @arg ADC_SAMPLE_TIME_28_5:  ADC 28.5 clock cycles
- *                           @arg ADC_SAMPLE_TIME_41_5:  ADC 41.5 clock cycles
- *                           @arg ADC_SAMPLE_TIME_55_5:  ADC 55.5 clock cycles
- *                           @arg ADC_SAMPLE_TIME_71_5:  ADC 71.5 clock cycles
- *                           @arg ADC_SAMPLE_TIME_239_5: ADC 239.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_1CYCLES5:   ADC 1.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_7CYCLES5:   ADC 7.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_13CYCLES5:  ADC 13.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_28CYCLES5:  ADC 28.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_41CYCLES5:  ADC 41.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_55CYCLES5:  ADC 55.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_71CYCLES5:  ADC 71.5 clock cycles
+ *                           @arg ADC_SAMPLETIME_239CYCLES5: ADC 239.5 clock cycles
  *
  * @retval       None
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
+void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
 {
     uint32_t temp1 = 0;
     uint32_t temp2 = 0;
@@ -674,9 +690,9 @@ void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_
     if (channel > ADC_CHANNEL_9)
     {
         temp1 = adc->SMPTIM1;
-        temp2 = SMPCYCCFG_SET_SMPTIM1 << (3*(channel - 10));
+        temp2 = SMPCYCCFG_SET_SMPTIM1 << (3 * (channel - 10));
         temp1 &= ~temp2;
-        temp2 = (uint32_t)sampleTime << (3*(channel - 10));
+        temp2 = (uint32_t)sampleTime << (3 * (channel - 10));
         temp1 |= temp2;
         adc->SMPTIM1 = temp1;
     }
@@ -690,7 +706,7 @@ void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_
         adc->SMPTIM2 = temp1;
     }
     temp1 = adc->INJSEQ;
-    temp3 =  (temp1 & INJSEQ_SET_INJSEQLEN)>> 20;
+    temp3 = (temp1 & INJSEQ_SET_INJSEQLEN) >> 20;
     temp2 = INJSEQ_SET_INJSEQC << (5 * (uint8_t)((rank + 3) - (temp3 + 1)));
     temp1 &= ~temp2;
     temp2 = (uint32_t)channel << (5 * (uint8_t)((rank + 3) - (temp3 + 1)));
@@ -710,7 +726,7 @@ void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_
  *
  * @note     adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length)
+void ADC_ConfigInjectedSequencerLength(ADC_T *adc, uint8_t length)
 {
     adc->INJSEQ_B.INJSEQLEN = RESET;
     adc->INJSEQ_B.INJSEQLEN |= length - 1;
@@ -735,7 +751,7 @@ void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length)
  *
  * @note      adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet)
+void ADC_ConfigInjectedOffset(ADC_T *adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet)
 {
     __IOM uint32_t tmp = 0;
 
@@ -761,14 +777,14 @@ void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t
  *
  * @note      adc can be ADC1, ADC2 or ADC3.
  */
-uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel)
+uint16_t ADC_ReadInjectedConversionValue(ADC_T *adc, ADC_INJEC_CHANNEL_T channel)
 {
-  __IOM uint32_t temp = 0;
+    __IOM uint32_t temp = 0;
 
-  temp = (uint32_t)adc;
-  temp += channel + INJDATA_OFFSET;
+    temp = (uint32_t)adc;
+    temp += channel + INJDATA_OFFSET;
 
-  return (uint16_t) (*(__IOM uint32_t*)  temp);
+    return (uint16_t)(*(__IOM uint32_t *)  temp);
 }
 
 /*!
@@ -790,7 +806,7 @@ uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog)
+void ADC_EnableAnalogWatchdog(ADC_T *adc, uint32_t analogWatchdog)
 {
     adc->CTRL1 &= 0xFF3FFDFF;
     adc->CTRL1 |= analogWatchdog;
@@ -805,7 +821,7 @@ void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableAnalogWatchdog(ADC_T* adc)
+void ADC_DisableAnalogWatchdog(ADC_T *adc)
 {
     adc->CTRL1 &= 0xFF3FFDFF;
 }
@@ -825,7 +841,7 @@ void ADC_DisableAnalogWatchdog(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold)
+void ADC_ConfigAnalogWatchdogThresholds(ADC_T *adc, uint16_t highThreshold, uint16_t lowThreshold)
 {
     adc->AWDHT = highThreshold;
     adc->AWDLT = lowThreshold;
@@ -861,7 +877,7 @@ void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel)
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T *adc, uint8_t channel)
 {
     adc->CTRL1_B.AWDCHSEL = BIT_RESET;
     adc->CTRL1 |= channel;
@@ -876,7 +892,7 @@ void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel)
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableTempSensorVrefint(ADC_T* adc)
+void ADC_EnableTempSensorVrefint(ADC_T *adc)
 {
     adc->CTRL2_B.TSVREFEN = BIT_SET;
 }
@@ -890,7 +906,7 @@ void ADC_EnableTempSensorVrefint(ADC_T* adc)
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableTempSensorVrefint(ADC_T* adc)
+void ADC_DisableTempSensorVrefint(ADC_T *adc)
 {
     adc->CTRL2_B.TSVREFEN = BIT_RESET;
 }
@@ -910,7 +926,7 @@ void ADC_DisableTempSensorVrefint(ADC_T* adc)
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt)
+void ADC_EnableInterrupt(ADC_T *adc, uint16_t interrupt)
 {
     uint8_t mask;
 
@@ -933,7 +949,7 @@ void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt)
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt)
+void ADC_DisableInterrupt(ADC_T *adc, uint16_t interrupt)
 {
     uint8_t mask;
 
@@ -958,19 +974,9 @@ void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt)
  *
  * @note      adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag)
+uint8_t ADC_ReadStatusFlag(ADC_T *adc, ADC_FLAG_T flag)
 {
-    uint8_t status = RESET;
-
-    if ((adc->STS & flag) != (uint8_t)RESET)
-    {
-        status = SET;
-    }
-    else
-    {
-    status = RESET;
-    }
-    return  status;
+    return (adc->STS & flag) ? SET : RESET;
 }
 
 /*!
@@ -990,7 +996,7 @@ uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag)
  *
  * @note      adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag)
+void ADC_ClearStatusFlag(ADC_T *adc, uint8_t flag)
 {
     adc->STS = ~(uint32_t)flag;
 }
@@ -1010,14 +1016,14 @@ void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T interrupt)
+uint8_t ADC_ReadIntFlag(ADC_T *adc, ADC_INT_T flag)
 {
     uint8_t bitStatus = RESET;
     uint32_t itmask = 0;
     uint32_t enableStatus = 0;
 
-    itmask = interrupt >> 8;
-    enableStatus = (adc->CTRL1 & (uint8_t)interrupt);
+    itmask = flag >> 8;
+    enableStatus = (adc->CTRL1 & (uint8_t)flag);
 
     if (((adc->STS & itmask) != (uint32_t)RESET) && enableStatus)
     {
@@ -1045,12 +1051,12 @@ uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T interrupt)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ClearIntFlag(ADC_T* adc, uint16_t interrupt)
+void ADC_ClearIntFlag(ADC_T *adc, uint16_t flag)
 {
-  uint8_t mask = 0;
+    uint8_t mask = 0;
 
-  mask = (uint8_t)(interrupt >> 8);
-  adc->STS = ~(uint32_t)mask;
+    mask = (uint8_t)(flag >> 8);
+    adc->STS = ~(uint32_t)mask;
 }
 
 /**@} end of group ADC_Fuctions*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c

@@ -1,12 +1,26 @@
 /*!
- * @file       apm32f10x_bakpr.c
+ * @file        apm32f10x_bakpr.c
  *
- * @brief      This file provides all the BAKPR firmware functions.
+ * @brief       This file provides all the BAKPR firmware functions.
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_bakpr.h"
@@ -114,16 +128,19 @@ void BAKPR_DisableInterrupt(void)
  */
 void BAKPR_ConfigRTCOutput(BAKPR_RTC_OUTPUT_SOURCE_T soure)
 {
-    if(soure == BAKPR_RTC_OUTPUT_SOURCE_NONE)
+    if (soure == BAKPR_RTC_OUTPUT_SOURCE_NONE)
     {
         BAKPR->CLKCAL = RESET;
-    } else if(soure == BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK)
+    }
+    else if (soure == BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK)
     {
         BAKPR->CLKCAL_B.CALCOEN = BIT_SET;
-    } else if(soure == BAKPR_RTC_OUTPUT_SOURCE_ALARM)
+    }
+    else if (soure == BAKPR_RTC_OUTPUT_SOURCE_ALARM)
     {
         BAKPR->CLKCAL_B.ASPOEN = BIT_SET;
-    } else if(soure == BAKPR_RTC_OUTPUT_SOURCE_SECOND)
+    }
+    else if (soure == BAKPR_RTC_OUTPUT_SOURCE_SECOND)
     {
         BAKPR->CLKCAL_B.ASPOSEL = BIT_SET;
     }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c

@@ -1,12 +1,26 @@
 /*!
- * @file       apm32f10x_can.c
+ * @file        apm32f10x_can.c
  *
- * @brief      This file provides all the CAN firmware functions
+ * @brief       This file provides all the CAN firmware functions
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_can.h"
@@ -33,7 +47,7 @@
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_Reset(CAN_T* can)
+void CAN_Reset(CAN_T *can)
 {
     if (can == CAN1)
     {
@@ -58,7 +72,7 @@ void CAN_Reset(CAN_T* can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
+uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
 {
     uint8_t  initStatus = ERROR;
     uint32_t wait_ack = 0x00000000;
@@ -69,27 +83,18 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
     can->MCTRL_B.INITREQ = BIT_SET;
 
     /** Wait the acknowledge */
-    while(((can->MSTS_B.INITFLG) != BIT_SET) && (wait_ack != 0x0000FFFF))
+    while (((can->MSTS_B.INITFLG) != BIT_SET) && (wait_ack != 0x0000FFFF))
     {
         wait_ack++;
     }
     /** Check acknowledge */
-    if(((can->MSTS_B.INITFLG) != BIT_SET))
+    if (((can->MSTS_B.INITFLG) != BIT_SET))
     {
         initStatus = ERROR;
     }
     else
     {
-        if(canConfig->timeTrigComMode == ENABLE)
-        {
-            can->MCTRL_B.TTCM = BIT_SET;
-        }
-        else
-        {
-            can->MCTRL_B.TTCM = BIT_RESET;
-        }
-
-        if(canConfig->autoBusOffManage == ENABLE)
+        if (canConfig->autoBusOffManage == ENABLE)
         {
             can->MCTRL_B.ALBOFFM = BIT_SET;
         }
@@ -98,7 +103,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
             can->MCTRL_B.ALBOFFM = BIT_RESET;
         }
 
-        if(canConfig->autoWakeUpMode == ENABLE)
+        if (canConfig->autoWakeUpMode == ENABLE)
         {
             can->MCTRL_B.AWUPCFG = BIT_SET;
         }
@@ -107,7 +112,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
             can->MCTRL_B.AWUPCFG = BIT_RESET;
         }
 
-        if(canConfig->nonAutoRetran == ENABLE)
+        if (canConfig->nonAutoRetran == ENABLE)
         {
             can->MCTRL_B.ARTXMD = BIT_SET;
         }
@@ -116,7 +121,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
             can->MCTRL_B.ARTXMD = BIT_RESET;
         }
 
-        if(canConfig->rxFIFOLockMode == ENABLE)
+        if (canConfig->rxFIFOLockMode == ENABLE)
         {
             can->MCTRL_B.RXFLOCK = BIT_SET;
         }
@@ -125,7 +130,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
             can->MCTRL_B.RXFLOCK = BIT_RESET;
         }
 
-        if(canConfig->txFIFOPriority == ENABLE)
+        if (canConfig->txFIFOPriority == ENABLE)
         {
             can->MCTRL_B.TXFPCFG = BIT_SET;
         }
@@ -147,12 +152,12 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
 
         wait_ack = 0;
         /** Wait the acknowledge */
-        while(((can->MSTS_B.INITFLG) != BIT_RESET) && (wait_ack != 0x0000FFFF))
+        while (((can->MSTS_B.INITFLG) != BIT_RESET) && (wait_ack != 0x0000FFFF))
         {
             wait_ack++;
         }
         /** Check acknowledge */
-        if(((can->MSTS_B.INITFLG) != BIT_RESET))
+        if (((can->MSTS_B.INITFLG) != BIT_RESET))
         {
             initStatus = ERROR;
         }
@@ -169,20 +174,20 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
  *
  * @param     can: Select the CAN peripheral which can be CAN1 or CAN2.
  *
- * @param     filterConfig :Point to a CAN_FILTER_CONFIG_T structure.
+ * @param     filterConfig :Point to a CAN_FilterConfig_T structure.
  *
  * @retval    None
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig)
+void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig)
 {
     can->FCTRL_B.FINITEN = BIT_SET;
 
     can->FACT &= ~(1 << filterConfig->filterNumber);
 
     /** Filter Scale */
-    if(filterConfig->filterScale == CAN_FILTER_SCALE_16BIT)
+    if (filterConfig->filterScale == CAN_FILTER_SCALE_16BIT)
     {
         /** 16-bit scale for the filter */
         can->FSCFG &= ~(1 << filterConfig->filterNumber);
@@ -196,7 +201,7 @@ void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig)
             (0x0000FFFF & filterConfig->filterIdHigh);
     }
 
-    if(filterConfig->filterScale == CAN_FILTER_SCALE_32BIT)
+    if (filterConfig->filterScale == CAN_FILTER_SCALE_32BIT)
     {
         can->FSCFG |= (1 << filterConfig->filterNumber);
 
@@ -210,7 +215,7 @@ void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig)
     }
 
     /** Filter Mode */
-    if(filterConfig->filterMode == CAN_FILTER_MODE_IDMASK)
+    if (filterConfig->filterMode == CAN_FILTER_MODE_IDMASK)
     {
         can->FMCFG &= ~(1 << filterConfig->filterNumber);
     }
@@ -220,17 +225,17 @@ void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig)
     }
 
     /** Filter FIFO assignment */
-    if(filterConfig->filterFIFO == CAN_FILTER_FIFO_0)
+    if (filterConfig->filterFIFO == CAN_FILTER_FIFO_0)
     {
         can->FFASS &= ~(1 << filterConfig->filterNumber);
     }
-    if(filterConfig->filterFIFO == CAN_FILTER_FIFO_1)
+    if (filterConfig->filterFIFO == CAN_FILTER_FIFO_1)
     {
         can->FFASS |= (1 << filterConfig->filterNumber);
     }
 
     /** Filter activation */
-    if(filterConfig->filterActivation == ENABLE)
+    if (filterConfig->filterActivation == ENABLE)
     {
         can->FACT |= (1 << filterConfig->filterNumber);
     }
@@ -246,9 +251,8 @@ void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_ConfigStructInit(CAN_Config_T* canConfig)
+void CAN_ConfigStructInit(CAN_Config_T *canConfig)
 {
-    canConfig->timeTrigComMode  = DISABLE;
     canConfig->autoBusOffManage = DISABLE;
     canConfig->autoWakeUpMode   = DISABLE;
     canConfig->nonAutoRetran    = DISABLE;
@@ -270,7 +274,7 @@ void CAN_ConfigStructInit(CAN_Config_T* canConfig)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_EnableDBGFreeze(CAN_T* can)
+void CAN_EnableDBGFreeze(CAN_T *can)
 {
     can->MCTRL_B.DBGFRZE = ENABLE;
 }
@@ -284,45 +288,23 @@ void CAN_EnableDBGFreeze(CAN_T* can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_DisableDBGFreeze(CAN_T* can)
+void CAN_DisableDBGFreeze(CAN_T *can)
 {
     can->MCTRL_B.DBGFRZE = DISABLE;
 }
 
 /*!
- * @brief     Enables the CAN Time TriggerOperation communication mode.
- *
- * @param     can: Select the CAN peripheral.
- *
- * @retval    None
- *
- * @note      CAN2 applies only to APM32F103xC device.
- */
-void CAN_EnableTTCComMode(CAN_T* can)
-{
-    can->MCTRL_B.TTCM = ENABLE;
-
-    can->sTxMailBox[0].TXDLEN_B.TXTS = BIT_SET;
-    can->sTxMailBox[1].TXDLEN_B.TXTS = BIT_SET;
-    can->sTxMailBox[2].TXDLEN_B.TXTS = BIT_SET;
-}
-
-/*!
- * @brief     Disable the CAN Time TriggerOperation communication mode.
+ * @brief     Select the start bank filter for slave CAN.
  *
- * @param     can: Select the CAN peripheral.
+ * @param     bankNum: the start slave bank filter from 1..27.
  *
  * @retval    None
- *
- * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_DisableTTCComMode(CAN_T* can)
+void CAN_SlaveStartBank(CAN_T *can, uint8_t bankNum)
 {
-    can->MCTRL_B.TTCM = DISABLE;
-
-    can->sTxMailBox[0].TXDLEN_B.TXTS = BIT_RESET;
-    can->sTxMailBox[1].TXDLEN_B.TXTS = BIT_RESET;
-    can->sTxMailBox[2].TXDLEN_B.TXTS = BIT_RESET;
+    can->FCTRL_B.FINITEN = SET;
+    can->FCTRL_B.CAN2BN  = bankNum;
+    can->FCTRL_B.FINITEN = RESET;
 }
 
 /*!
@@ -330,39 +312,41 @@ void CAN_DisableTTCComMode(CAN_T* can)
  *
  * @param     can: Select the CAN peripheral.
  *
- * @param     TxMessage: pointer to a CAN_TX_MESSAGE_T structure.
+ * @param     TxMessage: pointer to a CAN_TxMessage_T structure.
  *
  * @retval    The number of the mailbox which is used for transmission or 3 if No mailbox is empty.
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_TxMessage(CAN_T* can, CAN_TX_MESSAGE_T* TxMessage)
+uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage)
 {
     uint8_t transmit_milbox = 0;
 
     /** Select one empty transmit mailbox */
-    if((can->TXSTS & 0x04000000) == 0x04000000)
+    if ((can->TXSTS & 0x04000000) == 0x04000000)
     {
         transmit_milbox = 0;
     }
-    else if((can->TXSTS & 0x08000000) == 0x08000000)
+    else if ((can->TXSTS & 0x08000000) == 0x08000000)
     {
         transmit_milbox = 1;
     }
-    else if((can->TXSTS & 0x10000000) == 0x10000000)
+    else if ((can->TXSTS & 0x10000000) == 0x10000000)
     {
         transmit_milbox = 2;
-    } else
+    }
+    else
     {
         return 3;  //!< No mailbox is empty
     }
 
     /** Set up the Id */
     can->sTxMailBox[transmit_milbox].TXMID &= 0x00000001;
-    if(TxMessage->typeID == CAN_TYPEID_STD)
+    if (TxMessage->typeID == CAN_TYPEID_STD)
     {
         can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->stdID << 21) | (TxMessage->remoteTxReq);
-    } else
+    }
+    else
     {
         can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->extID << 3) | (TxMessage->typeID) | (TxMessage->remoteTxReq);
     }
@@ -396,45 +380,53 @@ uint8_t CAN_TxMessage(CAN_T* can, CAN_TX_MESSAGE_T* TxMessage)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
+uint8_t CAN_TxMessageStatus(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox)
 {
     uint32_t state = 0;
 
     switch (TxMailbox)
     {
-        case (CAN_TX_MAILBIX_0):
-            state =   can->TXSTS &  (0x00000001 | 0x00000002 | 0x04000000);
+    case (CAN_TX_MAILBIX_0):
+        state =   can->TXSTS & (0x00000001 | 0x00000002 | 0x04000000);
         break;
-        case (CAN_TX_MAILBIX_1):
-            state =   can->TXSTS &  (0x00000100 | 0x00000200 | 0x08000000);
+    case (CAN_TX_MAILBIX_1):
+        state =   can->TXSTS & (0x00000100 | 0x00000200 | 0x08000000);
         break;
-        case (CAN_TX_MAILBIX_2):
-            state =   can->TXSTS &  (0x00010000 | 0x00020000 | 0x10000000);
+    case (CAN_TX_MAILBIX_2):
+        state =   can->TXSTS & (0x00010000 | 0x00020000 | 0x10000000);
         break;
-        default:
-            state = 0;
+    default:
+        state = 0;
         break;
     }
     switch (state)
     {
-        /** transmit pending  */
-        case (0x0): state = 2;
+    /** Transmit pending  */
+    case (0x0):
+        state = 2;
         break;
-        /* transmit failed  */
-        case (0x00000001 | 0x04000000): state = 0;
+    /** Transmit failed  */
+    case (0x00000001 | 0x04000000):
+        state = 0;
         break;
-        case (0x00000100 | 0x08000000): state = 0;
+    case (0x00000100 | 0x08000000):
+        state = 0;
         break;
-        case (0x00010000 | 0x10000000): state = 0;
+    case (0x00010000 | 0x10000000):
+        state = 0;
         break;
-        /* transmit succeeded  */
-        case (0x00000001 | 0x00000002 | 0x04000000):state = 1;
+    /** Transmit succeeded  */
+    case (0x00000001 | 0x00000002 | 0x04000000):
+        state = 1;
         break;
-        case (0x00000100 | 0x00000200 | 0x08000000):state = 1;
+    case (0x00000100 | 0x00000200 | 0x08000000):
+        state = 1;
         break;
-        case (0x00010000 | 0x00020000 | 0x10000000):state = 1;
+    case (0x00010000 | 0x00020000 | 0x10000000):
+        state = 1;
         break;
-        default: state = 0;
+    default:
+        state = 0;
         break;
     }
     return (uint8_t) state;
@@ -455,7 +447,7 @@ uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
+void CAN_CancelTxMailbox(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox)
 {
     switch (TxMailbox)
     {
@@ -474,7 +466,7 @@ void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
 }
 
 /*!
- * @brief     Receives a message and save to a CAN_RX_MESSAGE_T structure.
+ * @brief     Receives a message and save to a CAN_RxMessage_T structure.
  *
  * @param     can: Select the CAN peripheral.
  *
@@ -489,11 +481,11 @@ void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RX_MESSAGE_T* RxMessage)
+void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMessage)
 {
-    /* Get the Id */
+    /** Get the Id */
     RxMessage->typeID = ((uint8_t)0x04 & (can->sRxMailBox[FIFONumber].RXMID));
-    if(RxMessage->typeID == CAN_TYPEID_STD)
+    if (RxMessage->typeID == CAN_TYPEID_STD)
     {
         RxMessage->stdID = (can->sRxMailBox[FIFONumber].RXMID >> 21) & 0x000007FF;
     }
@@ -506,16 +498,16 @@ void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RX_MESSAGE_T* RxMes
     RxMessage->dataLengthCode = can->sRxMailBox[FIFONumber].RXDLEN_B.DLCODE;
     RxMessage->filterMatchIndex = can->sRxMailBox[FIFONumber].RXDLEN_B.FMIDX;
     /** Get the data field */
-    RxMessage->data[0] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE1;
-    RxMessage->data[1] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE2;
-    RxMessage->data[2] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE3;
-    RxMessage->data[3] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE4;
-    RxMessage->data[4] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE5;
-    RxMessage->data[5] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE6;
-    RxMessage->data[6] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE7;
-    RxMessage->data[7] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE8;
-
-    if(FIFONumber == CAN_RX_FIFO_0)
+    RxMessage->data[0] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE0;
+    RxMessage->data[1] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE1;
+    RxMessage->data[2] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE2;
+    RxMessage->data[3] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE3;
+    RxMessage->data[4] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE4;
+    RxMessage->data[5] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE5;
+    RxMessage->data[6] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE6;
+    RxMessage->data[7] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE7;
+
+    if (FIFONumber == CAN_RX_FIFO_0)
     {
         can->RXF0_B.RFOM0 = BIT_SET;
     }
@@ -539,9 +531,9 @@ void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RX_MESSAGE_T* RxMes
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
+void CAN_ReleaseFIFO(CAN_T *can, CAN_RX_FIFO_T FIFONumber)
 {
-    if(FIFONumber == CAN_RX_FIFO_0)
+    if (FIFONumber == CAN_RX_FIFO_0)
     {
         can->RXF0_B.RFOM0 = BIT_SET;
     }
@@ -565,9 +557,9 @@ void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
+uint8_t CAN_PendingMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber)
 {
-    if(FIFONumber == CAN_RX_FIFO_0)
+    if (FIFONumber == CAN_RX_FIFO_0)
     {
         return  can->RXF0 & 0x03;
     }
@@ -594,53 +586,53 @@ uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode)
+uint8_t CAN_OperatingMode(CAN_T *can, CAN_OPERATING_MODE_T operatingMode)
 {
     uint8_t states = 0;
     uint32_t time_out = 0x0000FFFF;
 
-    if(operatingMode == CAN_OPERATING_MODE_INIT)
+    if (operatingMode == CAN_OPERATING_MODE_INIT)
     {
         can->MCTRL_B.SLEEPREQ = BIT_RESET;
         can->MCTRL_B.INITREQ = BIT_SET;
 
-        while((can->MSTS_B.INITFLG != BIT_SET && can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
+        while ((can->MSTS_B.INITFLG != BIT_SET && can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
         {
             time_out --;
         }
-        if((can->MSTS_B.INITFLG == BIT_SET && can->MSTS_B.SLEEPFLG == BIT_RESET))
+        if ((can->MSTS_B.INITFLG == BIT_SET && can->MSTS_B.SLEEPFLG == BIT_RESET))
         {
             states = 1;
         }
     }
-    else if(operatingMode == CAN_OPERATING_MODE_NORMAL)
+    else if (operatingMode == CAN_OPERATING_MODE_NORMAL)
     {
         can->MCTRL_B.SLEEPREQ = BIT_RESET;
         can->MCTRL_B.INITREQ = BIT_RESET;
 
         time_out = 0x0000FFFF;
 
-        while((can->MSTS_B.INITFLG != BIT_RESET || can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
+        while ((can->MSTS_B.INITFLG != BIT_RESET || can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
         {
             time_out --;
         }
-        if((can->MSTS_B.INITFLG == BIT_RESET || can->MSTS_B.SLEEPFLG == BIT_RESET))
+        if ((can->MSTS_B.INITFLG == BIT_RESET || can->MSTS_B.SLEEPFLG == BIT_RESET))
         {
             states = 1;
         }
     }
-    else if(operatingMode == CAN_OPERATING_MODE_SLEEP)
+    else if (operatingMode == CAN_OPERATING_MODE_SLEEP)
     {
         can->MCTRL_B.SLEEPREQ = BIT_SET;
         can->MCTRL_B.INITREQ = BIT_RESET;
 
         time_out = 0x0000FFFF;
 
-        while((can->MSTS_B.INITFLG != BIT_RESET && can->MSTS_B.SLEEPFLG != BIT_SET) && (time_out != 0))
+        while ((can->MSTS_B.INITFLG != BIT_RESET && can->MSTS_B.SLEEPFLG != BIT_SET) && (time_out != 0))
         {
             time_out --;
         }
-        if((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
+        if ((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
         {
             states = 1;
         }
@@ -659,12 +651,12 @@ uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_SleepMode(CAN_T* can)
+uint8_t CAN_SleepMode(CAN_T *can)
 {
     can->MCTRL_B.SLEEPREQ = BIT_SET;
     can->MCTRL_B.INITREQ = BIT_RESET;
 
-    if((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
+    if ((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
     {
         return 1;
     }
@@ -682,16 +674,16 @@ uint8_t CAN_SleepMode(CAN_T* can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_WakeUpMode(CAN_T* can)
+uint8_t CAN_WakeUpMode(CAN_T *can)
 {
     uint32_t time_out = 0x0000FFFF;
 
     can->MCTRL_B.SLEEPREQ = BIT_RESET;
-    while((can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
+    while ((can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
     {
         time_out --;
     }
-    if(can->MSTS_B.SLEEPFLG == BIT_RESET)
+    if (can->MSTS_B.SLEEPFLG == BIT_RESET)
     {
         return 1;
     }
@@ -707,7 +699,7 @@ uint8_t CAN_WakeUpMode(CAN_T* can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_ReadLastErrorCode(CAN_T* can)
+uint8_t CAN_ReadLastErrorCode(CAN_T *can)
 {
     return can->ERRSTS_B.LERRC;
 }
@@ -721,7 +713,7 @@ uint8_t CAN_ReadLastErrorCode(CAN_T* can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_ReadRxErrorCounter(CAN_T* can)
+uint8_t CAN_ReadRxErrorCounter(CAN_T *can)
 {
     return can->ERRSTS_B.RXERRCNT;
 }
@@ -735,7 +727,7 @@ uint8_t CAN_ReadRxErrorCounter(CAN_T* can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can)
+uint8_t CAN_ReadLSBTxErrorCounter(CAN_T *can)
 {
     return can->ERRSTS_B.TXERRCNT;
 }
@@ -766,7 +758,7 @@ uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupts)
+void CAN_EnableInterrupt(CAN_T *can, uint32_t interrupts)
 {
     can->INTEN |= interrupts;
 }
@@ -797,7 +789,7 @@ void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupts)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupts)
+void CAN_DisableInterrupt(CAN_T *can, uint32_t interrupts)
 {
     can->INTEN &= ~interrupts;
 }
@@ -829,13 +821,13 @@ void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupts)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
+uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag)
 {
     uint8_t status = 0;
 
-    if((flag & 0x00F00000) != RESET )
+    if ((flag & 0x00F00000) != RESET)
     {
-        if((can->ERRSTS & (flag & 0x000FFFFF)) != RESET)
+        if ((can->ERRSTS & (flag & 0x000FFFFF)) != RESET)
         {
             status = SET;
         }
@@ -844,9 +836,9 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
             status = RESET;
         }
     }
-    else if((flag & 0x01000000) != RESET )
+    else if ((flag & 0x01000000) != RESET)
     {
-        if((can->MSTS & (flag & 0x000FFFFF)) != RESET )
+        if ((can->MSTS & (flag & 0x000FFFFF)) != RESET)
         {
             status = SET;
         }
@@ -855,9 +847,9 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
             status = RESET ;
         }
     }
-    else if((flag & 0x08000000) != RESET )
+    else if ((flag & 0x08000000) != RESET)
     {
-        if((can->TXSTS & (flag & 0x000FFFFF)) != RESET )
+        if ((can->TXSTS & (flag & 0x000FFFFF)) != RESET)
         {
             status = SET;
         }
@@ -866,9 +858,9 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
             status = RESET;
         }
     }
-    else if((flag & 0x02000000) != RESET )
+    else if ((flag & 0x02000000) != RESET)
     {
-        if((can->RXF0 & (flag & 0x000FFFFF)) != RESET )
+        if ((can->RXF0 & (flag & 0x000FFFFF)) != RESET)
         {
             status = SET;
         }
@@ -879,7 +871,7 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
     }
     else
     {
-        if((can->RXF1 & (flag & 0x000FFFFF)) != RESET)
+        if ((can->RXF1 & (flag & 0x000FFFFF)) != RESET)
         {
             status = SET;
         }
@@ -913,27 +905,27 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag)
+void CAN_ClearStatusFlag(CAN_T *can, CAN_FLAG_T flag)
 {
     uint32_t flagtmp = 0;
 
     /** ERRSTS register */
-    if(flag == 0x30F00070)
+    if (flag == 0x30F00070)
     {
         can->ERRSTS = RESET;
     }
     else
     {
         flagtmp = flag & 0x000FFFFF;
-        if((flag & 0x02000000) != RESET)
+        if ((flag & 0x02000000) != RESET)
         {
             can->RXF0 = flagtmp;
         }
-        else if((flag & 0x04000000) != RESET)
+        else if ((flag & 0x04000000) != RESET)
         {
             can->RXF1 = flagtmp;
         }
-        else if((flag & 0x08000000) != RESET)
+        else if ((flag & 0x08000000) != RESET)
         {
             can->TXSTS = flagtmp;
         }
@@ -970,16 +962,18 @@ void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag)
+uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag)
 {
     uint8_t status = 0;
 
-    if((can->INTEN & flag) != RESET)
+    if ((can->INTEN & flag) != RESET)
     {
         switch (flag)
         {
         case CAN_INT_TXME:
-            status = can->TXSTS_B.REQCFLG0 | can->TXSTS_B.REQCFLG1 | can->TXSTS_B.REQCFLG2;
+            status = can->TXSTS_B.REQCFLG0;
+            status |= can->TXSTS_B.REQCFLG1;
+            status |= can->TXSTS_B.REQCFLG2;
             break;
         case CAN_INT_F0MP:
             status = can->RXF0_B.FMNUM0;
@@ -1056,7 +1050,7 @@ uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag)
+void CAN_ClearIntFlag(CAN_T *can, CAN_INT_T flag)
 {
     switch (flag)
     {

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c

@@ -1,12 +1,26 @@
 /*!
- * @file      apm32f10x_crc.c
+ * @file        apm32f10x_crc.c
  *
- * @brief     This file provides all the CRC firmware functions
+ * @brief       This file provides all the CRC firmware functions
  *
- * @version   V1.0.1
+ * @version     V1.0.2
  *
- * @date      2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_crc.h"
@@ -29,8 +43,6 @@
  * @param     None
  *
  * @retval    None
- *
- * @note
  */
 void CRC_ResetDATA(void)
 {
@@ -63,7 +75,7 @@ uint32_t CRC_CalculateCRC(uint32_t data)
  */
 uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen)
 {
-    while(bufLen--)
+    while (bufLen--)
     {
         CRC->DATA = *buf++;
     }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c

@@ -3,10 +3,24 @@
  *
  * @brief       This file provides all the DAC firmware functions
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_dac.h"
@@ -38,18 +52,18 @@ void DAC_Reset(void)
 }
 
 /*!
- * @brief        Config the DAC peripheral according to the specified parameters in the configStruct
+ * @brief        Config the DAC peripheral according to the specified parameters in the dacConfig
  *
  * @param        channel: Select the DAC channel.
  *                        This parameter can be one of the following values:
  *                        @arg DAC_CHANNEL_1 : DAC channel 1
  *                        @arg DAC_CHANNEL_2 : DAC channel 2
  *
- * @param        configStruct: pointer to a DAC_ConfigStruct_T structure
+ * @param        dacConfig: pointer to a DAC_Config_T structure
  *
  * @retval       None
  */
-void DAC_Config(uint32_t channel, DAC_ConfigStruct_T* configStruct)
+void DAC_Config(uint32_t channel, DAC_Config_T *dacConfig)
 {
     uint32_t tmp1 = 0, tmp2 = 0;
 
@@ -57,29 +71,33 @@ void DAC_Config(uint32_t channel, DAC_ConfigStruct_T* configStruct)
 
     tmp1 &= ~(((uint32_t)0x00000FFE) << channel);
 
-    tmp2 = (configStruct->trigger | configStruct->waveGeneration | configStruct->maskAmplitudeSelect | configStruct->outputBuffer);
+    tmp2 = ((uint32_t)dacConfig->trigger | \
+            (uint32_t)dacConfig->waveGeneration | \
+            (uint32_t)dacConfig->maskAmplitudeSelect | \
+            (uint32_t)dacConfig->outputBuffer);
+
     tmp1 |= tmp2 << channel;
 
     DAC->CTRL = tmp1;
 }
 
 /*!
- * @brief        Fills each DAC_ConfigStruct_T member with its default value
+ * @brief        Fills each DAC_Config_T member with its default value
  *
- * @param        configStruct: pointer to a DAC_ConfigStruct_T structure which will be initialized
+ * @param        dacConfig: pointer to a DAC_Config_T structure which will be initialized
  *
  * @retval       None
  */
-void DAC_ConfigStructInit(DAC_ConfigStruct_T* configStruct)
+void DAC_ConfigStructInit(DAC_Config_T *dacConfig)
 {
-    /* Initialize the DAC_Trigger member */
-    configStruct->trigger = DAC_TRIGGER_NONE;
-    /* Initialize the DAC_WaveGeneration member */
-    configStruct->waveGeneration = DAC_WAVE_GENERATION_NONE;
-    /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
-    configStruct->maskAmplitudeSelect = DAC_LFSR_MASK_BIT11_1;
-    /* Initialize the DAC_OutputBuffer member */
-    configStruct->outputBuffer = DAC_OUTPUT_BUFFER_ENBALE;
+    /** Initialize the DAC_Trigger member */
+    dacConfig->trigger = DAC_TRIGGER_NONE;
+    /** Initialize the DAC_WaveGeneration member */
+    dacConfig->waveGeneration = DAC_WAVE_GENERATION_NONE;
+    /** Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+    dacConfig->maskAmplitudeSelect = DAC_LFSR_MASK_BIT11_1;
+    /** Initialize the DAC_OutputBuffer member */
+    dacConfig->outputBuffer = DAC_OUTPUT_BUFFER_ENBALE;
 }
 
 /*!
@@ -303,7 +321,7 @@ void DAC_ConfigChannel1Data(DAC_ALIGN_T align, uint16_t data)
     tmp = (uint32_t)DAC_BASE;
     tmp += 0x00000008 + align;
 
-    /* Set the DAC channel1 selected data holding register */
+    /** Set the DAC channel1 selected data holding register */
     *(__IO uint32_t *) tmp = data;
 }
 
@@ -327,7 +345,7 @@ void DAC_ConfigChannel2Data(DAC_ALIGN_T align, uint16_t data)
     tmp = (uint32_t)DAC_BASE;
     tmp += 0x00000014 + align;
 
-    /* Set the DAC channel1 selected data holding register */
+    /** Set the DAC channel1 selected data holding register */
     *(__IO uint32_t *) tmp = data;
 }
 
@@ -350,7 +368,7 @@ void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1
 {
     uint32_t data = 0, tmp = 0;
 
-    /* Calculate and set dual DAC data holding register value */
+    /** Calculate and set dual DAC data holding register value */
     if (align == DAC_ALIGN_8BIT_R)
     {
         data = ((uint32_t)data2 << 8) | data1;
@@ -363,7 +381,7 @@ void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1
     tmp = (uint32_t)DAC_BASE;
     tmp += 0x00000020 + align;
 
-    /* Set the dual DAC selected data holding register */
+    /** Set the dual DAC selected data holding register */
     *(__IO uint32_t *)tmp = data;
 }
 
@@ -384,8 +402,8 @@ uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel)
     tmp = (uint32_t) DAC_BASE ;
     tmp += 0x0000002C + ((uint32_t)channel >> 2);
 
-    /* Returns the DAC channel data output register value */
-    return (uint16_t) (*(__IO uint32_t*) tmp);
+    /** Returns the DAC channel data output register value */
+    return (uint16_t)(*(__IO uint32_t *) tmp);
 }
 
 /**@} end of group DAC_Fuctions*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c

@@ -3,10 +3,24 @@
  *
  * @brief       This file provides all the DEBUG firmware functions
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_dbgmcu.h"
@@ -32,7 +46,7 @@
  */
 uint32_t DBGMCU_ReadDEVID(void)
 {
-   return(DBGMCU->IDCODE_B.EQR);
+    return (DBGMCU->IDCODE_B.EQR);
 }
 
 /*!
@@ -44,7 +58,7 @@ uint32_t DBGMCU_ReadDEVID(void)
  */
 uint32_t DBGMCU_ReadREVID(void)
 {
-   return(DBGMCU->IDCODE_B.WVR);
+    return (DBGMCU->IDCODE_B.WVR);
 }
 
 /*!
@@ -128,5 +142,5 @@ void DBGMCU_Disable(uint32_t periph)
 }
 
 /**@} end of group DBGMCU_Fuctions*/
-/**@} end of group DBGMCU_Driver */
+/**@} end of group DBGMCU_Driver*/
 /**@} end of group Peripherals_Library*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c

@@ -1,12 +1,26 @@
 /*!
- * @file       apm32f10x_dma.c
+ * @file        apm32f10x_dma.c
  *
- * @brief      This file provides all the DMA firmware functions
+ * @brief       This file provides all the DMA firmware functions
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_dma.h"
@@ -40,51 +54,51 @@ void DMA_Reset(DMA_Channel_T *channel)
     channel->CHMADDR = 0;
     channel->CHPADDR = 0;
 
-    if(channel == DMA1_Channel1)
+    if (channel == DMA1_Channel1)
     {
         DMA1->INTFCLR |= 0xFFFFFFF0;
     }
-    else if(channel == DMA1_Channel2)
+    else if (channel == DMA1_Channel2)
     {
         DMA1->INTFCLR |= 0xFFFFFF0F;
     }
-    else if(channel == DMA1_Channel3)
+    else if (channel == DMA1_Channel3)
     {
         DMA1->INTFCLR |= 0xFFFFF0FF;
     }
-    else if(channel == DMA1_Channel4)
+    else if (channel == DMA1_Channel4)
     {
         DMA1->INTFCLR |= 0xFFFF0FFF;
     }
-    else if(channel == DMA1_Channel5)
+    else if (channel == DMA1_Channel5)
     {
         DMA1->INTFCLR |= 0xFFF0FFFF;
     }
-    else if(channel == DMA1_Channel6)
+    else if (channel == DMA1_Channel6)
     {
         DMA1->INTFCLR |= 0xFF0FFFFF;
     }
-    else if(channel == DMA1_Channel7)
+    else if (channel == DMA1_Channel7)
     {
         DMA1->INTFCLR |= 0xF0FFFFFF;
     }
-    else if(channel == DMA2_Channel1)
+    else if (channel == DMA2_Channel1)
     {
         DMA2->INTFCLR |= 0xFFFFFFF0;
     }
-    else if(channel == DMA2_Channel2)
+    else if (channel == DMA2_Channel2)
     {
         DMA2->INTFCLR |= 0xFFFFFF0F;
     }
-    else if(channel == DMA2_Channel3)
+    else if (channel == DMA2_Channel3)
     {
         DMA2->INTFCLR |= 0xFFFFF0FF;
     }
-    else if(channel == DMA2_Channel4)
+    else if (channel == DMA2_Channel4)
     {
         DMA2->INTFCLR |= 0xFFFF0FFF;
     }
-    else if(channel == DMA2_Channel5)
+    else if (channel == DMA2_Channel5)
     {
         DMA2->INTFCLR |= 0xFFF0FFFF;
     }
@@ -101,7 +115,7 @@ void DMA_Reset(DMA_Channel_T *channel)
  *
  * @note      DMA2 Channel only for APM32 High density devices.
  */
-void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig)
+void DMA_Config(DMA_Channel_T *channel, DMA_Config_T *dmaConfig)
 {
     channel->CHCFG_B.DIRCFG = dmaConfig->dir;
     channel->CHCFG_B.CIRMODE = dmaConfig->loopMode;
@@ -124,7 +138,7 @@ void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig)
  *
  * @retval    None
  */
-void DMA_ConfigStructInit( DMA_Config_T* dmaConfig)
+void DMA_ConfigStructInit(DMA_Config_T *dmaConfig)
 {
     dmaConfig->peripheralBaseAddr = 0;
     dmaConfig->memoryBaseAddr = 0;
@@ -298,22 +312,24 @@ void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt)
  */
 uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag)
 {
-    if((flag & 0x10000000) != RESET )
+    if ((flag & 0x10000000) != RESET)
     {
-        if((DMA2->INTSTS & flag ) != RESET )
+        if ((DMA2->INTSTS & flag) != RESET)
         {
             return SET ;
-        } else
+        }
+        else
         {
             return RESET ;
         }
     }
     else
     {
-        if((DMA1->INTSTS & flag ) != RESET )
+        if ((DMA1->INTSTS & flag) != RESET)
         {
             return SET ;
-        } else
+        }
+        else
         {
             return RESET ;
         }
@@ -381,10 +397,11 @@ uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag)
  */
 void DMA_ClearStatusFlag(uint32_t flag)
 {
-    if((flag & 0x10000000) != RESET)
+    if ((flag & 0x10000000) != RESET)
     {
         DMA2->INTFCLR = flag;
-    } else
+    }
+    else
     {
         DMA1->INTFCLR = flag;
     }
@@ -451,21 +468,24 @@ void DMA_ClearStatusFlag(uint32_t flag)
  */
 uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag)
 {
-    if((flag & 0x10000000) != RESET )
+    if ((flag & 0x10000000) != RESET)
     {
-        if((DMA2->INTSTS & flag ) != RESET )
+        if ((DMA2->INTSTS & flag) != RESET)
         {
             return SET ;
-        } else
+        }
+        else
         {
             return RESET ;
         }
-    } else
+    }
+    else
     {
-        if((DMA1->INTSTS & flag ) != RESET )
+        if ((DMA1->INTSTS & flag) != RESET)
         {
             return SET ;
-        } else
+        }
+        else
         {
             return RESET ;
         }
@@ -532,10 +552,11 @@ uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag)
  */
 void DMA_ClearIntFlag(uint32_t flag)
 {
-    if((flag & 0x10000000) != RESET)
+    if ((flag & 0x10000000) != RESET)
     {
         DMA2->INTFCLR = flag;
-    } else
+    }
+    else
     {
         DMA1->INTFCLR = flag;
     }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c

@@ -3,11 +3,27 @@
  *
  * @brief       This file contains all the functions for the DMC controler peripheral
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
+
+#ifdef APM32F10X_HD
 #include "apm32f10x_dmc.h"
 
 /** @addtogroup Peripherals_Library Standard Peripheral Library
@@ -29,10 +45,10 @@
  *
  * @retval      None
  */
-void DMC_Config(DMC_Config_T * dmcConfig)
+void DMC_Config(DMC_Config_T *dmcConfig)
 {
     DMC->SW_B.MCSW = 1;
-    while(!DMC->CTRL1_B.INIT);
+    while (!DMC->CTRL1_B.INIT);
 
     DMC->CFG_B.BAWCFG = dmcConfig->bankWidth;
     DMC->CFG_B.RAWCFG = dmcConfig->rowWidth;
@@ -44,7 +60,7 @@ void DMC_Config(DMC_Config_T * dmcConfig)
     DMC_ConfigTiming(&dmcConfig->timing);
 
     DMC->CTRL1_B.MODESET = 1;
-    while(!DMC->CTRL1_B.MODESET);
+    while (!DMC->CTRL1_B.MODESET);
 
     DMC->CTRL2_B.RDDEN = 1;
     DMC->CTRL2_B.RDDCFG = 7;
@@ -57,7 +73,7 @@ void DMC_Config(DMC_Config_T * dmcConfig)
  *
  * @retval      None
  */
-void DMC_ConfigStructInit(DMC_Config_T * dmcConfig)
+void DMC_ConfigStructInit(DMC_Config_T *dmcConfig)
 {
     dmcConfig->bankWidth   = DMC_BANK_WIDTH_2;
     dmcConfig->clkPhase    = DMC_CLK_PHASE_REVERSE;
@@ -75,7 +91,7 @@ void DMC_ConfigStructInit(DMC_Config_T * dmcConfig)
  *
  * @retval      None
  */
-void DMC_ConfigTiming(DMC_TimingConfig_T * timingConfig)
+void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig)
 {
     DMC->TIM0_B.RASMINTSEL = timingConfig->tRAS;
     DMC->TIM0_B.DTIMSEL    = timingConfig->tRCD;
@@ -100,7 +116,7 @@ void DMC_ConfigTiming(DMC_TimingConfig_T * timingConfig)
  *
  * @retval      None
  */
-void DMC_ConfigTimingStructInit(DMC_TimingConfig_T * timingConfig)
+void DMC_ConfigTimingStructInit(DMC_TimingConfig_T *timingConfig)
 {
     timingConfig->latencyCAS = DMC_CAS_LATENCY_3;
     timingConfig->tARP = DMC_AUTO_REFRESH_10;
@@ -267,6 +283,30 @@ void DMC_EnterSlefRefreshMode(void)
     DMC->CTRL1_B.SRMEN = 1;
 }
 
+/*!
+ * @brief     Enable Accelerate Module
+ *
+ * @param     None
+ *
+ * @retval    None
+ */
+void DMC_EnableAccelerateModule(void)
+{
+    DMC->CTRL2_B.BUFFEN = BIT_SET;
+}
+
+/*!
+ * @brief     Disable Accelerate Module
+ *
+ * @param     None
+ *
+ * @retval    None
+ */
+void DMC_DisableAccelerateModule(void)
+{
+    DMC->CTRL2_B.BUFFEN = BIT_RESET;
+}
+
 /*!
  * @brief       Init DMC
  *
@@ -396,14 +436,29 @@ void DMC_Disable(void)
  *                @arg DMC_CLK_PHASE_REVERSE: Clock phase is reverse
  *
  * @retval      None
- *
  */
 void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase)
 {
     DMC->CTRL2_B.CPHACFG = clkPhase;
 }
 
+/*!
+ * @brief       Set DMC WRAP burst
+ *
+ * @param       burst: WRAP burst Type Selection
+ *                The parameter can be one of following values:
+ *                @arg DMC_WRAPB_4: wrap4 burst transfer
+ *                @arg DMC_WRAPB_8: wrap8 burst transfer
+ *
+ * @retval      None
+ */
+void DMC_ConfigWRAPB(DMC_WRPB_T burst)
+{
+    DMC->CTRL2_B.WRPBSEL = burst;
+}
+
+#endif //defined APM32F10X_HD
+
 /**@} end of group DMC_Fuctions*/
-/**@} end of group DMC_Driver */
+/**@} end of group DMC_Driver*/
 /**@} end of group Peripherals_Library*/
-

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c

@@ -1,12 +1,26 @@
 /*!
- * @file       apm32f10x_eint.c
+ * @file        apm32f10x_eint.c
  *
- * @brief      This file provides all the EINT firmware functions
+ * @brief       This file provides all the EINT firmware functions
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_eint.h"
@@ -46,12 +60,12 @@ void EINT_Reset(void)
  *
  * @retval       None
  */
-void EINT_Config(EINT_Config_T* eintConfig)
+void EINT_Config(EINT_Config_T *eintConfig)
 {
     uint32_t temp = 0;
     temp = (uint32_t)EINT_BASE;
 
-    if(eintConfig->lineCmd != DISABLE)
+    if (eintConfig->lineCmd != DISABLE)
     {
         EINT->IMASK &= ~eintConfig->line;
         EINT->EMASK &= ~eintConfig->line;
@@ -83,6 +97,21 @@ void EINT_Config(EINT_Config_T* eintConfig)
     }
 }
 
+/*!
+ * @brief        Fills each EINT_Config_T member with its reset value.
+ *
+ * @param        eintConfig: pointer to a EINT_Config_T structure
+ *
+ * @retval       None
+ */
+void EINT_ConfigStructInit(EINT_Config_T *eintConfig)
+{
+    eintConfig->line = EINT_LINENONE;
+    eintConfig->mode = EINT_MODE_INTERRUPT;
+    eintConfig->trigger = EINT_TRIGGER_FALLING;
+    eintConfig->lineCmd = DISABLE;
+}
+
 /*!
  * @brief    Select Software interrupt on EINT line
  *
@@ -108,7 +137,7 @@ uint8_t EINT_ReadStatusFlag(EINT_LINE_T line)
 {
     uint8_t status = RESET;
 
-    if((EINT->IPEND & line) != (uint32_t)RESET)
+    if ((EINT->IPEND & line) != (uint32_t)RESET)
     {
         status = SET;
     }
@@ -147,7 +176,7 @@ uint8_t EINT_ReadIntFlag(EINT_LINE_T line)
 
     enablestatus = EINT->IMASK & line;
 
-    if((EINT->IPEND & line) != ((uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+    if ((EINT->IPEND & line) != ((uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
     {
         status = SET;
     }
@@ -172,5 +201,5 @@ void EINT_ClearIntFlag(uint32_t line)
 }
 
 /**@} end of group EINT_Fuctions*/
-/**@} end of group EINT_Driver */
+/**@} end of group EINT_Driver*/
 /**@} end of group Peripherals_Library*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_emmc.c

@@ -1,12 +1,26 @@
 /*!
- * @file      apm32f10x_emmc.c
+ * @file        apm32f10x_emmc.c
  *
- * @brief     This file provides all the EMMC firmware functions
+ * @brief       This file provides all the EMMC firmware functions
  *
- * @version   V1.0.1
+ * @version     V1.0.2
  *
- * @date      2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_emmc.h"
@@ -39,7 +53,7 @@
 void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank)
 {
     /** EMMC_BANK1_NORSRAM_1 */
-    if(bank == EMMC_BANK1_NORSRAM_1)
+    if (bank == EMMC_BANK1_NORSRAM_1)
     {
         EMMC_Bank1->SNCTRL_T[bank] = 0x000030DB;
     }
@@ -64,7 +78,7 @@ void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank)
  */
 void EMMC_ResetNAND(EMMC_BANK_NAND_T bank)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         /** Set the EMMC_Bank2 registers to their reset values */
         EMMC_Bank2->CTRL2 = 0x00000018;
@@ -75,7 +89,7 @@ void EMMC_ResetNAND(EMMC_BANK_NAND_T bank)
     /** EMMC_BANK3_NAND */
     else
     {
-        /* Set the EMMC_Bank3 registers to their reset values */
+        /** Set the EMMC_Bank3 registers to their reset values */
         EMMC_Bank3->CTRL3 = 0x00000018;
         EMMC_Bank3->STSINT3 = 0x00000040;
         EMMC_Bank3->CMSTIM3 = 0xFCFCFCFC;
@@ -107,9 +121,9 @@ void EMMC_ResetPCCard(void)
  *
  * @retval    None
  */
-void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
+void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig)
 {
-    /* Bank1 NOR/SRAM control register configuration */
+    /** Bank1 NOR/SRAM control register configuration */
     EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] =
         (uint32_t)emmcNORSRAMConfig->dataAddressMux |
         emmcNORSRAMConfig->memoryType |
@@ -124,12 +138,12 @@ void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
         emmcNORSRAMConfig->extendedMode |
         emmcNORSRAMConfig->writeBurst;
 
-    if(emmcNORSRAMConfig->memoryType == EMMC_MEMORY_TYPE_NOR)
+    if (emmcNORSRAMConfig->memoryType == EMMC_MEMORY_TYPE_NOR)
     {
         EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] |= 0x00000040;
     }
 
-    /* Bank1 NOR/SRAM timing register configuration */
+    /** Bank1 NOR/SRAM timing register configuration */
     EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank + 1] =
         (uint32_t)emmcNORSRAMConfig->readWriteTimingStruct->addressSetupTime |
         (emmcNORSRAMConfig->readWriteTimingStruct->addressHodeTime << 4) |
@@ -139,8 +153,8 @@ void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
         (emmcNORSRAMConfig->readWriteTimingStruct->dataLatency << 24) |
         emmcNORSRAMConfig->readWriteTimingStruct->accessMode;
 
-    /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
-    if(emmcNORSRAMConfig->extendedMode == EMMC_EXTENDEN_MODE_ENABLE)
+    /** Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
+    if (emmcNORSRAMConfig->extendedMode == EMMC_EXTENDEN_MODE_ENABLE)
     {
         EMMC_Bank1E->WRTTIM[emmcNORSRAMConfig->bank] =
             (uint32_t)emmcNORSRAMConfig->writeTimingStruct->addressSetupTime |
@@ -163,11 +177,11 @@ void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
  *
  * @retval    None
  */
-void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig)
+void EMMC_ConfigNAND(EMMC_NANDConfig_T *emmcNANDConfig)
 {
     uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
 
-    /* Set the tmppcr value according to EMMC_NANDInitStruct parameters */
+    /** Set the tmppcr value according to EMMC_NANDInitStruct parameters */
     tmppcr = (uint32_t)emmcNANDConfig->waitFeature | 0x00000008 |
              emmcNANDConfig->memoryDataWidth |
              emmcNANDConfig->ECC |
@@ -175,28 +189,28 @@ void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig)
              (emmcNANDConfig->TCLRSetupTime << 9) |
              (emmcNANDConfig->TARSetupTime << 13);
 
-    /* Set tmppmem value according to EMMC_CommonSpaceTimingStructure parameters */
+    /** Set tmppmem value according to EMMC_CommonSpaceTimingStructure parameters */
     tmppmem = (uint32_t)emmcNANDConfig->commonSpaceTimingStruct->setupTime |
               (emmcNANDConfig->commonSpaceTimingStruct->waitSetupTime << 8) |
               (emmcNANDConfig->commonSpaceTimingStruct->holdSetupTime << 16) |
               (emmcNANDConfig->commonSpaceTimingStruct->HiZSetupTime << 24);
 
-    /* Set tmppatt value according to EMMC_AttributeSpaceTimingStructure parameters */
+    /** Set tmppatt value according to EMMC_AttributeSpaceTimingStructure parameters */
     tmppatt = (uint32_t)emmcNANDConfig->attributeSpaceTimingStruct->setupTime |
               (emmcNANDConfig->attributeSpaceTimingStruct->waitSetupTime << 8) |
               (emmcNANDConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
               (emmcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
 
-    if(emmcNANDConfig->bank == EMMC_BANK2_NAND)
+    if (emmcNANDConfig->bank == EMMC_BANK2_NAND)
     {
-        /* EMMC_BANK2_NAND registers configuration */
+        /** EMMC_BANK2_NAND registers configuration */
         EMMC_Bank2->CTRL2 = tmppcr;
         EMMC_Bank2->CMSTIM2 = tmppmem;
         EMMC_Bank2->AMSTIM2 = tmppatt;
     }
     else
     {
-        /* EMMC_BANK3_NAND registers configuration */
+        /** EMMC_BANK3_NAND registers configuration */
         EMMC_Bank3->CTRL3 = tmppcr;
         EMMC_Bank3->CMSTIM3 = tmppmem;
         EMMC_Bank3->AMSTIM3 = tmppatt;
@@ -211,30 +225,30 @@ void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig)
  *
  * @retval    None
  */
-void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig)
+void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T *emmcPCCardConfig)
 {
-    /* Set the PCR4 register value according to EMMC_PCCARDInitStruct parameters */
+    /** Set the PCR4 register value according to EMMC_PCCARDInitStruct parameters */
     EMMC_Bank4->CTRL4 = (uint32_t)emmcPCCardConfig->waitFeature | EMMC_MEMORY_DATA_WIDTH_16BIT |
-                          (emmcPCCardConfig->TCLRSetupTime << 9) |
-                          (emmcPCCardConfig->TARSetupTime << 13);
+                        (emmcPCCardConfig->TCLRSetupTime << 9) |
+                        (emmcPCCardConfig->TARSetupTime << 13);
 
-    /* Set PMEM4 register value according to EMMC_CommonSpaceTimingStructure parameters */
+    /** Set PMEM4 register value according to EMMC_CommonSpaceTimingStructure parameters */
     EMMC_Bank4->CMSTIM4 = (uint32_t)emmcPCCardConfig->commonSpaceTimingStruct->setupTime |
-                        (emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime << 8) |
-                        (emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime << 16) |
-                        (emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime << 24);
+                          (emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime << 8) |
+                          (emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime << 16) |
+                          (emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime << 24);
 
-    /* Set PATT4 register value according to EMMC_AttributeSpaceTimingStructure parameters */
+    /** Set PATT4 register value according to EMMC_AttributeSpaceTimingStructure parameters */
     EMMC_Bank4->AMSTIM4 = (uint32_t)emmcPCCardConfig->attributeSpaceTimingStruct->setupTime |
-                        (emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime << 8) |
-                        (emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
-                        (emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
+                          (emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime << 8) |
+                          (emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
+                          (emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
 
-    /* Set PIO4 register value according to EMMC_IOSpaceTimingStructure parameters */
+    /** Set PIO4 register value according to EMMC_IOSpaceTimingStructure parameters */
     EMMC_Bank4->IOSTIM4 = (uint32_t)emmcPCCardConfig->IOSpaceTimingStruct->setupTime |
-                        (emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime << 8) |
-                        (emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime << 16) |
-                        (emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime << 24);
+                          (emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime << 8) |
+                          (emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime << 16) |
+                          (emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime << 24);
 }
 
 /*!
@@ -244,9 +258,9 @@ void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig)
  *
  * @retval    None
  */
-void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
+void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig)
 {
-    /* Reset NOR/SRAM Init structure parameters values */
+    /** Reset NOR/SRAM Init structure parameters values */
     emmcNORSRAMConfig->bank = EMMC_BANK1_NORSRAM_1;
     emmcNORSRAMConfig->dataAddressMux = EMMC_DATA_ADDRESS_MUX_ENABLE;
     emmcNORSRAMConfig->memoryType = EMMC_MEMORY_TYPE_SRAM;
@@ -284,9 +298,9 @@ void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
  *
  * @retval    None
  */
-void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig)
+void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T *emmcNANDConfig)
 {
-    /* Reset NAND Init structure parameters values */
+    /** Reset NAND Init structure parameters values */
     emmcNANDConfig->bank = EMMC_BANK2_NAND;
     emmcNANDConfig->waitFeature = EMMC_WAIT_FEATURE_DISABLE;
     emmcNANDConfig->memoryDataWidth = EMMC_MEMORY_DATA_WIDTH_8BIT;
@@ -311,9 +325,9 @@ void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig)
  *
  * @retval    None
  */
-void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig)
+void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T *emmcPCCardConfig)
 {
-    /* Reset PCCARD Init structure parameters values */
+    /** Reset PCCARD Init structure parameters values */
     emmcPCCardConfig->waitFeature = EMMC_WAIT_FEATURE_DISABLE;
     emmcPCCardConfig->TCLRSetupTime = 0x0;
     emmcPCCardConfig->TARSetupTime = 0x0;
@@ -377,7 +391,7 @@ void EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank)
  */
 void EMMC_EnableNAND(EMMC_BANK_NAND_T bank)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->CTRL2_B.MBKEN = BIT_SET;
     }
@@ -399,7 +413,7 @@ void EMMC_EnableNAND(EMMC_BANK_NAND_T bank)
  */
 void EMMC_DisableNAND(EMMC_BANK_NAND_T bank)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->CTRL2_B.MBKEN = BIT_RESET;
     }
@@ -445,7 +459,7 @@ void EMMC_DisablePCCARD(void)
  */
 void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->CTRL2 |= 0x00000040;
     }
@@ -465,11 +479,10 @@ void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank)
  *
  * @retval    None
  *
- * @note
  */
 void EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->CTRL2 &= 0x000FFFBF;
     }
@@ -493,7 +506,7 @@ uint32_t  EMMC_ReadECC(EMMC_BANK_NAND_T bank)
 {
     uint32_t eccval = 0x00000000;
 
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         eccval = EMMC_Bank2->ECCRS2;
     }
@@ -523,11 +536,11 @@ uint32_t  EMMC_ReadECC(EMMC_BANK_NAND_T bank)
  */
 void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->STSINT2 |= interrupt;
     }
-    else if(bank == EMMC_BANK3_NAND)
+    else if (bank == EMMC_BANK3_NAND)
     {
         EMMC_Bank3->STSINT3 |= interrupt;
     }
@@ -556,11 +569,11 @@ void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt)
  */
 void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->STSINT2 &= ~interrupt;
     }
-    else if(bank == EMMC_BANK3_NAND)
+    else if (bank == EMMC_BANK3_NAND)
     {
         EMMC_Bank3->STSINT3 &= ~interrupt;
     }
@@ -588,17 +601,16 @@ void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt)
  *
  * @retval    SET or RESET
  *
- * @note
  */
 uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag)
 {
     uint32_t tmpsr = 0x00000000;
 
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         tmpsr = EMMC_Bank2->STSINT2;
     }
-    else if(bank == EMMC_BANK3_NAND)
+    else if (bank == EMMC_BANK3_NAND)
     {
         tmpsr = EMMC_Bank3->STSINT3;
     }
@@ -606,8 +618,8 @@ uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag)
     {
         tmpsr = EMMC_Bank4->STSINT4;
     }
-    /* Get the flag status */
-    if((tmpsr & flag) != RESET)
+    /** Get the flag status */
+    if ((tmpsr & flag) != RESET)
     {
         return SET;
     }
@@ -636,11 +648,11 @@ uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag)
  */
 void EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank, uint32_t flag)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->STSINT2 &= ~flag;
     }
-    else if(bank == EMMC_BANK3_NAND)
+    else if (bank == EMMC_BANK3_NAND)
     {
         EMMC_Bank3->STSINT3 &= ~flag;
     }
@@ -671,11 +683,11 @@ uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag)
 {
     uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
 
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         tmpsr = EMMC_Bank2->STSINT2;
     }
-    else if(bank == EMMC_BANK3_NAND)
+    else if (bank == EMMC_BANK3_NAND)
     {
         tmpsr = EMMC_Bank3->STSINT3;
     }
@@ -687,7 +699,7 @@ uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag)
     itstatus = tmpsr & flag;
     itenable = tmpsr & (flag >> 3);
 
-    if((itstatus != RESET) && (itenable != RESET))
+    if ((itstatus != RESET) && (itenable != RESET))
     {
         return SET;
     }
@@ -716,11 +728,11 @@ uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag)
  */
 void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->STSINT2 &= ~(flag >> 3);
     }
-    else if(bank == EMMC_BANK3_NAND)
+    else if (bank == EMMC_BANK3_NAND)
     {
         EMMC_Bank3->STSINT3 &= ~(flag >> 3);
     }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c

@@ -1,12 +1,26 @@
 /*!
- * @file       apm32f10x_fmc.c
+ * @file        apm32f10x_fmc.c
  *
- * @brief      This file provides all the FMC firmware functions
+ * @brief       This file provides all the FMC firmware functions
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_fmc.h"
@@ -126,7 +140,7 @@ FMC_STATUS_T FMC_ErasePage(uint32_t pageAddr)
     FMC_STATUS_T status = FMC_STATUS_COMPLETE;
 
     status = FMC_WaitForLastOperation(0x000B0000);
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->CTRL2_B.PAGEERA = BIT_SET;
         FMC->ADDR = pageAddr;
@@ -154,7 +168,7 @@ FMC_STATUS_T FMC_EraseAllPage(void)
     FMC_STATUS_T status = FMC_STATUS_COMPLETE;
 
     status = FMC_WaitForLastOperation(0x000B0000);
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->CTRL2_B.MASSERA = BIT_SET;
         FMC->CTRL2_B.STA = BIT_SET;
@@ -181,12 +195,12 @@ FMC_STATUS_T FMC_EraseOptionBytes(void)
     uint16_t rdtemp = 0x00A5;
     FMC_STATUS_T status = FMC_STATUS_COMPLETE;
 
-    if(FMC_GetReadProtectionStatus() != RESET)
+    if (FMC_GetReadProtectionStatus() != RESET)
     {
         rdtemp = 0x00;
     }
     status = FMC_WaitForLastOperation(0x000B0000);
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->OBKEY = 0x45670123;
         FMC->OBKEY = 0xCDEF89AB;
@@ -196,18 +210,18 @@ FMC_STATUS_T FMC_EraseOptionBytes(void)
 
         status = FMC_WaitForLastOperation(0x000B0000);
 
-        if(status == FMC_STATUS_COMPLETE)
+        if (status == FMC_STATUS_COMPLETE)
         {
             FMC->CTRL2_B.OBE = BIT_RESET;
             FMC->CTRL2_B.OBP = BIT_SET;
             OB->RDP = rdtemp;
             status = FMC_WaitForLastOperation(0x000B0000);
-            if(status != FMC_STATUS_TIMEOUT)
+            if (status != FMC_STATUS_TIMEOUT)
             {
                 FMC->CTRL2_B.OBP = BIT_RESET;
             }
         }
-        else if(status != FMC_STATUS_TIMEOUT)
+        else if (status != FMC_STATUS_TIMEOUT)
         {
             FMC->CTRL2_B.OBP = BIT_RESET;
         }
@@ -233,13 +247,13 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data)
     FMC_STATUS_T status = FMC_STATUS_COMPLETE;
     __IOM uint32_t temp = 0;
 
-    #ifdef APM32F10X_HD
-          __set_PRIMASK(1);
-    #endif
+#ifdef APM32F10X_HD
+    __set_PRIMASK(1);
+#endif
 
     status = FMC_WaitForLastOperation(0x000B0000);
 
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->CTRL2_B.PG = BIT_SET;
 
@@ -247,11 +261,11 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data)
 
         status = FMC_WaitForLastOperation(0x000B0000);
 
-        if(status == FMC_STATUS_COMPLETE)
+        if (status == FMC_STATUS_COMPLETE)
         {
             temp = address + 2;
 
-            *(__IOM uint16_t*) temp = data >> 16;
+            *(__IOM uint16_t *) temp = data >> 16;
 
             status = FMC_WaitForLastOperation(0x000B0000);
             FMC->CTRL2_B.PG = BIT_RESET;
@@ -262,9 +276,9 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data)
         }
     }
 
-    #ifdef APM32F10X_HD
-        __set_PRIMASK(0);
-    #endif
+#ifdef APM32F10X_HD
+    __set_PRIMASK(0);
+#endif
 
     return status;
 }
@@ -286,13 +300,13 @@ FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data)
 {
     FMC_STATUS_T status = FMC_STATUS_COMPLETE;
 
-    #ifdef APM32F10X_HD
-        __set_PRIMASK(1);
-    #endif
+#ifdef APM32F10X_HD
+    __set_PRIMASK(1);
+#endif
 
     status = FMC_WaitForLastOperation(0x000B0000);
 
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->CTRL2_B.PG = BIT_SET;
         *(__IOM uint16_t *)address = data;
@@ -300,9 +314,9 @@ FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data)
         FMC->CTRL2_B.PG = BIT_RESET;
     }
 
-    #ifdef APM32F10X_HD
-        __set_PRIMASK(0);
-    #endif
+#ifdef APM32F10X_HD
+    __set_PRIMASK(0);
+#endif
 
     return status;
 }
@@ -326,7 +340,7 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data)
 
     status = FMC_WaitForLastOperation(0x000B0000);
 
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->OBKEY = 0x45670123;
         FMC->OBKEY = 0xCDEF89AB;
@@ -334,7 +348,7 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data)
         FMC->CTRL2_B.OBP = BIT_SET;
         *(__IOM uint16_t *)address = data;
         status = FMC_WaitForLastOperation(0x000B0000);
-        if(status == FMC_STATUS_TIMEOUT)
+        if (status == FMC_STATUS_TIMEOUT)
         {
             FMC->CTRL2_B.OBP = BIT_RESET;
         }
@@ -347,11 +361,11 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data)
  *
  * @param     page:the address of the pages to be write protection
  *                This parameter can be any combination of the following values:
- *                 for APM32F10X_LD
+ *                 for APM32F10X_LD ：
  *                    @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_28_31
- *                 for APM32F10X_MD
+ *                 for APM32F10X_MD ：
  *                    @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_124_127
- *                 for APM32F10X_HD
+ *                 for APM32F10X_HD ：
  *                    @arg FLASH_WRP_PAGE_0_1 to FLASH_WRP_PAGE_60_61 or FLASH_WRP_PAGE_62_127
  *                 @arg FMC_WRP_PAGE_ALL
  *
@@ -374,34 +388,34 @@ FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page)
 
     status = FMC_WaitForLastOperation(0x000B0000);
 
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->OBKEY = 0x45670123;
         FMC->OBKEY = 0xCDEF89AB;
         FMC->CTRL2_B.OBP = BIT_SET;
 
-        if(WPP0_Data != 0xFF)
+        if (WPP0_Data != 0xFF)
         {
             OB->WRP0 = WPP0_Data;
             status = FMC_WaitForLastOperation(0x000B0000);
         }
-        if((status == FMC_STATUS_COMPLETE) && (WPP1_Data != 0xFF))
+        if ((status == FMC_STATUS_COMPLETE) && (WPP1_Data != 0xFF))
         {
             OB->WRP1 = WPP1_Data;
             status = FMC_WaitForLastOperation(0x000B0000);
         }
-        if((status == FMC_STATUS_COMPLETE) && (WPP2_Data != 0xFF))
+        if ((status == FMC_STATUS_COMPLETE) && (WPP2_Data != 0xFF))
         {
             OB->WRP2 = WPP2_Data;
             status = FMC_WaitForLastOperation(0x000B0000);
         }
-        if((status == FMC_STATUS_COMPLETE) && (WPP3_Data != 0xFF))
+        if ((status == FMC_STATUS_COMPLETE) && (WPP3_Data != 0xFF))
         {
             OB->WRP3 = WPP3_Data;
             status = FMC_WaitForLastOperation(0x000B0000);
         }
 
-        if(status != FMC_STATUS_TIMEOUT)
+        if (status != FMC_STATUS_TIMEOUT)
         {
             FMC->CTRL2_B.OBP = BIT_RESET;
         }
@@ -426,7 +440,7 @@ FMC_STATUS_T FMC_EnableReadOutProtection(void)
 
     status = FMC_WaitForLastOperation(0x000B0000);
 
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->OBKEY = 0x45670123;
         FMC->OBKEY = 0xCDEF89AB;
@@ -436,7 +450,7 @@ FMC_STATUS_T FMC_EnableReadOutProtection(void)
 
         status = FMC_WaitForLastOperation(0x000B0000);
 
-        if(status == FMC_STATUS_COMPLETE)
+        if (status == FMC_STATUS_COMPLETE)
         {
             FMC->CTRL2_B.OBE = BIT_RESET;
             FMC->CTRL2_B.OBP = BIT_SET;
@@ -444,12 +458,12 @@ FMC_STATUS_T FMC_EnableReadOutProtection(void)
 
             status = FMC_WaitForLastOperation(0x000B0000);
 
-            if(status != FMC_STATUS_TIMEOUT)
+            if (status != FMC_STATUS_TIMEOUT)
             {
                 FMC->CTRL2_B.OBP = BIT_RESET;
             }
         }
-        else if(status != FMC_STATUS_TIMEOUT)
+        else if (status != FMC_STATUS_TIMEOUT)
         {
             FMC->CTRL2_B.OBE = BIT_RESET;
         }
@@ -474,7 +488,7 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void)
 
     status = FMC_WaitForLastOperation(0x000B0000);
 
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->OBKEY = 0x45670123;
         FMC->OBKEY = 0xCDEF89AB;
@@ -483,7 +497,7 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void)
 
         status = FMC_WaitForLastOperation(0x000B0000);
 
-        if(status == FMC_STATUS_COMPLETE)
+        if (status == FMC_STATUS_COMPLETE)
         {
             FMC->CTRL2_B.OBE = BIT_RESET;
             FMC->CTRL2_B.OBP = BIT_SET;
@@ -491,12 +505,12 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void)
 
             status = FMC_WaitForLastOperation(0x000B0000);
 
-            if(status != FMC_STATUS_TIMEOUT)
+            if (status != FMC_STATUS_TIMEOUT)
             {
                 FMC->CTRL2_B.OBP = BIT_RESET;
             }
         }
-        else if(status != FMC_STATUS_TIMEOUT)
+        else if (status != FMC_STATUS_TIMEOUT)
         {
             FMC->CTRL2_B.OBE = BIT_RESET;
         }
@@ -515,7 +529,7 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void)
  *                 @arg FMC_STATUS_COMPLETE
  *                 @arg FMC_STATUS_TIMEOUT
  */
-FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig)
+FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T *userConfig)
 {
     FMC_STATUS_T status = FMC_STATUS_COMPLETE;
 
@@ -524,12 +538,14 @@ FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig)
 
     status = FMC_WaitForLastOperation(0x000B0000);
 
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->CTRL2_B.OBP = BIT_SET;
-        OB->USER = userConfig->iwdtSet | userConfig->stopSet | userConfig->stdbySet | 0xF8;
+        OB->USER = (uint32_t)userConfig->iwdtSet | \
+                   (uint32_t)userConfig->stopSet | \
+                   (uint32_t)userConfig->stdbySet | 0xF8;
         status = FMC_WaitForLastOperation(0x000B0000);
-        if(status == FMC_STATUS_TIMEOUT)
+        if (status == FMC_STATUS_TIMEOUT)
         {
             FMC->CTRL2_B.OBP = BIT_RESET;
         }
@@ -572,7 +588,7 @@ uint8_t FMC_GetReadProtectionStatus(void)
 {
     uint8_t flagstatus = RESET;
 
-    if(FMC->OBCS_B.READPROT != RESET)
+    if (FMC->OBCS_B.READPROT != RESET)
     {
         flagstatus = SET;
     }
@@ -607,7 +623,7 @@ uint8_t FMC_ReadPrefetchBufferStatus(void)
  */
 void FMC_EnableInterrupt(FMC_INT_T interrupt)
 {
-    if(interrupt == FMC_INT_ERR)
+    if (interrupt == FMC_INT_ERR)
     {
         FMC->CTRL2_B.ERRIE = ENABLE;
     }
@@ -629,7 +645,7 @@ void FMC_EnableInterrupt(FMC_INT_T interrupt)
  */
 void FMC_DisableInterrupt(FMC_INT_T interrupt)
 {
-    if(interrupt == FMC_INT_ERR)
+    if (interrupt == FMC_INT_ERR)
     {
         FMC->CTRL2_B.ERRIE = DISABLE;
     }
@@ -654,11 +670,11 @@ void FMC_DisableInterrupt(FMC_INT_T interrupt)
  */
 uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag)
 {
-    if(flag == FMC_FLAG_OBE)
+    if (flag == FMC_FLAG_OBE)
     {
         return FMC->OBCS_B.OBE;
     }
-    else if((FMC->STS & flag ) != RESET)
+    else if ((FMC->STS & flag) != RESET)
     {
         return SET;
     }
@@ -676,9 +692,8 @@ uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag)
  *
  * @retval    None
  *
- * @note
  */
-void FMC_ClearStatusFlag(FMC_FLAG_T flag)
+void FMC_ClearStatusFlag(uint32_t flag)
 {
     FMC->STS = flag;
 }
@@ -698,15 +713,15 @@ FMC_STATUS_T  FMC_ReadStatus(void)
 {
     FMC_STATUS_T status = FMC_STATUS_COMPLETE;
 
-    if(FMC->STS_B.BUSYF == BIT_SET)
+    if (FMC->STS_B.BUSYF == BIT_SET)
     {
         status = FMC_STATUS_BUSY;
     }
-    else if(FMC->STS_B.PEF == BIT_SET)
+    else if (FMC->STS_B.PEF == BIT_SET)
     {
         status = FMC_STATUS_ERROR_PG;
     }
-    else if(FMC->STS_B.WPEF == BIT_SET)
+    else if (FMC->STS_B.WPEF == BIT_SET)
     {
         status = FMC_STATUS_ERROR_WRP;
     }
@@ -736,12 +751,12 @@ FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut)
     status = FMC_ReadStatus();
 
     /** Wait for a Flash operation to complete or a TIMEOUT to occur */
-    while((status == FMC_STATUS_BUSY) && (timeOut !=0))
+    while ((status == FMC_STATUS_BUSY) && (timeOut != 0))
     {
         status = FMC_ReadStatus();
         timeOut--;
     }
-    if(timeOut == 0x00)
+    if (timeOut == 0x00)
     {
         status = FMC_STATUS_TIMEOUT;
     }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c

@@ -1,12 +1,26 @@
 /*!
- * @file       apm32f10x_gpio.c
+ * @file        apm32f10x_gpio.c
  *
- * @brief      This file provides all the GPIO firmware functions
+ * @brief       This file provides all the GPIO firmware functions
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_gpio.h"
@@ -32,7 +46,7 @@
  *
  * @retval    None
  */
-void GPIO_Reset(GPIO_T* port)
+void GPIO_Reset(GPIO_T *port)
 {
     RCM_APB2_PERIPH_T APB2Periph;
 
@@ -92,7 +106,7 @@ void GPIO_AFIOReset(void)
  *
  * @retval    None
  */
-void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig)
+void GPIO_Config(GPIO_T *port, GPIO_Config_T *gpioConfig)
 {
     uint8_t i;
     uint32_t mode;
@@ -167,10 +181,10 @@ void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig)
  *
  * @retval    None
  */
-void GPIO_StructInit(GPIO_Config_T* gpioConfig)
+void GPIO_ConfigStructInit(GPIO_Config_T *gpioConfig)
 {
     gpioConfig->pin  = GPIO_PIN_ALL;
-    gpioConfig->speed = GPIO_SPEED_2MHz;
+    gpioConfig->speed = GPIO_SPEED_20MHz;
     gpioConfig->mode = GPIO_MODE_IN_FLOATING;
 }
 
@@ -185,7 +199,7 @@ void GPIO_StructInit(GPIO_Config_T* gpioConfig)
  *
  * @retval    The input port pin value
  */
-uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin)
+uint8_t GPIO_ReadInputBit(GPIO_T *port, uint16_t pin)
 {
     uint8_t ret;
 
@@ -202,7 +216,7 @@ uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin)
  *
  * @retval    GPIO input data port value
  */
-uint16_t GPIO_ReadInputPort(GPIO_T* port)
+uint16_t GPIO_ReadInputPort(GPIO_T *port)
 {
     return ((uint16_t)port->IDATA);
 }
@@ -218,7 +232,7 @@ uint16_t GPIO_ReadInputPort(GPIO_T* port)
  *
  * @retval    The output port pin value
  */
-uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin)
+uint8_t GPIO_ReadOutputBit(GPIO_T *port, uint16_t pin)
 {
 
     uint8_t ret;
@@ -236,7 +250,7 @@ uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin)
  *
  * @retval    output data port value
  */
-uint16_t GPIO_ReadOutputPort(GPIO_T* port)
+uint16_t GPIO_ReadOutputPort(GPIO_T *port)
 {
     return ((uint16_t)port->ODATA);
 }
@@ -252,7 +266,7 @@ uint16_t GPIO_ReadOutputPort(GPIO_T* port)
  *
  * @retval    None
  */
-void GPIO_SetBits(GPIO_T* port, uint16_t pin)
+void GPIO_SetBit(GPIO_T *port, uint16_t pin)
 {
     port->BSC = (uint32_t)pin;
 }
@@ -268,7 +282,7 @@ void GPIO_SetBits(GPIO_T* port, uint16_t pin)
  *
  * @retval    None
  */
-void GPIO_ResetBits(GPIO_T* port, uint16_t pin)
+void GPIO_ResetBit(GPIO_T *port, uint16_t pin)
 {
     port->BC = (uint32_t)pin;
 }
@@ -290,7 +304,7 @@ void GPIO_ResetBits(GPIO_T* port, uint16_t pin)
  *
  * @retval    None
  */
-void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal)
+void GPIO_WriteBitValue(GPIO_T *port, uint16_t pin, uint8_t bitVal)
 {
     if (bitVal != BIT_RESET)
     {
@@ -312,7 +326,7 @@ void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal)
  *
  * @retval    None
  */
-void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue)
+void GPIO_WriteOutputPort(GPIO_T *port, uint16_t portValue)
 {
     port->ODATA = (uint32_t)portValue;
 }
@@ -328,20 +342,20 @@ void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue)
  *
  * @retval    None
  */
-void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin)
+void GPIO_ConfigPinLock(GPIO_T *port, uint16_t pin)
 {
     uint32_t val = 0x00010000;
 
     val  |= pin;
-    /* Set LCKK bit */
+    /** Set LCKK bit */
     port->LOCK = val ;
-    /* Reset LCKK bit */
+    /** Reset LCKK bit */
     port->LOCK =  pin;
-    /* Set LCKK bit */
+    /** Set LCKK bit */
     port->LOCK = val;
-    /* Read LCKK bit*/
+    /** Read LCKK bit*/
     val = port->LOCK;
-    /* Read LCKK bit*/
+    /** Read LCKK bit*/
     val = port->LOCK;
 }
 
@@ -457,7 +471,7 @@ void GPIO_ConfigPinRemap(GPIO_REMAP_T remap)
         regVal = AFIO->REMAP1;
     }
 
-    if(remap >> 8 == 0x18)
+    if (remap >> 8 == 0x18)
     {
         regVal &= 0xF0FFFFFF;
         AFIO->REMAP1 &= 0xF0FFFFFF;
@@ -500,28 +514,28 @@ void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSou
     if (pinSource <= GPIO_PIN_SOURCE_3)
     {
         shift = pinSource << 2;
-        AFIO->EINTSEL1 &= (uint32_t )~(0x0f << shift);
+        AFIO->EINTSEL1 &= (uint32_t)~(0x0f << shift);
         AFIO->EINTSEL1 |=  portSource << shift;
     }
 
     else if (pinSource <= GPIO_PIN_SOURCE_7)
     {
         shift = (pinSource - GPIO_PIN_SOURCE_4) << 2;
-        AFIO->EINTSEL2 &= (uint32_t )~(0x0f << shift);
+        AFIO->EINTSEL2 &= (uint32_t)~(0x0f << shift);
         AFIO->EINTSEL2 |=  portSource << shift;
     }
 
     else if (pinSource <= GPIO_PIN_SOURCE_11)
     {
         shift = (pinSource - GPIO_PIN_SOURCE_8) << 2;
-        AFIO->EINTSEL3 &= (uint32_t )~(0x0f << shift);
+        AFIO->EINTSEL3 &= (uint32_t)~(0x0f << shift);
         AFIO->EINTSEL3 |=  portSource << shift;
     }
 
     else if (pinSource <= GPIO_PIN_SOURCE_15)
     {
         shift = (pinSource - GPIO_PIN_SOURCE_12) << 2;
-        AFIO->EINTSEL4 &= (uint32_t )~(0x0f << shift);
+        AFIO->EINTSEL4 &= (uint32_t)~(0x0f << shift);
         AFIO->EINTSEL4 |=  portSource << shift;
     }
 }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c

@@ -1,12 +1,26 @@
 /*!
- * @file       apm32f10x_i2c.c
+ * @file        apm32f10x_i2c.c
  *
- * @brief      This file provides all the I2C firmware functions
+ * @brief       This file provides all the I2C firmware functions
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_i2c.h"
@@ -31,9 +45,9 @@
  *
  * @retval    None
  */
-void I2C_Reset(I2C_T* i2c)
+void I2C_Reset(I2C_T *i2c)
 {
-    if(i2c == I2C1)
+    if (i2c == I2C1)
     {
         RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1);
         RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1);
@@ -54,7 +68,7 @@ void I2C_Reset(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
+void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig)
 {
     uint16_t tmpreg = 0, freqrange = 0;
     uint32_t PCLK1 = 8000000, PCLK2 = 0;
@@ -65,15 +79,15 @@ void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
     /** I2C CTRL2 Configuration */
     RCM_ReadPCLKFreq(&PCLK1, &PCLK2);
     freqrange = PCLK1 / 1000000;
-    i2c->CTRL2_B.CLKFCFG= freqrange;
+    i2c->CTRL2_B.CLKFCFG = freqrange;
 
     /** I2C CLKCTRL Configuration */
     i2c->CTRL1_B.I2CEN = BIT_RESET;
 
-    if(i2cConfig->clockSpeed <= 100000)
+    if (i2cConfig->clockSpeed <= 100000)
     {
         result = (PCLK1 / (i2cConfig->clockSpeed << 1));
-        if(result < 0x04)
+        if (result < 0x04)
         {
             result = 0x04;
         }
@@ -83,7 +97,7 @@ void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
     /** Configure speed in fast mode */
     else
     {
-        if(i2cConfig->dutyCycle == I2C_DUTYCYCLE_2)
+        if (i2cConfig->dutyCycle == I2C_DUTYCYCLE_2)
         {
             result = (PCLK1 / (i2cConfig->clockSpeed * 3));
         }
@@ -93,7 +107,7 @@ void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
             result |= I2C_DUTYCYCLE_16_9;
         }
 
-        if((result & 0x0FFF) == 0)
+        if ((result & 0x0FFF) == 0)
         {
             result |= 0x0001;
         }
@@ -122,7 +136,7 @@ void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
  *
  * @retval    None
  */
-void I2C_ConfigStructInit(I2C_Config_T* i2cConfig)
+void I2C_ConfigStructInit(I2C_Config_T *i2cConfig)
 {
     i2cConfig->clockSpeed = 5000;
     i2cConfig->mode = I2C_MODE_I2C;
@@ -139,7 +153,7 @@ void I2C_ConfigStructInit(I2C_Config_T* i2cConfig)
  *
  * @retval    None
  */
-void I2C_Enable(I2C_T* i2c)
+void I2C_Enable(I2C_T *i2c)
 {
     i2c->CTRL1_B.I2CEN = ENABLE;
 }
@@ -151,7 +165,7 @@ void I2C_Enable(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_Disable(I2C_T* i2c)
+void I2C_Disable(I2C_T *i2c)
 {
     i2c->CTRL1_B.I2CEN = DISABLE;
 }
@@ -163,7 +177,7 @@ void I2C_Disable(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableGenerateStart(I2C_T* i2c)
+void I2C_EnableGenerateStart(I2C_T *i2c)
 {
     i2c->CTRL1_B.START = BIT_SET;
 }
@@ -175,7 +189,7 @@ void I2C_EnableGenerateStart(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableGenerateStart(I2C_T* i2c)
+void I2C_DisableGenerateStart(I2C_T *i2c)
 {
     i2c->CTRL1_B.START = BIT_RESET;
 }
@@ -187,7 +201,7 @@ void I2C_DisableGenerateStart(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableGenerateStop(I2C_T* i2c)
+void I2C_EnableGenerateStop(I2C_T *i2c)
 {
     i2c->CTRL1_B.STOP = BIT_SET;
 }
@@ -199,7 +213,7 @@ void I2C_EnableGenerateStop(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableGenerateStop(I2C_T* i2c)
+void I2C_DisableGenerateStop(I2C_T *i2c)
 {
     i2c->CTRL1_B.STOP = BIT_RESET;
 }
@@ -211,7 +225,7 @@ void I2C_DisableGenerateStop(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableAcknowledge(I2C_T* i2c)
+void I2C_EnableAcknowledge(I2C_T *i2c)
 {
     i2c->CTRL1_B.ACKEN = ENABLE;
 }
@@ -223,7 +237,7 @@ void I2C_EnableAcknowledge(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableAcknowledge(I2C_T* i2c)
+void I2C_DisableAcknowledge(I2C_T *i2c)
 {
     i2c->CTRL1_B.ACKEN = DISABLE;
 }
@@ -237,7 +251,7 @@ void I2C_DisableAcknowledge(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address)
+void I2C_ConfigOwnAddress2(I2C_T *i2c, uint8_t address)
 {
     i2c->SADDR2_B.ADDR2 = address;
 }
@@ -249,7 +263,7 @@ void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address)
  *
  * @retval    None
  */
-void I2C_EnableDualAddress(I2C_T* i2c)
+void I2C_EnableDualAddress(I2C_T *i2c)
 {
     i2c->SADDR2_B.ADDRNUM = ENABLE;
 }
@@ -261,7 +275,7 @@ void I2C_EnableDualAddress(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableDualAddress(I2C_T* i2c)
+void I2C_DisableDualAddress(I2C_T *i2c)
 {
     i2c->SADDR2_B.ADDRNUM = DISABLE;
 }
@@ -273,7 +287,7 @@ void I2C_DisableDualAddress(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableGeneralCall(I2C_T* i2c)
+void I2C_EnableGeneralCall(I2C_T *i2c)
 {
     i2c->CTRL1_B.SRBEN = ENABLE;
 }
@@ -285,7 +299,7 @@ void I2C_EnableGeneralCall(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableGeneralCall(I2C_T* i2c)
+void I2C_DisableGeneralCall(I2C_T *i2c)
 {
     i2c->CTRL1_B.SRBEN = DISABLE;
 }
@@ -299,7 +313,7 @@ void I2C_DisableGeneralCall(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_TxData(I2C_T* i2c, uint8_t data)
+void I2C_TxData(I2C_T *i2c, uint8_t data)
 {
     i2c->DATA_B.DATA = data;
 }
@@ -311,7 +325,7 @@ void I2C_TxData(I2C_T* i2c, uint8_t data)
  *
  * @retval    received data
  */
-uint8_t I2C_RxData(I2C_T* i2c)
+uint8_t I2C_RxData(I2C_T *i2c)
 {
     return i2c->DATA_B.DATA;
 }
@@ -329,9 +343,9 @@ uint8_t I2C_RxData(I2C_T* i2c)
  *              @arg I2C_DIRECTION_RX: Receiver mode
  * @retval    None
  */
-void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction)
+void I2C_Tx7BitAddress(I2C_T *i2c, uint8_t address, I2C_DIRECTION_T direction)
 {
-    if(direction != I2C_DIRECTION_TX)
+    if (direction != I2C_DIRECTION_TX)
     {
         i2c->DATA_B.DATA = address | 0x0001;
     }
@@ -361,7 +375,7 @@ void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction)
  *
  * @retval    The value of the read register
  */
-uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister)
+uint16_t I2C_ReadRegister(I2C_T *i2c, I2C_REGISTER_T i2cRegister)
 {
     switch (i2cRegister)
     {
@@ -397,7 +411,7 @@ uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister)
  *
  * @retval    None
  */
-void I2C_EnableSoftwareReset(I2C_T* i2c)
+void I2C_EnableSoftwareReset(I2C_T *i2c)
 {
     i2c->CTRL1_B.SWRST = ENABLE;
 }
@@ -409,7 +423,7 @@ void I2C_EnableSoftwareReset(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableSoftwareReset(I2C_T* i2c)
+void I2C_DisableSoftwareReset(I2C_T *i2c)
 {
     i2c->CTRL1_B.SWRST = DISABLE;
 }
@@ -423,9 +437,9 @@ void I2C_DisableSoftwareReset(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition)
+void I2C_ConfigNACKPosition(I2C_T *i2c, I2C_NACK_POSITION_T NACKPosition)
 {
-    if(NACKPosition == I2C_NACK_POSITION_NEXT)
+    if (NACKPosition == I2C_NACK_POSITION_NEXT)
     {
         i2c->CTRL1_B.ACKPOS = BIT_SET;
     }
@@ -446,9 +460,9 @@ void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition)
  *              @arg I2C_SMBUSALER_HIGH: SMBus Alert pin high
  * @retval    None
  */
-void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState)
+void I2C_ConfigSMBusAlert(I2C_T *i2c, I2C_SMBUSALER_T SMBusState)
 {
-    if(SMBusState == I2C_SMBUSALER_LOW)
+    if (SMBusState == I2C_SMBUSALER_LOW)
     {
         i2c->CTRL1_B.ALERTEN = BIT_SET;
     }
@@ -465,7 +479,7 @@ void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState)
  *
  * @retval    None
  */
-void I2C_EnablePECTransmit(I2C_T* i2c)
+void I2C_EnablePECTransmit(I2C_T *i2c)
 {
     i2c->CTRL1_B.PEC = BIT_SET;
 }
@@ -477,7 +491,7 @@ void I2C_EnablePECTransmit(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisablePECTransmit(I2C_T* i2c)
+void I2C_DisablePECTransmit(I2C_T *i2c)
 {
     i2c->CTRL1_B.PEC = BIT_RESET;
 }
@@ -493,9 +507,9 @@ void I2C_DisablePECTransmit(I2C_T* i2c)
  *              @arg I2C_PEC_POSITION_CURRENT: indicates that current byte is PEC
  * @retval    None
  */
-void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition)
+void I2C_ConfigPECPosition(I2C_T *i2c, I2C_PEC_POSITION_T PECPosition)
 {
-    if(PECPosition == I2C_PEC_POSITION_NEXT)
+    if (PECPosition == I2C_PEC_POSITION_NEXT)
     {
         i2c->CTRL1_B.ACKPOS = BIT_SET;
     }
@@ -512,7 +526,7 @@ void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition)
  *
  * @retval    None
  */
-void I2C_EnablePEC(I2C_T* i2c)
+void I2C_EnablePEC(I2C_T *i2c)
 {
     i2c->CTRL1_B.PECEN = BIT_SET;
 }
@@ -524,7 +538,7 @@ void I2C_EnablePEC(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisablePEC(I2C_T* i2c)
+void I2C_DisablePEC(I2C_T *i2c)
 {
     i2c->CTRL1_B.PECEN = BIT_RESET;
 }
@@ -536,7 +550,7 @@ void I2C_DisablePEC(I2C_T* i2c)
  *
  * @retval    value of PEC
  */
-uint8_t I2C_ReadPEC(I2C_T* i2c)
+uint8_t I2C_ReadPEC(I2C_T *i2c)
 {
     return i2c->STS2_B.PECVALUE;
 }
@@ -548,7 +562,7 @@ uint8_t I2C_ReadPEC(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableARP(I2C_T* i2c)
+void I2C_EnableARP(I2C_T *i2c)
 {
     i2c->CTRL1_B.ARPEN = BIT_SET;
 }
@@ -560,7 +574,7 @@ void I2C_EnableARP(I2C_T* i2c)
 *
 * @retval     None
 */
-void I2C_DisableARP(I2C_T* i2c)
+void I2C_DisableARP(I2C_T *i2c)
 {
     i2c->CTRL1_B.ARPEN = BIT_RESET;
 }
@@ -572,7 +586,7 @@ void I2C_DisableARP(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableStretchClock(I2C_T* i2c)
+void I2C_EnableStretchClock(I2C_T *i2c)
 {
     i2c->CTRL1_B.CLKSTRETCHD = BIT_RESET;
 }
@@ -584,7 +598,7 @@ void I2C_EnableStretchClock(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableStretchClock(I2C_T* i2c)
+void I2C_DisableStretchClock(I2C_T *i2c)
 {
     i2c->CTRL1_B.CLKSTRETCHD = BIT_SET;
 }
@@ -600,9 +614,9 @@ void I2C_DisableStretchClock(I2C_T* i2c)
  *              @arg I2C_DUTYCYCLE_2: I2C fast mode Tlow/Thigh = 2
  * @retval    None
  */
-void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle)
+void I2C_ConfigFastModeDutyCycle(I2C_T *i2c, I2C_DUTYCYCLE_T dutyCycle)
 {
-    if(dutyCycle == I2C_DUTYCYCLE_16_9)
+    if (dutyCycle == I2C_DUTYCYCLE_16_9)
     {
         i2c->CLKCTRL_B.FDUTYCFG = BIT_SET;
     }
@@ -619,7 +633,7 @@ void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle)
  *
  * @retval    None
  */
-void I2C_EnableDMA(I2C_T* i2c)
+void I2C_EnableDMA(I2C_T *i2c)
 {
     i2c->CTRL2_B.DMAEN = ENABLE;
 }
@@ -631,7 +645,7 @@ void I2C_EnableDMA(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableDMA(I2C_T* i2c)
+void I2C_DisableDMA(I2C_T *i2c)
 {
     i2c->CTRL2_B.DMAEN = DISABLE;
 }
@@ -643,7 +657,7 @@ void I2C_DisableDMA(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableDMALastTransfer(I2C_T* i2c)
+void I2C_EnableDMALastTransfer(I2C_T *i2c)
 {
     i2c->CTRL2_B.LTCFG = BIT_SET;
 }
@@ -655,7 +669,7 @@ void I2C_EnableDMALastTransfer(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableDMALastTransfer(I2C_T* i2c)
+void I2C_DisableDMALastTransfer(I2C_T *i2c)
 {
     i2c->CTRL2_B.LTCFG = BIT_RESET;
 }
@@ -673,7 +687,7 @@ void I2C_DisableDMALastTransfer(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt)
+void I2C_EnableInterrupt(I2C_T *i2c, uint16_t interrupt)
 {
     i2c->CTRL2 |= interrupt;
 }
@@ -691,7 +705,7 @@ void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt)
  *
  * @retval    None
  */
-void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt)
+void I2C_DisableInterrupt(I2C_T *i2c, uint16_t interrupt)
 {
     i2c->CTRL2 &= ~interrupt;
 }
@@ -722,7 +736,7 @@ void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt)
  *
  * @retval    Status: SUCCESS or ERROR
  */
-uint8_t  I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent)
+uint8_t  I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent)
 {
     uint32_t lastevent = 0;
     uint32_t flag1 = 0, flag2 = 0;
@@ -733,7 +747,7 @@ uint8_t  I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent)
 
     lastevent = (flag1 | flag2) & 0x00FFFFFF;
 
-    if((lastevent & i2cEvent) == i2cEvent)
+    if ((lastevent & i2cEvent) == i2cEvent)
     {
         return SUCCESS;
     }
@@ -747,7 +761,7 @@ uint8_t  I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent)
  *
  * @retval    The last event
  */
-uint32_t I2C_ReadLastEvent(I2C_T* i2c)
+uint32_t I2C_ReadLastEvent(I2C_T *i2c)
 {
     uint32_t lastevent = 0;
     uint32_t flag1 = 0, flag2 = 0;
@@ -792,7 +806,7 @@ uint32_t I2C_ReadLastEvent(I2C_T* i2c)
  *
  * @retval    Status: flag SET or RESET
  */
-uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
+uint8_t I2C_ReadStatusFlag(I2C_T *i2c, I2C_FLAG_T flag)
 {
 
     uint8_t status = 0;
@@ -900,7 +914,7 @@ uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
  *              a read operation to I2C_STS1 register (I2C_ReadStatusFlag())
  *              followed by a write operation to I2C_DATA register (I2C_TxData()).
  */
-void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
+void I2C_ClearStatusFlag(I2C_T *i2c, I2C_FLAG_T flag)
 {
     switch (flag)
     {
@@ -954,13 +968,13 @@ void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
  *
  * @retval    Status: flag SET or RESET
  */
-uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag)
+uint8_t I2C_ReadIntFlag(I2C_T *i2c, I2C_INT_FLAG_T flag)
 {
     uint32_t enablestatus = 0;
 
     enablestatus = ((flag & 0x07000000) >> 16) & (i2c->CTRL2);
     flag &= 0x00FFFFFF;
-    if(((i2c->STS1 & flag) != RESET) && enablestatus)
+    if (((i2c->STS1 & flag) != RESET) && enablestatus)
     {
         return SET;
     }
@@ -973,7 +987,7 @@ uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag)
  * @param     i2c: I2C selet 1 or 2
  *
  * @param     flag: specifies the I2C flag
- *              The parameter can be one of the following values:
+ *              The parameter can be any combination of the following values:
  *              @arg I2C_INT_FLAG_SMBALT:   SMBus Alert flag
  *              @arg I2C_INT_FLAG_TTE:      Timeout or Tlow error flag
  *              @arg I2C_INT_FLAG_PECE:     PEC error in reception flag
@@ -1000,12 +1014,9 @@ uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag)
  *              a read operation to I2C_STS1 register (I2C_ReadIntFlag())
  *              followed by a write operation to I2C_DATA register (I2C_TxData()).
  */
-void I2C_ClearIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag)
+void I2C_ClearIntFlag(I2C_T *i2c, uint32_t flag)
 {
-    uint32_t flagpos = 0;
-
-    flagpos = flag & 0x00FFFFFF;
-    i2c->STS1 = ~flagpos;
+    i2c->STS1 = (uint16_t)~(flag & 0x00FFFFFF);
 }
 
 /**@} end of group I2C_Fuctions*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c

@@ -3,10 +3,24 @@
  *
  * @brief       This file provides all the IWDT firmware functions
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_iwdt.h"
@@ -113,13 +127,12 @@ void IWDT_ConfigDivider(uint8_t div)
  *
  * @retval       status of IWDT_FLAG (SET or RESET)
  *
- * @note
  */
 uint8_t IWDT_ReadStatusFlag(uint16_t flag)
 {
     uint8_t bitStatus = RESET;
 
-    if((IWDT->STS & flag) != (uint32_t)RESET)
+    if ((IWDT->STS & flag) != (uint32_t)RESET)
     {
         bitStatus = SET;
     }
@@ -131,5 +144,5 @@ uint8_t IWDT_ReadStatusFlag(uint16_t flag)
 }
 
 /**@} end of group IWDT_Fuctions*/
-/**@} end of group IWDT_Driver */
+/**@} end of group IWDT_Driver*/
 /**@} end of group Peripherals_Library*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c

@@ -1,13 +1,27 @@
 /*!
- * @file       apm32f10x_misc.c
+ * @file        apm32f10x_misc.c
  *
- * @brief      This file provides all the miscellaneous firmware functions.
+ * @brief       This file provides all the miscellaneous firmware functions.
  *             Include NVIC,SystemTick and Power management.
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_misc.h"
@@ -26,7 +40,7 @@
 
 #define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
 
-/**@} end of group I2C_Macros*/
+/**@} end of group MISC_Macros*/
 
 
 /** @addtogroup MISC_Fuctions Fuctions
@@ -48,7 +62,7 @@
  */
 void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup)
 {
-   SCB->AIRCR = AIRCR_VECTKEY_MASK | priorityGroup;
+    SCB->AIRCR = AIRCR_VECTKEY_MASK | priorityGroup;
 }
 
 /*!
@@ -65,55 +79,55 @@ void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup)
  */
 void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t subPriority)
 {
-   uint32_t tempPriority, tempPrePri, tempSubPri;
-   uint32_t priorityGrp;
-
-   /** Get priority group */
-   priorityGrp = (SCB->AIRCR) & (uint32_t)0x700U;
-
-   /** get pre-emption priority and subpriority */
-   switch(priorityGrp)
-   {
-      case NVIC_PRIORITY_GROUP_0:
-         tempPrePri = 0;
-         tempSubPri = 4;
-         break;
-
-      case NVIC_PRIORITY_GROUP_1:
-         tempPrePri = 1;
-         tempSubPri = 3;
-         break;
-
-      case NVIC_PRIORITY_GROUP_2:
-         tempPrePri = 2;
-         tempSubPri = 2;
-         break;
-
-      case NVIC_PRIORITY_GROUP_3:
-         tempPrePri = 3;
-         tempSubPri = 1;
-         break;
-
-      case NVIC_PRIORITY_GROUP_4:
-         tempPrePri = 4;
-         tempSubPri = 0;
-         break;
-
-      default:
-         NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0);
-         tempPrePri = 0;
-         tempSubPri = 4;
-         break;
-   }
-
-   tempPrePri = 4 - tempPrePri;
-   tempSubPri = 4 - tempSubPri;
-   tempPriority = preemptionPriority << tempPrePri;
-   tempPriority |= subPriority & (0x0f >> tempSubPri);
-   tempPriority <<= 4;
-   NVIC->IP[irq] = (uint8_t)tempPriority;
-
-    /* enable the selected IRQ */
+    uint32_t tempPriority, tempPrePri, tempSubPri;
+    uint32_t priorityGrp;
+
+    /** Get priority group */
+    priorityGrp = (SCB->AIRCR) & (uint32_t)0x700U;
+
+    /** get pre-emption priority and subpriority */
+    switch (priorityGrp)
+    {
+    case NVIC_PRIORITY_GROUP_0:
+        tempPrePri = 0;
+        tempSubPri = 4;
+        break;
+
+    case NVIC_PRIORITY_GROUP_1:
+        tempPrePri = 1;
+        tempSubPri = 3;
+        break;
+
+    case NVIC_PRIORITY_GROUP_2:
+        tempPrePri = 2;
+        tempSubPri = 2;
+        break;
+
+    case NVIC_PRIORITY_GROUP_3:
+        tempPrePri = 3;
+        tempSubPri = 1;
+        break;
+
+    case NVIC_PRIORITY_GROUP_4:
+        tempPrePri = 4;
+        tempSubPri = 0;
+        break;
+
+    default:
+        NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0);
+        tempPrePri = 0;
+        tempSubPri = 4;
+        break;
+    }
+
+    tempPrePri = 4 - tempPrePri;
+    tempSubPri = 4 - tempSubPri;
+    tempPriority = preemptionPriority << tempPrePri;
+    tempPriority |= subPriority & (0x0f >> tempSubPri);
+    tempPriority <<= 4;
+    NVIC->IP[irq] = (uint8_t)tempPriority;
+
+    /** enable the selected IRQ */
     NVIC->ISER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU);
 }
 
@@ -126,7 +140,7 @@ void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t su
  */
 void NVIC_DisableIRQRequest(IRQn_Type irq)
 {
-    /* disable the selected IRQ.*/
+    /** disable the selected IRQ.*/
     NVIC->ICER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU);
 }
 
@@ -160,10 +174,9 @@ void NVIC_ConfigVectorTable(NVIC_VECT_TAB_T vectTab, uint32_t offset)
  */
 void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode)
 {
-   SCB->SCR |= lowPowerMode;
+    SCB->SCR |= lowPowerMode;
 }
 
-
 /*!
  * @brief     reset the state of the low power mode
  *
@@ -177,7 +190,7 @@ void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode)
  */
 void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode)
 {
-   SCB->SCR &= (uint32_t)(~(uint32_t)lowPowerMode);
+    SCB->SCR &= (uint32_t)(~(uint32_t)lowPowerMode);
 }
 
 /*!
@@ -192,16 +205,16 @@ void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode)
  */
 void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource)
 {
-   if (clkSource == SYSTICK_CLK_SOURCE_HCLK)
-   {
-      SysTick->CTRL |= (uint32_t)BIT2;
-   }
-   else
-   {
-      SysTick->CTRL &= (uint32_t)(~BIT2);
-   }
+    if (clkSource == SYSTICK_CLK_SOURCE_HCLK)
+    {
+        SysTick->CTRL |= (uint32_t)BIT2;
+    }
+    else
+    {
+        SysTick->CTRL &= (uint32_t)(~BIT2);
+    }
 }
 
 /**@} end of group MISC_Fuctions*/
-/**@} end of group MISC_Driver */
+/**@} end of group MISC_Driver*/
 /**@} end of group Peripherals_Library*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c

@@ -1,12 +1,26 @@
 /*!
- * @file       apm32f10x_pmu.c
+ * @file        apm32f10x_pmu.c
  *
- * @brief      This file provides all the PMU firmware functions.
+ * @brief       This file provides all the PMU firmware functions.
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_pmu.h"
@@ -33,8 +47,8 @@
  */
 void PMU_Reset(void)
 {
-    RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_PMU);
-    RCM_DisableAPB1PeriphClock(RCM_APB1_PERIPH_PMU);
+    RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_PMU);
+    RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_PMU);
 }
 
 /*!
@@ -88,7 +102,7 @@ void PMU_DisablePVD(void)
 /*!
  * @brief     Configure a voltage threshold detected by a power supply voltage detector (PVD).
  *
- * @param     level : specifies the PVD detection level
+ * @param     level：specifies the PVD detection level
  *                   This parameter can be one of the following values:
  *                   @arg PMU_PVD_LEVEL_2V2 : Config PVD detection level to 2.2V
  *                   @arg PMU_PVD_LEVEL_2V3 : Config PVD detection level to 2.3V
@@ -104,9 +118,9 @@ void PMU_DisablePVD(void)
 void PMU_ConfigPVDLevel(PMU_PVD_LEVEL_T level)
 {
 
-    /* Clear PLS[7:5] bits */
+    /** Clear PLS[7:5] bits */
     PMU->CTRL_B.PLSEL = 0x0000;
-    /* Store the new value */
+    /** Store the new value */
     PMU->CTRL_B.PLSEL = level;
 }
 
@@ -151,17 +165,20 @@ void PMU_DisableWakeUpPin(void)
  */
 void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry)
 {
-    /** Clear PLS and LPSM bits */
+    /** Clear PDDSCFG and LPDSCFG bits */
     PMU->CTRL_B.PDDSCFG = 0x00;
     PMU->CTRL_B.LPDSCFG = 0x00;
-    /** Set LPSM bit according to PWR_Regulator value */
-    PMU->CTRL_B.PDDSCFG = regulator;
+    /** Set LPDSCFG bit according to regulator value */
+    PMU->CTRL_B.LPDSCFG = regulator;
+    /** Set Cortex System Control Register */
+    SCB->SCR |= (uint32_t)0x04;
     /** Select STOP mode entry*/
-    if(entry == PMU_STOP_ENTRY_WFI)
+    if (entry == PMU_STOP_ENTRY_WFI)
     {
         /** Request Wait For Interrupt */
         __WFI();
-    } else
+    }
+    else
     {
         /** Request Wait For Event */
         __WFE();
@@ -169,7 +186,6 @@ void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry)
 
     /** Reset SLEEPDEEP bit of Cortex System Control Register */
     SCB->SCR &= (uint32_t)~((uint32_t)0x04);
-
 }
 
 /*!
@@ -181,16 +197,16 @@ void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry)
  */
 void PMU_EnterSTANDBYMode(void)
 {
-    /* Clear Wake-up flag */
+    /** Clear Wake-up flag */
     PMU->CTRL_B.WUFLGCLR = BIT_SET;
-    /* Select STANDBY mode */
+    /** Select STANDBY mode */
     PMU->CTRL_B.PDDSCFG = BIT_SET;
-    /* Set SLEEPDEEP bit of Cortex System Control Register */
-    SCB->SCR |= (uint8_t )0x04;
+    /** Set Cortex System Control Register */
+    SCB->SCR |= (uint32_t)0x04;
 #if defined ( __CC_ARM   )
     __force_stores();
 #endif
-    /* Request Wait For Interrupt */
+    /** Request Wait For Interrupt */
     __WFI();
 
 }
@@ -198,7 +214,7 @@ void PMU_EnterSTANDBYMode(void)
 /*!
  * @brief     Read the specified PWR flag is set or not.
  *
- * @param     flag : Reads the status of specifies the flag.
+ * @param     flag：Reads the status of specifies the flag.
  *                  This parameter can be one of the following values:
  *                    @arg PMU_FLAG_WUE : Wake Up flag
  *                    @arg PMU_FLAG_SB  : StandBy flag
@@ -210,13 +226,15 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag)
 {
     uint8_t BitStatus = BIT_RESET;
 
-    if(flag == PMU_FLAG_WUE)
+    if (flag == PMU_FLAG_WUE)
     {
         BitStatus = PMU->CSTS_B.WUEFLG;
-    } else if(flag == PMU_FLAG_SB)
+    }
+    else if (flag == PMU_FLAG_SB)
     {
         BitStatus = PMU->CSTS_B.SBFLG;
-    } else if(flag == PMU_FLAG_PVDO)
+    }
+    else if (flag == PMU_FLAG_PVDO)
     {
         BitStatus = PMU->CSTS_B.PVDOFLG;
     }
@@ -226,7 +244,7 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag)
 /*!
  * @brief     Clears the PWR's pending flags.
  *
- * @param     flag : Clears the status of specifies the flag.
+ * @param     flag：Clears the status of specifies the flag.
  *                  This parameter can be one of the following values:
  *                    @arg PMU_FLAG_WUE : Wake Up flag
  *                    @arg PMU_FLAG_SB  : StandBy flag
@@ -235,15 +253,16 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag)
  */
 void PMU_ClearStatusFlag(PMU_FLAG_T flag)
 {
-    if(flag == PMU_FLAG_WUE)
+    if (flag == PMU_FLAG_WUE)
     {
         PMU->CTRL_B.WUFLGCLR = BIT_SET;
-    } else if(flag == PMU_FLAG_SB)
+    }
+    else if (flag == PMU_FLAG_SB)
     {
         PMU->CTRL_B.SBFLGCLR = BIT_SET;
     }
 }
 
 /**@} end of group PMU_Fuctions*/
-/**@} end of group PMU_Driver */
+/**@} end of group PMU_Driver*/
 /**@} end of group Peripherals_Library*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c

@@ -3,12 +3,27 @@
  *
  * @brief       This file contains all the functions for the QSPI peripheral
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
+#if defined (APM32F10X_MD) || defined (APM32F10X_LD)
 #include "apm32f10x_qspi.h"
 
 /** @addtogroup Peripherals_Library Standard Peripheral Library
@@ -58,7 +73,7 @@ void QSPI_Reset(void)
  *
  * @retval      None
  */
-void QSPI_Config(QSPI_Config_T * qspiConfig)
+void QSPI_Config(QSPI_Config_T *qspiConfig)
 {
     QSPI->CTRL1_B.CPHA = qspiConfig->clockPhase;
     QSPI->CTRL1_B.CPOL = qspiConfig->clockPolarity;
@@ -67,7 +82,6 @@ void QSPI_Config(QSPI_Config_T * qspiConfig)
     QSPI->CTRL1_B.SSTEN = qspiConfig->selectSlaveToggle;
 
     QSPI->BR = qspiConfig->clockDiv;
-
 }
 
 /*!
@@ -571,24 +585,25 @@ void QSPI_ClearIntFlag(uint32_t flag)
 {
     volatile uint32_t dummy = 0;
 
-    if(flag & QSPI_INT_FLAG_TFO)
+    if (flag & QSPI_INT_FLAG_TFO)
     {
         dummy = QSPI->TFOIC;
     }
-    else if(flag & QSPI_INT_FLAG_RFO)
+    else if (flag & QSPI_INT_FLAG_RFO)
     {
         dummy = QSPI->RFOIC;
     }
-    else if(flag & QSPI_INT_FLAG_RFU)
+    else if (flag & QSPI_INT_FLAG_RFU)
     {
         dummy = QSPI->RFUIC;
     }
-    else if(flag & QSPI_INT_FLAG_MST)
+    else if (flag & QSPI_INT_FLAG_MST)
     {
         dummy = QSPI->MIC;
     }
 }
+#endif //defined APM32F10X_MD/LD
 
 /**@} end of group QSPI_Fuctions*/
-/**@} end of group QSPI_Driver */
+/**@} end of group QSPI_Driver*/
 /**@} end of group Peripherals_Library*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c

@@ -1,12 +1,26 @@
 /*!
- * @file       apm32f10x_rcm.c
+ * @file        apm32f10x_rcm.c
  *
- * @brief      This file provides all the RCM firmware functions
+ * @brief       This file provides all the RCM firmware functions
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_rcm.h"
@@ -102,14 +116,14 @@ uint8_t RCM_WaitHSEReady(void)
 }
 
 /*!
- * @brief     Set HSI trimming value
+ * @brief     Config HSI trimming value
  *
  * @param     HSITrim: HSI trimming value
  *                     This parameter must be a number between 0 and 0x1F.
  *
  * @retval    None
  */
-void RCM_SetHSITrim(uint8_t HSITrim)
+void RCM_ConfigHSITrim(uint8_t HSITrim)
 {
     RCM->CTRL_B.HSITRIM = HSITrim;
 }
@@ -145,10 +159,12 @@ void RCM_DisableHSI(void)
  * @brief     Configures the External Low Speed oscillator (LSE)
  *
  * @param     state : Specifies the new state of the LSE
+ *                    This parameter can be one of the following values:
+ *                    @arg RCM_LSE_CLOSE  : Close the LSE
+ *                    @arg RCM_LSE_OPEN   : Open the LSE
+ *                    @arg RCM_LSE_BYPASS : LSE bypass
  *
  * @retval    None
- *
- * @note
  */
 void RCM_ConfigLSE(RCM_LSE_T state)
 {
@@ -172,8 +188,6 @@ void RCM_ConfigLSE(RCM_LSE_T state)
  * @param     None
  *
  * @retval    None
- *
- * @note
  */
 void RCM_EnableLSI(void)
 {
@@ -186,8 +200,6 @@ void RCM_EnableLSI(void)
  * @param     None
  *
  * @retval    None
- *
- * @note
  */
 void RCM_DisableLSI(void)
 {
@@ -273,14 +285,12 @@ void RCM_DisableCSS(void)
  * @param     mcoClock: specifies the clock source to output
  *                      This parameter can be one of the following values:
  *                      @arg RCM_MCOCLK_NO_CLOCK     : No clock selected.
- *                      @arg RCM_MCOCLK_SYSCLK       : HSI14 oscillator clock selected.
- *                      @arg RCM_MCOCLK_HSI          : LSI oscillator clock selected.
- *                      @arg RCM_MCOCLK_HSE          : LSE oscillator clock selected.
- *                      @arg RCM_MCOCLK_PLLCLK_DIV_2 : System clock selected.
+ *                      @arg RCM_MCOCLK_SYSCLK       : System clock selected.
+ *                      @arg RCM_MCOCLK_HSI          : HSI oscillator clock selected.
+ *                      @arg RCM_MCOCLK_HSE          : HSE oscillator clock selected.
+ *                      @arg RCM_MCOCLK_PLLCLK_DIV_2 : PLL clock divided by 2 selected.
  *
  * @retval    None
- *
- * @note
  */
 void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock)
 {
@@ -300,7 +310,7 @@ void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock)
  */
 void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect)
 {
-    RCM->CFG_B.SCLKSW = sysClkSelect;
+    RCM->CFG_B.SCLKSEL = sysClkSelect;
 }
 
 /*!
@@ -312,11 +322,7 @@ void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect)
  */
 RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void)
 {
-    RCM_SYSCLK_SEL_T sysClock;
-
-    sysClock = (RCM_SYSCLK_SEL_T)RCM->CFG_B.SCLKSWSTS;
-
-    return sysClock;
+    return (RCM_SYSCLK_SEL_T)RCM->CFG_B.SCLKSELSTS;
 }
 
 /*!
@@ -335,8 +341,6 @@ RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void)
  *                     @arg RCM_AHB_DIV_512 : HCLK = SYSCLK / 512
  *
  * @retval    None
- *
- * @note
  */
 void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv)
 {
@@ -482,47 +486,47 @@ uint32_t RCM_ReadSYSCLKFreq(void)
     uint32_t sysClock, pllMull, pllSource;
 
     /** get sys clock */
-    sysClock = RCM->CFG_B.SCLKSW;
+    sysClock = RCM->CFG_B.SCLKSEL;
 
     switch (sysClock)
     {
-        /** sys clock is HSI */
-        case RCM_SYSCLK_SEL_HSI:
-            sysClock = HSI_VALUE;
-            break;
-
-        /** sys clock is HSE */
-        case RCM_SYSCLK_SEL_HSE:
-            sysClock = HSE_VALUE;
-            break;
-
-        /** sys clock is PLL */
-        case RCM_SYSCLK_SEL_PLL:
-            pllMull = RCM->CFG_B.PLLMULCFG + 2;
-            pllSource = RCM->CFG_B.PLLSRCSEL;
-
-            /** PLL entry clock source is HSE */
-            if (pllSource == BIT_SET)
-            {
-                sysClock = HSE_VALUE * pllMull;
+    /** sys clock is HSI */
+    case RCM_SYSCLK_SEL_HSI:
+        sysClock = HSI_VALUE;
+        break;
+
+    /** sys clock is HSE */
+    case RCM_SYSCLK_SEL_HSE:
+        sysClock = HSE_VALUE;
+        break;
+
+    /** sys clock is PLL */
+    case RCM_SYSCLK_SEL_PLL:
+        pllMull = RCM->CFG_B.PLLMULCFG + 2;
+        pllSource = RCM->CFG_B.PLLSRCSEL;
+
+        /** PLL entry clock source is HSE */
+        if (pllSource == BIT_SET)
+        {
+            sysClock = HSE_VALUE * pllMull;
 
-                /** HSE clock divided by 2 */
-                if (pllSource == RCM->CFG_B.PLLHSEPSC)
-                {
-                    sysClock >>= 1;
-                }
-            }
-            /** PLL entry clock source is HSI/2 */
-            else
+            /** HSE clock divided by 2 */
+            if (pllSource == RCM->CFG_B.PLLHSEPSC)
             {
-                sysClock = (HSI_VALUE >> 1) * pllMull;
+                sysClock >>= 1;
             }
+        }
+        /** PLL entry clock source is HSI/2 */
+        else
+        {
+            sysClock = (HSI_VALUE >> 1) * pllMull;
+        }
 
-            break;
+        break;
 
-        default:
-            sysClock  = HSI_VALUE;
-            break;
+    default:
+        sysClock  = HSI_VALUE;
+        break;
     }
 
     return sysClock;
@@ -557,7 +561,7 @@ uint32_t RCM_ReadHCLKFreq(void)
  *
  * @retval    None
  */
-void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2)
+void RCM_ReadPCLKFreq(uint32_t *PCLK1, uint32_t *PCLK2)
 {
     uint32_t hclk, divider;
     uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
@@ -897,7 +901,6 @@ void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph)
  *
  * @retval    None
  *
- * @note
  */
 void RCM_EnableBackupReset(void)
 {
@@ -948,7 +951,7 @@ void RCM_EnableInterrupt(uint32_t interrupt)
  *                        @arg RCM_INT_HSIRDY : HSI ready interrupt
  *                        @arg RCM_INT_HSERDY : HSE ready interrupt
  *                        @arg RCM_INT_PLLRDY : PLL ready interrupt
-RCM_DisableInterrupt(RCM_INT_LSIRDY) *
+ *
  * @retval    None
  */
 void RCM_DisableInterrupt(uint32_t interrupt)
@@ -989,20 +992,20 @@ uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag)
 
     switch (reg)
     {
-        case 0:
-            reg = RCM->CTRL;
-            break;
+    case 0:
+        reg = RCM->CTRL;
+        break;
 
-        case 1:
-            reg = RCM->BDCTRL;
-            break;
+    case 1:
+        reg = RCM->BDCTRL;
+        break;
 
-        case 2:
-            reg = RCM->CSTS;
-            break;
+    case 2:
+        reg = RCM->CSTS;
+        break;
 
-        default:
-            break;
+    default:
+        break;
     }
 
     if (reg & bit)
@@ -1032,7 +1035,7 @@ void RCM_ClearStatusFlag(void)
 /*!
  * @brief     Reads the specified RCM interrupt Flag
  *
- * @param     flag : Reads specifies RCM interrupt flag.
+ * @param     flag ：Reads specifies RCM interrupt flag.
  *                   This parameter can be one of the following values:
  *                   @arg RCM_INT_LSIRDY : LSI ready interrupt flag
  *                   @arg RCM_INT_LSERDY : LSE ready interrupt flag
@@ -1045,11 +1048,7 @@ void RCM_ClearStatusFlag(void)
  */
 uint8_t RCM_ReadIntFlag(RCM_INT_T flag)
 {
-    uint8_t ret;
-
-    ret = (RCM->INT& flag) ? SET : RESET;
-
-    return  ret;
+    return (RCM->INT &flag) ? SET : RESET;
 }
 
 /*!

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c

@@ -1,12 +1,26 @@
 /*!
- * @file       apm32f10x_rtc.c
+ * @file        apm32f10x_rtc.c
  *
- * @brief      This file provides all the RTC firmware functions
+ * @brief       This file provides all the RTC firmware functions
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 #include "apm32f10x_rtc.h"
 
@@ -55,7 +69,10 @@ void RTC_DisableConfigMode(void)
  */
 uint32_t RTC_ReadCounter(void)
 {
-    return (((RTC->CNTH_B.CNTH) << 16) | (RTC->CNTL_B.CNTL));
+    uint32_t reg = 0;
+    reg = (RTC->CNTH_B.CNTH) << 16;
+    reg |= (RTC->CNTL_B.CNTL);
+    return (reg);
 }
 
 /*!
@@ -112,7 +129,10 @@ void RTC_ConfigAlarm(uint32_t value)
  */
 uint32_t RTC_ReadDivider(void)
 {
-    return ((RTC->PSCH_B.PSCH & 0x000F) << 16 ) | (RTC->PSCL_B.PSCL);
+    uint32_t reg = 0;
+    reg = (RTC->PSCH_B.PSCH & 0x000F) << 16;
+    reg |= (RTC->PSCL_B.PSCL);
+    return (reg);
 }
 
 /*!
@@ -124,7 +144,7 @@ uint32_t RTC_ReadDivider(void)
  */
 void RTC_WaitForLastTask(void)
 {
-    while(RTC->CSTS_B.OCFLG == BIT_RESET)
+    while (RTC->CSTS_B.OCFLG == BIT_RESET)
     {
     }
 }
@@ -139,17 +159,17 @@ void RTC_WaitForLastTask(void)
 void RTC_WaitForSynchor(void)
 {
     RTC->CSTS_B.RSYNCFLG = BIT_RESET;
-    while(RTC->CSTS_B.RSYNCFLG == BIT_RESET)
-    {
-    }
+    while (RTC->CSTS_B.RSYNCFLG == BIT_RESET);
 }
 
 /*!
  * @brief     Enable RTC interrupts.
  *
- * @param     interrupt: RTC interrupt
- *
- * @retval    None
+ * @param     interrupt: specifies the RTC interrupt sources to be enabled
+ *                  This parameter can be any combination of the following values:
+ *                  @arg RTC_INT_OVR : Overflow interrupt
+ *                  @arg RTC_INT_ALR : Alarm interrupt
+ *                  @arg RTC_INT_SEC : Second interrupt
  */
 void RTC_EnableInterrupt(uint16_t interrupt)
 {
@@ -159,31 +179,45 @@ void RTC_EnableInterrupt(uint16_t interrupt)
 /*!
  * @brief     Disable RTC interrupts.
  *
- * @param     interrupt: RTC interrupt
+ * @param     interrupt: specifies the RTC interrupt sources to be disabled
+ *                  This parameter can be any combination of the following values:
+ *                  @arg RTC_INT_OVR : Overflow interrupt
+ *                  @arg RTC_INT_ALR : Alarm interrupt
+ *                  @arg RTC_INT_SEC : Second interrupt
  *
  * @retval    None
  */
 void RTC_DisableInterrupt(uint16_t interrupt)
 {
-    RTC->CTRL &= (uint32_t )~interrupt;
+    RTC->CTRL &= (uint32_t)~interrupt;
 }
 
 /*!
  * @brief     Read flag bit
  *
- * @param     flag: Flags to read
+ * @param     flag: specifies the flag to check.
+ *                  This parameter can be one of the following values:
+ *                  @arg RTC_FLAG_OC   : RTC Operation Complete flag
+ *                  @arg RTC_FLAG_RSYNC: Registers Synchronized flag
+ *                  @arg RTC_FLAG_OVR  : Overflow flag
+ *                  @arg RTC_FLAG_ALR  : Alarm flag
+ *                  @arg RTC_FLAG_SEC  : Second flag
  *
- * @retval    flag bit
+ * @retval    SET or RESET
  */
 uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag)
 {
-    return  (RTC->CSTS & flag) ? SET : RESET;
+    return (RTC->CSTS & flag) ? SET : RESET;
 }
 
 /*!
  * @brief     Clear flag bit
  *
- * @param     flag: Flags to clear
+ * @param     flag: specifies the flag to clear.
+ *                  This parameter can be any combination of the following values:
+ *                  @arg RTC_FLAG_OVR : Overflow flag
+ *                  @arg RTC_FLAG_ALR : Alarm flag
+ *                  @arg RTC_FLAG_SEC : Second flag
  *
  * @retval    None
  */
@@ -195,7 +229,11 @@ void RTC_ClearStatusFlag(uint16_t flag)
 /*!
  * @brief     Read interrupt flag bit is set
  *
- * @param     flag:Flag bit to check
+ * @param     flag: specifies the flag to check.
+ *                  This parameter can be any combination of the following values:
+ *                  @arg RTC_INT_OVR : Overflow interrupt
+ *                  @arg RTC_INT_ALR : Alarm interrupt
+ *                  @arg RTC_INT_SEC : Second interrupt
  *
  * @retval    None
  */
@@ -207,7 +245,11 @@ uint8_t RTC_ReadIntFlag(RTC_INT_T flag)
 /*!
  * @brief     Clear RTC interrupt flag bit
  *
- * @param     flag: Clears the specified interrupt flag bit
+ * @param     flag: specifies the flag to clear.
+ *                  This parameter can be one of the following values:
+ *                  @arg RTC_INT_OVR : Overflow interrupt
+ *                  @arg RTC_INT_ALR : Alarm interrupt
+ *                  @arg RTC_INT_SEC : Second interrupt
  *
  * @retval    None
  */

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c

@@ -3,10 +3,24 @@
  *
  * @brief       This file contains all the functions for the SCI2C peripheral
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_sci2c.h"
@@ -33,7 +47,7 @@
  */
 void SCI2C_Reset(SCI2C_T *i2c)
 {
-    if(i2c == I2C3)
+    if (i2c == I2C3)
     {
         RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1);
         RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1);
@@ -64,7 +78,7 @@ void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig)
 
     i2c->CTRL2_B.I2CEN = BIT_RESET;
 
-    if(sci2cConfig->mode == SCI2C_MODE_MASTER)
+    if (sci2cConfig->mode == SCI2C_MODE_MASTER)
     {
         i2c->CTRL1_B.MST = BIT_SET;
         i2c->CTRL1_B.SLADIS = BIT_SET;
@@ -84,17 +98,17 @@ void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig)
     i2c->CTRL1_B.SAM = sci2cConfig->addrMode;
     i2c->SLAADDR = sci2cConfig->slaveAddr;
 
-    if(sci2cConfig->speed == SCI2C_SPEED_STANDARD)
+    if (sci2cConfig->speed == SCI2C_SPEED_STANDARD)
     {
         i2c->SSCLC = sci2cConfig->clkLowPeriod;
         i2c->SSCHC = sci2cConfig->clkHighPeriod;
     }
-    else if(sci2cConfig->speed == SCI2C_SPEED_FAST)
+    else if (sci2cConfig->speed == SCI2C_SPEED_FAST)
     {
         i2c->FSCLC = sci2cConfig->clkLowPeriod;
         i2c->FSCHC = sci2cConfig->clkHighPeriod;
     }
-    else if(sci2cConfig->speed == SCI2C_SPEED_HIGH)
+    else if (sci2cConfig->speed == SCI2C_SPEED_HIGH)
     {
         i2c->HSCLC = sci2cConfig->clkLowPeriod;
         i2c->HSCHC = sci2cConfig->clkHighPeriod;
@@ -145,7 +159,7 @@ uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag)
 {
     uint8_t ret = RESET;
 
-    if(flag & BIT8)
+    if (flag & BIT8)
     {
         ret = i2c->STS2 & flag ? SET : RESET;
     }
@@ -214,47 +228,47 @@ void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag)
 {
     volatile uint32_t dummy = 0;
 
-    if(flag == SCI2C_INT_ALL)
+    if (flag == SCI2C_INT_ALL)
     {
         dummy = i2c->INTCLR;
     }
-    else if(flag == SCI2C_INT_RFU)
+    else if (flag == SCI2C_INT_RFU)
     {
         dummy = i2c->RFUIC;
     }
-    else if(flag == SCI2C_INT_RFO)
+    else if (flag == SCI2C_INT_RFO)
     {
         dummy = i2c->RFOIC;
     }
-    else if(flag == SCI2C_INT_TFO)
+    else if (flag == SCI2C_INT_TFO)
     {
         dummy = i2c->TFOIC;
     }
-    else if(flag == SCI2C_INT_RR)
+    else if (flag == SCI2C_INT_RR)
     {
         dummy = i2c->RRIC;
     }
-    else if(flag == SCI2C_INT_TA)
+    else if (flag == SCI2C_INT_TA)
     {
         dummy = i2c->TAIC;
     }
-    else if(flag == SCI2C_INT_RD)
+    else if (flag == SCI2C_INT_RD)
     {
         dummy = i2c->RDIC;
     }
-    else if(flag == SCI2C_INT_ACT)
+    else if (flag == SCI2C_INT_ACT)
     {
         dummy = i2c->AIC;
     }
-    else if(flag == SCI2C_INT_STPD)
+    else if (flag == SCI2C_INT_STPD)
     {
         dummy = i2c->STPDIC;
     }
-    else if(flag == SCI2C_INT_STAD)
+    else if (flag == SCI2C_INT_STAD)
     {
         dummy = i2c->STADIC;
     }
-    else if(flag == SCI2C_INT_GC)
+    else if (flag == SCI2C_INT_GC)
     {
         dummy = i2c->GCIC;
     }
@@ -442,7 +456,7 @@ void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed)
  *                      @arg SCI2C_ADDR_MODE_10BIT:     10-bit address mode.
  *
  * @param       addr:   Specifies the address.
-
+ *
  * @retval      None
  */
 void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr)
@@ -462,7 +476,7 @@ void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr)
  *                      @arg SCI2C_ADDR_MODE_10BIT:     10-bit address mode.
  *
  * @param       addr:   Specifies the address.
-
+ *
  * @retval      None
  */
 void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr)
@@ -570,7 +584,6 @@ void SCI2C_TxData(SCI2C_T *i2c, uint8_t data)
  *
  * @retval      Received data
  *
- * @note
  */
 uint8_t SCI2C_RxData(SCI2C_T *i2c)
 {
@@ -718,17 +731,17 @@ void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable)
  */
 void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod)
 {
-    if(speed == SCI2C_SPEED_STANDARD)
+    if (speed == SCI2C_SPEED_STANDARD)
     {
         i2c->SSCLC = lowPeriod;
         i2c->SSCHC = highPeriod;
     }
-    else if(speed == SCI2C_SPEED_FAST)
+    else if (speed == SCI2C_SPEED_FAST)
     {
         i2c->FSCLC = lowPeriod;
         i2c->FSCHC = highPeriod;
     }
-    else if(speed == SCI2C_SPEED_HIGH)
+    else if (speed == SCI2C_SPEED_HIGH)
     {
         i2c->HSCLC = lowPeriod;
         i2c->HSCHC = highPeriod;
@@ -882,7 +895,7 @@ void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt)
  */
 void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit)
 {
-    if(speed == SCI2C_SPEED_HIGH)
+    if (speed == SCI2C_SPEED_HIGH)
     {
         i2c->HSSSL = limit;
     }
@@ -895,4 +908,3 @@ void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_
 /**@} end of group SCI2C_Fuctions*/
 /**@} end of group SCI2C_Driver*/
 /**@} end of group Peripherals_Library*/
-

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c

@@ -1,12 +1,26 @@
 /*!
- * @file       apm32f10x_sdio.c
+ * @file        apm32f10x_sdio.c
  *
- * @brief      This file provides all the SDIO firmware functions
+ * @brief       This file provides all the SDIO firmware functions
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_sdio.h"
@@ -51,7 +65,7 @@ void SDIO_Reset(void)
  *
  * @retval       None
  */
-void SDIO_Config(SDIO_Config_T* sdioConfig)
+void SDIO_Config(SDIO_Config_T *sdioConfig)
 {
     uint32_t tmp = 0;
 
@@ -59,7 +73,7 @@ void SDIO_Config(SDIO_Config_T* sdioConfig)
     tmp &= 0xFFFF8100;
 
     tmp |= (sdioConfig->clockDiv  | sdioConfig->clockPowerSave | sdioConfig->clockBypass | sdioConfig->busWide |
-    sdioConfig->clockEdge | sdioConfig->hardwareFlowControl);
+            sdioConfig->clockEdge | sdioConfig->hardwareFlowControl);
 
     SDIO->CLKCTRL = tmp;
 }
@@ -71,14 +85,14 @@ void SDIO_Config(SDIO_Config_T* sdioConfig)
  *
  * @retval       None
  */
-void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig)
+void SDIO_ConfigStructInit(SDIO_Config_T *sdioConfig)
 {
-  sdioConfig->clockDiv = 0x00;
-  sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING;
-  sdioConfig->clockBypass = SDIO_CLOCK_BYPASS_DISABLE;
-  sdioConfig->clockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
-  sdioConfig->busWide = SDIO_BUSWIDE_1B;
-  sdioConfig->hardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+    sdioConfig->clockDiv = 0x00;
+    sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING;
+    sdioConfig->clockBypass = SDIO_CLOCK_BYPASS_DISABLE;
+    sdioConfig->clockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
+    sdioConfig->busWide = SDIO_BUS_WIDE_1B;
+    sdioConfig->hardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
 }
 
 /*!
@@ -161,13 +175,12 @@ void SDIO_DisableDMA(void)
 /*!
  * @brief        Configs the SDIO Command and send the command
  *
- * @param        cmdConfig: pointer to a SDIO_CMDConfig_T structure
+ * @param        cmdConfig: pointer to a SDIO_CmdConfig_T structure
  *
  * @retval       None
  *
- * @note
  */
-void SDIO_TxCommand(SDIO_CMDConfig_T *cmdConfig)
+void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig)
 {
     uint32_t tmpreg = 0;
 
@@ -175,26 +188,25 @@ void SDIO_TxCommand(SDIO_CMDConfig_T *cmdConfig)
     tmpreg = SDIO->CMD;
     tmpreg &= 0xFFFFF800;
     tmpreg |= (uint32_t)cmdConfig->cmdIndex | cmdConfig->response
-           | cmdConfig->wait | cmdConfig->CPSM;
+              | cmdConfig->wait | cmdConfig->CPSM;
     SDIO->CMD = tmpreg;
 }
 
 /*!
  * @brief        Fills each SDIO_CMD_ConfigStruct_T member with its default value
  *
- * @param        cmdConfig: pointer to a SDIO_CMDConfig_T structure
+ * @param        cmdConfig: pointer to a SDIO_CmdConfig_T structure
  *
  * @retval       None
  *
- * @note
  */
-void SDIO_TxCommandStructInit(SDIO_CMDConfig_T* cmdConfig)
+void SDIO_TxCommandStructInit(SDIO_CmdConfig_T *cmdConfig)
 {
-  cmdConfig->argument = 0x00;
-  cmdConfig->cmdIndex = 0x00;
-  cmdConfig->response = SDIO_RESPONSE_NO;
-  cmdConfig->wait = SDIO_WAIT_NO;
-  cmdConfig->CPSM = SDIO_CPSM_DISABLE;
+    cmdConfig->argument = 0x00;
+    cmdConfig->cmdIndex = 0x00;
+    cmdConfig->response = SDIO_RESPONSE_NO;
+    cmdConfig->wait = SDIO_WAIT_NO;
+    cmdConfig->CPSM = SDIO_CPSM_DISABLE;
 }
 
 /*!
@@ -204,7 +216,6 @@ void SDIO_TxCommandStructInit(SDIO_CMDConfig_T* cmdConfig)
  *
  * @retval       The command index of the last command response received
  *
- * @note
  */
 uint8_t SDIO_ReadCommandResponse(void)
 {
@@ -225,11 +236,11 @@ uint8_t SDIO_ReadCommandResponse(void)
  */
 uint32_t SDIO_ReadResponse(SDIO_RES_T res)
 {
-  __IO uint32_t tmp = 0;
+    __IO uint32_t tmp = 0;
 
-  tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res;
+    tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res;
 
-  return (*(__IO uint32_t *) tmp);
+    return (*(__IO uint32_t *) tmp);
 }
 
 /*!
@@ -239,7 +250,7 @@ uint32_t SDIO_ReadResponse(SDIO_RES_T res)
  *
  * @retval       None
  */
-void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig)
+void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig)
 {
     uint32_t tmpreg = 0;
 
@@ -252,7 +263,7 @@ void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig)
     tmpreg &= 0xFFFFFF08;
 
     tmpreg |= (uint32_t)dataConfig->dataBlockSize | dataConfig->transferDir
-           | dataConfig->transferMode | dataConfig->DPSM;
+              | dataConfig->transferMode | dataConfig->DPSM;
 
     SDIO->DCTRL = tmpreg;
 }
@@ -264,14 +275,14 @@ void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig)
  *
  * @retval       None
  */
-void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig)
+void SDIO_ConfigDataStructInit(SDIO_DataConfig_T *dataConfig)
 {
-  dataConfig->dataTimeOut = 0xFFFFFFFF;
-  dataConfig->dataLength = 0x00;
-  dataConfig->dataBlockSize = SDIO_DATA_BLOCKSIZE_1B;
-  dataConfig->transferDir = SDIO_TRANSFER_DIR_TOCARD;
-  dataConfig->transferMode = SDIO_TRANSFER_MODE_BLOCK;
-  dataConfig->DPSM = SDIO_DPSM_DISABLE;
+    dataConfig->dataTimeOut = 0xFFFFFFFF;
+    dataConfig->dataLength = 0x00;
+    dataConfig->dataBlockSize = SDIO_DATA_BLOCKSIZE_1B;
+    dataConfig->transferDir = SDIO_TRANSFER_DIR_TO_CARD;
+    dataConfig->transferMode = SDIO_TRANSFER_MODE_BLOCK;
+    dataConfig->DPSM = SDIO_DPSM_DISABLE;
 }
 
 /*!
@@ -289,7 +300,7 @@ uint32_t SDIO_ReadDataCounter(void)
 /*!
  * @brief       Write the SDIO Data
  *
- * @param       Data : Write 32-bit data
+ * @param       Data：Write 32-bit data
  *
  * @retval      None
  */
@@ -380,11 +391,10 @@ void SDIO_DisableStartReadWait(void)
  *
  * @retval       None
  *
- * @note
  */
 void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode)
 {
-  *(__IO uint32_t *) DCTRL_RDWAIT_BB = readWaitMode;
+    *(__IO uint32_t *) DCTRL_RDWAIT_BB = readWaitMode;
 }
 /*!
  * @brief        Enables SDIO SD I/O Mode Operation
@@ -395,7 +405,7 @@ void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode)
  */
 void SDIO_EnableSDIO(void)
 {
-  *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)SET;
+    *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)SET;
 }
 
 /*!
@@ -407,7 +417,7 @@ void SDIO_EnableSDIO(void)
  */
 void SDIO_DisableSDIO(void)
 {
-  *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)RESET;
+    *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)RESET;
 }
 
 /*!
@@ -612,17 +622,7 @@ void SDIO_DisableInterrupt(uint32_t interrupt)
  */
 uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag)
 {
-    uint8_t bitstatus = RESET;
-
-    if ((SDIO->STS & flag) != (uint32_t)RESET)
-    {
-        bitstatus = SET;
-    }
-    else
-    {
-        bitstatus = RESET;
-    }
-    return bitstatus;
+    return (SDIO->STS & flag) ? SET : RESET;
 }
 
 /*!
@@ -648,7 +648,7 @@ uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag)
  */
 void SDIO_ClearStatusFlag(uint32_t flag)
 {
-  SDIO->ICF = flag;
+    SDIO->ICF = flag;
 }
 
 /*!
@@ -722,7 +722,7 @@ uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag)
  */
 void SDIO_ClearIntFlag(uint32_t flag)
 {
-  SDIO->ICF = flag;
+    SDIO->ICF = flag;
 }
 
 /**@} end of group SDIO_Fuctions*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c

@@ -3,10 +3,24 @@
  *
  * @brief       This file provides all the SPI firmware functions
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_spi.h"
@@ -31,19 +45,19 @@
  *
  * @retval    None
  */
-void SPI_I2S_Reset(SPI_T* spi)
+void SPI_I2S_Reset(SPI_T *spi)
 {
-    if(spi == SPI1)
+    if (spi == SPI1)
     {
         RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1);
         RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1);
     }
-    else if(spi == SPI2)
+    else if (spi == SPI2)
     {
         RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2);
         RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2);
     }
-    else if(spi == SPI3)
+    else if (spi == SPI3)
     {
         RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI3);
         RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI3);
@@ -59,13 +73,13 @@ void SPI_I2S_Reset(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig)
+void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig)
 {
     spi->CTRL1 &= 0x3040;
     spi->CTRL1 |= (uint16_t)((uint32_t)spiConfig->direction | spiConfig->mode |
-                   spiConfig->length | spiConfig->polarity |
-                   spiConfig->phase | spiConfig->nss |
-                   spiConfig->baudrateDiv | spiConfig->firstBit);
+                             spiConfig->length | spiConfig->polarity |
+                             spiConfig->phase | spiConfig->nss |
+                             spiConfig->baudrateDiv | spiConfig->firstBit);
     spi->CRCPOLY = spiConfig->crcPolynomial;
 }
 
@@ -78,24 +92,24 @@ void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig)
  *
  * @retval    None
  */
-void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig)
+void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig)
 {
     uint16_t i2sDiv = 2, i2sOdd = 0, packetSize = 1;
     uint32_t tmp = 0;
     uint32_t sysClock = 0;
 
-  /* Clear MODESEL, I2SEN, I2SMOD, PFSSEL, I2SSSEL, CPOL, DATALEN and CHLEN bits */
+    /** Clear MODESEL, I2SEN, I2SMOD, PFSSEL, I2SSSEL, CPOL, DATALEN and CHLEN bits */
     spi->I2SCFG &= 0xF040;
     spi->I2SPSC = 0x0002;
 
-    if(i2sConfig->audioDiv == I2S_AUDIO_DIV_DEFAULT)
+    if (i2sConfig->audioDiv == I2S_AUDIO_DIV_DEFAULT)
     {
         spi->I2SPSC_B.ODDPSC = 0;
         spi->I2SPSC_B.I2SPSC = 2;
     }
     else
     {
-        if(i2sConfig->length == I2S_DATA_LENGHT_16B)
+        if (i2sConfig->length == I2S_DATA_LENGHT_16B)
         {
             packetSize = 1;
         }
@@ -106,13 +120,13 @@ void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig)
 
         sysClock = RCM_ReadSYSCLKFreq();
 
-        if(i2sConfig->MCLKOutput == I2S_MCLK_OUTPUT_ENABLE)
+        if (i2sConfig->MCLKOutput == I2S_MCLK_OUTPUT_ENABLE)
         {
             tmp = (uint16_t)(((((sysClock / 256) * 10) / i2sConfig ->audioDiv)) + 5);
         }
         else
         {
-            tmp = (uint16_t)(((((sysClock / (32 * packetSize)) *10 ) / i2sConfig ->audioDiv )) + 5);
+            tmp = (uint16_t)(((((sysClock / (32 * packetSize)) * 10) / i2sConfig ->audioDiv)) + 5);
         }
         tmp = tmp / 10;
 
@@ -130,7 +144,10 @@ void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig)
     spi->I2SPSC_B.ODDPSC = i2sOdd;
     spi->I2SPSC |= i2sConfig->MCLKOutput;
 
-    spi->I2SCFG = i2sConfig->mode | i2sConfig->standard | i2sConfig->length | i2sConfig->polarity;
+    spi->I2SCFG = (uint32_t)i2sConfig->mode | \
+                  (uint32_t)i2sConfig->standard | \
+                  (uint32_t)i2sConfig->length | \
+                  (uint32_t)i2sConfig->polarity;
 
     /** select I2S mode */
     spi->I2SCFG_B.MODESEL = BIT_SET;
@@ -143,7 +160,7 @@ void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig)
  *
  * @retval    None
  */
-void SPI_ConfigStructInit(SPI_Config_T* spiConfig)
+void SPI_ConfigStructInit(SPI_Config_T *spiConfig)
 {
     spiConfig->direction = SPI_DIRECTION_2LINES_FULLDUPLEX;
     spiConfig->mode = SPI_MODE_SLAVE;
@@ -163,7 +180,7 @@ void SPI_ConfigStructInit(SPI_Config_T* spiConfig)
  *
  * @retval    None
  */
-void I2S_ConfigStructInit(I2S_Config_T* i2sConfig)
+void I2S_ConfigStructInit(I2S_Config_T *i2sConfig)
 {
     i2sConfig->mode = I2S_MODE_SLAVE_TX;
     i2sConfig->standard = I2S_STANDARD_PHILLIPS;
@@ -179,7 +196,7 @@ void I2S_ConfigStructInit(I2S_Config_T* i2sConfig)
  *
  * @retval    None
  */
-void SPI_Enable(SPI_T* spi)
+void SPI_Enable(SPI_T *spi)
 {
     spi->CTRL1_B.SPIEN = BIT_SET;
 }
@@ -191,7 +208,7 @@ void SPI_Enable(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_Disable(SPI_T* spi)
+void SPI_Disable(SPI_T *spi)
 {
     spi->CTRL1_B.SPIEN = BIT_RESET;
 }
@@ -203,7 +220,7 @@ void SPI_Disable(SPI_T* spi)
  *
  * @retval    None
  */
-void I2S_Enable(SPI_T* spi)
+void I2S_Enable(SPI_T *spi)
 {
     spi->I2SCFG_B.I2SEN = BIT_SET;
 }
@@ -215,7 +232,7 @@ void I2S_Enable(SPI_T* spi)
  *
  * @retval    None
  */
-void I2S_Disable(SPI_T* spi)
+void I2S_Disable(SPI_T *spi)
 {
     spi->I2SCFG_B.I2SEN = BIT_RESET;
 }
@@ -231,9 +248,9 @@ void I2S_Disable(SPI_T* spi)
  *                     @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request
  * @retval    None
  */
-void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
+void SPI_I2S_EnableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq)
 {
-    if(dmaReq == SPI_I2S_DMA_REQ_TX)
+    if (dmaReq == SPI_I2S_DMA_REQ_TX)
     {
         spi->CTRL2_B.TXDEN = ENABLE;
     }
@@ -254,9 +271,9 @@ void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
  *                     @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request
  * @retval    None
  */
-void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
+void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq)
 {
-    if(dmaReq == SPI_I2S_DMA_REQ_TX)
+    if (dmaReq == SPI_I2S_DMA_REQ_TX)
     {
         spi->CTRL2_B.TXDEN = DISABLE;
     }
@@ -275,7 +292,7 @@ void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
  *
  * @retval    None
  */
-void SPI_I2S_TxData(SPI_T* spi, uint16_t data)
+void SPI_I2S_TxData(SPI_T *spi, uint16_t data)
 {
     spi->DATA = data;
 }
@@ -289,7 +306,7 @@ void SPI_I2S_TxData(SPI_T* spi, uint16_t data)
  *
  * @retval    None
  */
-uint16_t SPI_I2S_RxData(SPI_T* spi)
+uint16_t SPI_I2S_RxData(SPI_T *spi)
 {
     return spi->DATA;
 }
@@ -301,7 +318,7 @@ uint16_t SPI_I2S_RxData(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_SetSoftwareNSS(SPI_T* spi)
+void SPI_SetSoftwareNSS(SPI_T *spi)
 {
     spi->CTRL1_B.ISSEL = BIT_SET;
 }
@@ -313,7 +330,7 @@ void SPI_SetSoftwareNSS(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_ResetSoftwareNSS(SPI_T* spi)
+void SPI_ResetSoftwareNSS(SPI_T *spi)
 {
     spi->CTRL1_B.ISSEL = BIT_RESET;
 }
@@ -325,7 +342,7 @@ void SPI_ResetSoftwareNSS(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_EnableSSOutput(SPI_T* spi)
+void SPI_EnableSSOutput(SPI_T *spi)
 {
     spi->CTRL2_B.SSOEN = BIT_SET;
 }
@@ -337,7 +354,7 @@ void SPI_EnableSSOutput(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_DisableSSOutput(SPI_T* spi)
+void SPI_DisableSSOutput(SPI_T *spi)
 {
     spi->CTRL2_B.SSOEN = BIT_RESET;
 }
@@ -347,11 +364,14 @@ void SPI_DisableSSOutput(SPI_T* spi)
  *
  * @param     spi: The SPIx can be 1,2,3
  *
- * @param     length: Select the SPI data Size
+ * @param     length: specifies the SPI data size.
+ *                    This parameter can be one of the following values:
+ *                    @arg SPI_DATA_LENGTH_16B: Set data frame format to 16bit
+ *                    @arg SPI_DATA_LENGTH_8B : Set data frame format to 8bit
  *
  * @retval    None
  */
-void SPI_ConfigDataSize(SPI_T* spi, uint16_t length)
+void SPI_ConfigDataSize(SPI_T *spi, SPI_DATA_LENGTH_T length)
 {
     spi->CTRL1_B.DFLSEL = BIT_RESET;
     spi->CTRL1 |= length;
@@ -364,9 +384,9 @@ void SPI_ConfigDataSize(SPI_T* spi, uint16_t length)
  *
  * @retval    None
  */
-void SPI_TxCRC(SPI_T* spi)
+void SPI_TxCRC(SPI_T *spi)
 {
-    spi->CTRL1_B.CECNXT = BIT_SET;
+    spi->CTRL1_B.CRCNXT = BIT_SET;
 }
 
 /*!
@@ -376,7 +396,7 @@ void SPI_TxCRC(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_EnableCRC(SPI_T* spi)
+void SPI_EnableCRC(SPI_T *spi)
 {
     spi->CTRL1_B.CRCEN = BIT_SET;
 }
@@ -387,7 +407,7 @@ void SPI_EnableCRC(SPI_T* spi)
  * @param     spi: The SPIx can be 1,2,3
  *
  */
-void SPI_DisableCRC(SPI_T* spi)
+void SPI_DisableCRC(SPI_T *spi)
 {
     spi->CTRL1_B.CRCEN = BIT_RESET;
 }
@@ -399,7 +419,7 @@ void SPI_DisableCRC(SPI_T* spi)
  *
  * @retval    The SPI transmit CRC register value
  */
-uint16_t SPI_ReadTxCRC(SPI_T* spi)
+uint16_t SPI_ReadTxCRC(SPI_T *spi)
 {
     return spi->TXCRC_B.TXCRC;
 }
@@ -411,7 +431,7 @@ uint16_t SPI_ReadTxCRC(SPI_T* spi)
  *
  * @retval    The SPI receive CRC register value
  */
-uint16_t SPI_ReadRxCRC(SPI_T* spi)
+uint16_t SPI_ReadRxCRC(SPI_T *spi)
 {
     return spi->RXCRC_B.RXCRC;
 }
@@ -423,7 +443,7 @@ uint16_t SPI_ReadRxCRC(SPI_T* spi)
  *
  * @retval    The SPI CRC Polynomial register value
  */
-uint16_t SPI_ReadCRCPolynomial(SPI_T* spi)
+uint16_t SPI_ReadCRCPolynomial(SPI_T *spi)
 {
     return spi->CRCPOLY_B.CRCPOLY;
 }
@@ -439,9 +459,9 @@ uint16_t SPI_ReadCRCPolynomial(SPI_T* spi)
  *                     @arg SPI_DIRECTION_TX: Selects Tx transmission direction
  * @retval    None
  */
-void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction)
+void SPI_ConfigBiDirectionalLine(SPI_T *spi, SPI_DIRECTION_SELECT_T direction)
 {
-    if(direction == SPI_DIRECTION_TX)
+    if (direction == SPI_DIRECTION_TX)
     {
         spi->CTRL1 |= SPI_DIRECTION_TX;
     }
@@ -463,9 +483,9 @@ void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction)
  *                     @arg SPI_I2S_INT_ERR: Error interrupt
  * @retval       None
  */
-void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt)
+void SPI_I2S_EnableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt)
 {
-     spi->CTRL2 |= (interrupt >> 8);
+    spi->CTRL2 |= (interrupt >> 8);
 }
 
 /*!
@@ -480,9 +500,9 @@ void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt)
  *                     @arg SPI_I2S_INT_ERR: Error interrupt
  * @retval    None
  */
-void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt)
+void SPI_I2S_DisableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt)
 {
-         spi->CTRL2 &= ~(interrupt >> 8);
+    spi->CTRL2 &= ~(interrupt >> 8);
 }
 
 /*!
@@ -503,9 +523,9 @@ void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt)
  *
  * @retval     SET or RESET
  */
-uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
+uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag)
 {
-    if((spi->STS & flag) != RESET)
+    if ((spi->STS & flag) != RESET)
     {
         return SET;
     }
@@ -533,7 +553,7 @@ uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
  *              a read/write operation to SPI_STS register (SPI_I2S_ReadStatusFlag())
  *              followed by a write operation to SPI_CTRL1 register (SPI_Enable()).
  */
-void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
+void SPI_I2S_ClearStatusFlag(SPI_T *spi, SPI_FLAG_T flag)
 {
     spi->STS_B.CRCEFLG = BIT_RESET;
 }
@@ -554,12 +574,12 @@ void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
  *
  * @retval       SET or RESET
  */
-uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag)
+uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag)
 {
     uint32_t intEnable;
     uint32_t intStatus;
 
-    intEnable = (uint32_t)(spi->CTRL2 & (flag>>8));
+    intEnable = (uint32_t)(spi->CTRL2 & (flag >> 8));
     intStatus = (uint32_t)(spi->STS & flag);
 
     if (intEnable && intStatus)
@@ -588,7 +608,7 @@ uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag)
  *              a read/write operation to SPI_STS register (SPI_I2S_ReadIntFlag())
  *              followed by a write operation to SPI_CTRL1 register (SPI_Enable()).
  */
-void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag)
+void SPI_I2S_ClearIntFlag(SPI_T *spi, SPI_I2S_INT_T flag)
 {
     spi->STS_B.CRCEFLG = BIT_RESET;
 }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c

@@ -1,12 +1,26 @@
 /*!
- * @file       apm32f10x_usart.c
+ * @file        apm32f10x_usart.c
  *
- * @brief      This file provides all the USART firmware functions
+ * @brief       This file provides all the USART firmware functions
  *
- * @version    V1.0.1
+ * @version     V1.0.2
  *
- * @date       2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_usart.h"
@@ -33,7 +47,7 @@
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_Reset(USART_T* usart)
+void USART_Reset(USART_T *usart)
 {
     if (USART1 == usart)
     {
@@ -73,13 +87,15 @@ void USART_Reset(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_Config(USART_T* uart, USART_Config_T* usartConfig)
+void USART_Config(USART_T *uart, USART_Config_T *usartConfig)
 {
     uint32_t temp, fCLK, intDiv, fractionalDiv;
 
     temp = uart->CTRL1;
     temp &= 0xE9F3;
-    temp |= usartConfig->mode | usartConfig->parity | usartConfig->wordLength;
+    temp |= (uint32_t)usartConfig->mode | \
+            (uint32_t)usartConfig->parity | \
+            (uint32_t)usartConfig->wordLength;
     uart->CTRL1 = temp;
 
     temp = uart->CTRL2;
@@ -116,7 +132,7 @@ void USART_Config(USART_T* uart, USART_Config_T* usartConfig)
  *
  * @retval    None
  */
-void USART_ConfigStructInit(USART_Config_T* usartConfig)
+void USART_ConfigStructInit(USART_Config_T *usartConfig)
 {
     usartConfig->baudRate = 9600;
     usartConfig->wordLength = USART_WORD_LEN_8B;
@@ -137,7 +153,7 @@ void USART_ConfigStructInit(USART_Config_T* usartConfig)
  *
  * @note      The usart can be USART1, USART2, USART3
  */
-void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig)
+void USART_ConfigClock(USART_T *usart, USART_ClockConfig_T *clockConfig)
 {
     usart->CTRL2_B.CLKEN   = clockConfig->clock;
     usart->CTRL2_B.CPHA    = clockConfig->phase;
@@ -152,9 +168,8 @@ void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig)
  *
  * @retval    None
  *
- * @note
  */
-void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig)
+void USART_ConfigClockStructInit(USART_ClockConfig_T *clockConfig)
 {
     clockConfig->clock     = USART_CLKEN_DISABLE;
     clockConfig->phase     = USART_CLKPHA_1EDGE;
@@ -171,7 +186,7 @@ void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_Enable(USART_T* usart)
+void USART_Enable(USART_T *usart)
 {
     usart->CTRL1_B.UEN = BIT_SET;
 }
@@ -185,7 +200,7 @@ void USART_Enable(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_Disable(USART_T* usart)
+void USART_Disable(USART_T *usart)
 {
     usart->CTRL1_B.UEN = BIT_RESET;
 }
@@ -205,7 +220,7 @@ void USART_Disable(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq)
+void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq)
 {
     usart->CTRL3 |= dmaReq;
 }
@@ -225,7 +240,7 @@ void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq)
+void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq)
 {
     usart->CTRL3 &= (uint32_t)~dmaReq;
 }
@@ -241,7 +256,7 @@ void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_Address(USART_T* usart, uint8_t address)
+void USART_Address(USART_T *usart, uint8_t address)
 {
     usart->CTRL2_B.ADDR = address;
 }
@@ -260,7 +275,7 @@ void USART_Address(USART_T* usart, uint8_t address)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup)
+void USART_ConfigWakeUp(USART_T *usart, USART_WAKEUP_T wakeup)
 {
     usart->CTRL1_B.WUPMCFG = wakeup;
 }
@@ -274,7 +289,7 @@ void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableMuteMode(USART_T* usart)
+void USART_EnableMuteMode(USART_T *usart)
 {
     usart->CTRL1_B.RXMUTEEN = BIT_SET;
 }
@@ -288,7 +303,7 @@ void USART_EnableMuteMode(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableMuteMode(USART_T* usart)
+void USART_DisableMuteMode(USART_T *usart)
 {
     usart->CTRL1_B.RXMUTEEN = BIT_RESET;
 }
@@ -307,7 +322,7 @@ void USART_DisableMuteMode(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length)
+void USART_ConfigLINBreakDetectLength(USART_T *usart, USART_LBDL_T length)
 {
     usart->CTRL2_B.LBDLCFG = length;
 }
@@ -321,7 +336,7 @@ void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableLIN(USART_T* usart)
+void USART_EnableLIN(USART_T *usart)
 {
     usart->CTRL2_B.LINMEN = BIT_SET;
 }
@@ -335,7 +350,7 @@ void USART_EnableLIN(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableLIN(USART_T* usart)
+void USART_DisableLIN(USART_T *usart)
 {
     usart->CTRL2_B.LINMEN = BIT_RESET;
 }
@@ -349,7 +364,7 @@ void USART_DisableLIN(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableTx(USART_T* usart)
+void USART_EnableTx(USART_T *usart)
 {
     usart->CTRL1_B.TXEN = BIT_SET;
 }
@@ -363,7 +378,7 @@ void USART_EnableTx(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableTx(USART_T* usart)
+void USART_DisableTx(USART_T *usart)
 {
     usart->CTRL1_B.TXEN = BIT_RESET;
 }
@@ -377,7 +392,7 @@ void USART_DisableTx(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableRx(USART_T* usart)
+void USART_EnableRx(USART_T *usart)
 {
     usart->CTRL1_B.RXEN = BIT_SET;
 }
@@ -391,7 +406,7 @@ void USART_EnableRx(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableRx(USART_T* usart)
+void USART_DisableRx(USART_T *usart)
 {
     usart->CTRL1_B.RXEN = BIT_RESET;
 }
@@ -407,7 +422,7 @@ void USART_DisableRx(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_TxData(USART_T* usart, uint16_t data)
+void USART_TxData(USART_T *usart, uint16_t data)
 {
     usart->DATA_B.DATA = data;
 }
@@ -421,7 +436,7 @@ void USART_TxData(USART_T* usart, uint16_t data)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-uint16_t USART_RxData(USART_T* usart)
+uint16_t USART_RxData(USART_T *usart)
 {
     return (uint16_t)(usart->DATA_B.DATA);
 }
@@ -435,7 +450,7 @@ uint16_t USART_RxData(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_TxBreak(USART_T* usart)
+void USART_TxBreak(USART_T *usart)
 {
     usart->CTRL1_B.TXBF = BIT_SET;
 }
@@ -451,7 +466,7 @@ void USART_TxBreak(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3
  */
-void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime)
+void USART_ConfigGuardTime(USART_T *usart, uint8_t guardTime)
 {
     usart->GTPSC_B.GRDT = guardTime;
 }
@@ -467,7 +482,7 @@ void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime)
  *
  * @note      The usart can be USART1, USART2, USART3
  */
-void USART_ConfigPrescaler(USART_T* usart, uint8_t div)
+void USART_ConfigPrescaler(USART_T *usart, uint8_t div)
 {
     usart->GTPSC_B.PSC = div;
 }
@@ -481,7 +496,7 @@ void USART_ConfigPrescaler(USART_T* usart, uint8_t div)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_EnableSmartCard(USART_T* usart)
+void USART_EnableSmartCard(USART_T *usart)
 {
     usart->CTRL3_B.SCEN = BIT_SET;
 }
@@ -495,7 +510,7 @@ void USART_EnableSmartCard(USART_T* usart)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_DisableSmartCard(USART_T* usart)
+void USART_DisableSmartCard(USART_T *usart)
 {
     usart->CTRL3_B.SCEN = BIT_RESET;
 }
@@ -509,7 +524,7 @@ void USART_DisableSmartCard(USART_T* usart)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_EnableSmartCardNACK(USART_T* usart)
+void USART_EnableSmartCardNACK(USART_T *usart)
 {
     usart->CTRL3_B.SCNACKEN = BIT_SET;
 }
@@ -523,7 +538,7 @@ void USART_EnableSmartCardNACK(USART_T* usart)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_DisableSmartCardNACK(USART_T* usart)
+void USART_DisableSmartCardNACK(USART_T *usart)
 {
     usart->CTRL3_B.SCNACKEN = BIT_RESET;
 }
@@ -537,7 +552,7 @@ void USART_DisableSmartCardNACK(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableHalfDuplex(USART_T* usart)
+void USART_EnableHalfDuplex(USART_T *usart)
 {
     usart->CTRL3_B.HDEN = BIT_SET;
 }
@@ -551,7 +566,7 @@ void USART_EnableHalfDuplex(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableHalfDuplex(USART_T* usart)
+void USART_DisableHalfDuplex(USART_T *usart)
 {
     usart->CTRL3_B.HDEN = BIT_RESET;
 }
@@ -569,7 +584,7 @@ void USART_DisableHalfDuplex(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode)
+void USART_ConfigIrDA(USART_T *usart, USART_IRDALP_T IrDAMode)
 {
     usart->CTRL3_B.IRLPEN = IrDAMode;
 }
@@ -583,7 +598,7 @@ void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableIrDA(USART_T* usart)
+void USART_EnableIrDA(USART_T *usart)
 {
     usart->CTRL3_B.IREN = BIT_SET;
 }
@@ -597,7 +612,7 @@ void USART_EnableIrDA(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableIrDA(USART_T* usart)
+void USART_DisableIrDA(USART_T *usart)
 {
     usart->CTRL3_B.IREN = BIT_RESET;
 }
@@ -622,23 +637,23 @@ void USART_DisableIrDA(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt)
+void USART_EnableInterrupt(USART_T *usart, USART_INT_T interrupt)
 {
     uint32_t temp;
 
     temp = (uint32_t)(interrupt & 0xffff);
 
-    if (interrupt & 0X10000)
+    if (interrupt & 0x10000)
     {
         usart->CTRL1 |= temp;
     }
 
-    if (interrupt & 0X20000)
+    if (interrupt & 0x20000)
     {
         usart->CTRL2 |= temp;
     }
 
-    if (interrupt & 0X40000)
+    if (interrupt & 0x40000)
     {
         usart->CTRL3 |= temp;
     }
@@ -664,23 +679,23 @@ void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt)
+void USART_DisableInterrupt(USART_T *usart, USART_INT_T interrupt)
 {
     uint32_t temp;
 
     temp = (uint32_t)~(interrupt & 0xffff);
 
-    if (interrupt & 0X10000)
+    if (interrupt & 0x10000)
     {
         usart->CTRL1 &= temp;
     }
 
-    if (interrupt & 0X20000)
+    if (interrupt & 0x20000)
     {
         usart->CTRL2 &= temp;
     }
 
-    if (interrupt & 0X40000)
+    if (interrupt & 0x40000)
     {
         usart->CTRL3 &= temp;
     }
@@ -708,7 +723,7 @@ void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag)
+uint8_t USART_ReadStatusFlag(USART_T *usart, USART_FLAG_T flag)
 {
     return (usart->STS & flag) ? SET : RESET;
 }
@@ -729,7 +744,7 @@ uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag)
+void USART_ClearStatusFlag(USART_T *usart, USART_FLAG_T flag)
 {
     usart->STS &= (uint32_t)~flag;
 }
@@ -756,7 +771,7 @@ void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag)
+uint8_t USART_ReadIntFlag(USART_T *usart, USART_INT_T flag)
 {
     uint32_t itFlag, srFlag;
 
@@ -801,7 +816,7 @@ uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag)
+void USART_ClearIntFlag(USART_T *usart, USART_INT_T flag)
 {
     uint32_t srFlag;
 

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c

@@ -3,10 +3,24 @@
  *
  * @brief       This file contains all the functions for the WWDT peripheral
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x_wwdt.h"
@@ -125,7 +139,7 @@ void WWDT_Enable(uint8_t counter)
  */
 uint8_t WWDT_ReadFlag(void)
 {
-    return (uint8_t) (WWDT->STS);
+    return (uint8_t)(WWDT->STS);
 }
 
 /*!
@@ -141,5 +155,5 @@ void WWDT_ClearFlag(void)
 }
 
 /**@} end of group WWDT_Fuctions*/
-/**@} end of group WWDT_Driver */
+/**@} end of group WWDT_Driver*/
 /**@} end of group Peripherals_Library*/

bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/LICENSE.txt

@@ -0,0 +1,176 @@
+ Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
+      "Object" form shall mean any form resulting from mechanical
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+
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+
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+      on behalf of whom a Contribution has been received by Licensor and
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+
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+          Derivative Works a copy of this License; and
+
+      (b) You must cause any modified files to carry prominent notices
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+
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+
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+          within a display generated by the Derivative Works, if and
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+          of the NOTICE file are for informational purposes only and
+          do not modify the License. You may add Your own attribution
+          notices within Derivative Works that You distribute, alongside
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+          that such additional attribution notices cannot be construed
+          as modifying the License.
+
+      You may add Your own copyright statement to Your modifications and
+      may provide additional or different license terms and conditions
+      for use, reproduction, or distribution of Your modifications, or
+      for any such Derivative Works as a whole, provided Your use,
+      reproduction, and distribution of the Work otherwise complies with
+      the conditions stated in this License.
+
+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
+      with Licensor regarding such Contributions.
+
+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
+      origin of the Work and reproducing the content of the NOTICE file.
+
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+      implied, including, without limitation, any warranties or conditions
+      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
+
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
+      work stoppage, computer failure or malfunction, or any and all
+      other commercial damages or losses), even if such Contributor
+      has been advised of the possibility of such damages.
+
+   9. Accepting Warranty or Additional Liability. While redistributing
+      the Work or Derivative Works thereof, You may choose to offer,
+      and charge a fee for, acceptance of support, warranty, indemnity,
+      or other liability obligations and/or rights consistent with this
+      License. However, in accepting such obligations, You may act only
+      on Your own behalf and on Your sole responsibility, not on behalf
+      of any other Contributor, and only if You agree to indemnify,
+      defend, and hold each Contributor harmless for any liability
+      incurred by, or claims asserted against, such Contributor by reason
+      of your accepting any such warranty or additional liability.
+
+   END OF TERMS AND CONDITIONS

bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armcc.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_armcc.h
  * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
- * @version  V5.1.0
- * @date     08. May 2019
+ * @version  V5.0.4
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,107 +27,78 @@
 
 
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
-  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+    #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
 #endif
 
 /* CMSIS compiler control architecture macros */
 #if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
      (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
-  #define __ARM_ARCH_6M__           1
+#define __ARM_ARCH_6M__           1
 #endif
 
 #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
-  #define __ARM_ARCH_7M__           1
+    #define __ARM_ARCH_7M__           1
 #endif
 
 #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
-  #define __ARM_ARCH_7EM__          1
+    #define __ARM_ARCH_7EM__          1
 #endif
 
-  /* __ARM_ARCH_8M_BASE__  not applicable */
-  /* __ARM_ARCH_8M_MAIN__  not applicable */
+/* __ARM_ARCH_8M_BASE__  not applicable */
+/* __ARM_ARCH_8M_MAIN__  not applicable */
 
-/* CMSIS compiler control DSP macros */
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-  #define __ARM_FEATURE_DSP         1
-#endif
 
 /* CMSIS compiler specific defines */
 #ifndef   __ASM
-  #define __ASM                                  __asm
+    #define __ASM                                  __asm
 #endif
 #ifndef   __INLINE
-  #define __INLINE                               __inline
+    #define __INLINE                               __inline
 #endif
 #ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE                        static __inline
+    #define __STATIC_INLINE                        static __inline
 #endif
 #ifndef   __STATIC_FORCEINLINE
-  #define __STATIC_FORCEINLINE                   static __forceinline
+    #define __STATIC_FORCEINLINE                   static __forceinline
 #endif
 #ifndef   __NO_RETURN
-  #define __NO_RETURN                            __declspec(noreturn)
+    #define __NO_RETURN                            __declspec(noreturn)
 #endif
 #ifndef   __USED
-  #define __USED                                 __attribute__((used))
+    #define __USED                                 __attribute__((used))
 #endif
 #ifndef   __WEAK
-  #define __WEAK                                 __attribute__((weak))
+    #define __WEAK                                 __attribute__((weak))
 #endif
 #ifndef   __PACKED
-  #define __PACKED                               __attribute__((packed))
+    #define __PACKED                               __attribute__((packed))
 #endif
 #ifndef   __PACKED_STRUCT
-  #define __PACKED_STRUCT                        __packed struct
+    #define __PACKED_STRUCT                        __packed struct
 #endif
 #ifndef   __PACKED_UNION
-  #define __PACKED_UNION                         __packed union
+    #define __PACKED_UNION                         __packed union
 #endif
 #ifndef   __UNALIGNED_UINT32        /* deprecated */
-  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+    #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
 #endif
 #ifndef   __UNALIGNED_UINT16_WRITE
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
 #endif
 #ifndef   __UNALIGNED_UINT16_READ
-  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+    #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
 #endif
 #ifndef   __UNALIGNED_UINT32_WRITE
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
 #endif
 #ifndef   __UNALIGNED_UINT32_READ
-  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+    #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
 #endif
 #ifndef   __ALIGNED
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
 #endif
 #ifndef   __RESTRICT
-  #define __RESTRICT                             __restrict
-#endif
-#ifndef   __COMPILER_BARRIER
-  #define __COMPILER_BARRIER()                   __memory_changed()
-#endif
-
-/* #########################  Startup and Lowlevel Init  ######################## */
-
-#ifndef __PROGRAM_START
-#define __PROGRAM_START           __main
-#endif
-
-#ifndef __INITIAL_SP
-#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
-#endif
-
-#ifndef __STACK_LIMIT
-#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
-#endif
-
-#ifndef __VECTOR_TABLE
-#define __VECTOR_TABLE            __Vectors
-#endif
-
-#ifndef __VECTOR_TABLE_ATTRIBUTE
-#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section("RESET")))
+    #define __RESTRICT                             __restrict
 #endif
 
 /* ###########################  Core Function Access  ########################### */
@@ -158,8 +129,8 @@
  */
 __STATIC_INLINE uint32_t __get_CONTROL(void)
 {
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
+    register uint32_t __regControl         __ASM("control");
+    return (__regControl);
 }
 
 
@@ -170,8 +141,8 @@ __STATIC_INLINE uint32_t __get_CONTROL(void)
  */
 __STATIC_INLINE void __set_CONTROL(uint32_t control)
 {
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
+    register uint32_t __regControl         __ASM("control");
+    __regControl = control;
 }
 
 
@@ -182,8 +153,8 @@ __STATIC_INLINE void __set_CONTROL(uint32_t control)
  */
 __STATIC_INLINE uint32_t __get_IPSR(void)
 {
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
+    register uint32_t __regIPSR          __ASM("ipsr");
+    return (__regIPSR);
 }
 
 
@@ -194,8 +165,8 @@ __STATIC_INLINE uint32_t __get_IPSR(void)
  */
 __STATIC_INLINE uint32_t __get_APSR(void)
 {
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
+    register uint32_t __regAPSR          __ASM("apsr");
+    return (__regAPSR);
 }
 
 
@@ -206,8 +177,8 @@ __STATIC_INLINE uint32_t __get_APSR(void)
  */
 __STATIC_INLINE uint32_t __get_xPSR(void)
 {
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
+    register uint32_t __regXPSR          __ASM("xpsr");
+    return (__regXPSR);
 }
 
 
@@ -218,8 +189,8 @@ __STATIC_INLINE uint32_t __get_xPSR(void)
  */
 __STATIC_INLINE uint32_t __get_PSP(void)
 {
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
+    register uint32_t __regProcessStackPointer  __ASM("psp");
+    return (__regProcessStackPointer);
 }
 
 
@@ -230,8 +201,8 @@ __STATIC_INLINE uint32_t __get_PSP(void)
  */
 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
 {
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
+    register uint32_t __regProcessStackPointer  __ASM("psp");
+    __regProcessStackPointer = topOfProcStack;
 }
 
 
@@ -242,8 +213,8 @@ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
  */
 __STATIC_INLINE uint32_t __get_MSP(void)
 {
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
+    register uint32_t __regMainStackPointer     __ASM("msp");
+    return (__regMainStackPointer);
 }
 
 
@@ -254,8 +225,8 @@ __STATIC_INLINE uint32_t __get_MSP(void)
  */
 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
 {
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
+    register uint32_t __regMainStackPointer     __ASM("msp");
+    __regMainStackPointer = topOfMainStack;
 }
 
 
@@ -266,8 +237,8 @@ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
  */
 __STATIC_INLINE uint32_t __get_PRIMASK(void)
 {
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
+    register uint32_t __regPriMask         __ASM("primask");
+    return (__regPriMask);
 }
 
 
@@ -278,8 +249,8 @@ __STATIC_INLINE uint32_t __get_PRIMASK(void)
  */
 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
 {
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
+    register uint32_t __regPriMask         __ASM("primask");
+    __regPriMask = (priMask);
 }
 
 
@@ -309,8 +280,8 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
  */
 __STATIC_INLINE uint32_t  __get_BASEPRI(void)
 {
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
+    register uint32_t __regBasePri         __ASM("basepri");
+    return (__regBasePri);
 }
 
 
@@ -321,8 +292,8 @@ __STATIC_INLINE uint32_t  __get_BASEPRI(void)
  */
 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
 {
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xFFU);
+    register uint32_t __regBasePri         __ASM("basepri");
+    __regBasePri = (basePri & 0xFFU);
 }
 
 
@@ -334,8 +305,8 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
  */
 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
 {
-  register uint32_t __regBasePriMax      __ASM("basepri_max");
-  __regBasePriMax = (basePri & 0xFFU);
+    register uint32_t __regBasePriMax      __ASM("basepri_max");
+    __regBasePriMax = (basePri & 0xFFU);
 }
 
 
@@ -346,8 +317,8 @@ __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
  */
 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
 {
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
+    register uint32_t __regFaultMask       __ASM("faultmask");
+    return (__regFaultMask);
 }
 
 
@@ -358,8 +329,8 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void)
  */
 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1U);
+    register uint32_t __regFaultMask       __ASM("faultmask");
+    __regFaultMask = (faultMask & (uint32_t)1U);
 }
 
 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
@@ -375,10 +346,10 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
 {
 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
+    register uint32_t __regfpscr         __ASM("fpscr");
+    return (__regfpscr);
 #else
-   return(0U);
+    return (0U);
 #endif
 }
 
@@ -392,10 +363,10 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 {
 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
+    register uint32_t __regfpscr         __ASM("fpscr");
+    __regfpscr = (fpscr);
 #else
-  (void)fpscr;
+    (void)fpscr;
 #endif
 }
 
@@ -491,8 +462,8 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
 {
-  rev16 r0, r0
-  bx lr
+    rev16 r0, r0
+    bx lr
 }
 #endif
 
@@ -506,8 +477,8 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
 {
-  revsh r0, r0
-  bx lr
+    revsh r0, r0
+    bx lr
 }
 #endif
 
@@ -540,22 +511,22 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(in
  */
 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
      (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-  #define __RBIT                          __rbit
+#define __RBIT                          __rbit
 #else
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 {
-  uint32_t result;
-  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
-
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */
-  for (value >>= 1U; value != 0U; value >>= 1U)
-  {
-    result <<= 1U;
-    result |= value & 1U;
-    s--;
-  }
-  result <<= s;                        /* shift when v's highest bits are zero */
-  return result;
+    uint32_t result;
+    uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+    result = value;                      /* r will be reversed bits of v; first get LSB of v */
+    for (value >>= 1U; value != 0U; value >>= 1U)
+    {
+        result <<= 1U;
+        result |= value & 1U;
+        s--;
+    }
+    result <<= s;                        /* shift when v's highest bits are zero */
+    return result;
 }
 #endif
 
@@ -579,9 +550,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return             value of type uint8_t at (*ptr)
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+    #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
 #else
-  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+    #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
 #endif
 
 
@@ -592,9 +563,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return        value of type uint16_t at (*ptr)
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+    #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
 #else
-  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+    #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
 #endif
 
 
@@ -605,9 +576,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return        value of type uint32_t at (*ptr)
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+    #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
 #else
-  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+    #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
 #endif
 
 
@@ -620,9 +591,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return          1  Function failed
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+    #define __STREXB(value, ptr)                                                 __strex(value, ptr)
 #else
-  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+    #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
 #endif
 
 
@@ -635,9 +606,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return          1  Function failed
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+    #define __STREXH(value, ptr)                                                 __strex(value, ptr)
 #else
-  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+    #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
 #endif
 
 
@@ -650,9 +621,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return          1  Function failed
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+    #define __STREXW(value, ptr)                                                 __strex(value, ptr)
 #else
-  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+    #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
 #endif
 
 
@@ -693,8 +664,8 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
 {
-  rrx r0, r0
-  bx lr
+    rrx r0, r0
+    bx lr
 }
 #endif
 
@@ -764,20 +735,20 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
  */
 __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
 {
-  if ((sat >= 1U) && (sat <= 32U))
-  {
-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-    const int32_t min = -1 - max ;
-    if (val > max)
-    {
-      return max;
-    }
-    else if (val < min)
+    if ((sat >= 1U) && (sat <= 32U))
     {
-      return min;
+        const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+        const int32_t min = -1 - max ;
+        if (val > max)
+        {
+            return max;
+        }
+        else if (val < min)
+        {
+            return min;
+        }
     }
-  }
-  return val;
+    return val;
 }
 
 /**
@@ -789,25 +760,25 @@ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint3
  */
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
 {
-  if (sat <= 31U)
-  {
-    const uint32_t max = ((1U << sat) - 1U);
-    if (val > (int32_t)max)
-    {
-      return max;
-    }
-    else if (val < 0)
+    if (sat <= 31U)
     {
-      return 0U;
+        const uint32_t max = ((1U << sat) - 1U);
+        if (val > (int32_t)max)
+        {
+            return max;
+        }
+        else if (val < 0)
+        {
+            return 0U;
+        }
     }
-  }
-  return (uint32_t)val;
+    return (uint32_t)val;
 }
 
 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
            (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 
-/**@}*/ /* end of group CMSIS_Core_InstructionInterface */
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 
 
 /* ###################  Compiler specific Intrinsics  ########################### */
@@ -888,7 +859,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint
                                                       ((int64_t)(ARG3) << 32U)     ) >> 32U))
 
 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-/**@} end of group CMSIS_SIMD_intrinsics */
+/*@} end of group CMSIS_SIMD_intrinsics */
 
 
 #endif /* __CMSIS_ARMCC_H */

bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_compiler.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_compiler.h
  * @brief    CMSIS compiler generic header file
- * @version  V5.1.0
- * @date     09. October 2018
+ * @version  V5.0.4
+ * @date     10. January 2018
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -31,251 +31,243 @@
  * Arm Compiler 4/5
  */
 #if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
+#include "cmsis_armcc.h"
 
 
 /*
- * Arm Compiler 6.6 LTM (armclang)
+ * Arm Compiler 6 (armclang)
  */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
-  #include "cmsis_armclang_ltm.h"
-
-  /*
- * Arm Compiler above 6.10.1 (armclang)
- */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
-  #include "cmsis_armclang.h"
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include "cmsis_armclang.h"
 
 
 /*
  * GNU Compiler
  */
 #elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
+#include "cmsis_gcc.h"
 
 
 /*
  * IAR Compiler
  */
 #elif defined ( __ICCARM__ )
-  #include <cmsis_iccarm.h>
+#include <cmsis_iccarm.h>
 
 
 /*
  * TI Arm Compiler
  */
 #elif defined ( __TI_ARM__ )
-  #include <cmsis_ccs.h>
+#include <cmsis_ccs.h>
 
-  #ifndef   __ASM
+#ifndef   __ASM
     #define __ASM                                  __asm
-  #endif
-  #ifndef   __INLINE
+#endif
+#ifndef   __INLINE
     #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
+#endif
+#ifndef   __STATIC_INLINE
     #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __STATIC_FORCEINLINE
+#endif
+#ifndef   __STATIC_FORCEINLINE
     #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-  #endif
-  #ifndef   __NO_RETURN
+#endif
+#ifndef   __NO_RETURN
     #define __NO_RETURN                            __attribute__((noreturn))
-  #endif
-  #ifndef   __USED
+#endif
+#ifndef   __USED
     #define __USED                                 __attribute__((used))
-  #endif
-  #ifndef   __WEAK
+#endif
+#ifndef   __WEAK
     #define __WEAK                                 __attribute__((weak))
-  #endif
-  #ifndef   __PACKED
+#endif
+#ifndef   __PACKED
     #define __PACKED                               __attribute__((packed))
-  #endif
-  #ifndef   __PACKED_STRUCT
+#endif
+#ifndef   __PACKED_STRUCT
     #define __PACKED_STRUCT                        struct __attribute__((packed))
-  #endif
-  #ifndef   __PACKED_UNION
+#endif
+#ifndef   __PACKED_UNION
     #define __PACKED_UNION                         union __attribute__((packed))
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+struct __attribute__((packed)) T_UINT32
+{
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+#define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+#define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+#define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+#define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
     #define __ALIGNED(x)                           __attribute__((aligned(x)))
-  #endif
-  #ifndef   __RESTRICT
-    #define __RESTRICT                             __restrict
-  #endif
-  #ifndef   __COMPILER_BARRIER
-    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
-    #define __COMPILER_BARRIER()                   (void)0
-  #endif
+#endif
+#ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+#endif
 
 
 /*
  * TASKING Compiler
  */
 #elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
 
-  #ifndef   __ASM
+#ifndef   __ASM
     #define __ASM                                  __asm
-  #endif
-  #ifndef   __INLINE
+#endif
+#ifndef   __INLINE
     #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
+#endif
+#ifndef   __STATIC_INLINE
     #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __STATIC_FORCEINLINE
+#endif
+#ifndef   __STATIC_FORCEINLINE
     #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-  #endif
-  #ifndef   __NO_RETURN
+#endif
+#ifndef   __NO_RETURN
     #define __NO_RETURN                            __attribute__((noreturn))
-  #endif
-  #ifndef   __USED
+#endif
+#ifndef   __USED
     #define __USED                                 __attribute__((used))
-  #endif
-  #ifndef   __WEAK
+#endif
+#ifndef   __WEAK
     #define __WEAK                                 __attribute__((weak))
-  #endif
-  #ifndef   __PACKED
+#endif
+#ifndef   __PACKED
     #define __PACKED                               __packed__
-  #endif
-  #ifndef   __PACKED_STRUCT
+#endif
+#ifndef   __PACKED_STRUCT
     #define __PACKED_STRUCT                        struct __packed__
-  #endif
-  #ifndef   __PACKED_UNION
+#endif
+#ifndef   __PACKED_UNION
     #define __PACKED_UNION                         union __packed__
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    struct __packed__ T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+struct __packed__ T_UINT32
+{
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+#define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+#define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+#define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+#define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
     #define __ALIGNED(x)              __align(x)
-  #endif
-  #ifndef   __RESTRICT
+#endif
+#ifndef   __RESTRICT
     #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
-  #endif
-  #ifndef   __COMPILER_BARRIER
-    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
-    #define __COMPILER_BARRIER()                   (void)0
-  #endif
+#endif
 
 
 /*
  * COSMIC Compiler
  */
 #elif defined ( __CSMC__ )
-   #include <cmsis_csm.h>
+#include <cmsis_csm.h>
 
- #ifndef   __ASM
+#ifndef   __ASM
     #define __ASM                                  _asm
-  #endif
-  #ifndef   __INLINE
+#endif
+#ifndef   __INLINE
     #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
+#endif
+#ifndef   __STATIC_INLINE
     #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __STATIC_FORCEINLINE
+#endif
+#ifndef   __STATIC_FORCEINLINE
     #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-  #endif
-  #ifndef   __NO_RETURN
+#endif
+#ifndef   __NO_RETURN
     // NO RETURN is automatically detected hence no warning here
     #define __NO_RETURN
-  #endif
-  #ifndef   __USED
+#endif
+#ifndef   __USED
     #warning No compiler specific solution for __USED. __USED is ignored.
     #define __USED
-  #endif
-  #ifndef   __WEAK
+#endif
+#ifndef   __WEAK
     #define __WEAK                                 __weak
-  #endif
-  #ifndef   __PACKED
+#endif
+#ifndef   __PACKED
     #define __PACKED                               @packed
-  #endif
-  #ifndef   __PACKED_STRUCT
+#endif
+#ifndef   __PACKED_STRUCT
     #define __PACKED_STRUCT                        @packed struct
-  #endif
-  #ifndef   __PACKED_UNION
+#endif
+#ifndef   __PACKED_UNION
     #define __PACKED_UNION                         @packed union
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    @packed struct T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+@packed struct T_UINT32
+{
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+#define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+#define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+#define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+#define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
     #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
     #define __ALIGNED(x)
-  #endif
-  #ifndef   __RESTRICT
+#endif
+#ifndef   __RESTRICT
     #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
-  #endif
-  #ifndef   __COMPILER_BARRIER
-    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
-    #define __COMPILER_BARRIER()                   (void)0
-  #endif
+#endif
 
 
 #else
-  #error Unknown compiler.
+#error Unknown compiler.
 #endif
 
 

bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_gcc.h

@@ -0,0 +1,2092 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.4
+ * @date     09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+    #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+    #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+    #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif
+#ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+    #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpacked"
+#pragma GCC diagnostic ignored "-Wattributes"
+struct __attribute__((packed)) T_UINT32
+{
+    uint32_t v;
+};
+#pragma GCC diagnostic pop
+#define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpacked"
+#pragma GCC diagnostic ignored "-Wattributes"
+__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+#pragma GCC diagnostic pop
+#define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpacked"
+#pragma GCC diagnostic ignored "-Wattributes"
+__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+#pragma GCC diagnostic pop
+#define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpacked"
+#pragma GCC diagnostic ignored "-Wattributes"
+__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+#pragma GCC diagnostic pop
+#define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpacked"
+#pragma GCC diagnostic ignored "-Wattributes"
+__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+#pragma GCC diagnostic pop
+#define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+    __ASM volatile("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+    __ASM volatile("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, control" : "=r"(result));
+    return (result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, control_ns" : "=r"(result));
+    return (result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+    __ASM volatile("MSR control, %0" : : "r"(control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+    __ASM volatile("MSR control_ns, %0" : : "r"(control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, ipsr" : "=r"(result));
+    return (result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, apsr" : "=r"(result));
+    return (result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, xpsr" : "=r"(result));
+    return (result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, psp"  : "=r"(result));
+    return (result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, psp_ns"  : "=r"(result));
+    return (result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    __ASM volatile("MSR psp, %0" : : "r"(topOfProcStack) :);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+    __ASM volatile("MSR psp_ns, %0" : : "r"(topOfProcStack) :);
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, msp" : "=r"(result));
+    return (result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, msp_ns" : "=r"(result));
+    return (result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+    __ASM volatile("MSR msp, %0" : : "r"(topOfMainStack) :);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+    __ASM volatile("MSR msp_ns, %0" : : "r"(topOfMainStack) :);
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, sp_ns" : "=r"(result));
+    return (result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+    __ASM volatile("MSR sp_ns, %0" : : "r"(topOfStack) :);
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, primask" : "=r"(result) :: "memory");
+    return (result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, primask_ns" : "=r"(result) :: "memory");
+    return (result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+    __ASM volatile("MSR primask, %0" : : "r"(priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+    __ASM volatile("MSR primask_ns, %0" : : "r"(priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+    __ASM volatile("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+    __ASM volatile("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, basepri" : "=r"(result));
+    return (result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, basepri_ns" : "=r"(result));
+    return (result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+    __ASM volatile("MSR basepri, %0" : : "r"(basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+    __ASM volatile("MSR basepri_ns, %0" : : "r"(basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+    __ASM volatile("MSR basepri_max, %0" : : "r"(basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, faultmask" : "=r"(result));
+    return (result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, faultmask_ns" : "=r"(result));
+    return (result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+    __ASM volatile("MSR faultmask, %0" : : "r"(faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+    __ASM volatile("MSR faultmask_ns, %0" : : "r"(faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    return 0U;
+#else
+    uint32_t result;
+    __ASM volatile("MRS %0, psplim"  : "=r"(result));
+    return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    return 0U;
+#else
+    uint32_t result;
+    __ASM volatile("MRS %0, psplim_ns"  : "=r"(result));
+    return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    (void)ProcStackPtrLimit;
+#else
+    __ASM volatile("MSR psplim, %0" : : "r"(ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    (void)ProcStackPtrLimit;
+#else
+    __ASM volatile("MSR psplim_ns, %0\n" : : "r"(ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    return 0U;
+#else
+    uint32_t result;
+    __ASM volatile("MRS %0, msplim" : "=r"(result));
+    return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    return 0U;
+#else
+    uint32_t result;
+    __ASM volatile("MRS %0, msplim_ns" : "=r"(result));
+    return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    (void)MainStackPtrLimit;
+#else
+    __ASM volatile("MSR msplim, %0" : : "r"(MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    (void)MainStackPtrLimit;
+#else
+    __ASM volatile("MSR msplim_ns, %0" : : "r"(MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+    return __builtin_arm_get_fpscr();
+#else
+    uint32_t result;
+
+    __ASM volatile("VMRS %0, fpscr" : "=r"(result));
+    return (result);
+#endif
+#else
+    return (0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+    __builtin_arm_set_fpscr(fpscr);
+#else
+    __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr) : "vfpcc", "memory");
+#endif
+#else
+    (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+    #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+    #define __CMSIS_GCC_RW_REG(r) "+l" (r)
+    #define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+    #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+    #define __CMSIS_GCC_RW_REG(r) "+r" (r)
+    #define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+    __ASM volatile("isb 0xF"::: "memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+    __ASM volatile("dsb 0xF"::: "memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+    __ASM volatile("dmb 0xF"::: "memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+    return __builtin_bswap32(value);
+#else
+    uint32_t result;
+
+    __ASM volatile("rev %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value));
+    return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile("rev16 %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value));
+    return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    return (int16_t)__builtin_bswap16(value);
+#else
+    int16_t result;
+
+    __ASM volatile("revsh %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value));
+    return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+    op2 %= 32U;
+    if (op2 == 0U)
+    {
+        return op1;
+    }
+    return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+    uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+    __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value));
+#else
+    uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+    result = value;                      /* r will be reversed bits of v; first get LSB of v */
+    for (value >>= 1U; value != 0U; value >>= 1U)
+    {
+        result <<= 1U;
+        result |= value & 1U;
+        s--;
+    }
+    result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+    return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile("ldrexb %0, %1" : "=r"(result) : "Q"(*addr));
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr) : "memory");
+#endif
+    return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile("ldrexh %0, %1" : "=r"(result) : "Q"(*addr));
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr) : "memory");
+#endif
+    return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+    __ASM volatile("ldrex %0, %1" : "=r"(result) : "Q"(*addr));
+    return (result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+    uint32_t result;
+
+    __ASM volatile("strexb %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"((uint32_t)value));
+    return (result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+    uint32_t result;
+
+    __ASM volatile("strexh %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"((uint32_t)value));
+    return (result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+    uint32_t result;
+
+    __ASM volatile("strex %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"(value));
+    return (result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+    __ASM volatile("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile("rrx %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value));
+    return (result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile("ldrbt %0, %1" : "=r"(result) : "Q"(*ptr));
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile("ldrbt %0, [%1]" : "=r"(result) : "r"(ptr) : "memory");
+#endif
+    return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile("ldrht %0, %1" : "=r"(result) : "Q"(*ptr));
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile("ldrht %0, [%1]" : "=r"(result) : "r"(ptr) : "memory");
+#endif
+    return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+    __ASM volatile("ldrt %0, %1" : "=r"(result) : "Q"(*ptr));
+    return (result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+    __ASM volatile("strbt %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value));
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+    __ASM volatile("strht %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value));
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+    __ASM volatile("strt %1, %0" : "=Q"(*ptr) : "r"(value));
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+        const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+        const int32_t min = -1 - max ;
+        if (val > max)
+        {
+            return max;
+        }
+        else if (val < min)
+        {
+            return min;
+        }
+    }
+    return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+    if (sat <= 31U)
+    {
+        const uint32_t max = ((1U << sat) - 1U);
+        if (val > (int32_t)max)
+        {
+            return max;
+        }
+        else if (val < 0)
+        {
+            return 0U;
+        }
+    }
+    return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+    __ASM volatile("ldab %0, %1" : "=r"(result) : "Q"(*ptr));
+    return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+    __ASM volatile("ldah %0, %1" : "=r"(result) : "Q"(*ptr));
+    return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+    __ASM volatile("lda %0, %1" : "=r"(result) : "Q"(*ptr));
+    return (result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+    __ASM volatile("stlb %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value));
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+    __ASM volatile("stlh %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value));
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+    __ASM volatile("stl %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value));
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+    __ASM volatile("ldaexb %0, %1" : "=r"(result) : "Q"(*ptr));
+    return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+    __ASM volatile("ldaexh %0, %1" : "=r"(result) : "Q"(*ptr));
+    return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+    __ASM volatile("ldaex %0, %1" : "=r"(result) : "Q"(*ptr));
+    return (result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+    __ASM volatile("stlexb %0, %2, %1" : "=&r"(result), "=Q"(*ptr) : "r"((uint32_t)value));
+    return (result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+    __ASM volatile("stlexh %0, %2, %1" : "=&r"(result), "=Q"(*ptr) : "r"((uint32_t)value));
+    return (result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+    __ASM volatile("stlex %0, %2, %1" : "=&r"(result), "=Q"(*ptr) : "r"((uint32_t)value));
+    return (result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("sadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("qadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("shadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uqadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uhadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("ssub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("qsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("shsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("usub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uqsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uhsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("sadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("qadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("shadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uqadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uhadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("ssub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("qsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("shsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("usub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uqsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uhsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("sasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("qasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("shasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uqasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uhasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("ssax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("qsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("shsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("usax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uqsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uhsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("usad8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile("usada8 %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
+    return (result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+    uint32_t result;
+
+    __ASM volatile("uxtb16 %0, %1" : "=r"(result) : "r"(op1));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("uxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+    uint32_t result;
+
+    __ASM volatile("sxtb16 %0, %1" : "=r"(result) : "r"(op1));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("sxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("smuad %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("smuadx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile("smlad %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile("smladx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u
+    {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
+#else               /* Big endian */
+    __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
+#endif
+
+    return (llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u
+    {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
+#else               /* Big endian */
+    __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
+#endif
+
+    return (llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("smusd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("smusdx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile("smlsd %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile("smlsdx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
+    return (result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u
+    {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
+#else               /* Big endian */
+    __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
+#endif
+
+    return (llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u
+    {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
+#else               /* Big endian */
+    __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
+#endif
+
+    return (llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile("sel %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD(int32_t op1,  int32_t op2)
+{
+    int32_t result;
+
+    __ASM volatile("qadd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB(int32_t op1,  int32_t op2)
+{
+    int32_t result;
+
+    __ASM volatile("qsub %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
+    return (result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3)
+{
+    int32_t result;
+
+    __ASM volatile("smmla %0, %1, %2, %3" : "=r"(result): "r"(op1), "r"(op2), "r"(op3));
+    return (result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */

bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_iccarm.h

@@ -0,0 +1,941 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.7
+ * @date     19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+    #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+    #define __ICCARM_V8 1
+#else
+    #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+    #if __ICCARM_V8
+        #define __ALIGNED(x) __attribute__((aligned(x)))
+    #elif (__VER__ >= 7080000)
+        /* Needs IAR language extensions */
+        #define __ALIGNED(x) __attribute__((aligned(x)))
+    #else
+        #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+        #define __ALIGNED(x)
+    #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+    /* Macros already defined */
+#else
+    #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+        #define __ARM_ARCH_8M_MAIN__ 1
+    #elif defined(__ARM8M_BASELINE__)
+        #define __ARM_ARCH_8M_BASE__ 1
+    #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+        #if __ARM_ARCH == 6
+            #define __ARM_ARCH_6M__ 1
+        #elif __ARM_ARCH == 7
+            #if __ARM_FEATURE_DSP
+                #define __ARM_ARCH_7EM__ 1
+            #else
+                #define __ARM_ARCH_7M__ 1
+            #endif
+        #endif /* __ARM_ARCH */
+    #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+    #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+        #define __ARM_ARCH_6M__ 1
+    #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+        #define __ARM_ARCH_7M__ 1
+    #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+        #define __ARM_ARCH_7EM__  1
+    #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+        #define __ARM_ARCH_8M_BASE__ 1
+    #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+        #define __ARM_ARCH_8M_MAIN__ 1
+    #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+        #define __ARM_ARCH_8M_MAIN__ 1
+    #else
+        #error "Unknown target."
+    #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+    #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+    #define __IAR_M0_FAMILY  1
+#else
+    #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+    #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+    #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+    #if __ICCARM_V8
+        #define __NO_RETURN __attribute__((__noreturn__))
+    #else
+        #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+    #endif
+#endif
+
+#ifndef   __PACKED
+    #if __ICCARM_V8
+        #define __PACKED __attribute__((packed, aligned(1)))
+    #else
+        /* Needs IAR language extensions */
+        #define __PACKED __packed
+    #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+    #if __ICCARM_V8
+        #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+    #else
+        /* Needs IAR language extensions */
+        #define __PACKED_STRUCT __packed struct
+    #endif
+#endif
+
+#ifndef   __PACKED_UNION
+    #if __ICCARM_V8
+        #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+    #else
+        /* Needs IAR language extensions */
+        #define __PACKED_UNION __packed union
+    #endif
+#endif
+
+#ifndef   __RESTRICT
+    #define __RESTRICT            __restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+    #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+    return *(__packed uint16_t *)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+    *(__packed uint16_t *)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+    return *(__packed uint32_t *)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+    *(__packed uint32_t *)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32
+{
+    uint32_t v;
+};
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+    #if __ICCARM_V8
+        #define __USED __attribute__((used))
+    #else
+        #define __USED _Pragma("__root")
+    #endif
+#endif
+
+#ifndef   __WEAK
+    #if __ICCARM_V8
+        #define __WEAK __attribute__((weak))
+    #else
+        #define __WEAK _Pragma("__weak")
+    #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+    #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+#if defined(__CLZ)
+    #undef __CLZ
+#endif
+#if defined(__REVSH)
+    #undef __REVSH
+#endif
+#if defined(__RBIT)
+    #undef __RBIT
+#endif
+#if defined(__SSAT)
+    #undef __SSAT
+#endif
+#if defined(__USAT)
+    #undef __USAT
+#endif
+
+#include "iccarm_builtin.h"
+
+#define __disable_fault_irq __iar_builtin_disable_fiq
+#define __disable_irq       __iar_builtin_disable_interrupt
+#define __enable_fault_irq  __iar_builtin_enable_fiq
+#define __enable_irq        __iar_builtin_enable_interrupt
+#define __arm_rsr           __iar_builtin_rsr
+#define __arm_wsr           __iar_builtin_wsr
+
+
+#define __get_APSR()                (__arm_rsr("APSR"))
+#define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+#define __get_CONTROL()             (__arm_rsr("CONTROL"))
+#define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR()             (__arm_rsr("FPSCR"))
+#define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+#else
+#define __get_FPSCR()             ( 0 )
+#define __set_FPSCR(VALUE)        ((void)VALUE)
+#endif
+
+#define __get_IPSR()                (__arm_rsr("IPSR"))
+#define __get_MSP()                 (__arm_rsr("MSP"))
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+// without main extensions, the non-secure MSPLIM is RAZ/WI
+#define __get_MSPLIM()            (0U)
+#else
+#define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+#endif
+#define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+#define __get_PSP()                 (__arm_rsr("PSP"))
+
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+// without main extensions, the non-secure PSPLIM is RAZ/WI
+#define __get_PSPLIM()            (0U)
+#else
+#define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+#endif
+
+#define __get_xPSR()                (__arm_rsr("xPSR"))
+
+#define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+#define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+#define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+#define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+#define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+// without main extensions, the non-secure MSPLIM is RAZ/WI
+#define __set_MSPLIM(VALUE)       ((void)(VALUE))
+#else
+#define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+#endif
+#define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+#define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+// without main extensions, the non-secure PSPLIM is RAZ/WI
+#define __set_PSPLIM(VALUE)       ((void)(VALUE))
+#else
+#define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+#endif
+
+#define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+#define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+#define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+#define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+#define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+#define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+#define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+#define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+#define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+#define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+#define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+#define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+#define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+// without main extensions, the non-secure PSPLIM is RAZ/WI
+#define __TZ_get_PSPLIM_NS()      (0U)
+#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+#else
+#define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+#endif
+
+#define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+#define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+#define __NOP     __iar_builtin_no_operation
+
+#define __CLZ     __iar_builtin_CLZ
+#define __CLREX   __iar_builtin_CLREX
+
+#define __DMB     __iar_builtin_DMB
+#define __DSB     __iar_builtin_DSB
+#define __ISB     __iar_builtin_ISB
+
+#define __LDREXB  __iar_builtin_LDREXB
+#define __LDREXH  __iar_builtin_LDREXH
+#define __LDREXW  __iar_builtin_LDREX
+
+#define __RBIT    __iar_builtin_RBIT
+#define __REV     __iar_builtin_REV
+#define __REV16   __iar_builtin_REV16
+
+__IAR_FT int16_t __REVSH(int16_t val)
+{
+    return (int16_t) __iar_builtin_REVSH(val);
+}
+
+#define __ROR     __iar_builtin_ROR
+#define __RRX     __iar_builtin_RRX
+
+#define __SEV     __iar_builtin_SEV
+
+#if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+#endif
+
+#define __STREXB  __iar_builtin_STREXB
+#define __STREXH  __iar_builtin_STREXH
+#define __STREXW  __iar_builtin_STREX
+
+#if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+#endif
+
+#define __WFE     __iar_builtin_WFE
+#define __WFI     __iar_builtin_WFI
+
+#if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+#endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#if __IAR_M0_FAMILY
+    /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+#endif
+
+
+#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+#endif
+
+#ifdef __INTRINSICS_INCLUDED
+    #error intrinsics.h is already included previously!
+#endif
+
+#include <intrinsics.h>
+
+#if __IAR_M0_FAMILY
+/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+#undef __CLZ
+#undef __SSAT
+#undef __USAT
+#undef __RBIT
+#undef __get_APSR
+
+__STATIC_INLINE uint8_t __CLZ(uint32_t data)
+{
+    if (data == 0U)
+    {
+        return 32U;
+    }
+
+    uint32_t count = 0U;
+    uint32_t mask = 0x80000000U;
+
+    while ((data & mask) == 0U)
+    {
+        count += 1U;
+        mask = mask >> 1U;
+    }
+    return count;
+}
+
+__STATIC_INLINE uint32_t __RBIT(uint32_t v)
+{
+    uint8_t sc = 31U;
+    uint32_t r = v;
+    for (v >>= 1U; v; v >>= 1U)
+    {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+    }
+    return (r << sc);
+}
+
+__STATIC_INLINE  uint32_t __get_APSR(void)
+{
+    uint32_t res;
+    __asm("MRS      %0,APSR" : "=r"(res));
+    return res;
+}
+
+#endif
+
+#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+#undef __get_FPSCR
+#undef __set_FPSCR
+#define __get_FPSCR()       (0)
+#define __set_FPSCR(VALUE)  ((void)VALUE)
+#endif
+
+#pragma diag_suppress=Pe940
+#pragma diag_suppress=Pe177
+
+#define __enable_irq    __enable_interrupt
+#define __disable_irq   __disable_interrupt
+#define __NOP           __no_operation
+
+#define __get_xPSR      __get_PSR
+
+#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+{
+    return __LDREX((unsigned long *)ptr);
+}
+
+__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+{
+    return __STREX(value, (unsigned long *)ptr);
+}
+#endif
+
+
+/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+#if (__CORTEX_M >= 0x03)
+
+__IAR_FT uint32_t __RRX(uint32_t value)
+{
+    uint32_t result;
+    __ASM("RRX      %0, %1" : "=r"(result) : "r"(value) : "cc");
+    return (result);
+}
+
+__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+{
+    __asm volatile("MSR      BASEPRI_MAX,%0"::"r"(value));
+}
+
+
+#define __enable_fault_irq  __enable_fiq
+#define __disable_fault_irq __disable_fiq
+
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+    return (op1 >> op2) | (op1 << ((sizeof(op1) * 8) - op2));
+}
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+__IAR_FT uint32_t __get_MSPLIM(void)
+{
+    uint32_t res;
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    res = 0U;
+#else
+    __asm volatile("MRS      %0,MSPLIM" : "=r"(res));
+#endif
+    return res;
+}
+
+__IAR_FT void   __set_MSPLIM(uint32_t value)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    (void)value;
+#else
+    __asm volatile("MSR      MSPLIM,%0" :: "r"(value));
+#endif
+}
+
+__IAR_FT uint32_t __get_PSPLIM(void)
+{
+    uint32_t res;
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    res = 0U;
+#else
+    __asm volatile("MRS      %0,PSPLIM" : "=r"(res));
+#endif
+    return res;
+}
+
+__IAR_FT void   __set_PSPLIM(uint32_t value)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    (void)value;
+#else
+    __asm volatile("MSR      PSPLIM,%0" :: "r"(value));
+#endif
+}
+
+__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+{
+    uint32_t res;
+    __asm volatile("MRS      %0,CONTROL_NS" : "=r"(res));
+    return res;
+}
+
+__IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+{
+    __asm volatile("MSR      CONTROL_NS,%0" :: "r"(value));
+}
+
+__IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+{
+    uint32_t res;
+    __asm volatile("MRS      %0,PSP_NS" : "=r"(res));
+    return res;
+}
+
+__IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+{
+    __asm volatile("MSR      PSP_NS,%0" :: "r"(value));
+}
+
+__IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+{
+    uint32_t res;
+    __asm volatile("MRS      %0,MSP_NS" : "=r"(res));
+    return res;
+}
+
+__IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+{
+    __asm volatile("MSR      MSP_NS,%0" :: "r"(value));
+}
+
+__IAR_FT uint32_t   __TZ_get_SP_NS(void)
+{
+    uint32_t res;
+    __asm volatile("MRS      %0,SP_NS" : "=r"(res));
+    return res;
+}
+__IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+{
+    __asm volatile("MSR      SP_NS,%0" :: "r"(value));
+}
+
+__IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+{
+    uint32_t res;
+    __asm volatile("MRS      %0,PRIMASK_NS" : "=r"(res));
+    return res;
+}
+
+__IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+{
+    __asm volatile("MSR      PRIMASK_NS,%0" :: "r"(value));
+}
+
+__IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+{
+    uint32_t res;
+    __asm volatile("MRS      %0,BASEPRI_NS" : "=r"(res));
+    return res;
+}
+
+__IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+{
+    __asm volatile("MSR      BASEPRI_NS,%0" :: "r"(value));
+}
+
+__IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+{
+    uint32_t res;
+    __asm volatile("MRS      %0,FAULTMASK_NS" : "=r"(res));
+    return res;
+}
+
+__IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+{
+    __asm volatile("MSR      FAULTMASK_NS,%0" :: "r"(value));
+}
+
+__IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+{
+    uint32_t res;
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    res = 0U;
+#else
+    __asm volatile("MRS      %0,PSPLIM_NS" : "=r"(res));
+#endif
+    return res;
+}
+
+__IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    (void)value;
+#else
+    __asm volatile("MSR      PSPLIM_NS,%0" :: "r"(value));
+#endif
+}
+
+__IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+{
+    uint32_t res;
+    __asm volatile("MRS      %0,MSPLIM_NS" : "=r"(res));
+    return res;
+}
+
+__IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+{
+    __asm volatile("MSR      MSPLIM_NS,%0" :: "r"(value));
+}
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+        const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+        const int32_t min = -1 - max ;
+        if (val > max)
+        {
+            return max;
+        }
+        else if (val < min)
+        {
+            return min;
+        }
+    }
+    return val;
+}
+
+__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+    if (sat <= 31U)
+    {
+        const uint32_t max = ((1U << sat) - 1U);
+        if (val > (int32_t)max)
+        {
+            return max;
+        }
+        else if (val < 0)
+        {
+            return 0U;
+        }
+    }
+    return (uint32_t)val;
+}
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r"(res) : "r"(addr) : "memory");
+    return ((uint8_t)res);
+}
+
+__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r"(res) : "r"(addr) : "memory");
+    return ((uint16_t)res);
+}
+
+__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r"(res) : "r"(addr) : "memory");
+    return res;
+}
+
+__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+    __ASM("STRBT %1, [%0]" : : "r"(addr), "r"((uint32_t)value) : "memory");
+}
+
+__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+    __ASM("STRHT %1, [%0]" : : "r"(addr), "r"((uint32_t)value) : "memory");
+}
+
+__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+    __ASM("STRT %1, [%0]" : : "r"(addr), "r"(value) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t res;
+    __ASM volatile("LDAB %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
+    return ((uint8_t)res);
+}
+
+__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t res;
+    __ASM volatile("LDAH %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
+    return ((uint16_t)res);
+}
+
+__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t res;
+    __ASM volatile("LDA %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
+    return res;
+}
+
+__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+    __ASM volatile("STLB %1, [%0]" :: "r"(ptr), "r"(value) : "memory");
+}
+
+__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+    __ASM volatile("STLH %1, [%0]" :: "r"(ptr), "r"(value) : "memory");
+}
+
+__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+    __ASM volatile("STL %1, [%0]" :: "r"(ptr), "r"(value) : "memory");
+}
+
+__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t res;
+    __ASM volatile("LDAEXB %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
+    return ((uint8_t)res);
+}
+
+__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t res;
+    __ASM volatile("LDAEXH %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
+    return ((uint16_t)res);
+}
+
+__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t res;
+    __ASM volatile("LDAEX %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
+    return res;
+}
+
+__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+    uint32_t res;
+    __ASM volatile("STLEXB %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory");
+    return res;
+}
+
+__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+    uint32_t res;
+    __ASM volatile("STLEXH %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory");
+    return res;
+}
+
+__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+    uint32_t res;
+    __ASM volatile("STLEX %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory");
+    return res;
+}
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_version.h

@@ -23,9 +23,9 @@
  */
 
 #if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
+    #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
+    #pragma clang system_header   /* treat file as system include file */
 #endif
 
 #ifndef __CMSIS_VERSION_H

bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h

@@ -3,17 +3,31 @@
  *
  * @brief       CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #ifndef __SYSTEM_APM32F10X_H
 #define __SYSTEM_APM32F10X_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 extern uint32_t SystemCoreClock;

bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s

@@ -1,262 +1,367 @@
 ;/*!
-; * @file       startup_apm32f10x_hd.s
+; * @file        startup_apm32f10x_hd.s
 ; *
-; * @brief      CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd
+; * @brief       CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd
 ; *
-; * @version    V1.0.1
+; * @version     V1.0.2
 ; *
-; * @date       2021-03-23
+; * @date        2022-01-05
 ; *
+; * @attention
+; *
+; *  Copyright (C) 2020-2022 Geehy Semiconductor
+; *
+; *  You may not use this file except in compliance with the
+; *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+; *
+; *  The program is only for reference, which is distributed in the hope
+; *  that it will be usefull and instructional for customers to develop
+; *  their software. Unless required by applicable law or agreed to in
+; *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+; *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+; *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+; *  and limitations under the License.
 ; */
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;
+<h> Stack Configuration
+;
+<o> Stack Size(in Bytes) < 0x0 - 0xFFFFFFFF: 8 >
+;
+< / h >
 
 Stack_Size      EQU     0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
+AREA    STACK, NOINIT, READWRITE, ALIGN = 3
+        Stack_Mem       SPACE   Stack_Size
+        __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+        ;
+<h> Heap Configuration
+;
+<o>  Heap Size(in Bytes) < 0x0 - 0xFFFFFFFF: 8 >
+;
+< / h >
 
 Heap_Size       EQU     0x00000200
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                 ; Top of Stack
-                DCD     Reset_Handler                ; Reset Handler
-                DCD     NMI_Handler                  ; NMI Handler
-                DCD     HardFault_Handler            ; Hard Fault Handler
-                DCD     MemManage_Handler            ; MPU Fault Handler
-                DCD     BusFault_Handler             ; Bus Fault Handler
-                DCD     UsageFault_Handler           ; Usage Fault Handler
-                DCD     0                            ; Reserved
-                DCD     0                            ; Reserved
-                DCD     0                            ; Reserved
-                DCD     0                            ; Reserved
-                DCD     SVC_Handler                  ; SVCall Handler
-                DCD     DebugMon_Handler             ; Debug Monitor Handler
-                DCD     0                            ; Reserved
-                DCD     PendSV_Handler               ; PendSV Handler
-                DCD     SysTick_Handler              ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDT_IRQHandler              ; Window Watchdog
-                DCD     PVD_IRQHandler               ; PVD through EINT Line detect
-                DCD     TAMPER_IRQHandler            ; Tamper
-                DCD     RTC_IRQHandler               ; RTC
-                DCD     FMC_IRQHandler               ; Flash
-                DCD     RCM_IRQHandler               ; RCM
-                DCD     EINT0_IRQHandler             ; EINT Line 0
-                DCD     EINT1_IRQHandler             ; EINT Line 1
-                DCD     EINT2_IRQHandler             ; EINT Line 2
-                DCD     EINT3_IRQHandler             ; EINT Line 3
-                DCD     EINT4_IRQHandler             ; EINT Line 4
-                DCD     DMA1_Channel1_IRQHandler     ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler     ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler     ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler     ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler     ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler     ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler     ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler            ; ADC1 & ADC2
-                DCD     USBD1_HP_CAN1_TX_IRQHandler  ; USBD1 High Priority or CAN1 TX
-                DCD     USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler          ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler          ; CAN1 SCE
-                DCD     EINT9_5_IRQHandler           ; EINT Line 9..5
-                DCD     TMR1_BRK_IRQHandler          ; TMR1 Break
-                DCD     TMR1_UP_IRQHandler           ; TMR1 Update
-                DCD     TMR1_TRG_COM_IRQHandler      ; TMR1 Trigger and Commutation
-                DCD     TMR1_CC_IRQHandler           ; TMR1 Capture Compare
-                DCD     TMR2_IRQHandler              ; TMR2
-                DCD     TMR3_IRQHandler              ; TMR3
-                DCD     TMR4_IRQHandler              ; TMR4
-                DCD     I2C1_EV_IRQHandler           ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler           ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler           ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler           ; I2C2 Error
-                DCD     SPI1_IRQHandler              ; SPI1
-                DCD     SPI2_IRQHandler              ; SPI2
-                DCD     USART1_IRQHandler            ; USART1
-                DCD     USART2_IRQHandler            ; USART2
-                DCD     USART3_IRQHandler            ; USART3
-                DCD     EINT15_10_IRQHandler         ; EINT Line 15..10
-                DCD     RTCAlarm_IRQHandler          ; RTC Alarm through EINT Line
-                DCD     USBDWakeUp_IRQHandler        ; USBD Wakeup from suspend
-                DCD     TMR8_BRK_IRQHandler          ; TMR8 Break
-                DCD     TMR8_UP_IRQHandler           ; TMR8 Update
-                DCD     TMR8_TRG_COM_IRQHandler      ; TMR8 Trigger and Commutation
-                DCD     TMR8_CC_IRQHandler           ; TMR8 Capture Compare
-                DCD     ADC3_IRQHandler              ; ADC3
-                DCD     EMMC_IRQHandler              ; EMMC
-                DCD     SDIO_IRQHandler              ; SDIO
-                DCD     TMR5_IRQHandler              ; TMR5
-                DCD     SPI3_IRQHandler              ; SPI3
-                DCD     UART4_IRQHandler             ; UART4
-                DCD     UART5_IRQHandler             ; UART5
-                DCD     TMR6_IRQHandler              ; TMR6
-                DCD     TMR7_IRQHandler              ; TMR7
-                DCD     DMA2_Channel1_IRQHandler     ; DMA2 Channel1
-                DCD     DMA2_Channel2_IRQHandler     ; DMA2 Channel2
-                DCD     DMA2_Channel3_IRQHandler     ; DMA2 Channel3
-                DCD     DMA2_Channel4_5_IRQHandler   ; DMA2 Channel4 & Channel5
-                DCD     0                            ; Reserved
-                DCD     USBD2_HP_CAN2_TX_IRQHandler  ; USBD2 High Priority or CAN2 TX
-                DCD     USBD2_LP_CAN2_RX0_IRQHandler ; USBD2 Low  Priority or CAN2 RX0
-                DCD     CAN2_RX1_IRQHandler          ; CAN2 RX1
-                DCD     CAN2_SCE_IRQHandler          ; CAN2 SCE
+AREA    HEAP, NOINIT, READWRITE, ALIGN = 3
+        __heap_base
+        Heap_Mem        SPACE   Heap_Size
+        __heap_limit
+
+        PRESERVE8
+        THUMB
+
+
+        ;
+Vector Table Mapped to Address 0 at Reset
+AREA    RESET, DATA, READONLY
+EXPORT  __Vectors
+EXPORT  __Vectors_End
+EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                 ;
+Top of Stack
+DCD     Reset_Handler                ;
+Reset Handler
+DCD     NMI_Handler                  ;
+NMI Handler
+DCD     HardFault_Handler            ;
+Hard Fault Handler
+DCD     MemManage_Handler            ;
+MPU Fault Handler
+DCD     BusFault_Handler             ;
+Bus Fault Handler
+DCD     UsageFault_Handler           ;
+Usage Fault Handler
+DCD     0                            ;
+Reserved
+DCD     0                            ;
+Reserved
+DCD     0                            ;
+Reserved
+DCD     0                            ;
+Reserved
+DCD     SVC_Handler                  ;
+SVCall Handler
+DCD     DebugMon_Handler             ;
+Debug Monitor Handler
+DCD     0                            ;
+Reserved
+DCD     PendSV_Handler               ;
+PendSV Handler
+DCD     SysTick_Handler              ;
+SysTick Handler
+
+;
+External Interrupts
+DCD     WWDT_IRQHandler              ;
+Window Watchdog
+DCD     PVD_IRQHandler               ;
+PVD through EINT Line detect
+DCD     TAMPER_IRQHandler            ;
+Tamper
+DCD     RTC_IRQHandler               ;
+RTC
+DCD     FLASH_IRQHandler             ;
+Flash
+DCD     RCM_IRQHandler               ;
+RCM
+DCD     EINT0_IRQHandler             ;
+EINT Line 0
+DCD     EINT1_IRQHandler             ;
+EINT Line 1
+DCD     EINT2_IRQHandler             ;
+EINT Line 2
+DCD     EINT3_IRQHandler             ;
+EINT Line 3
+DCD     EINT4_IRQHandler             ;
+EINT Line 4
+DCD     DMA1_Channel1_IRQHandler     ;
+DMA1 Channel 1
+DCD     DMA1_Channel2_IRQHandler     ;
+DMA1 Channel 2
+DCD     DMA1_Channel3_IRQHandler     ;
+DMA1 Channel 3
+DCD     DMA1_Channel4_IRQHandler     ;
+DMA1 Channel 4
+DCD     DMA1_Channel5_IRQHandler     ;
+DMA1 Channel 5
+DCD     DMA1_Channel6_IRQHandler     ;
+DMA1 Channel 6
+DCD     DMA1_Channel7_IRQHandler     ;
+DMA1 Channel 7
+DCD     ADC1_2_IRQHandler            ;
+ADC1 &ADC2
+DCD     USBD1_HP_CAN1_TX_IRQHandler  ;
+USBD1 High Priority or CAN1 TX
+DCD     USBD1_LP_CAN1_RX0_IRQHandler ;
+USBD1 Low  Priority or CAN1 RX0
+DCD     CAN1_RX1_IRQHandler          ;
+CAN1 RX1
+DCD     CAN1_SCE_IRQHandler          ;
+CAN1 SCE
+DCD     EINT9_5_IRQHandler           ;
+EINT Line 9..5
+DCD     TMR1_BRK_IRQHandler          ;
+TMR1 Break
+DCD     TMR1_UP_IRQHandler           ;
+TMR1 Update
+DCD     TMR1_TRG_COM_IRQHandler      ;
+TMR1 Trigger and Commutation
+DCD     TMR1_CC_IRQHandler           ;
+TMR1 Capture Compare
+DCD     TMR2_IRQHandler              ;
+TMR2
+DCD     TMR3_IRQHandler              ;
+TMR3
+DCD     TMR4_IRQHandler              ;
+TMR4
+DCD     I2C1_EV_IRQHandler           ;
+I2C1 Event
+DCD     I2C1_ER_IRQHandler           ;
+I2C1 Error
+DCD     I2C2_EV_IRQHandler           ;
+I2C2 Event
+DCD     I2C2_ER_IRQHandler           ;
+I2C2 Error
+DCD     SPI1_IRQHandler              ;
+SPI1
+DCD     SPI2_IRQHandler              ;
+SPI2
+DCD     USART1_IRQHandler            ;
+USART1
+DCD     USART2_IRQHandler            ;
+USART2
+DCD     USART3_IRQHandler            ;
+USART3
+DCD     EINT15_10_IRQHandler         ;
+EINT Line 15..10
+DCD     RTCAlarm_IRQHandler          ;
+RTC Alarm through EINT Line
+DCD     USBDWakeUp_IRQHandler        ;
+USBD Wakeup from suspend
+DCD     TMR8_BRK_IRQHandler          ;
+TMR8 Break
+DCD     TMR8_UP_IRQHandler           ;
+TMR8 Update
+DCD     TMR8_TRG_COM_IRQHandler      ;
+TMR8 Trigger and Commutation
+DCD     TMR8_CC_IRQHandler           ;
+TMR8 Capture Compare
+DCD     ADC3_IRQHandler              ;
+ADC3
+DCD     EMMC_IRQHandler              ;
+EMMC
+DCD     SDIO_IRQHandler              ;
+SDIO
+DCD     TMR5_IRQHandler              ;
+TMR5
+DCD     SPI3_IRQHandler              ;
+SPI3
+DCD     UART4_IRQHandler             ;
+UART4
+DCD     UART5_IRQHandler             ;
+UART5
+DCD     TMR6_IRQHandler              ;
+TMR6
+DCD     TMR7_IRQHandler              ;
+TMR7
+DCD     DMA2_Channel1_IRQHandler     ;
+DMA2 Channel1
+DCD     DMA2_Channel2_IRQHandler     ;
+DMA2 Channel2
+DCD     DMA2_Channel3_IRQHandler     ;
+DMA2 Channel3
+DCD     DMA2_Channel4_5_IRQHandler   ;
+DMA2 Channel4 &Channel5
+DCD     0                            ;
+Reserved
+DCD     USBD2_HP_CAN2_TX_IRQHandler  ;
+USBD2 High Priority or CAN2 TX
+DCD     USBD2_LP_CAN2_RX0_IRQHandler ;
+USBD2 Low  Priority or CAN2 RX0
+DCD     CAN2_RX1_IRQHandler          ;
+CAN2 RX1
+DCD     CAN2_SCE_IRQHandler          ;
+CAN2 SCE
 __Vectors_End
 
 __Vectors_Size  EQU  __Vectors_End - __Vectors
 
-                AREA    |.text|, CODE, READONLY
+AREA    | .text |, CODE, READONLY
 
-; Reset handler
+;
+Reset handler
 Reset_Handler   PROC
-                EXPORT  Reset_Handler                [WEAK]
-                IMPORT  __main
-                IMPORT  SystemInit
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
+EXPORT  Reset_Handler                [WEAK]
+IMPORT  __main
+IMPORT  SystemInit
+LDR     R0, = SystemInit
+              BLX     R0
+              LDR     R0, = __main
+                            BX      R0
+                            ENDP
+
+                            ;
+Dummy Exception Handlers(infinite loops which can be modified)
 
 NMI_Handler     PROC
-                EXPORT  NMI_Handler                  [WEAK]
-                B       .
-                ENDP
+EXPORT  NMI_Handler                  [WEAK]
+B       .
+ENDP
 HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler            [WEAK]
-                B       .
-                ENDP
+PROC
+EXPORT  HardFault_Handler            [WEAK]
+B       .
+ENDP
 MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler            [WEAK]
-                B       .
-                ENDP
+PROC
+EXPORT  MemManage_Handler            [WEAK]
+B       .
+ENDP
 BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler             [WEAK]
-                B       .
-                ENDP
+PROC
+EXPORT  BusFault_Handler             [WEAK]
+B       .
+ENDP
 UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler           [WEAK]
-                B       .
-                ENDP
+PROC
+EXPORT  UsageFault_Handler           [WEAK]
+B       .
+ENDP
 SVC_Handler     PROC
-                EXPORT  SVC_Handler                  [WEAK]
-                B       .
-                ENDP
+EXPORT  SVC_Handler                  [WEAK]
+B       .
+ENDP
 DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler             [WEAK]
-                B       .
-                ENDP
+PROC
+EXPORT  DebugMon_Handler             [WEAK]
+B       .
+ENDP
 PendSV_Handler  PROC
-                EXPORT  PendSV_Handler               [WEAK]
-                B       .
-                ENDP
+EXPORT  PendSV_Handler               [WEAK]
+B       .
+ENDP
 SysTick_Handler PROC
-                EXPORT  SysTick_Handler              [WEAK]
-                B       .
-                ENDP
+EXPORT  SysTick_Handler              [WEAK]
+B       .
+ENDP
 
 Default_Handler PROC
 
-                EXPORT  WWDT_IRQHandler              [WEAK]
-                EXPORT  PVD_IRQHandler               [WEAK]
-                EXPORT  TAMPER_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler               [WEAK]
-                EXPORT  FMC_IRQHandler               [WEAK]
-                EXPORT  RCM_IRQHandler               [WEAK]
-                EXPORT  EINT0_IRQHandler             [WEAK]
-                EXPORT  EINT1_IRQHandler             [WEAK]
-                EXPORT  EINT2_IRQHandler             [WEAK]
-                EXPORT  EINT3_IRQHandler             [WEAK]
-                EXPORT  EINT4_IRQHandler             [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler     [WEAK]
-                EXPORT  ADC1_2_IRQHandler            [WEAK]
-                EXPORT  USBD1_HP_CAN1_TX_IRQHandler  [WEAK]
-                EXPORT  USBD1_LP_CAN1_RX0_IRQHandler [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler          [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler          [WEAK]
-                EXPORT  EINT9_5_IRQHandler           [WEAK]
-                EXPORT  TMR1_BRK_IRQHandler          [WEAK]
-                EXPORT  TMR1_UP_IRQHandler           [WEAK]
-                EXPORT  TMR1_TRG_COM_IRQHandler      [WEAK]
-                EXPORT  TMR1_CC_IRQHandler           [WEAK]
-                EXPORT  TMR2_IRQHandler              [WEAK]
-                EXPORT  TMR3_IRQHandler              [WEAK]
-                EXPORT  TMR4_IRQHandler              [WEAK]
-                EXPORT  I2C1_EV_IRQHandler           [WEAK]
-                EXPORT  I2C1_ER_IRQHandler           [WEAK]
-                EXPORT  I2C2_EV_IRQHandler           [WEAK]
-                EXPORT  I2C2_ER_IRQHandler           [WEAK]
-                EXPORT  SPI1_IRQHandler              [WEAK]
-                EXPORT  SPI2_IRQHandler              [WEAK]
-                EXPORT  USART1_IRQHandler            [WEAK]
-                EXPORT  USART2_IRQHandler            [WEAK]
-                EXPORT  USART3_IRQHandler            [WEAK]
-                EXPORT  EINT15_10_IRQHandler         [WEAK]
-                EXPORT  RTCAlarm_IRQHandler          [WEAK]
-                EXPORT  USBDWakeUp_IRQHandler        [WEAK]
-                EXPORT  TMR8_BRK_IRQHandler          [WEAK]
-                EXPORT  TMR8_UP_IRQHandler           [WEAK]
-                EXPORT  TMR8_TRG_COM_IRQHandler      [WEAK]
-                EXPORT  TMR8_CC_IRQHandler           [WEAK]
-                EXPORT  ADC3_IRQHandler              [WEAK]
-                EXPORT  EMMC_IRQHandler              [WEAK]
-                EXPORT  SDIO_IRQHandler              [WEAK]
-                EXPORT  TMR5_IRQHandler              [WEAK]
-                EXPORT  SPI3_IRQHandler              [WEAK]
-                EXPORT  UART4_IRQHandler             [WEAK]
-                EXPORT  UART5_IRQHandler             [WEAK]
-                EXPORT  TMR6_IRQHandler              [WEAK]
-                EXPORT  TMR7_IRQHandler              [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler     [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler     [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler     [WEAK]
-                EXPORT  DMA2_Channel4_5_IRQHandler   [WEAK]
-                EXPORT  USBD2_HP_CAN2_TX_IRQHandler  [WEAK]
-                EXPORT  USBD2_LP_CAN2_RX0_IRQHandler [WEAK]
-                EXPORT  CAN2_RX1_IRQHandler          [WEAK]
-                EXPORT  CAN2_SCE_IRQHandler          [WEAK]
+EXPORT  WWDT_IRQHandler              [WEAK]
+EXPORT  PVD_IRQHandler               [WEAK]
+EXPORT  TAMPER_IRQHandler            [WEAK]
+EXPORT  RTC_IRQHandler               [WEAK]
+EXPORT  FLASH_IRQHandler             [WEAK]
+EXPORT  RCM_IRQHandler               [WEAK]
+EXPORT  EINT0_IRQHandler             [WEAK]
+EXPORT  EINT1_IRQHandler             [WEAK]
+EXPORT  EINT2_IRQHandler             [WEAK]
+EXPORT  EINT3_IRQHandler             [WEAK]
+EXPORT  EINT4_IRQHandler             [WEAK]
+EXPORT  DMA1_Channel1_IRQHandler     [WEAK]
+EXPORT  DMA1_Channel2_IRQHandler     [WEAK]
+EXPORT  DMA1_Channel3_IRQHandler     [WEAK]
+EXPORT  DMA1_Channel4_IRQHandler     [WEAK]
+EXPORT  DMA1_Channel5_IRQHandler     [WEAK]
+EXPORT  DMA1_Channel6_IRQHandler     [WEAK]
+EXPORT  DMA1_Channel7_IRQHandler     [WEAK]
+EXPORT  ADC1_2_IRQHandler            [WEAK]
+EXPORT  USBD1_HP_CAN1_TX_IRQHandler  [WEAK]
+EXPORT  USBD1_LP_CAN1_RX0_IRQHandler [WEAK]
+EXPORT  CAN1_RX1_IRQHandler          [WEAK]
+EXPORT  CAN1_SCE_IRQHandler          [WEAK]
+EXPORT  EINT9_5_IRQHandler           [WEAK]
+EXPORT  TMR1_BRK_IRQHandler          [WEAK]
+EXPORT  TMR1_UP_IRQHandler           [WEAK]
+EXPORT  TMR1_TRG_COM_IRQHandler      [WEAK]
+EXPORT  TMR1_CC_IRQHandler           [WEAK]
+EXPORT  TMR2_IRQHandler              [WEAK]
+EXPORT  TMR3_IRQHandler              [WEAK]
+EXPORT  TMR4_IRQHandler              [WEAK]
+EXPORT  I2C1_EV_IRQHandler           [WEAK]
+EXPORT  I2C1_ER_IRQHandler           [WEAK]
+EXPORT  I2C2_EV_IRQHandler           [WEAK]
+EXPORT  I2C2_ER_IRQHandler           [WEAK]
+EXPORT  SPI1_IRQHandler              [WEAK]
+EXPORT  SPI2_IRQHandler              [WEAK]
+EXPORT  USART1_IRQHandler            [WEAK]
+EXPORT  USART2_IRQHandler            [WEAK]
+EXPORT  USART3_IRQHandler            [WEAK]
+EXPORT  EINT15_10_IRQHandler         [WEAK]
+EXPORT  RTCAlarm_IRQHandler          [WEAK]
+EXPORT  USBDWakeUp_IRQHandler        [WEAK]
+EXPORT  TMR8_BRK_IRQHandler          [WEAK]
+EXPORT  TMR8_UP_IRQHandler           [WEAK]
+EXPORT  TMR8_TRG_COM_IRQHandler      [WEAK]
+EXPORT  TMR8_CC_IRQHandler           [WEAK]
+EXPORT  ADC3_IRQHandler              [WEAK]
+EXPORT  EMMC_IRQHandler              [WEAK]
+EXPORT  SDIO_IRQHandler              [WEAK]
+EXPORT  TMR5_IRQHandler              [WEAK]
+EXPORT  SPI3_IRQHandler              [WEAK]
+EXPORT  UART4_IRQHandler             [WEAK]
+EXPORT  UART5_IRQHandler             [WEAK]
+EXPORT  TMR6_IRQHandler              [WEAK]
+EXPORT  TMR7_IRQHandler              [WEAK]
+EXPORT  DMA2_Channel1_IRQHandler     [WEAK]
+EXPORT  DMA2_Channel2_IRQHandler     [WEAK]
+EXPORT  DMA2_Channel3_IRQHandler     [WEAK]
+EXPORT  DMA2_Channel4_5_IRQHandler   [WEAK]
+EXPORT  USBD2_HP_CAN2_TX_IRQHandler  [WEAK]
+EXPORT  USBD2_LP_CAN2_RX0_IRQHandler [WEAK]
+EXPORT  CAN2_RX1_IRQHandler          [WEAK]
+EXPORT  CAN2_SCE_IRQHandler          [WEAK]
 
 WWDT_IRQHandler
 PVD_IRQHandler
 TAMPER_IRQHandler
 RTC_IRQHandler
-FMC_IRQHandler
+FLASH_IRQHandler
 RCM_IRQHandler
 EINT0_IRQHandler
 EINT1_IRQHandler
@@ -316,39 +421,45 @@ USBD2_HP_CAN2_TX_IRQHandler
 USBD2_LP_CAN2_RX0_IRQHandler
 CAN2_RX1_IRQHandler
 CAN2_SCE_IRQHandler
-                B       .
+B       .
 
-                ENDP
+ENDP
 
-                ALIGN
+ALIGN
 
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
+;
+*******************************************************************************
+;
+User Stack and Heap initialization
+;
+*******************************************************************************
+IF      :
+DEF:
+__MICROLIB
 
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
+EXPORT  __initial_sp
+EXPORT  __heap_base
+EXPORT  __heap_limit
 
-                 ELSE
+ELSE
 
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
+IMPORT  __use_two_region_memory
+EXPORT  __user_initial_stackheap
 
 __user_initial_stackheap
 
-                 LDR     R0, = Heap_Mem
-                 LDR     R1, = (Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem  + Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
+LDR     R0, = Heap_Mem
+              LDR     R1, = (Stack_Mem + Stack_Size)
+                            LDR     R2, = (Heap_Mem  + Heap_Size)
+                                    LDR     R3, = Stack_Mem
+                                            BX      LR
 
-                 ALIGN
+                                            ALIGN
 
-                 ENDIF
+                                            ENDIF
 
-                 END
+                                            END
 
-;*******************************END OF FILE************************************
+                                            ;
+*******************************END OF FILE ************************************
 

bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_md.s

@@ -1,227 +1,314 @@
 ;/*!
-; * @file       startup_apm32f10x_md.s
+; * @file        startup_apm32f10x_md.s
 ; *
-; * @brief      CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_md
+; * @brief       CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_md
 ; *
-; * @version    V1.0.1
+; * @version     V1.0.2
 ; *
-; * @date       2021-03-23
+; * @date        2022-01-05
 ; *
+; * @attention
+; *
+; *  Copyright (C) 2020-2022 Geehy Semiconductor
+; *
+; *  You may not use this file except in compliance with the
+; *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+; *
+; *  The program is only for reference, which is distributed in the hope
+; *  that it will be usefull and instructional for customers to develop
+; *  their software. Unless required by applicable law or agreed to in
+; *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+; *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+; *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+; *  and limitations under the License.
 ; */
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;
+<h> Stack Configuration
+;
+<o> Stack Size(in Bytes) < 0x0 - 0xFFFFFFFF: 8 >
+;
+< / h >
 
 Stack_Size      EQU     0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
+AREA    STACK, NOINIT, READWRITE, ALIGN = 3
+        Stack_Mem       SPACE   Stack_Size
+        __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+        ;
+<h> Heap Configuration
+;
+<o>  Heap Size(in Bytes) < 0x0 - 0xFFFFFFFF: 8 >
+;
+< / h >
 
 Heap_Size       EQU     0x00000200
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                 ; Top of Stack
-                DCD     Reset_Handler                ; Reset Handler
-                DCD     NMI_Handler                  ; NMI Handler
-                DCD     HardFault_Handler            ; Hard Fault Handler
-                DCD     MemManage_Handler            ; MPU Fault Handler
-                DCD     BusFault_Handler             ; Bus Fault Handler
-                DCD     UsageFault_Handler           ; Usage Fault Handler
-                DCD     0                            ; Reserved
-                DCD     0                            ; Reserved
-                DCD     0                            ; Reserved
-                DCD     0                            ; Reserved
-                DCD     SVC_Handler                  ; SVCall Handler
-                DCD     DebugMon_Handler             ; Debug Monitor Handler
-                DCD     0                            ; Reserved
-                DCD     PendSV_Handler               ; PendSV Handler
-                DCD     SysTick_Handler              ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDT_IRQHandler              ; Window Watchdog
-                DCD     PVD_IRQHandler               ; PVD through EINT Line detect
-                DCD     TAMPER_IRQHandler            ; Tamper
-                DCD     RTC_IRQHandler               ; RTC
-                DCD     FMC_IRQHandler               ; Flash
-                DCD     RCM_IRQHandler               ; RCM
-                DCD     EINT0_IRQHandler             ; EINT Line 0
-                DCD     EINT1_IRQHandler             ; EINT Line 1
-                DCD     EINT2_IRQHandler             ; EINT Line 2
-                DCD     EINT3_IRQHandler             ; EINT Line 3
-                DCD     EINT4_IRQHandler             ; EINT Line 4
-                DCD     DMA1_Channel1_IRQHandler     ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler     ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler     ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler     ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler     ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler     ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler     ; DMA1 Channel 7
-                DCD     ADC1_2_IRQHandler            ; ADC1_2
-                DCD     USBD1_HP_CAN1_TX_IRQHandler  ; USBD1 High Priority or CAN1 TX
-                DCD     USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low  Priority or CAN1 RX0
-                DCD     CAN1_RX1_IRQHandler          ; CAN1 RX1
-                DCD     CAN1_SCE_IRQHandler          ; CAN1 SCE
-                DCD     EINT9_5_IRQHandler           ; EINT Line 9..5
-                DCD     TMR1_BRK_IRQHandler          ; TMR1 Break
-                DCD     TMR1_UP_IRQHandler           ; TMR1 Update
-                DCD     TMR1_TRG_COM_IRQHandler      ; TMR1 Trigger and Commutation
-                DCD     TMR1_CC_IRQHandler           ; TMR1 Capture Compare
-                DCD     TMR2_IRQHandler              ; TMR2
-                DCD     TMR3_IRQHandler              ; TMR3
-                DCD     TMR4_IRQHandler              ; TMR4
-                DCD     I2C1_EV_IRQHandler           ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler           ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler           ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler           ; I2C2 Error
-                DCD     SPI1_IRQHandler              ; SPI1
-                DCD     SPI2_IRQHandler              ; SPI2
-                DCD     USART1_IRQHandler            ; USART1
-                DCD     USART2_IRQHandler            ; USART2
-                DCD     USART3_IRQHandler            ; USART3
-                DCD     EINT15_10_IRQHandler         ; EINT Line 15..10
-                DCD     RTCAlarm_IRQHandler          ; RTC Alarm through EINT Line
-                DCD     USBDWakeUp_IRQHandler        ; USBD Wakeup from suspend
-                DCD     FPU_IRQHandler               ; FPU
-                DCD     QSPI_IRQHandler              ; QSPI
-                DCD     USBD2_HP_IRQHandler          ; USBD2 High Priority
-                DCD     USBD2_LP_IRQHandler          ; USBD2 Low Priority
+AREA    HEAP, NOINIT, READWRITE, ALIGN = 3
+        __heap_base
+        Heap_Mem        SPACE   Heap_Size
+        __heap_limit
+
+        PRESERVE8
+        THUMB
+
+
+        ;
+Vector Table Mapped to Address 0 at Reset
+AREA    RESET, DATA, READONLY
+EXPORT  __Vectors
+EXPORT  __Vectors_End
+EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                 ;
+Top of Stack
+DCD     Reset_Handler                ;
+Reset Handler
+DCD     NMI_Handler                  ;
+NMI Handler
+DCD     HardFault_Handler            ;
+Hard Fault Handler
+DCD     MemManage_Handler            ;
+MPU Fault Handler
+DCD     BusFault_Handler             ;
+Bus Fault Handler
+DCD     UsageFault_Handler           ;
+Usage Fault Handler
+DCD     0                            ;
+Reserved
+DCD     0                            ;
+Reserved
+DCD     0                            ;
+Reserved
+DCD     0                            ;
+Reserved
+DCD     SVC_Handler                  ;
+SVCall Handler
+DCD     DebugMon_Handler             ;
+Debug Monitor Handler
+DCD     0                            ;
+Reserved
+DCD     PendSV_Handler               ;
+PendSV Handler
+DCD     SysTick_Handler              ;
+SysTick Handler
+
+;
+External Interrupts
+DCD     WWDT_IRQHandler              ;
+Window Watchdog
+DCD     PVD_IRQHandler               ;
+PVD through EINT Line detect
+DCD     TAMPER_IRQHandler            ;
+Tamper
+DCD     RTC_IRQHandler               ;
+RTC
+DCD     FLASH_IRQHandler             ;
+Flash
+DCD     RCM_IRQHandler               ;
+RCM
+DCD     EINT0_IRQHandler             ;
+EINT Line 0
+DCD     EINT1_IRQHandler             ;
+EINT Line 1
+DCD     EINT2_IRQHandler             ;
+EINT Line 2
+DCD     EINT3_IRQHandler             ;
+EINT Line 3
+DCD     EINT4_IRQHandler             ;
+EINT Line 4
+DCD     DMA1_Channel1_IRQHandler     ;
+DMA1 Channel 1
+DCD     DMA1_Channel2_IRQHandler     ;
+DMA1 Channel 2
+DCD     DMA1_Channel3_IRQHandler     ;
+DMA1 Channel 3
+DCD     DMA1_Channel4_IRQHandler     ;
+DMA1 Channel 4
+DCD     DMA1_Channel5_IRQHandler     ;
+DMA1 Channel 5
+DCD     DMA1_Channel6_IRQHandler     ;
+DMA1 Channel 6
+DCD     DMA1_Channel7_IRQHandler     ;
+DMA1 Channel 7
+DCD     ADC1_2_IRQHandler            ;
+ADC1_2
+DCD     USBD1_HP_CAN1_TX_IRQHandler  ;
+USBD1 High Priority or CAN1 TX
+DCD     USBD1_LP_CAN1_RX0_IRQHandler ;
+USBD1 Low  Priority or CAN1 RX0
+DCD     CAN1_RX1_IRQHandler          ;
+CAN1 RX1
+DCD     CAN1_SCE_IRQHandler          ;
+CAN1 SCE
+DCD     EINT9_5_IRQHandler           ;
+EINT Line 9..5
+DCD     TMR1_BRK_IRQHandler          ;
+TMR1 Break
+DCD     TMR1_UP_IRQHandler           ;
+TMR1 Update
+DCD     TMR1_TRG_COM_IRQHandler      ;
+TMR1 Trigger and Commutation
+DCD     TMR1_CC_IRQHandler           ;
+TMR1 Capture Compare
+DCD     TMR2_IRQHandler              ;
+TMR2
+DCD     TMR3_IRQHandler              ;
+TMR3
+DCD     TMR4_IRQHandler              ;
+TMR4
+DCD     I2C1_EV_IRQHandler           ;
+I2C1 Event
+DCD     I2C1_ER_IRQHandler           ;
+I2C1 Error
+DCD     I2C2_EV_IRQHandler           ;
+I2C2 Event
+DCD     I2C2_ER_IRQHandler           ;
+I2C2 Error
+DCD     SPI1_IRQHandler              ;
+SPI1
+DCD     SPI2_IRQHandler              ;
+SPI2
+DCD     USART1_IRQHandler            ;
+USART1
+DCD     USART2_IRQHandler            ;
+USART2
+DCD     USART3_IRQHandler            ;
+USART3
+DCD     EINT15_10_IRQHandler         ;
+EINT Line 15..10
+DCD     RTCAlarm_IRQHandler          ;
+RTC Alarm through EINT Line
+DCD     USBDWakeUp_IRQHandler        ;
+USBD Wakeup from suspend
+DCD     FPU_IRQHandler               ;
+FPU
+DCD     QSPI_IRQHandler              ;
+QSPI
+DCD     USBD2_HP_IRQHandler          ;
+USBD2 High Priority
+DCD     USBD2_LP_IRQHandler          ;
+USBD2 Low Priority
 __Vectors_End
 
 __Vectors_Size  EQU  __Vectors_End - __Vectors
 
-                AREA    |.text|, CODE, READONLY
+AREA    | .text |, CODE, READONLY
 
-; Reset handler
+;
+Reset handler
 Reset_Handler    PROC
-                 EXPORT  Reset_Handler               [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
+EXPORT  Reset_Handler               [WEAK]
+IMPORT  __main
+IMPORT  SystemInit
+LDR     R0, = SystemInit
+              BLX     R0
+              LDR     R0, = __main
+                            BX      R0
+                            ENDP
+
+                            ;
+Dummy Exception Handlers(infinite loops which can be modified)
 
 NMI_Handler     PROC
-                EXPORT  NMI_Handler                  [WEAK]
-                B       .
-                ENDP
+EXPORT  NMI_Handler                  [WEAK]
+B       .
+ENDP
 HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler            [WEAK]
-                B       .
-                ENDP
+PROC
+EXPORT  HardFault_Handler            [WEAK]
+B       .
+ENDP
 MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler            [WEAK]
-                B       .
-                ENDP
+PROC
+EXPORT  MemManage_Handler            [WEAK]
+B       .
+ENDP
 BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler             [WEAK]
-                B       .
-                ENDP
+PROC
+EXPORT  BusFault_Handler             [WEAK]
+B       .
+ENDP
 UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler           [WEAK]
-                B       .
-                ENDP
+PROC
+EXPORT  UsageFault_Handler           [WEAK]
+B       .
+ENDP
 SVC_Handler     PROC
-                EXPORT  SVC_Handler                  [WEAK]
-                B       .
-                ENDP
+EXPORT  SVC_Handler                  [WEAK]
+B       .
+ENDP
 DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler             [WEAK]
-                B       .
-                ENDP
+PROC
+EXPORT  DebugMon_Handler             [WEAK]
+B       .
+ENDP
 PendSV_Handler  PROC
-                EXPORT  PendSV_Handler               [WEAK]
-                B       .
-                ENDP
+EXPORT  PendSV_Handler               [WEAK]
+B       .
+ENDP
 SysTick_Handler PROC
-                EXPORT  SysTick_Handler              [WEAK]
-                B       .
-                ENDP
+EXPORT  SysTick_Handler              [WEAK]
+B       .
+ENDP
 
 Default_Handler PROC
 
-                EXPORT  WWDT_IRQHandler              [WEAK]
-                EXPORT  PVD_IRQHandler               [WEAK]
-                EXPORT  TAMPER_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler               [WEAK]
-                EXPORT  FMC_IRQHandler               [WEAK]
-                EXPORT  RCM_IRQHandler               [WEAK]
-                EXPORT  EINT0_IRQHandler             [WEAK]
-                EXPORT  EINT1_IRQHandler             [WEAK]
-                EXPORT  EINT2_IRQHandler             [WEAK]
-                EXPORT  EINT3_IRQHandler             [WEAK]
-                EXPORT  EINT4_IRQHandler             [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler     [WEAK]
-                EXPORT  ADC1_2_IRQHandler            [WEAK]
-                EXPORT  USBD1_HP_CAN1_TX_IRQHandler  [WEAK]
-                EXPORT  USBD1_LP_CAN1_RX0_IRQHandler [WEAK]
-                EXPORT  CAN1_RX1_IRQHandler          [WEAK]
-                EXPORT  CAN1_SCE_IRQHandler          [WEAK]
-                EXPORT  EINT9_5_IRQHandler           [WEAK]
-                EXPORT  TMR1_BRK_IRQHandler          [WEAK]
-                EXPORT  TMR1_UP_IRQHandler           [WEAK]
-                EXPORT  TMR1_TRG_COM_IRQHandler      [WEAK]
-                EXPORT  TMR1_CC_IRQHandler           [WEAK]
-                EXPORT  TMR2_IRQHandler              [WEAK]
-                EXPORT  TMR3_IRQHandler              [WEAK]
-                EXPORT  TMR4_IRQHandler              [WEAK]
-                EXPORT  I2C1_EV_IRQHandler           [WEAK]
-                EXPORT  I2C1_ER_IRQHandler           [WEAK]
-                EXPORT  I2C2_EV_IRQHandler           [WEAK]
-                EXPORT  I2C2_ER_IRQHandler           [WEAK]
-                EXPORT  SPI1_IRQHandler              [WEAK]
-                EXPORT  SPI2_IRQHandler              [WEAK]
-                EXPORT  USART1_IRQHandler            [WEAK]
-                EXPORT  USART2_IRQHandler            [WEAK]
-                EXPORT  USART3_IRQHandler            [WEAK]
-                EXPORT  EINT15_10_IRQHandler         [WEAK]
-                EXPORT  RTCAlarm_IRQHandler          [WEAK]
-                EXPORT  USBDWakeUp_IRQHandler        [WEAK]
-                EXPORT  FPU_IRQHandler               [WEAK]
-                EXPORT  QSPI_IRQHandler              [WEAK]
-                EXPORT  USBD2_HP_IRQHandler          [WEAK]
-                EXPORT  USBD2_LP_IRQHandler          [WEAK]
+EXPORT  WWDT_IRQHandler              [WEAK]
+EXPORT  PVD_IRQHandler               [WEAK]
+EXPORT  TAMPER_IRQHandler            [WEAK]
+EXPORT  RTC_IRQHandler               [WEAK]
+EXPORT  FLASH_IRQHandler             [WEAK]
+EXPORT  RCM_IRQHandler               [WEAK]
+EXPORT  EINT0_IRQHandler             [WEAK]
+EXPORT  EINT1_IRQHandler             [WEAK]
+EXPORT  EINT2_IRQHandler             [WEAK]
+EXPORT  EINT3_IRQHandler             [WEAK]
+EXPORT  EINT4_IRQHandler             [WEAK]
+EXPORT  DMA1_Channel1_IRQHandler     [WEAK]
+EXPORT  DMA1_Channel2_IRQHandler     [WEAK]
+EXPORT  DMA1_Channel3_IRQHandler     [WEAK]
+EXPORT  DMA1_Channel4_IRQHandler     [WEAK]
+EXPORT  DMA1_Channel5_IRQHandler     [WEAK]
+EXPORT  DMA1_Channel6_IRQHandler     [WEAK]
+EXPORT  DMA1_Channel7_IRQHandler     [WEAK]
+EXPORT  ADC1_2_IRQHandler            [WEAK]
+EXPORT  USBD1_HP_CAN1_TX_IRQHandler  [WEAK]
+EXPORT  USBD1_LP_CAN1_RX0_IRQHandler [WEAK]
+EXPORT  CAN1_RX1_IRQHandler          [WEAK]
+EXPORT  CAN1_SCE_IRQHandler          [WEAK]
+EXPORT  EINT9_5_IRQHandler           [WEAK]
+EXPORT  TMR1_BRK_IRQHandler          [WEAK]
+EXPORT  TMR1_UP_IRQHandler           [WEAK]
+EXPORT  TMR1_TRG_COM_IRQHandler      [WEAK]
+EXPORT  TMR1_CC_IRQHandler           [WEAK]
+EXPORT  TMR2_IRQHandler              [WEAK]
+EXPORT  TMR3_IRQHandler              [WEAK]
+EXPORT  TMR4_IRQHandler              [WEAK]
+EXPORT  I2C1_EV_IRQHandler           [WEAK]
+EXPORT  I2C1_ER_IRQHandler           [WEAK]
+EXPORT  I2C2_EV_IRQHandler           [WEAK]
+EXPORT  I2C2_ER_IRQHandler           [WEAK]
+EXPORT  SPI1_IRQHandler              [WEAK]
+EXPORT  SPI2_IRQHandler              [WEAK]
+EXPORT  USART1_IRQHandler            [WEAK]
+EXPORT  USART2_IRQHandler            [WEAK]
+EXPORT  USART3_IRQHandler            [WEAK]
+EXPORT  EINT15_10_IRQHandler         [WEAK]
+EXPORT  RTCAlarm_IRQHandler          [WEAK]
+EXPORT  USBDWakeUp_IRQHandler        [WEAK]
+EXPORT  FPU_IRQHandler               [WEAK]
+EXPORT  QSPI_IRQHandler              [WEAK]
+EXPORT  USBD2_HP_IRQHandler          [WEAK]
+EXPORT  USBD2_LP_IRQHandler          [WEAK]
 
 WWDT_IRQHandler
 PVD_IRQHandler
 TAMPER_IRQHandler
 RTC_IRQHandler
-FMC_IRQHandler
+FLASH_IRQHandler
 RCM_IRQHandler
 EINT0_IRQHandler
 EINT1_IRQHandler
@@ -264,38 +351,44 @@ FPU_IRQHandler
 QSPI_IRQHandler
 USBD2_HP_IRQHandler
 USBD2_LP_IRQHandler
-                B       .
+B       .
 
-                ENDP
+ENDP
 
-                ALIGN
+ALIGN
 
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
+;
+*******************************************************************************
+;
+User Stack and Heap initialization
+;
+*******************************************************************************
+IF      :
+DEF:
+__MICROLIB
 
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
+EXPORT  __initial_sp
+EXPORT  __heap_base
+EXPORT  __heap_limit
 
-                 ELSE
+ELSE
 
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
+IMPORT  __use_two_region_memory
+EXPORT  __user_initial_stackheap
 
 __user_initial_stackheap
 
-                 LDR     R0, = Heap_Mem
-                 LDR     R1, = (Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem  + Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
+LDR     R0, = Heap_Mem
+              LDR     R1, = (Stack_Mem + Stack_Size)
+                            LDR     R2, = (Heap_Mem  + Heap_Size)
+                                    LDR     R3, = Stack_Mem
+                                            BX      LR
 
-                 ALIGN
+                                            ALIGN
 
-                 ENDIF
+                                            ENDIF
 
-                 END
+                                            END
 
-;*******************************END OF FILE************************************
+                                            ;
+*******************************END OF FILE ************************************

bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s

@@ -0,0 +1,281 @@
+;/*!
+; * @file        startup_apm32f10x_hd.s
+; *
+; * @brief       CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd
+; *
+; * @version     V1.0.0
+; *
+; * @date        2022-01-05
+; *
+; * @attention
+; *
+; *  Copyright (C) 2020-2022 Geehy Semiconductor
+; *
+; *  You may not use this file except in compliance with the
+; *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+; *
+; *  The program is only for reference, which is distributed in the hope
+; *  that it will be usefull and instructional for customers to develop
+; *  their software. Unless required by applicable law or agreed to in
+; *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+; *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+; *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+; *  and limitations under the License.
+; */
+
+.syntax unified
+.cpu cortex - m3
+.fpu softvfp
+.thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+.section  .isr_vector, "a", % progbits
+.type  g_pfnVectors, % object
+
+g_pfnVectors:
+.word     _estack                           // Top of Stack
+.word     Reset_Handler                     // Reset Handler
+.word     NMI_Handler                       // NMI Handler
+.word     HardFault_Handler                 // Hard Fault Handler
+.word     MemManage_Handler                 // MPU Fault Handler
+.word     BusFault_Handler                  // Bus Fault Handler
+.word     UsageFault_Handler                // Usage Fault Handler
+.word     0                                 // Reserved
+.word     0                                 // Reserved
+.word     0                                 // Reserved
+.word     0                                 // Reserved
+.word     SVC_Handler                       // SVCall Handler
+.word     DebugMon_Handler                  // Debug Monitor Handler
+.word     0                                 // Reserved
+.word     PendSV_Handler                    // PendSV Handler
+.word     SysTick_Handler                   // SysTick Handler
+
+// external interrupts handler
+.word     WWDT_IRQHandler                    // Window Watchdog
+.word     PVD_IRQHandler                     // PVD through EINT Line detect
+.word     TAMPER_IRQHandler                  // Tamper
+.word     RTC_IRQHandler                     // RTC
+.word     FLASH_IRQHandler                   // Flash
+.word     RCM_IRQHandler                     // RCM
+.word     EINT0_IRQHandler                   // EINT Line 0
+.word     EINT1_IRQHandler                   // EINT Line 1
+.word     EINT2_IRQHandler                   // EINT Line 2
+.word     EINT3_IRQHandler                   // EINT Line 3
+.word     EINT4_IRQHandler                   // EINT Line 4
+.word     DMA1_Channel1_IRQHandler           // DMA1 Channel 1
+.word     DMA1_Channel2_IRQHandler           // DMA1 Channel 2
+.word     DMA1_Channel3_IRQHandler           // DMA1 Channel 3
+.word     DMA1_Channel4_IRQHandler           // DMA1 Channel 4
+.word     DMA1_Channel5_IRQHandler           // DMA1 Channel 5
+.word     DMA1_Channel6_IRQHandler           // DMA1 Channel 6
+.word     DMA1_Channel7_IRQHandler           // DMA1 Channel 7
+.word     ADC1_2_IRQHandler                  // ADC1 & ADC2
+.word     USBD1_HP_CAN1_TX_IRQHandler        // USBD1 High Priority or CAN1 TX
+.word     USBD1_LP_CAN1_RX0_IRQHandler       // USBD1 Low  Priority or CAN1 RX0
+.word     CAN1_RX1_IRQHandler                // CAN1 RX1
+.word     CAN1_SCE_IRQHandler                // CAN1 SCE
+.word     EINT9_5_IRQHandler                 // EINT Line 9..5
+.word     TMR1_BRK_IRQHandler                // TMR1 Break
+.word     TMR1_UP_IRQHandler                 // TMR1 Update
+.word     TMR1_TRG_COM_IRQHandler            // TMR1 Trigger and Commutation
+.word     TMR1_CC_IRQHandler                 // TMR1 Capture Compare
+.word     TMR2_IRQHandler                    // TMR2
+.word     TMR3_IRQHandler                    // TMR3
+.word     TMR4_IRQHandler                    // TMR4
+.word     I2C1_EV_IRQHandler                 // I2C1 Event
+.word     I2C1_ER_IRQHandler                 // I2C1 Error
+.word     I2C2_EV_IRQHandler                 // I2C2 Event
+.word     I2C2_ER_IRQHandler                 // I2C2 Error
+.word     SPI1_IRQHandler                    // SPI1
+.word     SPI2_IRQHandler                    // SPI2
+.word     USART1_IRQHandler                  // USART1
+.word     USART2_IRQHandler                  // USART2
+.word     USART3_IRQHandler                  // USART3
+.word     EINT15_10_IRQHandler               // EINT Line 15..10
+.word     RTCAlarm_IRQHandler                // RTC Alarm through EINT Line
+.word     USBDWakeUp_IRQHandler              // USBD Wakeup from suspend
+.word     TMR8_BRK_IRQHandler                // TMR8 Break
+.word     TMR8_UP_IRQHandler                 // TMR8 Update
+.word     TMR8_TRG_COM_IRQHandler            // TMR8 Trigger and Commutation
+.word     TMR8_CC_IRQHandler                 // TMR8 Capture Compare
+.word     ADC3_IRQHandler                    // ADC3
+.word     EMMC_IRQHandler                    // EMMC
+.word     SDIO_IRQHandler                    // SDIO
+.word     TMR5_IRQHandler                    // TMR5
+.word     SPI3_IRQHandler                    // SPI3
+.word     UART4_IRQHandler                   // UART4
+.word     UART5_IRQHandler                   // UART5
+.word     TMR6_IRQHandler                    // TMR6
+.word     TMR7_IRQHandler                    // TMR7
+.word     DMA2_Channel1_IRQHandler           // DMA2 Channel1
+.word     DMA2_Channel2_IRQHandler           // DMA2 Channel2
+.word     DMA2_Channel3_IRQHandler           // DMA2 Channel3
+.word     DMA2_Channel4_5_IRQHandler         // DMA2 Channel4 & Channel5
+.word     0                                  // Reserved
+.word     USBD2_HP_CAN2_TX_IRQHandler        // USBD2 High Priority or CAN2 TX
+.word     USBD2_LP_CAN2_RX0_IRQHandler       // USBD2 Low  Priority or CAN2 RX0
+.word     CAN2_RX1_IRQHandler                // CAN2 RX1
+.word     CAN2_SCE_IRQHandler                // CAN2 SCE
+
+.size  g_pfnVectors, . - g_pfnVectors
+
+.section  .text.Reset_Handler
+.weak  Reset_Handler
+.type  Reset_Handler, % function
+Reset_Handler:
+ldr r1, = _sidata
+          ldr r2, = _sdata
+                    ldr r3, = _edata
+
+                              subs r3, r2
+                              ble fill_bss_start
+
+                              loop_copy_data:
+                              subs r3, #4
+                              ldr r0, [r1, r3]
+                              str r0, [r2, r3]
+                              bgt loop_copy_data
+
+                              fill_bss_start:
+                              ldr r1, = __bss_start
+                                        ldr r2, = __bss_end
+                                                movs r0, 0
+                                                subs r2, r1
+                                                ble startup_enter
+
+                                                loop_fill_bss:
+                                                subs r2, #4
+                                                str r0, [r1, r2]
+                                                bgt loop_fill_bss
+
+                                                startup_enter:
+                                                bl SystemInit
+                                                bl entry
+
+                                                /* Exception Handlers */
+                                                .weak   NMI_Handler
+                                                .type   NMI_Handler, % function
+                                                NMI_Handler:
+                                                b       .
+                                                .size   NMI_Handler, . - NMI_Handler
+
+                                                .weak   MemManage_Handler
+                                                .type   MemManage_Handler, % function
+                                                MemManage_Handler:
+                                                b       .
+                                                .size   MemManage_Handler, . - MemManage_Handler
+
+                                                .weak   BusFault_Handler
+                                                .type   BusFault_Handler, % function
+                                                BusFault_Handler:
+                                                b       .
+                                                .size   BusFault_Handler, . - BusFault_Handler
+
+                                                .weak   UsageFault_Handler
+                                                .type   UsageFault_Handler, % function
+                                                UsageFault_Handler:
+                                                b       .
+                                                .size   UsageFault_Handler, . - UsageFault_Handler
+
+                                                .weak   SVC_Handler
+                                                .type   SVC_Handler, % function
+                                                SVC_Handler:
+                                                b       .
+                                                .size   SVC_Handler, . - SVC_Handler
+
+                                                .weak   DebugMon_Handler
+                                                .type   DebugMon_Handler, % function
+                                                DebugMon_Handler:
+                                                b       .
+                                                .size   DebugMon_Handler, . - DebugMon_Handler
+
+                                                .weak   PendSV_Handler
+                                                .type   PendSV_Handler, % function
+                                                PendSV_Handler:
+                                                b       .
+                                                .size   PendSV_Handler, . - PendSV_Handler
+
+                                                .weak   SysTick_Handler
+                                                .type   SysTick_Handler, % function
+                                                SysTick_Handler:
+                                                b       .
+                                                .size   SysTick_Handler, . - SysTick_Handler
+
+                                                /* IQR Handler */
+                                                .section  .text.Default_Handler, "ax", % progbits
+                                                .type  Default_Handler, % function
+                                                Default_Handler:
+                                                b  .
+                                                .size  Default_Handler, . - Default_Handler
+
+                                                .macro  IRQ handler
+                                                .weak   \handler
+                                                .set    \handler, Default_Handler
+                                                .endm
+
+                                                IRQ WWDT_IRQHandler
+                                                IRQ PVD_IRQHandler
+                                                IRQ TAMPER_IRQHandler
+                                                IRQ RTC_IRQHandler
+                                                IRQ FLASH_IRQHandler
+                                                IRQ RCM_IRQHandler
+                                                IRQ EINT0_IRQHandler
+                                                IRQ EINT1_IRQHandler
+                                                IRQ EINT2_IRQHandler
+                                                IRQ EINT3_IRQHandler
+                                                IRQ EINT4_IRQHandler
+                                                IRQ DMA1_Channel1_IRQHandler
+                                                IRQ DMA1_Channel2_IRQHandler
+                                                IRQ DMA1_Channel3_IRQHandler
+                                                IRQ DMA1_Channel4_IRQHandler
+                                                IRQ DMA1_Channel5_IRQHandler
+                                                IRQ DMA1_Channel6_IRQHandler
+                                                IRQ DMA1_Channel7_IRQHandler
+                                                IRQ ADC1_2_IRQHandler
+                                                IRQ USBD1_HP_CAN1_TX_IRQHandler
+                                                IRQ USBD1_LP_CAN1_RX0_IRQHandler
+                                                IRQ CAN1_RX1_IRQHandler
+                                                IRQ CAN1_SCE_IRQHandler
+                                                IRQ EINT9_5_IRQHandler
+                                                IRQ TMR1_BRK_IRQHandler
+                                                IRQ TMR1_UP_IRQHandler
+                                                IRQ TMR1_TRG_COM_IRQHandler
+                                                IRQ TMR1_CC_IRQHandler
+                                                IRQ TMR2_IRQHandler
+                                                IRQ TMR3_IRQHandler
+                                                IRQ TMR4_IRQHandler
+                                                IRQ I2C1_EV_IRQHandler
+                                                IRQ I2C1_ER_IRQHandler
+                                                IRQ I2C2_EV_IRQHandler
+                                                IRQ I2C2_ER_IRQHandler
+                                                IRQ SPI1_IRQHandler
+                                                IRQ SPI2_IRQHandler
+                                                IRQ USART1_IRQHandler
+                                                IRQ USART2_IRQHandler
+                                                IRQ USART3_IRQHandler
+                                                IRQ EINT15_10_IRQHandler
+                                                IRQ RTCAlarm_IRQHandler
+                                                IRQ USBDWakeUp_IRQHandler
+                                                IRQ TMR8_BRK_IRQHandler
+                                                IRQ TMR8_UP_IRQHandler
+                                                IRQ TMR8_TRG_COM_IRQHandler
+                                                IRQ TMR8_CC_IRQHandler
+                                                IRQ ADC3_IRQHandler
+                                                IRQ EMMC_IRQHandler
+                                                IRQ SDIO_IRQHandler
+                                                IRQ TMR5_IRQHandler
+                                                IRQ SPI3_IRQHandler
+                                                IRQ UART4_IRQHandler
+                                                IRQ UART5_IRQHandler
+                                                IRQ TMR6_IRQHandler
+                                                IRQ TMR7_IRQHandler
+                                                IRQ DMA2_Channel1_IRQHandler
+                                                IRQ DMA2_Channel2_IRQHandler
+                                                IRQ DMA2_Channel3_IRQHandler
+                                                IRQ DMA2_Channel4_5_IRQHandler
+                                                IRQ USBD2_HP_CAN2_TX_IRQHandler
+                                                IRQ USBD2_LP_CAN2_RX0_IRQHandler
+                                                IRQ CAN2_RX1_IRQHandler
+                                                IRQ CAN2_SCE_IRQHandler

bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_md.s

@@ -0,0 +1,246 @@
+;/*!
+; * @file        startup_apm32f10x_hd.s
+; *
+; * @brief       CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd
+; *
+; * @version     V1.0.0
+; *
+; * @date        2022-01-05
+; *
+; * @attention
+; *
+; *  Copyright (C) 2020-2022 Geehy Semiconductor
+; *
+; *  You may not use this file except in compliance with the
+; *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+; *
+; *  The program is only for reference, which is distributed in the hope
+; *  that it will be usefull and instructional for customers to develop
+; *  their software. Unless required by applicable law or agreed to in
+; *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+; *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+; *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+; *  and limitations under the License.
+; */
+
+.syntax unified
+.cpu cortex - m3
+.fpu softvfp
+.thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+.section  .isr_vector, "a", % progbits
+.type  g_pfnVectors, % object
+
+g_pfnVectors:
+.word     _estack                           // Top of Stack
+.word     Reset_Handler                     // Reset Handler
+.word     NMI_Handler                       // NMI Handler
+.word     HardFault_Handler                 // Hard Fault Handler
+.word     MemManage_Handler                 // MPU Fault Handler
+.word     BusFault_Handler                  // Bus Fault Handler
+.word     UsageFault_Handler                // Usage Fault Handler
+.word     0                                 // Reserved
+.word     0                                 // Reserved
+.word     0                                 // Reserved
+.word     0                                 // Reserved
+.word     SVC_Handler                       // SVCall Handler
+.word     DebugMon_Handler                  // Debug Monitor Handler
+.word     0                                 // Reserved
+.word     PendSV_Handler                    // PendSV Handler
+.word     SysTick_Handler                   // SysTick Handler
+
+// external interrupts handler
+.word     WWDT_IRQHandler              // Window Watchdog
+.word     PVD_IRQHandler               // PVD through EINT Line detect
+.word     TAMPER_IRQHandler            // Tamper
+.word     RTC_IRQHandler               // RTC
+.word     FLASH_IRQHandler             // Flash
+.word     RCM_IRQHandler               // RCM
+.word     EINT0_IRQHandler             // EINT Line 0
+.word     EINT1_IRQHandler             // EINT Line 1
+.word     EINT2_IRQHandler             // EINT Line 2
+.word     EINT3_IRQHandler             // EINT Line 3
+.word     EINT4_IRQHandler             // EINT Line 4
+.word     DMA1_Channel1_IRQHandler     // DMA1 Channel 1
+.word     DMA1_Channel2_IRQHandler     // DMA1 Channel 2
+.word     DMA1_Channel3_IRQHandler     // DMA1 Channel 3
+.word     DMA1_Channel4_IRQHandler     // DMA1 Channel 4
+.word     DMA1_Channel5_IRQHandler     // DMA1 Channel 5
+.word     DMA1_Channel6_IRQHandler     // DMA1 Channel 6
+.word     DMA1_Channel7_IRQHandler     // DMA1 Channel 7
+.word     ADC1_2_IRQHandler            // ADC1_2
+.word     USBD1_HP_CAN1_TX_IRQHandler  // USBD1 High Priority or CAN1 TX
+.word     USBD1_LP_CAN1_RX0_IRQHandler // USBD1 Low  Priority or CAN1 RX0
+.word     CAN1_RX1_IRQHandler          // CAN1 RX1
+.word     CAN1_SCE_IRQHandler          // CAN1 SCE
+.word     EINT9_5_IRQHandler           // EINT Line 9..5
+.word     TMR1_BRK_IRQHandler          // TMR1 Break
+.word     TMR1_UP_IRQHandler           // TMR1 Update
+.word     TMR1_TRG_COM_IRQHandler      // TMR1 Trigger and Commutation
+.word     TMR1_CC_IRQHandler           // TMR1 Capture Compare
+.word     TMR2_IRQHandler              // TMR2
+.word     TMR3_IRQHandler              // TMR3
+.word     TMR4_IRQHandler              // TMR4
+.word     I2C1_EV_IRQHandler           // I2C1 Event
+.word     I2C1_ER_IRQHandler           // I2C1 Error
+.word     I2C2_EV_IRQHandler           // I2C2 Event
+.word     I2C2_ER_IRQHandler           // I2C2 Error
+.word     SPI1_IRQHandler              // SPI1
+.word     SPI2_IRQHandler              // SPI2
+.word     USART1_IRQHandler            // USART1
+.word     USART2_IRQHandler            // USART2
+.word     USART3_IRQHandler            // USART3
+.word     EINT15_10_IRQHandler         // EINT Line 15..10
+.word     RTCAlarm_IRQHandler          // RTC Alarm through EINT Line
+.word     USBDWakeUp_IRQHandler        // USBD Wakeup from suspend
+.word     FPU_IRQHandler               // FPU
+.word     QSPI_IRQHandler              // QSPI
+.word     USBD2_HP_IRQHandler          // USBD2 High Priority
+.word     USBD2_LP_IRQHandler          // USBD2 Low Priority
+
+.size  g_pfnVectors, . - g_pfnVectors
+
+.section  .text.Reset_Handler
+.weak  Reset_Handler
+.type  Reset_Handler, % function
+Reset_Handler:
+ldr r1, = _sidata
+          ldr r2, = _sdata
+                    ldr r3, = _edata
+
+                              subs r3, r2
+                              ble fill_bss_start
+
+                              loop_copy_data:
+                              subs r3, #4
+                              ldr r0, [r1, r3]
+                              str r0, [r2, r3]
+                              bgt loop_copy_data
+
+                              fill_bss_start:
+                              ldr r1, = __bss_start
+                                        ldr r2, = __bss_end
+                                                movs r0, 0
+                                                subs r2, r1
+                                                ble startup_enter
+
+                                                loop_fill_bss:
+                                                subs r2, #4
+                                                str r0, [r1, r2]
+                                                bgt loop_fill_bss
+
+                                                startup_enter:
+                                                bl SystemInit
+                                                bl entry
+
+                                                /* Exception Handlers */
+                                                .weak   NMI_Handler
+                                                .type   NMI_Handler, % function
+                                                NMI_Handler:
+                                                b       .
+                                                .size   NMI_Handler, . - NMI_Handler
+
+                                                .weak   MemManage_Handler
+                                                .type   MemManage_Handler, % function
+                                                MemManage_Handler:
+                                                b       .
+                                                .size   MemManage_Handler, . - MemManage_Handler
+
+                                                .weak   BusFault_Handler
+                                                .type   BusFault_Handler, % function
+                                                BusFault_Handler:
+                                                b       .
+                                                .size   BusFault_Handler, . - BusFault_Handler
+
+                                                .weak   UsageFault_Handler
+                                                .type   UsageFault_Handler, % function
+                                                UsageFault_Handler:
+                                                b       .
+                                                .size   UsageFault_Handler, . - UsageFault_Handler
+
+                                                .weak   SVC_Handler
+                                                .type   SVC_Handler, % function
+                                                SVC_Handler:
+                                                b       .
+                                                .size   SVC_Handler, . - SVC_Handler
+
+                                                .weak   DebugMon_Handler
+                                                .type   DebugMon_Handler, % function
+                                                DebugMon_Handler:
+                                                b       .
+                                                .size   DebugMon_Handler, . - DebugMon_Handler
+
+                                                .weak   PendSV_Handler
+                                                .type   PendSV_Handler, % function
+                                                PendSV_Handler:
+                                                b       .
+                                                .size   PendSV_Handler, . - PendSV_Handler
+
+                                                .weak   SysTick_Handler
+                                                .type   SysTick_Handler, % function
+                                                SysTick_Handler:
+                                                b       .
+                                                .size   SysTick_Handler, . - SysTick_Handler
+
+                                                /* IQR Handler */
+                                                .section  .text.Default_Handler, "ax", % progbits
+                                                .type  Default_Handler, % function
+                                                Default_Handler:
+                                                b  .
+                                                .size  Default_Handler, . - Default_Handler
+
+                                                .macro  IRQ handler
+                                                .weak   \handler
+                                                .set    \handler, Default_Handler
+                                                .endm
+
+                                                IRQ WWDT_IRQHandler
+                                                IRQ PVD_IRQHandler
+                                                IRQ TAMPER_IRQHandler
+                                                IRQ RTC_IRQHandler
+                                                IRQ FLASH_IRQHandler
+                                                IRQ RCM_IRQHandler
+                                                IRQ EINT0_IRQHandler
+                                                IRQ EINT1_IRQHandler
+                                                IRQ EINT2_IRQHandler
+                                                IRQ EINT3_IRQHandler
+                                                IRQ EINT4_IRQHandler
+                                                IRQ DMA1_Channel1_IRQHandler
+                                                IRQ DMA1_Channel2_IRQHandler
+                                                IRQ DMA1_Channel3_IRQHandler
+                                                IRQ DMA1_Channel4_IRQHandler
+                                                IRQ DMA1_Channel5_IRQHandler
+                                                IRQ DMA1_Channel6_IRQHandler
+                                                IRQ DMA1_Channel7_IRQHandler
+                                                IRQ ADC1_2_IRQHandler
+                                                IRQ USBD1_HP_CAN1_TX_IRQHandler
+                                                IRQ USBD1_LP_CAN1_RX0_IRQHandler
+                                                IRQ CAN1_RX1_IRQHandler
+                                                IRQ CAN1_SCE_IRQHandler
+                                                IRQ EINT9_5_IRQHandler
+                                                IRQ TMR1_BRK_IRQHandler
+                                                IRQ TMR1_UP_IRQHandler
+                                                IRQ TMR1_TRG_COM_IRQHandler
+                                                IRQ TMR1_CC_IRQHandler
+                                                IRQ TMR2_IRQHandler
+                                                IRQ TMR3_IRQHandler
+                                                IRQ TMR4_IRQHandler
+                                                IRQ I2C1_EV_IRQHandler
+                                                IRQ I2C1_ER_IRQHandler
+                                                IRQ I2C2_EV_IRQHandler
+                                                IRQ I2C2_ER_IRQHandler
+                                                IRQ SPI1_IRQHandler
+                                                IRQ SPI2_IRQHandler
+                                                IRQ USART1_IRQHandler
+                                                IRQ USART2_IRQHandler
+                                                IRQ USART3_IRQHandler
+                                                IRQ EINT15_10_IRQHandler
+                                                IRQ RTCAlarm_IRQHandler
+                                                IRQ USBDWakeUp_IRQHandler
+                                                IRQ FPU_IRQHandler
+                                                IRQ QSPI_IRQHandler
+                                                IRQ USBD2_HP_IRQHandler
+                                                IRQ USBD2_LP_IRQHandler

bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s

@@ -0,0 +1,813 @@
+;/*!
+; * @file        startup_apm32f10x_hd.s
+; *
+; * @brief       CMSIS Cortex-M3 based Core Device Startup File for Device APM32F103
+; *
+; * @version     V1.0.0
+; *
+; * @date        2022-01-05
+; *
+; * @attention
+; *
+; *  Copyright (C) 2020-2022 Geehy Semiconductor
+; *
+; *  You may not use this file except in compliance with the
+; *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+; *
+; *  The program is only for reference, which is distributed in the hope
+; *  that it will be usefull and instructional for customers to develop
+; *  their software. Unless required by applicable law or agreed to in
+; *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+; *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+; *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+; *  and limitations under the License.
+; */
+
+MODULE  ? cstartup
+
+;;
+Forward declaration of sections.
+SECTION CSTACK:
+DATA:
+NOROOT(3)
+
+SECTION .intvec:
+CODE:
+NOROOT(2)
+
+
+EXTERN  __iar_program_start
+EXTERN  SystemInit
+PUBLIC  __vector_table
+
+DATA
+
+__vector_table
+DCD     sfe(CSTACK)
+DCD     Reset_Handler                ;
+Reset Handler
+DCD     NMI_Handler                  ;
+NMI Handler
+DCD     HardFault_Handler            ;
+Hard Fault Handler
+DCD     MemManage_Handler            ;
+MPU Fault Handler
+DCD     BusFault_Handler             ;
+Bus Fault Handler
+DCD     UsageFault_Handler           ;
+Usage Fault Handler
+DCD     0                            ;
+Reserved
+DCD     0                            ;
+Reserved
+DCD     0                            ;
+Reserved
+DCD     0                            ;
+Reserved
+DCD     SVC_Handler                  ;
+SVCall Handler
+DCD     DebugMon_Handler             ;
+Debug Monitor Handler
+DCD     0                            ;
+Reserved
+DCD     PendSV_Handler               ;
+PendSV Handler
+DCD     SysTick_Handler              ;
+SysTick Handler
+
+;
+External Interrupts
+DCD     WWDT_IRQHandler              ;
+Window Watchdog
+DCD     PVD_IRQHandler               ;
+PVD through EINT Line detect
+DCD     TAMPER_IRQHandler            ;
+Tamper
+DCD     RTC_IRQHandler               ;
+RTC
+DCD     FLASH_IRQHandler             ;
+Flash
+DCD     RCM_IRQHandler               ;
+RCM
+DCD     EINT0_IRQHandler             ;
+EINT Line 0
+DCD     EINT1_IRQHandler             ;
+EINT Line 1
+DCD     EINT2_IRQHandler             ;
+EINT Line 2
+DCD     EINT3_IRQHandler             ;
+EINT Line 3
+DCD     EINT4_IRQHandler             ;
+EINT Line 4
+DCD     DMA1_Channel1_IRQHandler     ;
+DMA1 Channel 1
+DCD     DMA1_Channel2_IRQHandler     ;
+DMA1 Channel 2
+DCD     DMA1_Channel3_IRQHandler     ;
+DMA1 Channel 3
+DCD     DMA1_Channel4_IRQHandler     ;
+DMA1 Channel 4
+DCD     DMA1_Channel5_IRQHandler     ;
+DMA1 Channel 5
+DCD     DMA1_Channel6_IRQHandler     ;
+DMA1 Channel 6
+DCD     DMA1_Channel7_IRQHandler     ;
+DMA1 Channel 7
+DCD     ADC1_2_IRQHandler            ;
+ADC1 &ADC2
+DCD     USBD1_HP_CAN1_TX_IRQHandler  ;
+USBD1 High Priority or CAN1 TX
+DCD     USBD1_LP_CAN1_RX0_IRQHandler ;
+USBD1 Low  Priority or CAN1 RX0
+DCD     CAN1_RX1_IRQHandler          ;
+CAN1 RX1
+DCD     CAN1_SCE_IRQHandler          ;
+CAN1 SCE
+DCD     EINT9_5_IRQHandler           ;
+EINT Line 9..5
+DCD     TMR1_BRK_IRQHandler          ;
+TMR1 Break
+DCD     TMR1_UP_IRQHandler           ;
+TMR1 Update
+DCD     TMR1_TRG_COM_IRQHandler      ;
+TMR1 Trigger and Commutation
+DCD     TMR1_CC_IRQHandler           ;
+TMR1 Capture Compare
+DCD     TMR2_IRQHandler              ;
+TMR2
+DCD     TMR3_IRQHandler              ;
+TMR3
+DCD     TMR4_IRQHandler              ;
+TMR4
+DCD     I2C1_EV_IRQHandler           ;
+I2C1 Event
+DCD     I2C1_ER_IRQHandler           ;
+I2C1 Error
+DCD     I2C2_EV_IRQHandler           ;
+I2C2 Event
+DCD     I2C2_ER_IRQHandler           ;
+I2C2 Error
+DCD     SPI1_IRQHandler              ;
+SPI1
+DCD     SPI2_IRQHandler              ;
+SPI2
+DCD     USART1_IRQHandler            ;
+USART1
+DCD     USART2_IRQHandler            ;
+USART2
+DCD     USART3_IRQHandler            ;
+USART3
+DCD     EINT15_10_IRQHandler         ;
+EINT Line 15..10
+DCD     RTCAlarm_IRQHandler          ;
+RTC Alarm through EINT Line
+DCD     USBDWakeUp_IRQHandler        ;
+USBD Wakeup from suspend
+DCD     TMR8_BRK_IRQHandler          ;
+TMR8 Break
+DCD     TMR8_UP_IRQHandler           ;
+TMR8 Update
+DCD     TMR8_TRG_COM_IRQHandler      ;
+TMR8 Trigger and Commutation
+DCD     TMR8_CC_IRQHandler           ;
+TMR8 Capture Compare
+DCD     ADC3_IRQHandler              ;
+ADC3
+DCD     EMMC_IRQHandler              ;
+EMMC
+DCD     SDIO_IRQHandler              ;
+SDIO
+DCD     TMR5_IRQHandler              ;
+TMR5
+DCD     SPI3_IRQHandler              ;
+SPI3
+DCD     UART4_IRQHandler             ;
+UART4
+DCD     UART5_IRQHandler             ;
+UART5
+DCD     TMR6_IRQHandler              ;
+TMR6
+DCD     TMR7_IRQHandler              ;
+TMR7
+DCD     DMA2_Channel1_IRQHandler     ;
+DMA2 Channel1
+DCD     DMA2_Channel2_IRQHandler     ;
+DMA2 Channel2
+DCD     DMA2_Channel3_IRQHandler     ;
+DMA2 Channel3
+DCD     DMA2_Channel4_5_IRQHandler   ;
+DMA2 Channel4 &Channel5
+DCD     0                            ;
+Reserved
+DCD     USBD2_HP_CAN2_TX_IRQHandler  ;
+USBD2 High Priority or CAN2 TX
+DCD     USBD2_LP_CAN2_RX0_IRQHandler ;
+USBD2 Low  Priority or CAN2 RX0
+DCD     CAN2_RX1_IRQHandler          ;
+CAN2 RX1
+DCD     CAN2_SCE_IRQHandler          ;
+CAN2 SCE
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;;
+Default interrupt handlers.
+;;
+THUMB
+
+PUBWEAK Reset_Handler
+SECTION .text:
+CODE:
+REORDER:
+NOROOT(2)
+Reset_Handler
+LDR     R0, = SystemInit
+              BLX     R0
+              LDR     R0, = __iar_program_start
+                            BX      R0
+
+                            PUBWEAK NMI_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            NMI_Handler
+                            B NMI_Handler
+
+                            PUBWEAK HardFault_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            HardFault_Handler
+                            B HardFault_Handler
+
+                            PUBWEAK MemManage_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            MemManage_Handler
+                            B MemManage_Handler
+
+                            PUBWEAK BusFault_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            BusFault_Handler
+                            B BusFault_Handler
+
+                            PUBWEAK UsageFault_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            UsageFault_Handler
+                            B UsageFault_Handler
+
+                            PUBWEAK SVC_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            SVC_Handler
+                            B SVC_Handler
+
+                            PUBWEAK DebugMon_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DebugMon_Handler
+                            B DebugMon_Handler
+
+                            PUBWEAK PendSV_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            PendSV_Handler
+                            B PendSV_Handler
+
+                            PUBWEAK SysTick_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            SysTick_Handler
+                            B SysTick_Handler
+
+                            PUBWEAK WWDT_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            WWDT_IRQHandler
+                            B WWDT_IRQHandler
+
+                            PUBWEAK PVD_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            PVD_IRQHandler
+                            B PVD_IRQHandler
+
+                            PUBWEAK TAMPER_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TAMPER_IRQHandler
+                            B TAMPER_IRQHandler
+
+                            PUBWEAK RTC_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            RTC_IRQHandler
+                            B RTC_IRQHandler
+
+                            PUBWEAK FLASH_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            FLASH_IRQHandler
+                            B FLASH_IRQHandler
+
+                            PUBWEAK RCM_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            RCM_IRQHandler
+                            B RCM_IRQHandler
+
+                            PUBWEAK EINT0_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            EINT0_IRQHandler
+                            B EINT0_IRQHandler
+
+                            PUBWEAK EINT1_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            EINT1_IRQHandler
+                            B EINT1_IRQHandler
+
+                            PUBWEAK EINT2_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            EINT2_IRQHandler
+                            B EINT2_IRQHandler
+
+                            PUBWEAK EINT3_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            EINT3_IRQHandler
+                            B EINT3_IRQHandler
+
+                            PUBWEAK EINT4_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            EINT4_IRQHandler
+                            B EINT4_IRQHandler
+
+                            PUBWEAK DMA1_Channel1_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA1_Channel1_IRQHandler
+                            B DMA1_Channel1_IRQHandler
+
+                            PUBWEAK DMA1_Channel2_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA1_Channel2_IRQHandler
+                            B DMA1_Channel2_IRQHandler
+
+                            PUBWEAK DMA1_Channel3_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA1_Channel3_IRQHandler
+                            B DMA1_Channel3_IRQHandler
+
+                            PUBWEAK DMA1_Channel4_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA1_Channel4_IRQHandler
+                            B DMA1_Channel4_IRQHandler
+
+                            PUBWEAK DMA1_Channel5_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA1_Channel5_IRQHandler
+                            B DMA1_Channel5_IRQHandler
+
+                            PUBWEAK DMA1_Channel6_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA1_Channel6_IRQHandler
+                            B DMA1_Channel6_IRQHandler
+
+                            PUBWEAK DMA1_Channel7_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA1_Channel7_IRQHandler
+                            B DMA1_Channel7_IRQHandler
+
+                            PUBWEAK ADC1_2_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            ADC1_2_IRQHandler
+                            B ADC1_2_IRQHandler
+
+                            PUBWEAK USBD1_HP_CAN1_TX_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USBD1_HP_CAN1_TX_IRQHandler
+                            B USBD1_HP_CAN1_TX_IRQHandler
+
+                            PUBWEAK USBD1_LP_CAN1_RX0_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USBD1_LP_CAN1_RX0_IRQHandler
+                            B USBD1_LP_CAN1_RX0_IRQHandler
+
+                            PUBWEAK CAN1_RX1_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            CAN1_RX1_IRQHandler
+                            B CAN1_RX1_IRQHandler
+
+                            PUBWEAK CAN1_SCE_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            CAN1_SCE_IRQHandler
+                            B CAN1_SCE_IRQHandler
+
+                            PUBWEAK EINT9_5_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            EINT9_5_IRQHandler
+                            B EINT9_5_IRQHandler
+
+                            PUBWEAK TMR1_BRK_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR1_BRK_IRQHandler
+                            B TMR1_BRK_IRQHandler
+
+                            PUBWEAK TMR1_UP_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR1_UP_IRQHandler
+                            B TMR1_UP_IRQHandler
+
+                            PUBWEAK TMR1_TRG_COM_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR1_TRG_COM_IRQHandler
+                            B TMR1_TRG_COM_IRQHandler
+
+                            PUBWEAK TMR1_CC_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR1_CC_IRQHandler
+                            B TMR1_CC_IRQHandler
+
+                            PUBWEAK TMR2_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR2_IRQHandler
+                            B TMR2_IRQHandler
+
+                            PUBWEAK TMR3_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR3_IRQHandler
+                            B TMR3_IRQHandler
+
+                            PUBWEAK TMR4_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR4_IRQHandler
+                            B TMR4_IRQHandler
+
+                            PUBWEAK I2C1_EV_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            I2C1_EV_IRQHandler
+                            B I2C1_EV_IRQHandler
+
+                            PUBWEAK I2C1_ER_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            I2C1_ER_IRQHandler
+                            B I2C1_ER_IRQHandler
+
+                            PUBWEAK I2C2_EV_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            I2C2_EV_IRQHandler
+                            B I2C2_EV_IRQHandler
+
+                            PUBWEAK I2C2_ER_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            I2C2_ER_IRQHandler
+                            B I2C2_ER_IRQHandler
+
+                            PUBWEAK SPI1_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            SPI1_IRQHandler
+                            B SPI1_IRQHandler
+
+                            PUBWEAK SPI2_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            SPI2_IRQHandler
+                            B SPI2_IRQHandler
+
+                            PUBWEAK USART1_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USART1_IRQHandler
+                            B USART1_IRQHandler
+
+                            PUBWEAK USART2_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USART2_IRQHandler
+                            B USART2_IRQHandler
+
+                            PUBWEAK USART3_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USART3_IRQHandler
+                            B USART3_IRQHandler
+
+                            PUBWEAK EINT15_10_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            EINT15_10_IRQHandler
+                            B EINT15_10_IRQHandler
+
+                            PUBWEAK RTCAlarm_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            RTCAlarm_IRQHandler
+                            B RTCAlarm_IRQHandler
+
+                            PUBWEAK USBDWakeUp_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USBDWakeUp_IRQHandler
+                            B USBDWakeUp_IRQHandler
+
+                            PUBWEAK TMR8_BRK_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR8_BRK_IRQHandler
+                            B TMR8_BRK_IRQHandler
+
+                            PUBWEAK TMR8_UP_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR8_UP_IRQHandler
+                            B TMR8_UP_IRQHandler
+
+                            PUBWEAK TMR8_TRG_COM_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR8_TRG_COM_IRQHandler
+                            B TMR8_TRG_COM_IRQHandler
+
+                            PUBWEAK TMR8_CC_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR8_CC_IRQHandler
+                            B TMR8_CC_IRQHandler
+
+                            PUBWEAK ADC3_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            ADC3_IRQHandler
+                            B ADC3_IRQHandler
+
+                            PUBWEAK EMMC_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            EMMC_IRQHandler
+                            B EMMC_IRQHandler
+
+                            PUBWEAK SDIO_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            SDIO_IRQHandler
+                            B SDIO_IRQHandler
+
+                            PUBWEAK TMR5_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR5_IRQHandler
+                            B TMR5_IRQHandler
+
+                            PUBWEAK SPI3_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            SPI3_IRQHandler
+                            B SPI3_IRQHandler
+
+                            PUBWEAK UART4_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            UART4_IRQHandler
+                            B UART4_IRQHandler
+
+                            PUBWEAK UART5_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            UART5_IRQHandler
+                            B UART5_IRQHandler
+
+                            PUBWEAK TMR6_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR6_IRQHandler
+                            B TMR6_IRQHandler
+
+                            PUBWEAK TMR7_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR7_IRQHandler
+                            B TMR7_IRQHandler
+
+                            PUBWEAK DMA2_Channel1_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA2_Channel1_IRQHandler
+                            B DMA2_Channel1_IRQHandler
+
+                            PUBWEAK DMA2_Channel2_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA2_Channel2_IRQHandler
+                            B DMA2_Channel2_IRQHandler
+
+                            PUBWEAK DMA2_Channel3_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA2_Channel3_IRQHandler
+                            B DMA2_Channel3_IRQHandler
+
+                            PUBWEAK DMA2_Channel4_5_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA2_Channel4_5_IRQHandler
+                            B DMA2_Channel4_5_IRQHandler
+
+                            PUBWEAK USBD2_HP_CAN2_TX_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USBD2_HP_CAN2_TX_IRQHandler
+                            B USBD2_HP_CAN2_TX_IRQHandler
+
+                            PUBWEAK USBD2_LP_CAN2_RX0_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USBD2_LP_CAN2_RX0_IRQHandler
+                            B USBD2_LP_CAN2_RX0_IRQHandler
+
+                            PUBWEAK CAN2_RX1_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            CAN2_RX1_IRQHandler
+                            B CAN2_RX1_IRQHandler
+
+                            PUBWEAK CAN2_SCE_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            CAN2_SCE_IRQHandler
+                            B CAN2_SCE_IRQHandler
+
+                            END
+

bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_md.s

@@ -0,0 +1,644 @@
+;/*!
+; * @file        startup_apm32f10x_hd.s
+; *
+; * @brief       CMSIS Cortex-M3 based Core Device Startup File for Device APM32F103
+; *
+; * @version     V1.0.0
+; *
+; * @date        2022-01-05
+; *
+; * @attention
+; *
+; *  Copyright (C) 2020-2022 Geehy Semiconductor
+; *
+; *  You may not use this file except in compliance with the
+; *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+; *
+; *  The program is only for reference, which is distributed in the hope
+; *  that it will be usefull and instructional for customers to develop
+; *  their software. Unless required by applicable law or agreed to in
+; *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+; *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+; *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+; *  and limitations under the License.
+; */
+
+MODULE  ? cstartup
+
+;;
+Forward declaration of sections.
+SECTION CSTACK:
+DATA:
+NOROOT(3)
+
+SECTION .intvec:
+CODE:
+NOROOT(2)
+
+
+EXTERN  __iar_program_start
+EXTERN  SystemInit
+PUBLIC  __vector_table
+
+DATA
+
+__vector_table
+DCD     sfe(CSTACK)
+DCD     Reset_Handler                ;
+Reset Handler
+DCD     NMI_Handler                  ;
+NMI Handler
+DCD     HardFault_Handler            ;
+Hard Fault Handler
+DCD     MemManage_Handler            ;
+MPU Fault Handler
+DCD     BusFault_Handler             ;
+Bus Fault Handler
+DCD     UsageFault_Handler           ;
+Usage Fault Handler
+DCD     0                            ;
+Reserved
+DCD     0                            ;
+Reserved
+DCD     0                            ;
+Reserved
+DCD     0                            ;
+Reserved
+DCD     SVC_Handler                  ;
+SVCall Handler
+DCD     DebugMon_Handler             ;
+Debug Monitor Handler
+DCD     0                            ;
+Reserved
+DCD     PendSV_Handler               ;
+PendSV Handler
+DCD     SysTick_Handler              ;
+SysTick Handler
+
+;
+External Interrupts
+DCD     WWDT_IRQHandler              ;
+Window Watchdog
+DCD     PVD_IRQHandler               ;
+PVD through EINT Line detect
+DCD     TAMPER_IRQHandler            ;
+Tamper
+DCD     RTC_IRQHandler               ;
+RTC
+DCD     FLASH_IRQHandler             ;
+Flash
+DCD     RCM_IRQHandler               ;
+RCM
+DCD     EINT0_IRQHandler             ;
+EINT Line 0
+DCD     EINT1_IRQHandler             ;
+EINT Line 1
+DCD     EINT2_IRQHandler             ;
+EINT Line 2
+DCD     EINT3_IRQHandler             ;
+EINT Line 3
+DCD     EINT4_IRQHandler             ;
+EINT Line 4
+DCD     DMA1_Channel1_IRQHandler     ;
+DMA1 Channel 1
+DCD     DMA1_Channel2_IRQHandler     ;
+DMA1 Channel 2
+DCD     DMA1_Channel3_IRQHandler     ;
+DMA1 Channel 3
+DCD     DMA1_Channel4_IRQHandler     ;
+DMA1 Channel 4
+DCD     DMA1_Channel5_IRQHandler     ;
+DMA1 Channel 5
+DCD     DMA1_Channel6_IRQHandler     ;
+DMA1 Channel 6
+DCD     DMA1_Channel7_IRQHandler     ;
+DMA1 Channel 7
+DCD     ADC1_2_IRQHandler            ;
+ADC1 &ADC2
+DCD     USBD1_HP_CAN1_TX_IRQHandler  ;
+USBD1 High Priority or CAN1 TX
+DCD     USBD1_LP_CAN1_RX0_IRQHandler ;
+USBD1 Low  Priority or CAN1 RX0
+DCD     CAN1_RX1_IRQHandler          ;
+CAN1 RX1
+DCD     CAN1_SCE_IRQHandler          ;
+CAN1 SCE
+DCD     EINT9_5_IRQHandler           ;
+EINT Line 9..5
+DCD     TMR1_BRK_IRQHandler          ;
+TMR1 Break
+DCD     TMR1_UP_IRQHandler           ;
+TMR1 Update
+DCD     TMR1_TRG_COM_IRQHandler      ;
+TMR1 Trigger and Commutation
+DCD     TMR1_CC_IRQHandler           ;
+TMR1 Capture Compare
+DCD     TMR2_IRQHandler              ;
+TMR2
+DCD     TMR3_IRQHandler              ;
+TMR3
+DCD     TMR4_IRQHandler              ;
+TMR4
+DCD     I2C1_EV_IRQHandler           ;
+I2C1 Event
+DCD     I2C1_ER_IRQHandler           ;
+I2C1 Error
+DCD     I2C2_EV_IRQHandler           ;
+I2C2 Event
+DCD     I2C2_ER_IRQHandler           ;
+I2C2 Error
+DCD     SPI1_IRQHandler              ;
+SPI1
+DCD     SPI2_IRQHandler              ;
+SPI2
+DCD     USART1_IRQHandler            ;
+USART1
+DCD     USART2_IRQHandler            ;
+USART2
+DCD     USART3_IRQHandler            ;
+USART3
+DCD     EINT15_10_IRQHandler         ;
+EINT Line 15..10
+DCD     RTCAlarm_IRQHandler          ;
+RTC Alarm through EINT Line
+DCD     USBDWakeUp_IRQHandler        ;
+USBD Wakeup from suspend
+DCD     FPU_IRQHandler               ;
+FPU
+DCD     QSPI_IRQHandler              ;
+QSPI
+DCD     USBD2_HP_IRQHandler          ;
+USBD2 High Priority
+DCD     USBD2_LP_IRQHandler          ;
+USBD2 Low Priority
+__Vectors_End
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;;
+Default interrupt handlers.
+;;
+THUMB
+
+PUBWEAK Reset_Handler
+SECTION .text:
+CODE:
+REORDER:
+NOROOT(2)
+Reset_Handler
+LDR     R0, = SystemInit
+              BLX     R0
+              LDR     R0, = __iar_program_start
+                            BX      R0
+
+                            PUBWEAK NMI_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            NMI_Handler
+                            B NMI_Handler
+
+                            PUBWEAK HardFault_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            HardFault_Handler
+                            B HardFault_Handler
+
+                            PUBWEAK MemManage_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            MemManage_Handler
+                            B MemManage_Handler
+
+                            PUBWEAK BusFault_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            BusFault_Handler
+                            B BusFault_Handler
+
+                            PUBWEAK UsageFault_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            UsageFault_Handler
+                            B UsageFault_Handler
+
+                            PUBWEAK SVC_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            SVC_Handler
+                            B SVC_Handler
+
+                            PUBWEAK DebugMon_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DebugMon_Handler
+                            B DebugMon_Handler
+
+                            PUBWEAK PendSV_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            PendSV_Handler
+                            B PendSV_Handler
+
+                            PUBWEAK SysTick_Handler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            SysTick_Handler
+                            B SysTick_Handler
+
+                            PUBWEAK WWDT_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            WWDT_IRQHandler
+                            B WWDT_IRQHandler
+
+                            PUBWEAK PVD_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            PVD_IRQHandler
+                            B PVD_IRQHandler
+
+                            PUBWEAK TAMPER_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TAMPER_IRQHandler
+                            B TAMPER_IRQHandler
+
+                            PUBWEAK RTC_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            RTC_IRQHandler
+                            B RTC_IRQHandler
+
+                            PUBWEAK FLASH_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            FLASH_IRQHandler
+                            B FLASH_IRQHandler
+
+                            PUBWEAK RCM_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            RCM_IRQHandler
+                            B RCM_IRQHandler
+
+                            PUBWEAK EINT0_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            EINT0_IRQHandler
+                            B EINT0_IRQHandler
+
+                            PUBWEAK EINT1_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            EINT1_IRQHandler
+                            B EINT1_IRQHandler
+
+                            PUBWEAK EINT2_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            EINT2_IRQHandler
+                            B EINT2_IRQHandler
+
+                            PUBWEAK EINT3_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            EINT3_IRQHandler
+                            B EINT3_IRQHandler
+
+                            PUBWEAK EINT4_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            EINT4_IRQHandler
+                            B EINT4_IRQHandler
+
+                            PUBWEAK DMA1_Channel1_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA1_Channel1_IRQHandler
+                            B DMA1_Channel1_IRQHandler
+
+                            PUBWEAK DMA1_Channel2_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA1_Channel2_IRQHandler
+                            B DMA1_Channel2_IRQHandler
+
+                            PUBWEAK DMA1_Channel3_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA1_Channel3_IRQHandler
+                            B DMA1_Channel3_IRQHandler
+
+                            PUBWEAK DMA1_Channel4_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA1_Channel4_IRQHandler
+                            B DMA1_Channel4_IRQHandler
+
+                            PUBWEAK DMA1_Channel5_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA1_Channel5_IRQHandler
+                            B DMA1_Channel5_IRQHandler
+
+                            PUBWEAK DMA1_Channel6_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA1_Channel6_IRQHandler
+                            B DMA1_Channel6_IRQHandler
+
+                            PUBWEAK DMA1_Channel7_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            DMA1_Channel7_IRQHandler
+                            B DMA1_Channel7_IRQHandler
+
+                            PUBWEAK ADC1_2_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            ADC1_2_IRQHandler
+                            B ADC1_2_IRQHandler
+
+                            PUBWEAK USBD1_HP_CAN1_TX_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USBD1_HP_CAN1_TX_IRQHandler
+                            B USBD1_HP_CAN1_TX_IRQHandler
+
+                            PUBWEAK USBD1_LP_CAN1_RX0_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USBD1_LP_CAN1_RX0_IRQHandler
+                            B USBD1_LP_CAN1_RX0_IRQHandler
+
+                            PUBWEAK CAN1_RX1_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            CAN1_RX1_IRQHandler
+                            B CAN1_RX1_IRQHandler
+
+                            PUBWEAK CAN1_SCE_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            CAN1_SCE_IRQHandler
+                            B CAN1_SCE_IRQHandler
+
+                            PUBWEAK EINT9_5_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            EINT9_5_IRQHandler
+                            B EINT9_5_IRQHandler
+
+                            PUBWEAK TMR1_BRK_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR1_BRK_IRQHandler
+                            B TMR1_BRK_IRQHandler
+
+                            PUBWEAK TMR1_UP_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR1_UP_IRQHandler
+                            B TMR1_UP_IRQHandler
+
+                            PUBWEAK TMR1_TRG_COM_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR1_TRG_COM_IRQHandler
+                            B TMR1_TRG_COM_IRQHandler
+
+                            PUBWEAK TMR1_CC_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR1_CC_IRQHandler
+                            B TMR1_CC_IRQHandler
+
+                            PUBWEAK TMR2_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR2_IRQHandler
+                            B TMR2_IRQHandler
+
+                            PUBWEAK TMR3_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR3_IRQHandler
+                            B TMR3_IRQHandler
+
+                            PUBWEAK TMR4_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            TMR4_IRQHandler
+                            B TMR4_IRQHandler
+
+                            PUBWEAK I2C1_EV_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            I2C1_EV_IRQHandler
+                            B I2C1_EV_IRQHandler
+
+                            PUBWEAK I2C1_ER_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            I2C1_ER_IRQHandler
+                            B I2C1_ER_IRQHandler
+
+                            PUBWEAK I2C2_EV_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            I2C2_EV_IRQHandler
+                            B I2C2_EV_IRQHandler
+
+                            PUBWEAK I2C2_ER_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            I2C2_ER_IRQHandler
+                            B I2C2_ER_IRQHandler
+
+                            PUBWEAK SPI1_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            SPI1_IRQHandler
+                            B SPI1_IRQHandler
+
+                            PUBWEAK SPI2_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            SPI2_IRQHandler
+                            B SPI2_IRQHandler
+
+                            PUBWEAK USART1_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USART1_IRQHandler
+                            B USART1_IRQHandler
+
+                            PUBWEAK USART2_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USART2_IRQHandler
+                            B USART2_IRQHandler
+
+                            PUBWEAK USART3_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USART3_IRQHandler
+                            B USART3_IRQHandler
+
+                            PUBWEAK EINT15_10_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            EINT15_10_IRQHandler
+                            B EINT15_10_IRQHandler
+
+                            PUBWEAK RTCAlarm_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            RTCAlarm_IRQHandler
+                            B RTCAlarm_IRQHandler
+
+                            PUBWEAK USBDWakeUp_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USBDWakeUp_IRQHandler
+                            B USBDWakeUp_IRQHandler
+
+                            PUBWEAK FPU_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            FPU_IRQHandler
+                            B FPU_IRQHandler
+
+                            PUBWEAK QSPI_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            QSPI_IRQHandler
+                            B QSPI_IRQHandler
+
+                            PUBWEAK USBD2_HP_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USBD2_HP_IRQHandler
+                            B USBD2_HP_IRQHandler
+
+                            PUBWEAK USBD2_LP_IRQHandler
+                            SECTION .text:
+                            CODE:
+                            REORDER:
+                            NOROOT(1)
+                            USBD2_LP_IRQHandler
+                            B USBD2_LP_IRQHandler
+
+
+                            END
+

bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c

@@ -3,14 +3,33 @@
  *
  * @brief       CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
  *
- * @version     V1.0.1
+ * @version     V1.0.2
  *
- * @date        2021-03-23
+ * @date        2022-01-05
  *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
  */
 
 #include "apm32f10x.h"
 
+/*****************************************************************
+ * If SYSCLK source is PLL,SystemCoreClock will contain the      *
+ * HSE_VALUE or HSI_VALUE multiplied/divided by the PLL factors. *
+******************************************************************/
+
 //#define SYSTEM_CLOCK_HSE    HSE_VALUE
 //#define SYSTEM_CLOCK_24MHz  (24000000)
 //#define SYSTEM_CLOCK_36MHz  (36000000)
@@ -20,42 +39,42 @@
 //#define SYSTEM_CLOCK_96MHz  (96000000)
 
 
-/* #define VECT_TAB_SRAM */
+/** #define VECT_TAB_SRAM */
 #define VECT_TAB_OFFSET     0x00
 
 #ifdef SYSTEM_CLOCK_HSE
-uint32_t SystemCoreClock         = SYSTEM_CLOCK_HSE;
+    uint32_t SystemCoreClock         = SYSTEM_CLOCK_HSE;
 #elif defined SYSTEM_CLOCK_24MHz
-uint32_t SystemCoreClock         = SYSTEM_CLOCK_24MHz;
+    uint32_t SystemCoreClock         = SYSTEM_CLOCK_24MHz;
 #elif defined SYSTEM_CLOCK_36MHz
-uint32_t SystemCoreClock         = SYSTEM_CLOCK_36MHz;
+    uint32_t SystemCoreClock         = SYSTEM_CLOCK_36MHz;
 #elif defined SYSTEM_CLOCK_48MHz
-uint32_t SystemCoreClock         = SYSTEM_CLOCK_48MHz;
+    uint32_t SystemCoreClock         = SYSTEM_CLOCK_48MHz;
 #elif defined SYSTEM_CLOCK_56MHz
-uint32_t SystemCoreClock         = SYSTEM_CLOCK_56MHz;
+    uint32_t SystemCoreClock         = SYSTEM_CLOCK_56MHz;
 #elif defined SYSTEM_CLOCK_72MHz
-uint32_t SystemCoreClock         = SYSTEM_CLOCK_72MHz;
+    uint32_t SystemCoreClock         = SYSTEM_CLOCK_72MHz;
 #else
-uint32_t SystemCoreClock         = SYSTEM_CLOCK_96MHz;
+    uint32_t SystemCoreClock         = SYSTEM_CLOCK_96MHz;
 #endif
 
 
 static void SystemClockConfig(void);
 
 #ifdef SYSTEM_CLOCK_HSE
-static void SystemClockHSE(void);
+    static void SystemClockHSE(void);
 #elif defined SYSTEM_CLOCK_24MHz
-static void SystemClock24M(void);
+    static void SystemClock24M(void);
 #elif defined SYSTEM_CLOCK_36MHz
-static void SystemClock36M(void);
+    static void SystemClock36M(void);
 #elif defined SYSTEM_CLOCK_48MHz
-static void SystemClock48M(void);
+    static void SystemClock48M(void);
 #elif defined SYSTEM_CLOCK_56MHz
-static void SystemClock56M(void);
+    static void SystemClock56M(void);
 #elif defined SYSTEM_CLOCK_72MHz
-static void SystemClock72M(void);
+    static void SystemClock72M(void);
 #elif defined SYSTEM_CLOCK_96MHz
-static void SystemClock96M(void);
+    static void SystemClock96M(void);
 #endif
 
 /*!
@@ -65,13 +84,12 @@ static void SystemClock96M(void);
  *
  * @retval      None
  *
- * @note
  */
-void SystemInit (void)
+void SystemInit(void)
 {
     /** Set HSIEN bit */
     RCM->CTRL_B.HSIEN = BIT_SET;
-    /** Reset SCLKSW, AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */
+    /** Reset SCLKSEL, AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */
     RCM->CFG &= (uint32_t)0xF8FF0000;
     /** Reset HSEEN, CSSEN and PLLEN bits */
     RCM->CTRL &= (uint32_t)0xFEF6FFFF;
@@ -99,52 +117,51 @@ void SystemInit (void)
  *
  * @retval      None
  *
- * @note
  */
-void SystemCoreClockUpdate (void)
+void SystemCoreClockUpdate(void)
 {
     uint32_t sysClock, pllMull, pllSource, Prescaler;
     uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 
-    sysClock = RCM->CFG_B.SCLKSWSTS;
+    sysClock = RCM->CFG_B.SCLKSELSTS;
 
-    switch(sysClock)
+    switch (sysClock)
     {
-        /** sys clock is HSI */
-        case 0:
-            SystemCoreClock = HSI_VALUE;
+    /** sys clock is HSI */
+    case 0:
+        SystemCoreClock = HSI_VALUE;
         break;
 
-        /** sys clock is HSE */
-        case 1:
-            SystemCoreClock = HSE_VALUE;
+    /** sys clock is HSE */
+    case 1:
+        SystemCoreClock = HSE_VALUE;
         break;
 
-        /** sys clock is PLL */
-        case 2:
-            pllMull = RCM->CFG_B.PLLMULCFG + 2;
-            pllSource = RCM->CFG_B.PLLSRCSEL;
+    /** sys clock is PLL */
+    case 2:
+        pllMull = RCM->CFG_B.PLLMULCFG + 2;
+        pllSource = RCM->CFG_B.PLLSRCSEL;
 
-            /** PLL entry clock source is HSE */
-            if(pllSource == BIT_SET)
-            {
-                SystemCoreClock = HSE_VALUE * pllMull;
+        /** PLL entry clock source is HSE */
+        if (pllSource == BIT_SET)
+        {
+            SystemCoreClock = HSE_VALUE * pllMull;
 
-                /** HSE clock divided by 2 */
-                if(pllSource == RCM->CFG_B.PLLHSEPSC)
-                {
-                    SystemCoreClock >>= 1;
-                }
-            }
-            /** PLL entry clock source is HSI/2 */
-            else
+            /** HSE clock divided by 2 */
+            if (pllSource == RCM->CFG_B.PLLHSEPSC)
             {
-                SystemCoreClock = (HSI_VALUE >> 1) * pllMull;
+                SystemCoreClock >>= 1;
             }
-            break;
+        }
+        /** PLL entry clock source is HSI/2 */
+        else
+        {
+            SystemCoreClock = (HSI_VALUE >> 1) * pllMull;
+        }
+        break;
 
-        default:
-            SystemCoreClock  = HSI_VALUE;
+    default:
+        SystemCoreClock  = HSI_VALUE;
         break;
     }
 
@@ -159,7 +176,6 @@ void SystemCoreClockUpdate (void)
  *
  * @retval      None
  *
- * @note
  */
 static void SystemClockConfig(void)
 {
@@ -188,41 +204,40 @@ static void SystemClockConfig(void)
  *
  * @retval      None
  *
- * @note
  */
 static void SystemClockHSE(void)
 {
     __IO uint32_t i;
 
-    RCM->CTRL_B.HSEEN= BIT_SET;
+    RCM->CTRL_B.HSEEN = BIT_SET;
 
-    for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
+    for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
     {
-        if(RCM->CTRL_B.HSERDYFLG)
+        if (RCM->CTRL_B.HSERDYFLG)
         {
             break;
         }
     }
 
-    if(RCM->CTRL_B.HSERDYFLG)
+    if (RCM->CTRL_B.HSERDYFLG)
     {
-        /* Enable Prefetch Buffer */
+        /** Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
-        /* Flash 0 wait state */
+        /** Flash 0 wait state */
         FMC->CTRL1_B.WS = 0;
 
-        /* HCLK = SYSCLK */
-        RCM->CFG_B.AHBPSC= 0X00;
-        /* PCLK2 = HCLK */
-        RCM->CFG_B.APB2PSC= 0;
-        /* PCLK1 = HCLK */
+        /** HCLK = SYSCLK */
+        RCM->CFG_B.AHBPSC = 0X00;
+        /** PCLK2 = HCLK */
+        RCM->CFG_B.APB2PSC = 0;
+        /** PCLK1 = HCLK */
         RCM->CFG_B.APB1PSC = 0;
 
-        /* Select HSE as system clock source */
-        RCM->CFG_B.SCLKSW = 1;
+        /** Select HSE as system clock source */
+        RCM->CFG_B.SCLKSEL = 1;
 
         /** Wait till HSE is used as system clock source */
-        while(RCM->CFG_B.SCLKSWSTS!= 0x01);
+        while (RCM->CFG_B.SCLKSELSTS != 0x01);
     }
 }
 
@@ -235,34 +250,33 @@ static void SystemClockHSE(void)
  *
  * @retval      None
  *
- * @note
  */
 static void SystemClock24M(void)
 {
     __IO uint32_t i;
 
-    RCM->CTRL_B.HSEEN= BIT_SET;
+    RCM->CTRL_B.HSEEN = BIT_SET;
 
-    for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
+    for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
     {
-        if(RCM->CTRL_B.HSERDYFLG)
+        if (RCM->CTRL_B.HSERDYFLG)
         {
             break;
         }
     }
 
-    if(RCM->CTRL_B.HSERDYFLG)
+    if (RCM->CTRL_B.HSERDYFLG)
     {
-        /* Enable Prefetch Buffer */
+        /** Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
-        /* Flash 0 wait state */
+        /** Flash 0 wait state */
         FMC->CTRL1_B.WS = 0;
 
-        /* HCLK = SYSCLK */
-        RCM->CFG_B.AHBPSC= 0X00;
-        /* PCLK2 = HCLK */
-        RCM->CFG_B.APB2PSC= 0;
-        /* PCLK1 = HCLK */
+        /** HCLK = SYSCLK */
+        RCM->CFG_B.AHBPSC = 0X00;
+        /** PCLK2 = HCLK */
+        RCM->CFG_B.APB2PSC = 0;
+        /** PCLK1 = HCLK */
         RCM->CFG_B.APB1PSC = 0;
 
         /** PLL: (HSE / 2) * 6 */
@@ -273,12 +287,12 @@ static void SystemClock24M(void)
         /** Enable PLL */
         RCM->CTRL_B.PLLEN = 1;
         /** Wait PLL Ready */
-        while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
 
-        /* Select PLL as system clock source */
-        RCM->CFG_B.SCLKSW = 2;
-        /* Wait till PLL is used as system clock source */
-        while(RCM->CFG_B.SCLKSWSTS!= 0x02);
+        /** Select PLL as system clock source */
+        RCM->CFG_B.SCLKSEL = 2;
+        /** Wait till PLL is used as system clock source */
+        while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 }
 
@@ -290,34 +304,33 @@ static void SystemClock24M(void)
  *
  * @retval      None
  *
- * @note
  */
 static void SystemClock36M(void)
 {
     __IO uint32_t i;
 
-    RCM->CTRL_B.HSEEN= BIT_SET;
+    RCM->CTRL_B.HSEEN = BIT_SET;
 
-    for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
+    for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
     {
-        if(RCM->CTRL_B.HSERDYFLG)
+        if (RCM->CTRL_B.HSERDYFLG)
         {
             break;
         }
     }
 
-    if(RCM->CTRL_B.HSERDYFLG)
+    if (RCM->CTRL_B.HSERDYFLG)
     {
-        /* Enable Prefetch Buffer */
+        /** Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
-        /* Flash 1 wait state */
+        /** Flash 1 wait state */
         FMC->CTRL1_B.WS = 1;
 
-        /* HCLK = SYSCLK */
-        RCM->CFG_B.AHBPSC= 0X00;
-        /* PCLK2 = HCLK */
-        RCM->CFG_B.APB2PSC= 0;
-        /* PCLK1 = HCLK */
+        /** HCLK = SYSCLK */
+        RCM->CFG_B.AHBPSC = 0X00;
+        /** PCLK2 = HCLK */
+        RCM->CFG_B.APB2PSC = 0;
+        /** PCLK1 = HCLK */
         RCM->CFG_B.APB1PSC = 0;
 
         /** PLL: (HSE / 2) * 9 */
@@ -328,12 +341,12 @@ static void SystemClock36M(void)
         /** Enable PLL */
         RCM->CTRL_B.PLLEN = 1;
         /** Wait PLL Ready */
-        while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
 
-        /* Select PLL as system clock source */
-        RCM->CFG_B.SCLKSW = 2;
-        /* Wait till PLL is used as system clock source */
-        while(RCM->CFG_B.SCLKSWSTS != 0x02);
+        /** Select PLL as system clock source */
+        RCM->CFG_B.SCLKSEL = 2;
+        /** Wait till PLL is used as system clock source */
+        while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 }
 
@@ -345,34 +358,33 @@ static void SystemClock36M(void)
  *
  * @retval      None
  *
- * @note
  */
 static void SystemClock48M(void)
 {
     __IO uint32_t i;
 
-    RCM->CTRL_B.HSEEN= BIT_SET;
+    RCM->CTRL_B.HSEEN = BIT_SET;
 
-    for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
+    for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
     {
-        if(RCM->CTRL_B.HSERDYFLG)
+        if (RCM->CTRL_B.HSERDYFLG)
         {
             break;
         }
     }
 
-    if(RCM->CTRL_B.HSERDYFLG)
+    if (RCM->CTRL_B.HSERDYFLG)
     {
-        /* Enable Prefetch Buffer */
+        /** Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
-        /* Flash 1 wait state */
+        /** Flash 1 wait state */
         FMC->CTRL1_B.WS = 1;
 
-        /* HCLK = SYSCLK */
-        RCM->CFG_B.AHBPSC= 0X00;
-        /* PCLK2 = HCLK */
-        RCM->CFG_B.APB2PSC= 0;
-        /* PCLK1 = HCLK / 2 */
+        /** HCLK = SYSCLK */
+        RCM->CFG_B.AHBPSC = 0X00;
+        /** PCLK2 = HCLK */
+        RCM->CFG_B.APB2PSC = 0;
+        /** PCLK1 = HCLK / 2 */
         RCM->CFG_B.APB1PSC = 4;
 
         /** PLL: HSE * 6 */
@@ -382,12 +394,12 @@ static void SystemClock48M(void)
         /** Enable PLL */
         RCM->CTRL_B.PLLEN = 1;
         /** Wait PLL Ready */
-        while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
 
-        /* Select PLL as system clock source */
-        RCM->CFG_B.SCLKSW = 2;
-        /* Wait till PLL is used as system clock source */
-        while(RCM->CFG_B.SCLKSWSTS!= 0x02);
+        /** Select PLL as system clock source */
+        RCM->CFG_B.SCLKSEL = 2;
+        /** Wait till PLL is used as system clock source */
+        while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 }
 
@@ -399,34 +411,33 @@ static void SystemClock48M(void)
  *
  * @retval      None
  *
- * @note
  */
 static void SystemClock56M(void)
 {
     __IO uint32_t i;
 
-    RCM->CTRL_B.HSEEN= BIT_SET;
+    RCM->CTRL_B.HSEEN = BIT_SET;
 
-    for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
+    for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
     {
-        if(RCM->CTRL_B.HSERDYFLG)
+        if (RCM->CTRL_B.HSERDYFLG)
         {
             break;
         }
     }
 
-    if(RCM->CTRL_B.HSERDYFLG)
+    if (RCM->CTRL_B.HSERDYFLG)
     {
-        /* Enable Prefetch Buffer */
+        /** Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
-        /* Flash 2 wait state */
+        /** Flash 2 wait state */
         FMC->CTRL1_B.WS = 2;
 
-        /* HCLK = SYSCLK */
-        RCM->CFG_B.AHBPSC= 0X00;
-        /* PCLK2 = HCLK */
-        RCM->CFG_B.APB2PSC= 0;
-        /* PCLK1 = HCLK / 2 */
+        /** HCLK = SYSCLK */
+        RCM->CFG_B.AHBPSC = 0X00;
+        /** PCLK2 = HCLK */
+        RCM->CFG_B.APB2PSC = 0;
+        /** PCLK1 = HCLK / 2 */
         RCM->CFG_B.APB1PSC = 4;
 
         /** PLL: HSE * 7 */
@@ -436,12 +447,12 @@ static void SystemClock56M(void)
         /** Enable PLL */
         RCM->CTRL_B.PLLEN = 1;
         /** Wait PLL Ready */
-        while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
 
-        /* Select PLL as system clock source */
-        RCM->CFG_B.SCLKSW = 2;
-        /* Wait till PLL is used as system clock source */
-        while(RCM->CFG_B.SCLKSWSTS!= 0x02);
+        /** Select PLL as system clock source */
+        RCM->CFG_B.SCLKSEL = 2;
+        /** Wait till PLL is used as system clock source */
+        while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 }
 
@@ -453,34 +464,33 @@ static void SystemClock56M(void)
  *
  * @retval      None
  *
- * @note
  */
 static void SystemClock72M(void)
 {
     __IO uint32_t i;
 
-    RCM->CTRL_B.HSEEN= BIT_SET;
+    RCM->CTRL_B.HSEEN = BIT_SET;
 
-    for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
+    for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
     {
-        if(RCM->CTRL_B.HSERDYFLG)
+        if (RCM->CTRL_B.HSERDYFLG)
         {
             break;
         }
     }
 
-    if(RCM->CTRL_B.HSERDYFLG)
+    if (RCM->CTRL_B.HSERDYFLG)
     {
-        /* Enable Prefetch Buffer */
+        /** Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
-        /* Flash 2 wait state */
+        /** Flash 2 wait state */
         FMC->CTRL1_B.WS = 2;
 
-        /* HCLK = SYSCLK */
-        RCM->CFG_B.AHBPSC= 0X00;
-        /* PCLK2 = HCLK */
-        RCM->CFG_B.APB2PSC= 0;
-        /* PCLK1 = HCLK / 2 */
+        /** HCLK = SYSCLK */
+        RCM->CFG_B.AHBPSC = 0X00;
+        /** PCLK2 = HCLK */
+        RCM->CFG_B.APB2PSC = 0;
+        /** PCLK1 = HCLK / 2 */
         RCM->CFG_B.APB1PSC = 4;
 
         /** PLL: HSE * 9 */
@@ -490,12 +500,12 @@ static void SystemClock72M(void)
         /** Enable PLL */
         RCM->CTRL_B.PLLEN = 1;
         /** Wait PLL Ready */
-        while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
 
-        /* Select PLL as system clock source */
-        RCM->CFG_B.SCLKSW = 2;
-        /* Wait till PLL is used as system clock source */
-        while(RCM->CFG_B.SCLKSWSTS!= 0x02);
+        /** Select PLL as system clock source */
+        RCM->CFG_B.SCLKSEL = 2;
+        /** Wait till PLL is used as system clock source */
+        while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 
 }
@@ -508,34 +518,33 @@ static void SystemClock72M(void)
  *
  * @retval      None
  *
- * @note
  */
 static void SystemClock96M(void)
 {
     __IO uint32_t i;
 
-    RCM->CTRL_B.HSEEN= BIT_SET;
+    RCM->CTRL_B.HSEEN = BIT_SET;
 
-    for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
+    for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
     {
-        if(RCM->CTRL_B.HSERDYFLG)
+        if (RCM->CTRL_B.HSERDYFLG)
         {
             break;
         }
     }
 
-    if(RCM->CTRL_B.HSERDYFLG)
+    if (RCM->CTRL_B.HSERDYFLG)
     {
-        /* Enable Prefetch Buffer */
+        /** Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
-        /* Flash 3 wait state */
+        /** Flash 3 wait state */
         FMC->CTRL1_B.WS = 3;
 
-        /* HCLK = SYSCLK */
-        RCM->CFG_B.AHBPSC= 0X00;
-        /* PCLK2 = HCLK */
-        RCM->CFG_B.APB2PSC= 0;
-        /* PCLK1 = HCLK / 2 */
+        /** HCLK = SYSCLK */
+        RCM->CFG_B.AHBPSC = 0X00;
+        /** PCLK2 = HCLK */
+        RCM->CFG_B.APB2PSC = 0;
+        /** PCLK1 = HCLK / 2 */
         RCM->CFG_B.APB1PSC = 4;
 
         /** PLL: HSE * 12 */
@@ -545,12 +554,12 @@ static void SystemClock96M(void)
         /** Enable PLL */
         RCM->CTRL_B.PLLEN = 1;
         /** Wait PLL Ready */
-        while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
 
-        /* Select PLL as system clock source */
-        RCM->CFG_B.SCLKSW = 2;
-        /* Wait till PLL is used as system clock source */
-        while(RCM->CFG_B.SCLKSWSTS!= 0x02);
+        /** Select PLL as system clock source */
+        RCM->CFG_B.SCLKSEL = 2;
+        /** Wait till PLL is used as system clock source */
+        while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 }
 #endif

bsp/apm32/libraries/APM32F10x_Library/SConscript

@@ -15,6 +15,26 @@ APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c
 APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c
 """)
 
+if GetDepend(['RT_USING_ADC']):
+    src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c']
+
+if GetDepend(['RT_USING_DAC']):
+    src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c']
+
+if GetDepend(['RT_USING_RTC']):
+    src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c']
+    src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c']
+
+if GetDepend(['RT_USING_SPI']):
+    src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c']
+
+if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']):
+    src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c']
+    
+if GetDepend(['RT_USING_WDT']):
+    src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c']
+    src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c']
+    
 path = [cwd + '/Device/Geehy/APM32F10x/Include', 
     cwd + '/APM32F10x_StdPeriphDriver/inc',
     cwd + '/CMSIS/Include']

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/inc/usbd_class_cdc.h

@@ -0,0 +1,33 @@
+/*!
+ * @file        usbd_class_cdc.h
+ *
+ * @brief       CDC Class handler file head file
+ *
+ * @version     V1.0.0
+ *
+ * @date        2021-12-06
+ *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+#ifndef __CDC_CLASS_
+#define __CDC_CLASS_
+
+#include "usbd_core.h"
+
+void USBD_ClassHandler(USBD_DevReqData_T *reqData);
+
+#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/src/usbd_class_cdc.c

@@ -0,0 +1,71 @@
+/*!
+ * @file        usbd_class_cdc.c
+ *
+ * @brief       CDC Class handler file
+ *
+ * @version     V1.0.0
+ *
+ * @date        2021-12-06
+ *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+#include "usbd_class_cdc.h"
+
+static uint8_t cmdBuf[8] = {0};
+
+/*!
+ * @brief       USB CDC Class request handler
+ *
+ * @param       reqData : point to USBD_DevReqData_T structure
+ *
+ * @retval      None
+ */
+void USBD_ClassHandler(USBD_DevReqData_T *reqData)
+{
+    uint16_t length = ((uint16_t)reqData->byte.wLength[1] << 8) | \
+                      reqData->byte.wLength[0] ;
+
+    if (!length)
+    {
+        if (!reqData->byte.bmRequestType.bit.dir)
+        {
+            USBD_CtrlTxStatus();
+        }
+        else
+        {
+            USBD_CtrlRxStatus();
+        }
+    }
+    else
+    {
+        switch (reqData->byte.bRequest)
+        {
+
+        case 0x20:
+            USBD_CtrlOutData(cmdBuf, length);
+            break;
+        case 0x21:
+            USBD_CtrlInData(cmdBuf, length);
+            break;
+        case 0x22:
+            USBD_CtrlOutData(cmdBuf, length);
+            break;
+        default:
+            break;
+        }
+    }
+}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/inc/usbd_class_hid.h

@@ -0,0 +1,37 @@
+/*!
+ * @file        usbd_class_hid.h
+ *
+ * @brief       HID Class handler file head file
+ *
+ * @version     V1.0.0
+ *
+ * @date        2021-12-06
+ *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+#include "usbd_core.h"
+
+#define HID_CLASS_REQ_SET_PROTOCOL          0x0B
+#define HID_CLASS_REQ_GET_PROTOCOL          0x03
+
+#define HID_CLASS_REQ_SET_IDLE              0x0A
+#define HID_CLASS_REQ_GET_IDLE              0x02
+
+#define HID_CLASS_REQ_SET_REPORT            0x09
+#define HID_CLASS_REQ_GET_REPORT            0x01
+
+void USBD_ClassHandler(USBD_DevReqData_T *reqData);

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/src/usbd_class_hid.c

@@ -0,0 +1,63 @@
+/*!
+ * @file        usbd_class_hid.c
+ *
+ * @brief       HID Class handler file
+ *
+ * @version     V1.0.0
+ *
+ * @date        2021-12-06
+ *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+#include "usbd_class_hid.h"
+
+static uint8_t s_hidIdleState;
+static uint8_t s_hidProtocol;
+
+/*!
+ * @brief       USB HID Class request handler
+ *
+ * @param       reqData : point to USBD_DevReqData_T structure
+ *
+ * @retval      None
+ */
+void USBD_ClassHandler(USBD_DevReqData_T *reqData)
+{
+    switch (reqData->byte.bRequest)
+    {
+    case HID_CLASS_REQ_SET_IDLE:
+        s_hidIdleState = reqData->byte.wValue[1];
+        USBD_CtrlInData(NULL, 0);
+        break;
+
+    case HID_CLASS_REQ_GET_IDLE:
+        USBD_CtrlInData(&s_hidIdleState, 1);
+        break;
+
+    case HID_CLASS_REQ_SET_PROTOCOL:
+        s_hidProtocol = reqData->byte.wValue[0];
+        USBD_CtrlInData(NULL, 0);
+        break;
+
+    case HID_CLASS_REQ_GET_PROTOCOL:
+        USBD_CtrlInData(&s_hidProtocol, 1);
+        break;
+
+    default:
+        break;
+    }
+}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_class_msc.h

@@ -0,0 +1,37 @@
+/*!
+ * @file        usbd_class_msc.h
+ *
+ * @brief       MSC Class handler file head file
+ *
+ * @version     V1.0.0
+ *
+ * @date        2021-12-06
+ *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+#ifndef __USBD_CLASS_MSC
+#define __USBD_CLASS_MSC
+
+#include "usbd_core.h"
+
+
+#define BOT_GET_MAX_LUN              0xFE
+#define BOT_RESET                    0xFF
+
+void USBD_MSC_ClassHandler(USBD_DevReqData_T *reqData);
+
+#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_bot.h

@@ -0,0 +1,106 @@
+/*!
+ * @file        usbd_msc_bot.h
+ *
+ * @brief       MSC BOT protocol core functions
+ *
+ * @version     V1.0.0
+ *
+ * @date        2021-12-25
+ *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+#include "usbd_core.h"
+
+#ifndef __USBD_MSC_BOT_H
+#define __USBD_MSC_BOT_H
+
+#define MSC_BOT_CBW_SIGNATURE             (uint32_t)(0x43425355)
+#define MSC_BOT_CBW_LENGTH                31
+
+#define MSC_BOT_CSW_SIGNATURE             (uint32_t)(0x53425355)
+#define MSC_BOT_CSW_LENGTH                13
+
+typedef enum
+{
+    BOT_STATE_IDLE,          //!< Idle state
+    BOT_STATE_DATA_OUT,      //!< Data Out state
+    BOT_STATE_DATA_IN,       //!< Data In state
+    BOT_STATE_LAST_DATA_IN,  //!< Last Data In Last
+    BOT_STATE_SEND_DATA      //!< Send Immediate data
+} BOT_STATE_T;
+
+typedef enum
+{
+    BOT_STATUS_NORMAL,
+    BOT_STATUS_RECOVERY,
+    BOT_STATUS_ERROR
+} BOT_STATUS_T;
+
+typedef enum
+{
+    BOT_CSW_STATUS_CMD_OK,
+    BOT_CSW_STATUS_CMD_FAIL,
+    BOT_CSW_STATUS_PHASE_ERROR
+} BOT_CSW_STATUS_T;
+
+
+/**
+ * @brief   Command Block Wrapper
+ */
+typedef struct
+{
+    uint32_t dSignature;
+    uint32_t dTag;
+    uint32_t dDataXferLen;
+    uint8_t  bmFlags;
+    uint8_t  bLUN;
+    uint8_t  bCBLen;
+    uint8_t  CB[16];
+} BOT_CBW_T;
+
+/**
+ * @brief   Command Status Wrapper
+ */
+typedef struct
+{
+    uint32_t dSignature;
+    uint32_t dTag;
+    uint32_t dDataResidue;
+    uint8_t  bStatus;
+} BOT_CSW_T;
+
+typedef struct
+{
+    uint8_t   state;
+    uint8_t   status;
+    uint16_t  dataLen;
+    BOT_CBW_T CBW;
+    BOT_CSW_T CSW;
+    uint8_t   data[MSC_MEDIA_PACKET];
+} BOT_Info_T;
+
+extern BOT_Info_T g_BOTInfo;
+
+void USBD_MSC_BOT_Reset(void);
+void USBD_MSC_BOT_Init(void);
+void USBD_MSC_BOT_OutData(uint8_t ep);
+void USBD_MSC_BOT_InData(uint8_t ep);
+void USBD_MSC_BOT_TxCSW(uint8_t cswStatus);
+void USBD_MSC_BOT_Stall(void);
+void USBD_MSV_BOT_ClearFeatureHandler(void);
+
+#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_scsi.h

@@ -0,0 +1,132 @@
+/*!
+ * @file        usbd_msc_scsi.h
+ *
+ * @brief       MSC scsi
+ *
+ * @version     V1.0.0
+ *
+ * @date        2021-12-25
+ *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+#include "usbd_core.h"
+#ifndef __USBD_MSC_SCSI_H_
+#define __USBD_MSC_SCSI_H_
+
+/**
+ * @brief   SCSI function status
+ */
+enum
+{
+    SCSI_OK,
+    SCSI_FAIL
+};
+
+/**
+ * @brief   SCSI Sense Key
+ */
+typedef enum
+{
+    SCSI_SKEY_NO_SENSE,
+    SCSI_SKEY_RECOVERED_ERROR,
+    SCSI_SKEY_NOT_READY,
+    SCSI_SKEY_MEDIUM_ERROR,
+    SCSI_SKEY_HARDWARE_ERROR,
+    SCSI_SKEY_ILLEGAL_REQUEST,
+    SCSI_SKEY_UNIT_ATTENTION,
+    SCSI_SKEY_DATA_PROTECT,
+    SCSI_SKEY_BLANK_CHECK,
+    SCSI_SKEY_VENDOR_SPECIFIC,
+    SCSI_SKEY_COPY_ABORTED,
+    SCSI_SKEY_ABORTED_COMMAND,
+    SCSI_SKEY_VOLUME_OVERFLOW = 13,
+    SCSI_SKEY_MISCOMPARE      = 14
+} SCSI_SKEY_T;
+
+/**
+ * @brief   SCSI Sense
+ */
+typedef struct
+{
+    uint8_t sensekey;
+    uint8_t ASC;
+    uint8_t ASCQ;
+} SCSI_Sense_T;
+
+
+#define SCSI_SENSE_LIST_NUMBER                      4
+#define SCSI_INQUIRY_LENGTH                         36
+
+/** SCSI Commands */
+#define SCSI_CMD_FORMAT_UNIT                        ((uint8_t)0x04)
+#define SCSI_CMD_INQUIRY                            ((uint8_t)0x12)
+#define SCSI_CMD_MODE_SELECT_6                      ((uint8_t)0x15)
+#define SCSI_CMD_MODE_SELECT_10                     ((uint8_t)0x55)
+#define SCSI_CMD_MODE_SENSE_6                       ((uint8_t)0x1A)
+#define SCSI_CMD_MODE_SENSE_10                      ((uint8_t)0x5A)
+#define SCSI_CMD_ALLOW_MEDIUM_REMOVAL               ((uint8_t)0x1E)
+#define SCSI_CMD_READ_6                             ((uint8_t)0x08)
+#define SCSI_CMD_READ_10                            ((uint8_t)0x28)
+#define SCSI_CMD_READ_12                            ((uint8_t)0xA8)
+#define SCSI_CMD_READ_16                            ((uint8_t)0x88)
+
+#define SCSI_CMD_READ_CAPACITY_10                   ((uint8_t)0x25)
+#define SCSI_CMD_READ_CAPACITY_16                   ((uint8_t)0x9E)
+
+#define SCSI_CMD_REQUEST_SENSE                      ((uint8_t)0x03)
+#define SCSI_CMD_START_STOP_UNIT                    ((uint8_t)0x1B)
+#define SCSI_CMD_TEST_UNIT_READY                    ((uint8_t)0x00)
+#define SCSI_CMD_WRITE6                             ((uint8_t)0x0A)
+#define SCSI_CMD_WRITE10                            ((uint8_t)0x2A)
+#define SCSI_CMD_WRITE12                            ((uint8_t)0xAA)
+#define SCSI_CMD_WRITE16                            ((uint8_t)0x8A)
+
+#define SCSI_CMD_VERIFY_10                          ((uint8_t)0x2F)
+#define SCSI_CMD_VERIFY_12                          ((uint8_t)0xAF)
+#define SCSI_CMD_VERIFY_16                          ((uint8_t)0x8F)
+
+#define SCSI_CMD_SEND_DIAGNOSTIC                    ((uint8_t)0x1D)
+#define SCSI_CMD_READ_FORMAT_CAPACITIES             ((uint8_t)0x23)
+
+
+#define SCSI_ASC_INVALID_CDB                         0x20
+#define SCSI_ASC_INVALID_FIELED_IN_COMMAND           0x24
+#define SCSI_ASC_PARAMETER_LIST_LENGTH_ERROR         0x1A
+#define SCSI_ASC_INVALID_FIELD_IN_PARAMETER_LIST     0x26
+#define SCSI_ASC_ADDRESS_OUT_OF_RANGE                0x21
+#define SCSI_ASC_MEDIUM_NOT_PRESENT                  0x3A
+#define SCSI_ASC_MEDIUM_HAVE_CHANGED                 0x28
+#define SCSI_ASC_WRITE_PROTECTED                     0x27
+#define SCSI_ASC_UNRECOVERED_READ_ERROR              0x11
+#define SCSI_ASC_WRITE_FAULT                         0x03
+
+#define SCSI_READ_FORMAT_CAPACITY_DATA_LEN           0x0C
+#define SCSI_READ_CAPACITY10_DATA_LEN                0x08
+#define SCSI_MODE_SENSE10_DATA_LEN                   0x08
+#define SCSI_MODE_SENSE6_DATA_LEN                    0x04
+#define SCSI_REQUEST_SENSE_DATA_LEN                  0x12
+#define SCSI_STANDARD_INQUIRY_DATA_LEN               0x24
+#define SCSI_BLKVFY                                  0x04
+
+extern SCSI_Sense_T g_scsiSense[SCSI_SENSE_LIST_NUMBER];
+extern uint8_t g_senseTxCnt;
+extern uint8_t g_sensePutCnt;
+
+uint8_t SCSI_CmdHandler(uint8_t lun, uint8_t *cmd);
+void   SCSI_PutSenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC, uint8_t ASCQ);
+
+#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_class_msc.c

@@ -0,0 +1,79 @@
+/*!
+ * @file        usbd_class_msc.c
+ *
+ * @brief       MSC Class file
+ *
+ * @version     V1.0.0
+ *
+ * @date        2021-12-06
+ *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+#include "usbd_class_msc.h"
+#include "usbd_msc_bot.h"
+
+static uint8_t s_mscMaxLen = 0;
+
+/*!
+ * @brief       USB MSC Class request handler
+ *
+ * @param       reqData : point to USBD_DevReqData_T structure
+ *
+ * @retval      None
+ */
+void USBD_MSC_ClassHandler(USBD_DevReqData_T *reqData)
+{
+    uint16_t wValue = ((uint16_t)reqData->byte.wValue[1] << 8) | \
+                      reqData->byte.wValue[0];
+    uint16_t wLength = ((uint16_t)reqData->byte.wLength[1] << 8) | \
+                       reqData->byte.wLength[0];
+
+    switch (reqData->byte.bRequest)
+    {
+    case BOT_GET_MAX_LUN :
+        if ((wValue == 0) && (wLength == 1) && \
+                (reqData->byte.bmRequestType.bit.dir == 1))
+        {
+            s_mscMaxLen = STORAGE_MAX_LUN - 1;
+
+            USBD_CtrlInData(&s_mscMaxLen, 1);
+        }
+        else
+        {
+            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
+        }
+        break;
+    case BOT_RESET :
+        if ((wValue == 0) && (wLength == 0) && \
+                (reqData->byte.bmRequestType.bit.dir == 0))
+        {
+            USBD_CtrlInData(NULL, 0);
+            /** Reset */
+            USBD_MSC_BOT_Reset();
+        }
+        else
+        {
+            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
+        }
+
+        break;
+
+    default:
+        USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
+        break;
+    }
+}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_bot.c

@@ -0,0 +1,242 @@
+/*!
+ * @file        usbd_msv_bot.c
+ *
+ * @brief       MSC BOT protocol core functions
+ *
+ * @version     V1.0.0
+ *
+ * @date        2021-12-25
+ *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+#include "usbd_msc_bot.h"
+#include "usbd_core.h"
+#include "usbd_storage_disk.h"
+#include "usbd_msc_scsi.h"
+
+BOT_Info_T g_BOTInfo;
+
+static void USBD_MSC_BOT_DecodeCBW(void);
+static void USBD_MSC_BOT_TxData(uint8_t *txBuf, uint16_t len);
+static void USBD_MSC_BOT_Stall(void);
+
+/*!
+ * @brief       BOT Process Reset.
+ *
+ * @param       None
+ *
+ * @retval      None
+ */
+void USBD_MSC_BOT_Reset(void)
+{
+    g_BOTInfo.state = BOT_STATE_IDLE;
+    g_BOTInfo.status = BOT_STATUS_RECOVERY;
+
+    USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW, MSC_BOT_CBW_LENGTH);
+}
+
+/*!
+ * @brief       BOT Process initialization.
+ *
+ * @param       None
+ *
+ * @retval      None
+ */
+void USBD_MSC_BOT_Init(void)
+{
+    g_BOTInfo.state = BOT_STATE_IDLE;
+    g_BOTInfo.status = BOT_STATUS_NORMAL;
+
+    g_storageCallBack.Init(0);
+
+    USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW, MSC_BOT_CBW_LENGTH);
+}
+
+/*!
+ * @brief       Bulk OUT data handler.
+ *
+ * @param       ep : OUT endpoint
+ *
+ * @retval      None
+ */
+void USBD_MSC_BOT_OutData(uint8_t ep)
+{
+    if (g_BOTInfo.state == BOT_STATE_IDLE)
+    {
+        USBD_MSC_BOT_DecodeCBW();
+    }
+    else if (g_BOTInfo.state == BOT_STATE_DATA_OUT)
+    {
+        if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK)
+        {
+            USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL);
+        }
+    }
+}
+
+/*!
+ * @brief       Bulk IN data handler.
+ *
+ * @param       ep : IN endpoint
+ *
+ * @retval      None
+ */
+void USBD_MSC_BOT_InData(uint8_t ep)
+{
+    if (g_BOTInfo.state == BOT_STATE_DATA_IN)
+    {
+        if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK)
+        {
+            USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL);
+        }
+    }
+    else if ((g_BOTInfo.state == BOT_STATE_SEND_DATA) || \
+             (g_BOTInfo.state == BOT_STATE_LAST_DATA_IN))
+    {
+        USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK);
+    }
+}
+
+/*!
+ * @brief       Decode CBW.
+ *
+ * @param       None
+ *
+ * @retval      None
+ */
+static void USBD_MSC_BOT_DecodeCBW(void)
+{
+    uint32_t xferCnt = g_usbDev.outBuf[MSC_OUT_EP & 0x7f].xferCnt;
+
+    g_BOTInfo.CSW.dTag = g_BOTInfo.CBW.dTag;
+    g_BOTInfo.CSW.dDataResidue = g_BOTInfo.CBW.dDataXferLen;
+
+    if ((xferCnt != MSC_BOT_CBW_LENGTH) || \
+            (g_BOTInfo.CBW.dSignature != MSC_BOT_CBW_SIGNATURE) || \
+            (g_BOTInfo.CBW.bLUN > 1) || (g_BOTInfo.CBW.bCBLen < 1) || \
+            (g_BOTInfo.CBW.bCBLen > 16))
+    {
+        SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
+                          SCSI_ASC_INVALID_CDB, 0);
+
+        g_BOTInfo.status = BOT_STATUS_ERROR;
+    }
+    else
+    {
+        if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK)
+        {
+            USBD_MSC_BOT_Stall();
+        }
+        else if ((g_BOTInfo.state == BOT_STATE_IDLE) || \
+                 (g_BOTInfo.state == BOT_STATE_SEND_DATA))
+        {
+            if (g_BOTInfo.dataLen)
+            {
+                USBD_MSC_BOT_TxData(g_BOTInfo.data, g_BOTInfo.dataLen);
+            }
+            else
+            {
+                USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK);
+            }
+        }
+    }
+}
+
+/*!
+ * @brief       MSC send data.
+ *
+ * @param       txBuf : buffer to send
+ *
+ * @param       len : buffer length
+ *
+ * @retval      None
+ */
+static void USBD_MSC_BOT_TxData(uint8_t *txBuf, uint16_t len)
+{
+    len = USB_MIN(len, g_BOTInfo.CBW.dDataXferLen);
+
+    g_BOTInfo.CSW.dDataResidue -= len;
+    g_BOTInfo.CSW.bStatus = BOT_CSW_STATUS_CMD_OK;
+    g_BOTInfo.state = BOT_STATE_SEND_DATA;
+
+    USBD_TxData(MSC_IN_EP & 0x7f, txBuf, len);
+}
+
+/*!
+ * @brief       Send CSW.
+ *
+ * @param       cswStatus : status of CSW
+ *
+ * @retval      None
+ */
+void USBD_MSC_BOT_TxCSW(uint8_t cswStatus)
+{
+    g_BOTInfo.CSW.dSignature = MSC_BOT_CSW_SIGNATURE;
+    g_BOTInfo.CSW.bStatus = cswStatus;
+    g_BOTInfo.state = BOT_STATE_IDLE;
+
+    USBD_TxData(MSC_IN_EP & 0x7f, (uint8_t *)&g_BOTInfo.CSW,
+                MSC_BOT_CSW_LENGTH);
+
+    USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW,
+                MSC_BOT_CBW_LENGTH);
+}
+
+/*!
+ * @brief       handler clearFeature in standard request.
+ *
+ * @param       None
+ *
+ * @retval      None
+ */
+void USBD_MSV_BOT_ClearFeatureHandler(void)
+{
+    if (g_BOTInfo.status == BOT_STATUS_ERROR)
+    {
+        USBD_SetEPTxStatus(MSC_IN_EP & 0x7f, USBD_EP_STATUS_NAK);
+        g_BOTInfo.status = BOT_STATUS_NORMAL;
+    }
+    else if (((g_usbDev.reqData.byte.wIndex[0] & 0x80) == 0x80) && \
+             g_BOTInfo.status != BOT_STATUS_RECOVERY)
+    {
+        USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL);
+    }
+}
+
+/*!
+ * @brief       Stall MSC.
+ *
+ * @param       None
+ *
+ * @retval      None
+ */
+static void USBD_MSC_BOT_Stall(void)
+{
+    if ((g_BOTInfo.CBW.bmFlags == 0) && (g_BOTInfo.CBW.dDataXferLen != 0) && \
+            (g_BOTInfo.status == BOT_STATUS_NORMAL))
+    {
+        USBD_SetEPRxStatus(MSC_OUT_EP & 0x7f, USBD_EP_STATUS_STALL);
+    }
+
+    USBD_SetEPTxStatus(MSC_IN_EP & 0x7f, USBD_EP_STATUS_STALL);
+
+    if (g_BOTInfo.status == BOT_STATUS_ERROR)
+    {
+        USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW,
+                    MSC_BOT_CBW_LENGTH);
+    }
+}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_scsi.c

@@ -0,0 +1,701 @@
+/*!
+ * @file        usbd_msc_scsi.c
+ *
+ * @brief       MSC scsi
+ *
+ * @version     V1.0.0
+ *
+ * @date        2021-12-25
+ *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be usefull and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+#include "usbd_msc_bot.h"
+#include "usbd_msc_scsi.h"
+#include "usbd_storage_disk.h"
+
+SCSI_Sense_T g_scsiSenseCode[SCSI_SENSE_LIST_NUMBER];
+uint8_t g_senseTxCnt;
+uint8_t g_sensePutCnt;
+
+static uint32_t  s_blkSize;
+static uint32_t  s_blkNbr;
+
+static uint32_t  s_blkAddr;
+static uint32_t  s_blkLen;
+
+/** USB Mass storage Page 0 Inquiry Data */
+static const uint8_t  s_page00InquiryData[] =
+{
+    0x00,
+    0x00,
+    0x00,
+    (7 - 4),
+    0x00,
+    0x80,
+    0x83
+};
+/** USB Mass storage sense 6 Data */
+static const uint8_t  s_modeSense6Data[] =
+{
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00
+};
+/** USB Mass storage sense 10 Data */
+static const uint8_t  s_modeSense10Data[] =
+{
+    0x00,
+    0x06,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00
+};
+
+static uint8_t SCSI_TestUnitReady(uint8_t lun);
+static uint8_t SCSI_Inquiry(uint8_t lun, uint8_t *command);
+static uint8_t SCSI_RequestSense(uint8_t lun, uint8_t *command);
+
+static uint8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *command);
+static uint8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *command);
+static uint8_t SCSI_Read10(uint8_t lun, uint8_t *command);
+static uint8_t SCSI_Write10(uint8_t lun, uint8_t *command);
+static uint8_t SCSI_Verify10(uint8_t lun, uint8_t *command);
+
+static uint8_t SCSI_StartStopUnit(void);
+static uint8_t SCSI_ModeSense6(uint8_t lun, uint8_t *command);
+static uint8_t SCSI_ModeSense10(uint8_t lun, uint8_t *command);
+
+static uint8_t SCSI_Read(uint8_t lun);
+static uint8_t SCSI_Write(uint8_t lun);
+static uint8_t SCSI_CheckAddress(uint8_t lun, uint32_t blkOffset, uint16_t blkNbr);
+
+/*!
+ * @brief       SCSI command handler.
+ *
+ * @param       lun: Logical unit number
+ *
+ * @param       command: Command pointer
+ *
+ * @retval      SCSI_OK or SCSI_FAILL
+ */
+uint8_t SCSI_CmdHandler(uint8_t lun, uint8_t *command)
+{
+    uint8_t ret = SCSI_OK;
+
+    switch (command[0])
+    {
+    case SCSI_CMD_TEST_UNIT_READY:
+        ret = SCSI_TestUnitReady(lun);
+        break;
+
+    case SCSI_CMD_INQUIRY:
+        ret = SCSI_Inquiry(lun, command);
+        break;
+
+    case SCSI_CMD_REQUEST_SENSE:
+        ret = SCSI_RequestSense(lun, command);
+        break;
+
+    case SCSI_CMD_READ_FORMAT_CAPACITIES:
+        ret = SCSI_ReadFormatCapacity(lun, command);
+        break;
+
+    case SCSI_CMD_READ_CAPACITY_10:
+        ret = SCSI_ReadCapacity10(lun, command);
+        break;
+
+    case SCSI_CMD_READ_10:
+        ret = SCSI_Read10(lun, command);
+        break;
+
+    case SCSI_CMD_WRITE10:
+        ret = SCSI_Write10(lun, command);
+        break;
+
+    case SCSI_CMD_VERIFY_10:
+        ret = SCSI_Verify10(lun, command);
+        break;
+    case SCSI_CMD_ALLOW_MEDIUM_REMOVAL:
+    case SCSI_CMD_START_STOP_UNIT:
+        ret = SCSI_StartStopUnit();
+        break;
+
+    case SCSI_CMD_MODE_SENSE_6:
+        ret = SCSI_ModeSense6(lun, command);
+        break;
+
+    case SCSI_CMD_MODE_SENSE_10:
+        ret = SCSI_ModeSense10(lun, command);
+        break;
+
+    default:
+        SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST,
+                          SCSI_ASC_INVALID_CDB, 0);
+        ret = SCSI_FAIL;
+    }
+
+    return ret;
+}
+
+/*!
+ * @brief       Put the sense code to array.
+ *
+ * @param       sKey: sense Key
+ *
+ * @param       ASC: Additional Sense Code
+ *
+ * @param       ASCQ: Additional Sense Code Qualifier
+ *
+ * @retval      None
+ */
+void SCSI_PutSenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC, uint8_t ASCQ)
+{
+    g_scsiSenseCode[g_sensePutCnt].sensekey = sKey;
+    g_scsiSenseCode[g_sensePutCnt].ASC = ASC;
+    g_scsiSenseCode[g_sensePutCnt].ASCQ = ASCQ;
+
+    if ((++g_sensePutCnt) == SCSI_SENSE_LIST_NUMBER)
+    {
+        g_sensePutCnt = 0;
+    }
+}
+
+/*!
+ * @brief       SCSI Test Unit Ready handler.
+ *
+ * @param       lun: Logical unit number
+ *
+ * @retval      SCSI_OK or SCSI_FAILL
+ */
+static uint8_t SCSI_TestUnitReady(uint8_t lun)
+{
+    if (g_BOTInfo.CBW.dDataXferLen)
+    {
+        SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
+                          SCSI_ASC_INVALID_CDB, 0);
+
+        return SCSI_FAIL;
+    }
+    else if (g_storageCallBack.CheckReady(lun) != SCSI_OK)
+    {
+        SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
+                          SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
+
+        return SCSI_FAIL;
+    }
+    else
+    {
+        g_BOTInfo.dataLen = 0;
+        return SCSI_OK;
+    }
+}
+
+/*!
+ * @brief       SCSI Inquiry handler.
+ *
+ * @param       lun: Logical unit number
+ *
+ * @param       command: command pointer
+ *
+ * @retval      SCSI_OK or SCSI_FAILL
+ */
+static uint8_t SCSI_Inquiry(uint8_t lun, uint8_t *command)
+{
+    uint16_t i;
+    uint8_t *pInquiryData;
+
+    if (command[1] & 0x01)
+    {
+        pInquiryData = (uint8_t *)s_page00InquiryData;
+        g_BOTInfo.dataLen = s_page00InquiryData[3] + 4;
+    }
+    else
+    {
+        pInquiryData = &g_storageCallBack.pInquiryData[lun * SCSI_INQUIRY_LENGTH];
+
+        g_BOTInfo.dataLen = USB_MIN((pInquiryData[4] + 5), command[4]);
+    }
+
+    for (i = 0; i < g_BOTInfo.dataLen; i++)
+    {
+        g_BOTInfo.data[i] = pInquiryData[i];
+    }
+
+    return SCSI_OK;
+}
+
+/*!
+ * @brief       SCSI Request Sense handler.
+ *
+ * @param       lun: Logical unit number
+ *
+ * @param       command: command pointer
+ *
+ * @retval      SCSI_OK or SCSI_FAILL
+ */
+static uint8_t SCSI_RequestSense(uint8_t lun, uint8_t *command)
+{
+    uint8_t i = 0;
+
+    while (i < SCSI_REQUEST_SENSE_DATA_LEN)
+    {
+        g_BOTInfo.data[i++] = 0;
+    }
+
+    g_BOTInfo.data[0] = 0x70;
+    g_BOTInfo.data[7] = SCSI_REQUEST_SENSE_DATA_LEN - 6;
+
+    if (g_senseTxCnt != g_sensePutCnt)
+    {
+        g_BOTInfo.data[2] = g_scsiSenseCode[g_senseTxCnt].sensekey;
+        g_BOTInfo.data[12] = g_scsiSenseCode[g_senseTxCnt].ASC;
+        g_BOTInfo.data[13] = g_scsiSenseCode[g_senseTxCnt].ASCQ;
+
+        if ((++g_senseTxCnt) == SCSI_SENSE_LIST_NUMBER)
+        {
+            g_senseTxCnt = 0;
+        }
+    }
+
+    g_BOTInfo.dataLen = (SCSI_REQUEST_SENSE_DATA_LEN < command[4]) ? \
+                        SCSI_REQUEST_SENSE_DATA_LEN : command[4];
+
+    return SCSI_OK;
+}
+
+/*!
+ * @brief       SCSI Read Format Capacity handler.
+ *
+ * @param       lun: Logical unit number
+ *
+ * @param       command: command pointer
+ *
+ * @retval      SCSI_OK or SCSI_FAILL
+ */
+static uint8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *command)
+{
+    uint16_t i = 0;
+    uint32_t blkSize;
+    uint32_t blkNbr;
+
+    while (i < 12)
+    {
+        g_BOTInfo.data[i++] = 0;
+    }
+
+    if (g_storageCallBack.ReadCapacity(lun, &blkNbr, &blkSize) != SCSI_OK)
+    {
+        SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
+                          SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
+
+        return SCSI_FAIL;
+    }
+    else
+    {
+        blkNbr--;
+
+        g_BOTInfo.data[3] = 0x08;
+        g_BOTInfo.data[4] = (uint8_t)(blkNbr >> 24);
+        g_BOTInfo.data[5] = (uint8_t)(blkNbr >> 16);
+        g_BOTInfo.data[6] = (uint8_t)(blkNbr >> 8);
+        g_BOTInfo.data[7] = (uint8_t)(blkNbr);
+        g_BOTInfo.data[8] = 0x02;
+        g_BOTInfo.data[9] = (uint8_t)(blkSize >> 16);
+        g_BOTInfo.data[10] = (uint8_t)(blkSize >> 8);
+        g_BOTInfo.data[11] = (uint8_t)blkSize;
+
+        g_BOTInfo.dataLen = 12;
+
+        return SCSI_OK;
+    }
+}
+
+/*!
+ * @brief       SCSI Read Capacity10 handler.
+ *
+ * @param       lun: Logical unit number
+ *
+ * @param       command: command pointer
+ *
+ * @retval      SCSI_OK or SCSI_FAILL
+ */
+static uint8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *command)
+{
+    if (g_storageCallBack.ReadCapacity(lun, &s_blkNbr, &s_blkSize) != SCSI_OK)
+    {
+        SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
+                          SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
+
+        return SCSI_FAIL;
+    }
+    else
+    {
+        g_BOTInfo.data[0] = (uint8_t)((s_blkNbr - 1) >> 24);
+        g_BOTInfo.data[1] = (uint8_t)((s_blkNbr - 1) >> 16);
+        g_BOTInfo.data[2] = (uint8_t)((s_blkNbr - 1) >>  8);
+        g_BOTInfo.data[3] = (uint8_t)(s_blkNbr - 1);
+        g_BOTInfo.data[4] = (uint8_t)(s_blkSize >>  24);
+        g_BOTInfo.data[5] = (uint8_t)(s_blkSize >>  16);
+        g_BOTInfo.data[6] = (uint8_t)(s_blkSize >>  8);
+        g_BOTInfo.data[7] = (uint8_t)(s_blkSize);
+
+        g_BOTInfo.dataLen = 8;
+
+        return SCSI_OK;
+    }
+}
+
+/*!
+ * @brief       SCSI Read10 handler.
+ *
+ * @param       lun: Logical unit number
+ *
+ * @param       command: command pointer
+ *
+ * @retval      SCSI_OK or SCSI_FAILL
+ */
+static uint8_t SCSI_Read10(uint8_t lun, uint8_t *command)
+{
+    uint8_t ret = SCSI_OK;
+
+    if (g_BOTInfo.state == BOT_STATE_IDLE)
+    {
+        if ((g_BOTInfo.CBW.bmFlags & 0x80) != 0x80)
+        {
+            SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
+                              SCSI_ASC_INVALID_CDB, 0);
+
+            return SCSI_FAIL;
+        }
+
+        if (g_storageCallBack.CheckReady(lun) != SCSI_OK)
+        {
+            SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
+                              SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
+
+            return SCSI_FAIL;
+        }
+
+        s_blkAddr = ((uint32_t)command[2] << 24) | \
+                    ((uint32_t)command[3] << 16) | \
+                    ((uint32_t)command[4] << 8)  | \
+                    (uint32_t)command[5];
+
+        s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t)command[8]);
+
+        if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK)
+        {
+            return SCSI_FAIL;
+        }
+
+        g_BOTInfo.state = BOT_STATE_DATA_IN;
+        s_blkAddr *= s_blkSize;
+        s_blkLen *= s_blkSize;
+
+        if (g_BOTInfo.CBW.dDataXferLen != s_blkLen)
+        {
+            SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
+                              SCSI_ASC_INVALID_CDB, 0);
+
+            return SCSI_FAIL;
+        }
+
+    }
+
+    g_BOTInfo.dataLen = MSC_MEDIA_PACKET;
+
+    ret = SCSI_Read(lun);
+
+    return ret;
+}
+
+/*!
+ * @brief       SCSI write10 handler.
+ *
+ * @param       lun: Logical unit number
+ *
+ * @param       command: command pointer
+ *
+ * @retval      SCSI_OK or SCSI_FAILL
+ */
+static uint8_t SCSI_Write10(uint8_t lun, uint8_t *command)
+{
+    uint8_t ret = SCSI_OK;
+    uint32_t len;
+
+    if (g_BOTInfo.state == BOT_STATE_IDLE)
+    {
+        if (g_BOTInfo.CBW.bmFlags & 0x80)
+        {
+            SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
+                              SCSI_ASC_INVALID_CDB, 0);
+
+            return SCSI_FAIL;
+        }
+
+        if (g_storageCallBack.CheckReady(lun) != SCSI_OK)
+        {
+            SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
+                              SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
+
+            return SCSI_FAIL;
+        }
+
+        if (g_storageCallBack.CheckWPR(lun) != SCSI_OK)
+        {
+            SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
+                              SCSI_ASC_WRITE_PROTECTED, 0);
+
+            return SCSI_FAIL;
+        }
+
+        s_blkAddr = ((uint32_t)command[2] << 24) | \
+                    ((uint32_t)command[3] << 16) | \
+                    ((uint32_t)command[4] << 8)  | \
+                    (uint32_t)command[5];
+
+        s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t)command[8]);
+
+        if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK)
+        {
+            return SCSI_FAIL;
+        }
+
+        s_blkAddr *= s_blkSize;
+        s_blkLen  *= s_blkSize;
+
+        if (g_BOTInfo.CBW.dDataXferLen != s_blkLen)
+        {
+            SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
+                              SCSI_ASC_INVALID_CDB, 0);
+
+            return SCSI_FAIL;
+        }
+
+        g_BOTInfo.state = BOT_STATE_DATA_OUT;
+        len = USB_MIN(s_blkLen, MSC_MEDIA_PACKET);
+
+        USBD_RxData(MSC_OUT_EP & 0x7F, g_BOTInfo.data, len);
+
+    }
+    else
+    {
+        ret = SCSI_Write(lun);
+    }
+
+    return ret;
+}
+
+/*!
+ * @brief       SCSI Verify10 Handler.
+ *
+ * @param       lun: Logical unit number
+ *
+ * @param       command: command pointer
+ *
+ * @retval      SCSI_OK or SCSI_FAILL
+ */
+static uint8_t SCSI_Verify10(uint8_t lun, uint8_t *command)
+{
+    if (command[1] & 0x02)
+    {
+        SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST,
+                          SCSI_ASC_INVALID_FIELED_IN_COMMAND, 0);
+
+        return SCSI_FAIL;
+    }
+
+    s_blkAddr = ((uint32_t)command[2] << 24) | \
+                ((uint32_t)command[3] << 16) | \
+                ((uint32_t)command[4] << 8)  | \
+                (uint32_t)command[5];
+
+    s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t)command[8]);
+
+    if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK)
+    {
+        return SCSI_FAIL;
+    }
+
+    g_BOTInfo.dataLen = 0;
+
+    return SCSI_OK;
+}
+
+/*!
+ * @brief       SCSI Start Stop Unit Handler.
+ *
+ * @param       None
+ *
+ * @retval      SCSI_OK or SCSI_FAILL
+ */
+static uint8_t SCSI_StartStopUnit(void)
+{
+    g_BOTInfo.dataLen = 0;
+    return SCSI_OK;
+}
+
+/*!
+ * @brief       SCSI Mode Sense6 Handler.
+ *
+ * @param       lun: Logical unit number
+ *
+ * @param       command: command pointer
+ *
+ * @retval      SCSI_OK or SCSI_FAILL
+ */
+static uint8_t SCSI_ModeSense6(uint8_t lun, uint8_t *command)
+{
+    for (uint16_t i = 0; i < 8; i++)
+    {
+        g_BOTInfo.data[i] = s_modeSense6Data[i];
+    }
+
+    g_BOTInfo.dataLen = 8;
+
+    return SCSI_OK;
+}
+
+/*!
+ * @brief       SCSI Mode Sense10 Handler.
+ *
+ * @param       lun: Logical unit number
+ *
+ * @param       command: command pointer
+ *
+ * @retval      SCSI_OK or SCSI_FAILL
+ */
+static uint8_t SCSI_ModeSense10(uint8_t lun, uint8_t *command)
+{
+    for (uint16_t i = 0; i < 8; i++)
+    {
+        g_BOTInfo.data[i] = s_modeSense10Data[i];
+    }
+
+    g_BOTInfo.dataLen = 8;
+
+    return SCSI_OK;
+}
+
+/*!
+ * @brief       SCSI Read Process.
+ *
+ * @param       lun: Logical unit number
+ *
+ * @retval      SCSI_OK or SCSI_FAILL
+ */
+static uint8_t SCSI_Read(uint8_t lun)
+{
+    uint32_t len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen);
+
+    if (g_storageCallBack.ReadData(len, g_BOTInfo.data, (s_blkAddr / s_blkSize),
+                                   (len / s_blkSize)) != SCSI_OK)
+    {
+        SCSI_PutSenseCode(lun, SCSI_SKEY_HARDWARE_ERROR,
+                          SCSI_ASC_UNRECOVERED_READ_ERROR, 0);
+
+        return SCSI_FAIL;
+    }
+
+    USBD_TxData(MSC_IN_EP & 0x7F, g_BOTInfo.data, len);
+
+    s_blkAddr += len;
+    s_blkLen  -= len;
+
+    g_BOTInfo.CSW.dDataResidue -= len;
+
+    if (s_blkLen == 0)
+    {
+        g_BOTInfo.state = BOT_STATE_LAST_DATA_IN;
+    }
+
+    return SCSI_OK;
+}
+
+/*!
+ * @brief       SCSI Write Process.
+ *
+ * @param       lun: Logical unit number
+ *
+ * @retval      SCSI_OK or SCSI_FAILL
+ */
+static uint8_t SCSI_Write(uint8_t lun)
+{
+    uint32_t len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen);
+
+    if (s_blkLen - len)
+    {
+        __NOP();
+    }
+    if (g_storageCallBack.WriteData(lun, g_BOTInfo.data, s_blkAddr / s_blkSize,
+                                    len / s_blkSize) != SCSI_OK)
+    {
+        SCSI_PutSenseCode(lun, SCSI_SKEY_HARDWARE_ERROR, SCSI_ASC_WRITE_FAULT, 0);
+
+        return SCSI_FAIL;
+    }
+
+    s_blkAddr += len;
+    s_blkLen  -= len;
+
+    g_BOTInfo.CSW.dDataResidue -= len;
+
+    if (s_blkLen)
+    {
+        len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen);
+
+        USBD_RxData(MSC_OUT_EP & 0x7f, g_BOTInfo.data, len);
+    }
+    else
+    {
+        USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK);
+    }
+
+    return SCSI_OK;
+}
+
+/*!
+ * @brief       SCSI Check Address Range.
+ *
+ * @param       lun: Logical unit number
+ *
+ * @param       blkOffset: first block address
+ *
+ * @param       blkNbr: number of block to be processed
+ *
+ * @retval      SCSI_OK or SCSI_FAILL
+ */
+static uint8_t SCSI_CheckAddress(uint8_t lun, uint32_t blkOffset, uint16_t blkNbr)
+{
+    if (s_blkNbr < (blkNbr + blkOffset))
+    {
+        SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST,
+                          SCSI_ASC_ADDRESS_OUT_OF_RANGE, 0);
+
+        return SCSI_FAIL;
+    }
+
+    return SCSI_OK;
+}