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@@ -30,6 +30,7 @@ void rt_hw_cpu_icache_invalidate(void *addr, int size)
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rt_uint32_t start_addr = (rt_uint32_t)addr;
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rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
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+ asm volatile ("dmb":::"memory");
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start_addr &= ~(line_size-1);
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end_addr &= ~(line_size-1);
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while (start_addr < end_addr)
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@@ -37,6 +38,7 @@ void rt_hw_cpu_icache_invalidate(void *addr, int size)
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asm volatile ("mcr p15, 0, %0, c7, c5, 1" :: "r"(start_addr)); /* icimvau */
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start_addr += line_size;
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}
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+ asm volatile ("dsb\n\tisb":::"memory");
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}
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void rt_hw_cpu_dcache_invalidate(void *addr, int size)
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@@ -45,6 +47,7 @@ void rt_hw_cpu_dcache_invalidate(void *addr, int size)
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rt_uint32_t start_addr = (rt_uint32_t)addr;
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rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
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+ asm volatile ("dmb":::"memory");
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start_addr &= ~(line_size-1);
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end_addr &= ~(line_size-1);
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while (start_addr < end_addr)
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@@ -52,6 +55,7 @@ void rt_hw_cpu_dcache_invalidate(void *addr, int size)
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asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr)); /* dcimvac */
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start_addr += line_size;
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}
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+ asm volatile ("dsb":::"memory");
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}
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void rt_hw_cpu_dcache_clean(void *addr, int size)
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@@ -60,6 +64,7 @@ void rt_hw_cpu_dcache_clean(void *addr, int size)
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rt_uint32_t start_addr = (rt_uint32_t)addr;
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rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
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+ asm volatile ("dmb":::"memory");
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start_addr &= ~(line_size-1);
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end_addr &= ~(line_size-1);
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while (start_addr < end_addr)
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@@ -67,6 +72,7 @@ void rt_hw_cpu_dcache_clean(void *addr, int size)
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asm volatile ("mcr p15, 0, %0, c7, c10, 1" :: "r"(start_addr)); /* dccmvac */
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start_addr += line_size;
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}
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+ asm volatile ("dsb":::"memory");
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}
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void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
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ZYH