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@@ -52,52 +52,10 @@
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#endif /* ENABLE_FPU */
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.macro SAVE_ALL
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+
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#ifdef ENABLE_FPU
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- /* save float registers */
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+ /* reserve float registers */
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addi sp, sp, -CTX_FPU_REG_NR * REGBYTES
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-
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- li t0, SSTATUS_FS
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- csrs sstatus, t0
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- fsd f0, FPU_CTX_F0_OFF(sp)
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- fsd f1, FPU_CTX_F1_OFF(sp)
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- fsd f2, FPU_CTX_F2_OFF(sp)
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- fsd f3, FPU_CTX_F3_OFF(sp)
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- fsd f4, FPU_CTX_F4_OFF(sp)
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- fsd f5, FPU_CTX_F5_OFF(sp)
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- fsd f6, FPU_CTX_F6_OFF(sp)
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- fsd f7, FPU_CTX_F7_OFF(sp)
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- fsd f8, FPU_CTX_F8_OFF(sp)
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- fsd f9, FPU_CTX_F9_OFF(sp)
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- fsd f10, FPU_CTX_F10_OFF(sp)
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- fsd f11, FPU_CTX_F11_OFF(sp)
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- fsd f12, FPU_CTX_F12_OFF(sp)
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- fsd f13, FPU_CTX_F13_OFF(sp)
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- fsd f14, FPU_CTX_F14_OFF(sp)
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- fsd f15, FPU_CTX_F15_OFF(sp)
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- fsd f16, FPU_CTX_F16_OFF(sp)
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- fsd f17, FPU_CTX_F17_OFF(sp)
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- fsd f18, FPU_CTX_F18_OFF(sp)
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- fsd f19, FPU_CTX_F19_OFF(sp)
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- fsd f20, FPU_CTX_F20_OFF(sp)
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- fsd f21, FPU_CTX_F21_OFF(sp)
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- fsd f22, FPU_CTX_F22_OFF(sp)
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- fsd f23, FPU_CTX_F23_OFF(sp)
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- fsd f24, FPU_CTX_F24_OFF(sp)
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- fsd f25, FPU_CTX_F25_OFF(sp)
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- fsd f26, FPU_CTX_F26_OFF(sp)
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- fsd f27, FPU_CTX_F27_OFF(sp)
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- fsd f28, FPU_CTX_F28_OFF(sp)
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- fsd f29, FPU_CTX_F29_OFF(sp)
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- fsd f30, FPU_CTX_F30_OFF(sp)
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- fsd f31, FPU_CTX_F31_OFF(sp)
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-
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- /* clr FS domain */
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- csrc sstatus, t0
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-
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- /* clean status would clr sr_sd; */
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- li t0, SSTATUS_FS_CLEAN
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- csrs sstatus, t0
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-
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#endif /* ENABLE_FPU */
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/* save general registers */
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@@ -141,49 +99,59 @@
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STORE x31, 31 * REGBYTES(sp)
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csrr t0, sscratch
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STORE t0, 32 * REGBYTES(sp)
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-.endm
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-.macro RESTORE_ALL
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- /* restore general register */
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+#ifdef ENABLE_FPU
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+ /* backup sp and adjust sp to save float registers */
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+ mv t1, sp
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+ addi t1, t1, CTX_GENERAL_REG_NR * REGBYTES
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- /* resw ra to sepc */
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- LOAD x1, 0 * REGBYTES(sp)
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- csrw sepc, x1
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+ li t0, SSTATUS_FS
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+ csrs sstatus, t0
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+ fsd f0, FPU_CTX_F0_OFF(t1)
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+ fsd f1, FPU_CTX_F1_OFF(t1)
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+ fsd f2, FPU_CTX_F2_OFF(t1)
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+ fsd f3, FPU_CTX_F3_OFF(t1)
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+ fsd f4, FPU_CTX_F4_OFF(t1)
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+ fsd f5, FPU_CTX_F5_OFF(t1)
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+ fsd f6, FPU_CTX_F6_OFF(t1)
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+ fsd f7, FPU_CTX_F7_OFF(t1)
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+ fsd f8, FPU_CTX_F8_OFF(t1)
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+ fsd f9, FPU_CTX_F9_OFF(t1)
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+ fsd f10, FPU_CTX_F10_OFF(t1)
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+ fsd f11, FPU_CTX_F11_OFF(t1)
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+ fsd f12, FPU_CTX_F12_OFF(t1)
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+ fsd f13, FPU_CTX_F13_OFF(t1)
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+ fsd f14, FPU_CTX_F14_OFF(t1)
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+ fsd f15, FPU_CTX_F15_OFF(t1)
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+ fsd f16, FPU_CTX_F16_OFF(t1)
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+ fsd f17, FPU_CTX_F17_OFF(t1)
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+ fsd f18, FPU_CTX_F18_OFF(t1)
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+ fsd f19, FPU_CTX_F19_OFF(t1)
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+ fsd f20, FPU_CTX_F20_OFF(t1)
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+ fsd f21, FPU_CTX_F21_OFF(t1)
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+ fsd f22, FPU_CTX_F22_OFF(t1)
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+ fsd f23, FPU_CTX_F23_OFF(t1)
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+ fsd f24, FPU_CTX_F24_OFF(t1)
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+ fsd f25, FPU_CTX_F25_OFF(t1)
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+ fsd f26, FPU_CTX_F26_OFF(t1)
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+ fsd f27, FPU_CTX_F27_OFF(t1)
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+ fsd f28, FPU_CTX_F28_OFF(t1)
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+ fsd f29, FPU_CTX_F29_OFF(t1)
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+ fsd f30, FPU_CTX_F30_OFF(t1)
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+ fsd f31, FPU_CTX_F31_OFF(t1)
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- LOAD x1, 2 * REGBYTES(sp)
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- csrw sstatus, x1
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+ /* clr FS domain */
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+ csrc sstatus, t0
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- LOAD x1, 1 * REGBYTES(sp)
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+ /* clean status would clr sr_sd; */
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+ li t0, SSTATUS_FS_CLEAN
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+ csrs sstatus, t0
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- LOAD x3, 3 * REGBYTES(sp)
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- LOAD x4, 4 * REGBYTES(sp)
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- LOAD x5, 5 * REGBYTES(sp)
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- LOAD x6, 6 * REGBYTES(sp)
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- LOAD x7, 7 * REGBYTES(sp)
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- LOAD x8, 8 * REGBYTES(sp)
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- LOAD x9, 9 * REGBYTES(sp)
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- LOAD x10, 10 * REGBYTES(sp)
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- LOAD x11, 11 * REGBYTES(sp)
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- LOAD x12, 12 * REGBYTES(sp)
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- LOAD x13, 13 * REGBYTES(sp)
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- LOAD x14, 14 * REGBYTES(sp)
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- LOAD x15, 15 * REGBYTES(sp)
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- LOAD x16, 16 * REGBYTES(sp)
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- LOAD x17, 17 * REGBYTES(sp)
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- LOAD x18, 18 * REGBYTES(sp)
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- LOAD x19, 19 * REGBYTES(sp)
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- LOAD x20, 20 * REGBYTES(sp)
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- LOAD x21, 21 * REGBYTES(sp)
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- LOAD x22, 22 * REGBYTES(sp)
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- LOAD x23, 23 * REGBYTES(sp)
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- LOAD x24, 24 * REGBYTES(sp)
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- LOAD x25, 25 * REGBYTES(sp)
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- LOAD x26, 26 * REGBYTES(sp)
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- LOAD x27, 27 * REGBYTES(sp)
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- LOAD x28, 28 * REGBYTES(sp)
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- LOAD x29, 29 * REGBYTES(sp)
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- LOAD x30, 30 * REGBYTES(sp)
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- LOAD x31, 31 * REGBYTES(sp)
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+#endif /* ENABLE_FPU */
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+
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+.endm
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+
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+.macro RESTORE_ALL
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#ifdef ENABLE_FPU
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/* restore float register */
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@@ -233,6 +201,48 @@
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csrs sstatus, t0
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#endif /* ENABLE_FPU */
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+
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+ /* restore general register */
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+
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+ /* resw ra to sepc */
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+ LOAD x1, 0 * REGBYTES(sp)
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+ csrw sepc, x1
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+
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+ LOAD x1, 2 * REGBYTES(sp)
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+ csrw sstatus, x1
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+
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+ LOAD x1, 1 * REGBYTES(sp)
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+
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+ LOAD x3, 3 * REGBYTES(sp)
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+ LOAD x4, 4 * REGBYTES(sp)
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+ LOAD x5, 5 * REGBYTES(sp)
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+ LOAD x6, 6 * REGBYTES(sp)
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+ LOAD x7, 7 * REGBYTES(sp)
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+ LOAD x8, 8 * REGBYTES(sp)
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+ LOAD x9, 9 * REGBYTES(sp)
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+ LOAD x10, 10 * REGBYTES(sp)
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+ LOAD x11, 11 * REGBYTES(sp)
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+ LOAD x12, 12 * REGBYTES(sp)
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+ LOAD x13, 13 * REGBYTES(sp)
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+ LOAD x14, 14 * REGBYTES(sp)
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+ LOAD x15, 15 * REGBYTES(sp)
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+ LOAD x16, 16 * REGBYTES(sp)
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+ LOAD x17, 17 * REGBYTES(sp)
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+ LOAD x18, 18 * REGBYTES(sp)
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+ LOAD x19, 19 * REGBYTES(sp)
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+ LOAD x20, 20 * REGBYTES(sp)
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+ LOAD x21, 21 * REGBYTES(sp)
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+ LOAD x22, 22 * REGBYTES(sp)
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+ LOAD x23, 23 * REGBYTES(sp)
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+ LOAD x24, 24 * REGBYTES(sp)
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+ LOAD x25, 25 * REGBYTES(sp)
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+ LOAD x26, 26 * REGBYTES(sp)
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+ LOAD x27, 27 * REGBYTES(sp)
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+ LOAD x28, 28 * REGBYTES(sp)
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+ LOAD x29, 29 * REGBYTES(sp)
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+ LOAD x30, 30 * REGBYTES(sp)
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+ LOAD x31, 31 * REGBYTES(sp)
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+
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/* restore user sp */
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LOAD sp, 32 * REGBYTES(sp)
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.endm
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jasonhu