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@@ -33,7 +33,7 @@
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.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
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.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
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-.equ UND_Stack_Size, 0x00000000
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+.equ UND_Stack_Size, 0x00000200
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.equ SVC_Stack_Size, 0x00000100
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.equ ABT_Stack_Size, 0x00000000
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.equ FIQ_Stack_Size, 0x00000000
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@@ -135,7 +135,15 @@ vector_undef:
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sub sp, sp, #72
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stmia sp, {r0 - r12} @/* Calling r0-r12 */
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add r8, sp, #60
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- stmdb r8, {sp, lr} @/* Calling SP, LR */
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+
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+ mrs r1, cpsr
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+ mrs r2, spsr
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+ orr r2,r2, #I_Bit|F_Bit
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+ msr cpsr_c, r2
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+ mov r0, r0
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+ stmdb r8, {sp, lr} @/* Calling SP, LR */
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+ msr cpsr_c, r1 @/* return to Undefined Instruction mode */
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+
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str lr, [r8, #0] @/* Save calling PC */
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mrs r6, spsr
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str r6, [r8, #4] @/* Save CPSR */
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@@ -144,6 +152,12 @@ vector_undef:
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bl rt_hw_trap_udef
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+ ldmia sp, {r0 - r12} @/* Calling r0 - r2 */
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+ mov r0, r0
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+ ldr lr, [sp, #60] @/* Get PC */
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+ add sp, sp, #72
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+ movs pc, lr @/* return & move spsr_svc into cpsr */
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+
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.align 5
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.globl vector_swi
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vector_swi:
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@@ -169,6 +183,12 @@ vector_dabt:
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bl rt_hw_trap_dabt
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+ ldmia sp, {r0 - r12} @/* Calling r0 - r2 */
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+ mov r0, r0
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+ ldr lr, [sp, #60] @/* Get PC */
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+ add sp, sp, #72
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+ movs pc, lr @/* return & move spsr_svc into cpsr */
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+
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.align 5
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.globl vector_resv
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vector_resv:
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