# SPDX-License-Identifier: GPL-2.0-or-later

# This is a stm32h735g-dk with a single STM32H735IGK6 chip.
# https://www.st.com/en/evaluation-tools/stm32h735g-dk.html
#

# This is for using the onboard STLINK
source [find interface/stlink.cfg]

transport select hla_swd

set CHIPNAME stm32h730vbt6

set OCTOSPI1 1

source [find target/stm32h7x.cfg]

# OCTOSPI initialization
# octo: 4-line mode
proc octospi_init { octo } {
	global a b
	mmw 0x58024540 0x000006FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
	mmw 0x58024534 0x00284000 0				;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks)
	sleep 1									;# Wait for clock startup

	mww 0x5200B404 0x03010111				;# OCTOSPIM_P1CR: enable port 1
	mww 0x5200B408 0x00000000				;# OCTOSPIM_P2CR: disable Port 2


# PA07:AF10:V, PA06:AF06:V, PB02:AF09:V, PB01:AF04:V, PB00:AF04:V, PE11:AF11:V
        # Port A: PA07:AF10:V, PA06:AF06:V
        mmw 0x58020000 0x0000A000 0x00005000    ;# MODER
        mmw 0x58020008 0x0000F000 0x00000000    ;# OSPEEDR
        mmw 0x5802000C 0x00000000 0x0000F000    ;# PUPDR
        mmw 0x58020020 0xA6000000 0x59000000    ;# AFRL
        # Port B: PB02:AF09:V, PB01:AF04:V, PB00:AF04:V
        mmw 0x58020400 0x0000002A 0x00000015    ;# MODER
        mmw 0x58020408 0x0000003F 0x00000000    ;# OSPEEDR
        mmw 0x5802040C 0x00000000 0x0000003F    ;# PUPDR
        mmw 0x58020420 0x00000944 0x000006BB    ;# AFRL
        # Port E: PE11:AF11:V
        mmw 0x58021000 0x00800000 0x00400000    ;# MODER
        mmw 0x58021008 0x00C00000 0x00000000    ;# OSPEEDR
        mmw 0x5802100C 0x00000000 0x00C00000    ;# PUPDR
        mmw 0x58021024 0x0000B000 0x00004000    ;# AFRH


	# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
	mww 0x52005130 0x00001000
	mww 0x52005000 0x3040000B
	mww 0x52005008 0x01160100
	mww 0x5200500c 0x00000005

	mww 0x52005108 0x00000000
	mww 0x52005100 0x01012101
	mww 0x52005110 0x00000013

	sleep 1

	flash probe $a							;# load configuration from CR, TCR, CCR, IR register values
}

$_CHIPNAME.cpu0 configure -event reset-init {
	global OCTOSPI1
	global OCTOSPI2

	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for 192 MHZ HCLK

	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
	mmw 0x58024410 0x10000000 0xEE000007	;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
	mww 0x58024418 0x00000040				;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
	mww 0x5802441C 0x00000440				;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
	mww 0x58024420 0x00000040				;# RCC_D3CFGR: D3PPRE=2
	mww 0x58024428 0x00000040				;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
	mmw 0x5802442C 0x0001000C 0x00000002	;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
	mww 0x58024430 0x01070217				;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
	sleep 1
	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
	sleep 1

	adapter speed 24000

    octospi_init 1
}