/* * Copyright (c) 2012, Freescale Semiconductor, Inc. * All rights reserved. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ // File: gpmi_iomux_config.c /* ------------------------------------------------------------------------------ * * This code was generated by a tool. * Runtime Version:3.4.0.0 * * Changes to this file may cause incorrect behavior and will be lost if * the code is regenerated. * * ------------------------------------------------------------------------------ */ #include "iomux_config.h" #include "registers/regsiomuxc.h" // Function to configure IOMUXC for gpmi module. void gpmi_iomux_config(void) { // Config gpmi.NAND_ALE to pad NAND_ALE(A16) // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_WR(0x00000000); // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_NAND_ALE(0x020E026C) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: gpmi signal: NAND_ALE // ALT1 (1) - Select instance: usdhc4 signal: SD4_RESET // ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO08 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_WR( BF_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE_V(ALT0)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_NAND_ALE(0x020E0654) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE_V(SLOW)); // Config gpmi.NAND_CE0_B to pad NAND_CS0_B(F15) // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_WR(0x00000000); // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B(0x020E0274) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: gpmi signal: NAND_CE0_B // ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO11 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_WR( BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE_V(ALT0)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B(0x020E065C) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE_V(SLOW)); // Config gpmi.NAND_CE1_B to pad NAND_CS1_B(C16) // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_WR(0x00000000); // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B(0x020E0278) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: gpmi signal: NAND_CE1_B // ALT1 (1) - Select instance: usdhc4 signal: SD4_VSELECT // ALT2 (2) - Select instance: usdhc3 signal: SD3_VSELECT // ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO14 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_WR( BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE_V(ALT0)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B(0x020E0660) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE_V(SLOW)); // Config gpmi.NAND_CLE to pad NAND_CLE(C15) // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_WR(0x00000000); // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_NAND_CLE(0x020E0270) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: gpmi signal: NAND_CLE // ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO07 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_WR( BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE_V(ALT0)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_NAND_CLE(0x020E0658) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE_V(SLOW)); // Config gpmi.NAND_DATA00 to pad NAND_DATA00(A18) // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_WR(0x00000000); // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00(0x020E0284) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: gpmi signal: NAND_DATA00 // ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA4 // ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO00 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_WR( BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE_V(ALT0)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00(0x020E066C) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE_V(SLOW)); // Config gpmi.NAND_DATA01 to pad NAND_DATA01(C17) // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_WR(0x00000000); // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01(0x020E0288) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: gpmi signal: NAND_DATA01 // ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA5 // ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO01 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_WR( BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE_V(ALT0)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01(0x020E0670) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE_V(SLOW)); // Config gpmi.NAND_DATA02 to pad NAND_DATA02(F16) // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_WR(0x00000000); // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02(0x020E028C) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: gpmi signal: NAND_DATA02 // ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA6 // ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO02 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_WR( BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE_V(ALT0)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02(0x020E0674) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE_V(SLOW)); // Config gpmi.NAND_DATA03 to pad NAND_DATA03(D17) // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_WR(0x00000000); // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03(0x020E0290) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: gpmi signal: NAND_DATA03 // ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA7 // ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO03 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_WR( BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE_V(ALT0)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03(0x020E0678) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE_V(SLOW)); // Config gpmi.NAND_DATA04 to pad NAND_DATA04(A19) // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_WR(0x00000000); // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04(0x020E0294) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: gpmi signal: NAND_DATA04 // ALT1 (1) - Select instance: usdhc2 signal: SD2_DATA4 // ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO04 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_WR( BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE_V(ALT0)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04(0x020E067C) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE_V(SLOW)); // Config gpmi.NAND_DATA05 to pad NAND_DATA05(B18) // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_WR(0x00000000); // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05(0x020E0298) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: gpmi signal: NAND_DATA05 // ALT1 (1) - Select instance: usdhc2 signal: SD2_DATA5 // ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO05 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_WR( BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE_V(ALT0)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05(0x020E0680) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE_V(SLOW)); // Config gpmi.NAND_DATA06 to pad NAND_DATA06(E17) // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_WR(0x00000000); // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06(0x020E029C) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: gpmi signal: NAND_DATA06 // ALT1 (1) - Select instance: usdhc2 signal: SD2_DATA6 // ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO06 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_WR( BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE_V(ALT0)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06(0x020E0684) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE_V(SLOW)); // Config gpmi.NAND_DATA07 to pad NAND_DATA07(C18) // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_WR(0x00000000); // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07(0x020E02A0) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: gpmi signal: NAND_DATA07 // ALT1 (1) - Select instance: usdhc2 signal: SD2_DATA7 // ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO07 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_WR( BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE_V(ALT0)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07(0x020E0688) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE_V(SLOW)); // Config gpmi.NAND_DQS to pad SD4_DATA0(D18) // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_WR(0x00000002); // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0(0x020E0340) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT1 (1) - Select instance: usdhc4 signal: SD4_DATA0 // ALT2 (2) - Select instance: gpmi signal: NAND_DQS // ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO08 HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_WR( BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE_V(ALT2)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0(0x020E0728) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR( BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE_V(SLOW)); // Config gpmi.NAND_READY to pad NAND_READY(B16) // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_WR(0x00000000); // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_NAND_READY(0x020E02A4) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: gpmi signal: NAND_READY // ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO10 HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_WR( BF_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE_V(ALT0)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_NAND_READY(0x020E068C) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE_V(SLOW)); // Config gpmi.NAND_RE_B to pad SD4_CMD(B17) // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_WR(0x00000001); // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_SD4_CMD(0x020E033C) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: usdhc4 signal: SD4_CMD // ALT1 (1) - Select instance: gpmi signal: NAND_RE_B // ALT2 (2) - Select instance: uart3 signal: UART3_TX_DATA // ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO09 HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_WR( BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE_V(ALT1)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_SD4_CMD(0x020E0724) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR( BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE_V(SLOW)); // Config gpmi.NAND_WE_B to pad SD4_CLK(E16) // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_WR(0x00000001); // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_SD4_CLK(0x020E0338) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: usdhc4 signal: SD4_CLK // ALT1 (1) - Select instance: gpmi signal: NAND_WE_B // ALT2 (2) - Select instance: uart3 signal: UART3_RX_DATA // ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO10 HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_WR( BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE_V(ALT1)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_SD4_CLK(0x020E0720) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR( BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE_V(SLOW)); // Config gpmi.NAND_WP_B to pad NAND_WP_B(E15) // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_WR(0x00000000); // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR(0x0001B0B0); // Mux Register: // IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B(0x020E02A8) // SION [4] - Software Input On Field Reset: DISABLED // Force the selected mux mode Input path no matter of MUX_MODE functionality. // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular). // ENABLED (1) - Force input path of pad. // MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5 // Select iomux modes to be used for pad. // ALT0 (0) - Select instance: gpmi signal: NAND_WP_B // ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO09 // ALT9 (9) - Select instance: i2c4 signal: I2C4_SCL HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_WR( BF_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION_V(DISABLED) | BF_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE_V(ALT0)); // Pad Control Register: // IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B(0x020E0690) // HYS [16] - Hysteresis Enable Field Reset: ENABLED // DISABLED (0) - CMOS input // ENABLED (1) - Schmitt trigger input // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU // 100K_OHM_PD (0) - 100K Ohm Pull Down // 47K_OHM_PU (1) - 47K Ohm Pull Up // 100K_OHM_PU (2) - 100K Ohm Pull Up // 22K_OHM_PU (3) - 22K Ohm Pull Up // PUE [13] - Pull / Keep Select Field Reset: PULL // KEEP (0) - Keeper Enabled // PULL (1) - Pull Enabled // PKE [12] - Pull / Keep Enable Field Reset: ENABLED // DISABLED (0) - Pull/Keeper Disabled // ENABLED (1) - Pull/Keeper Enabled // ODE [11] - Open Drain Enable Field Reset: DISABLED // Enables open drain of the pin. // DISABLED (0) - Output is CMOS. // ENABLED (1) - Output is Open Drain. // SPEED [7:6] - Speed Field Reset: 100MHZ // RESERVED0 (0) - Reserved // 50MHZ (1) - Low (50 MHz) // 100MHZ (2) - Medium (100 MHz) // 200MHZ (3) - Maximum (200 MHz) // DSE [5:3] - Drive Strength Field Reset: 40_OHM // HIZ (0) - HI-Z // 240_OHM (1) - 240 Ohm // 120_OHM (2) - 120 Ohm // 80_OHM (3) - 80 Ohm // 60_OHM (4) - 60 Ohm // 48_OHM (5) - 48 Ohm // 40_OHM (6) - 40 Ohm // 34_OHM (7) - 34 Ohm // SRE [0] - Slew Rate Field Reset: SLOW // Slew rate control. // SLOW (0) - Slow Slew Rate // FAST (1) - Fast Slew Rate HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE_V(SLOW)); }