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 * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
 * All rights reserved.
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 * are permitted provided that the following conditions are met:
 *
 * o Redistributions of source code must retain the above copyright notice, this list
 *   of conditions and the following disclaimer.
 *
 * o Redistributions in binary form must reproduce the above copyright notice, this
 *   list of conditions and the following disclaimer in the documentation and/or
 *   other materials provided with the distribution.
 *
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 *   contributors may be used to endorse or promote products derived from this
 *   software without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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/*!
 * @file dcp.h
 * @brief Interface for DCP module
 */

#ifndef _DCP_H_
#define _DCP_H_

#include "sdk.h"
#include "registers/regsdcp.h"

#define HW_DCP_CHnCMDPTR_WR(ch, v)	(((ch) == 0) ? HW_DCP_CH0CMDPTR_WR((v)) : \
					((ch) == 1) ? HW_DCP_CH1CMDPTR_WR((v)): \
					((ch) == 2) ? HW_DCP_CH2CMDPTR_WR((v)): \
					HW_DCP_CH3CMDPTR_WR((v)))

#define HW_DCP_CHnSEMA_WR(ch, v)	(((ch) == 0) ? HW_DCP_CH0SEMA_WR((v)) : \
                                        ((ch) == 1) ? HW_DCP_CH1SEMA_WR((v)): \
                                        ((ch) == 2) ? HW_DCP_CH2SEMA_WR((v)): \
                                        HW_DCP_CH3SEMA_WR((v)))


typedef enum {
    DCP_CHANNEL_1 = 0,
    DCP_CHANNEL_2,
    DCP_CHANNEL_3,
    DCP_CHANNEL_4,
    DCP_CHANNEL_MAX,
} dcp_channel_e;

//! Data struture for DCP's work packet
typedef struct {
    uint32_t* next_pkt;
    hw_dcp_packet1_t ctrl0;
    hw_dcp_packet2_t ctrl1;
    uint8_t *src_buf;
    uint8_t *dst_buf;
    uint32_t buf_size;
    uint8_t *payload;
    uint32_t stat;
} dcp_work_pkt_t, *dcp_work_pkt_p;

int dcp_init(void);
int dcp_deinit(void);
int dcp_config_channel(uint32_t ch, dcp_work_pkt_p pkt_list);
int dcp_start_channel(uint32_t ch, uint32_t pkt_num);
int dcp_wait_channel_cmpl(uint32_t ch);
int dcp_memcpy(void* dst, void* src, uint32_t size);

#endif