/* * @brief DMA master ROM API declarations and functions * * @note * Copyright(C) NXP Semiconductors, 2014 * All rights reserved. * * @par * Software that is described herein is for illustrative purposes only * which provides customers with programming information regarding the * LPC products. This software is supplied "AS IS" without any warranties of * any kind, and NXP Semiconductors and its licensor disclaim any and * all warranties, express or implied, including all implied warranties of * merchantability, fitness for a particular purpose and non-infringement of * intellectual property rights. NXP Semiconductors assumes no responsibility * or liability for the use of the software, conveys no license or rights under any * patent, copyright, mask work right, or any other intellectual property rights in * or to any products. NXP Semiconductors reserves the right to make changes * in the software without notification. NXP Semiconductors also makes no * representation or warranty that such application will be suitable for the * specified use without further testing or modification. * * @par * Permission to use, copy, modify, and distribute this software and its * documentation is hereby granted, under NXP Semiconductors' and its * licensor's relevant copyrights in the software, without fee, provided that it * is used in conjunction with NXP Semiconductors microcontrollers. This * copyright, permission, and disclaimer notice must appear in all copies of * this code. */ #ifndef __HW_DMA_REGS_H_ #define __HW_DMA_REGS_H_ /** * @brief DMA Controller shared registers structure */ typedef struct { /*!< DMA shared registers structure */ volatile uint32_t ENABLESET; /*!< DMA Channel Enable read and Set for all DMA channels */ volatile uint32_t RESERVED0; volatile uint32_t ENABLECLR; /*!< DMA Channel Enable Clear for all DMA channels */ volatile uint32_t RESERVED1; volatile uint32_t ACTIVE; /*!< DMA Channel Active status for all DMA channels */ volatile uint32_t RESERVED2; volatile uint32_t BUSY; /*!< DMA Channel Busy status for all DMA channels */ volatile uint32_t RESERVED3; volatile uint32_t ERRINT; /*!< DMA Error Interrupt status for all DMA channels */ volatile uint32_t RESERVED4; volatile uint32_t INTENSET; /*!< DMA Interrupt Enable read and Set for all DMA channels */ volatile uint32_t RESERVED5; volatile uint32_t INTENCLR; /*!< DMA Interrupt Enable Clear for all DMA channels */ volatile uint32_t RESERVED6; volatile uint32_t INTA; /*!< DMA Interrupt A status for all DMA channels */ volatile uint32_t RESERVED7; volatile uint32_t INTB; /*!< DMA Interrupt B status for all DMA channels */ volatile uint32_t RESERVED8; volatile uint32_t SETVALID; /*!< DMA Set ValidPending control bits for all DMA channels */ volatile uint32_t RESERVED9; volatile uint32_t SETTRIG; /*!< DMA Set Trigger control bits for all DMA channels */ volatile uint32_t RESERVED10; volatile uint32_t ABORT; /*!< DMA Channel Abort control for all DMA channels */ } LPC_DMA_COMMON_T; /** * @brief DMA Controller shared registers structure */ typedef struct { /*!< DMA channel register structure */ volatile uint32_t CFG; /*!< DMA Configuration register */ volatile uint32_t CTLSTAT; /*!< DMA Control and status register */ volatile uint32_t XFERCFG; /*!< DMA Transfer configuration register */ volatile uint32_t RESERVED; } LPC_DMA_CHANNEL_T; /* On LPC540XX, Max DMA channel is 22 */ #define MAX_DMA_CHANNEL (22) /** * @brief DMA Controller register block structure */ typedef struct { /*!< DMA Structure */ volatile uint32_t CTRL; /*!< DMA control register */ volatile uint32_t INTSTAT; /*!< DMA Interrupt status register */ volatile uint32_t SRAMBASE; /*!< DMA SRAM address of the channel configuration table */ volatile uint32_t RESERVED2[5]; LPC_DMA_COMMON_T DMACOMMON[1]; /*!< DMA shared channel (common) registers */ volatile uint32_t RESERVED0[225]; LPC_DMA_CHANNEL_T DMACH[MAX_DMA_CHANNEL]; /*!< DMA channel registers */ } LPC_DMA_T; /* DMA interrupt status bits (common) */ #define DMA_INTSTAT_ACTIVEINT 0x2 /*!< Summarizes whether any enabled interrupts are pending */ #define DMA_INTSTAT_ACTIVEERRINT 0x4 /*!< Summarizes whether any error interrupts are pending */ /* Support macro for DMA_CHDESC_T */ #define DMA_ADDR(addr) ((uint32_t) (addr)) /* Support definitions for setting the configuration of a DMA channel. You will need to get more information on these options from the User manual. */ #define DMA_CFG_PERIPHREQEN (1 << 0) /*!< Enables Peripheral DMA requests */ #define DMA_CFG_HWTRIGEN (1 << 1) /*!< Use hardware triggering via imput mux */ #define DMA_CFG_TRIGPOL_LOW (0 << 4) /*!< Hardware trigger is active low or falling edge */ #define DMA_CFG_TRIGPOL_HIGH (1 << 4) /*!< Hardware trigger is active high or rising edge */ #define DMA_CFG_TRIGTYPE_EDGE (0 << 5) /*!< Hardware trigger is edge triggered */ #define DMA_CFG_TRIGTYPE_LEVEL (1 << 5) /*!< Hardware trigger is level triggered */ #define DMA_CFG_TRIGBURST_SNGL (0 << 6) /*!< Single transfer. Hardware trigger causes a single transfer */ #define DMA_CFG_TRIGBURST_BURST (1 << 6) /*!< Burst transfer (see UM) */ #define DMA_CFG_BURSTPOWER_1 (0 << 8) /*!< Set DMA burst size to 1 transfer */ #define DMA_CFG_BURSTPOWER_2 (1 << 8) /*!< Set DMA burst size to 2 transfers */ #define DMA_CFG_BURSTPOWER_4 (2 << 8) /*!< Set DMA burst size to 4 transfers */ #define DMA_CFG_BURSTPOWER_8 (3 << 8) /*!< Set DMA burst size to 8 transfers */ #define DMA_CFG_BURSTPOWER_16 (4 << 8) /*!< Set DMA burst size to 16 transfers */ #define DMA_CFG_BURSTPOWER_32 (5 << 8) /*!< Set DMA burst size to 32 transfers */ #define DMA_CFG_BURSTPOWER_64 (6 << 8) /*!< Set DMA burst size to 64 transfers */ #define DMA_CFG_BURSTPOWER_128 (7 << 8) /*!< Set DMA burst size to 128 transfers */ #define DMA_CFG_BURSTPOWER_256 (8 << 8) /*!< Set DMA burst size to 256 transfers */ #define DMA_CFG_BURSTPOWER_512 (9 << 8) /*!< Set DMA burst size to 512 transfers */ #define DMA_CFG_BURSTPOWER_1024 (10 << 8) /*!< Set DMA burst size to 1024 transfers */ #define DMA_CFG_BURSTPOWER(n) ((n) << 8) /*!< Set DMA burst size to 2^n transfers, max n=10 */ #define DMA_CFG_SRCBURSTWRAP (1 << 14) /*!< Source burst wrapping is enabled for this DMA channel */ #define DMA_CFG_DSTBURSTWRAP (1 << 15) /*!< Destination burst wrapping is enabled for this DMA channel */ #define DMA_CFG_CHPRIORITY(p) ((p) << 16) /*!< Sets DMA channel priority, min 0 (highest), max 3 (lowest) */ /* DMA channel control and status register definitions */ #define DMA_CTLSTAT_VALIDPENDING (1 << 0) /*!< Valid pending flag for this channel */ #define DMA_CTLSTAT_TRIG (1 << 2) /*!< Trigger flag. Indicates that the trigger for this channel is currently set */ /* DMA channel transfer configuration registers definitions */ #define DMA_XFERCFG_CFGVALID (1 << 0) /*!< Configuration Valid flag */ #define DMA_XFERCFG_RELOAD (1 << 1) /*!< Indicates whether the channels control structure will be reloaded when the current descriptor is exhausted */ #define DMA_XFERCFG_SWTRIG (1 << 2) /*!< Software Trigger */ #define DMA_XFERCFG_CLRTRIG (1 << 3) /*!< Clear Trigger */ #define DMA_XFERCFG_SETINTA (1 << 4) /*!< Set Interrupt flag A for this channel to fire when descriptor is complete */ #define DMA_XFERCFG_SETINTB (1 << 5) /*!< Set Interrupt flag B for this channel to fire when descriptor is complete */ #define DMA_XFERCFG_WIDTH_8 (0 << 8) /*!< 8-bit transfers are performed */ #define DMA_XFERCFG_WIDTH_16 (1 << 8) /*!< 16-bit transfers are performed */ #define DMA_XFERCFG_WIDTH_32 (2 << 8) /*!< 32-bit transfers are performed */ #define DMA_XFERCFG_SRCINC_0 (0 << 12) /*!< DMA source address is not incremented after a transfer */ #define DMA_XFERCFG_SRCINC_1 (1 << 12) /*!< DMA source address is incremented by 1 (width) after a transfer */ #define DMA_XFERCFG_SRCINC_2 (2 << 12) /*!< DMA source address is incremented by 2 (width) after a transfer */ #define DMA_XFERCFG_SRCINC_4 (3 << 12) /*!< DMA source address is incremented by 4 (width) after a transfer */ #define DMA_XFERCFG_DSTINC_0 (0 << 14) /*!< DMA destination address is not incremented after a transfer */ #define DMA_XFERCFG_DSTINC_1 (1 << 14) /*!< DMA destination address is incremented by 1 (width) after a transfer */ #define DMA_XFERCFG_DSTINC_2 (2 << 14) /*!< DMA destination address is incremented by 2 (width) after a transfer */ #define DMA_XFERCFG_DSTINC_4 (3 << 14) /*!< DMA destination address is incremented by 4 (width) after a transfer */ #define DMA_XFERCFG_XFERCOUNT(n) ((n - 1) << 16) /*!< DMA transfer count in 'transfers', between (0)1 and (1023)1024 */ #endif /* __HW_DMA_REGS_H_ */