/*
 * Copyright (C) 2011-2012, Freescale Semiconductor, Inc. All Rights Reserved
 * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
 * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
 * Freescale Semiconductor, Inc.
*/

#ifndef _CCM_PLL_REG_DEFINE_H_
#define _CCM_PLL_REG_DEFINE_H_

//#########################################
//# DPLLIP peripheral defines
//#########################################
#define DPLLIP_DP_CTL_OFFSET	0x000
#define DPLLIP_DP_CONFIG_OFFSET	0x004
#define DPLLIP_DP_OP_OFFSET	0x008
#define DPLLIP_DP_MFD_OFFSET	0x00C
#define DPLLIP_DP_MFN_OFFSET	0x010
#define DPLLIP_DP_MFNMINUS_OFFSET	0x014
#define DPLLIP_DP_MFNPLUS_OFFSET	0x018
#define DPLLIP_DP_HFS_OP_OFFSET	0x01C
#define DPLLIP_DP_HFS_MFD_OFFSET	0x020
#define DPLLIP_DP_HFS_MFN_OFFSET	0x024
#define DPLLIP_DP_MFN_TOGC_OFFSET	0x028
#define DPLLIP_DP_DESTAT_OFFSET	0x02C

#define DPLLIP1_DP_CONFIG          DPLLIP1_BASE_ADDR+DPLLIP_DP_CONFIG_OFFSET
#define DPLLIP1_DP_CTL             DPLLIP1_BASE_ADDR+DPLLIP_DP_CTL_OFFSET
#define DPLLIP1_DP_OP              DPLLIP1_BASE_ADDR+DPLLIP_DP_OP_OFFSET
#define DPLLIP1_DP_MFD             DPLLIP1_BASE_ADDR+DPLLIP_DP_MFD_OFFSET
#define DPLLIP1_DP_MFN             DPLLIP1_BASE_ADDR+DPLLIP_DP_MFN_OFFSET

#define DPLLIP2_DP_CONFIG          DPLLIP2_BASE_ADDR+DPLLIP_DP_CONFIG_OFFSET
#define DPLLIP2_DP_CTL             DPLLIP2_BASE_ADDR+DPLLIP_DP_CTL_OFFSET
#define DPLLIP2_DP_OP              DPLLIP2_BASE_ADDR+DPLLIP_DP_OP_OFFSET
#define DPLLIP2_DP_MFD             DPLLIP2_BASE_ADDR+DPLLIP_DP_MFD_OFFSET
#define DPLLIP2_DP_MFN             DPLLIP2_BASE_ADDR+DPLLIP_DP_MFN_OFFSET

#define DPLLIP3_DP_CONFIG          DPLLIP3_BASE_ADDR+DPLLIP_DP_CONFIG_OFFSET
#define DPLLIP3_DP_CTL             DPLLIP3_BASE_ADDR+DPLLIP_DP_CTL_OFFSET
#define DPLLIP3_DP_OP              DPLLIP3_BASE_ADDR+DPLLIP_DP_OP_OFFSET
#define DPLLIP3_DP_MFD             DPLLIP3_BASE_ADDR+DPLLIP_DP_MFD_OFFSET
#define DPLLIP3_DP_MFN             DPLLIP3_BASE_ADDR+DPLLIP_DP_MFN_OFFSET

//#########################################
//# CCM peripheral defines
//#########################################
#define CCM_CCR_OFFSET  0x00
#define CCM_CCDR_OFFSET 0x04
#define CCM_CSR_OFFSET  0x08
#define CCM_CCSR_OFFSET 0x0C
#define CCM_CACRR_OFFSET        0x10
#define CCM_CBCDR_OFFSET        0x14
#define CCM_CBCMR_OFFSET 0X18
#define CCM_CSCMR1_OFFSET 0x1c
#define CCM_CSCMR2_OFFSET 0x20
#define CCM_CSCDR1_OFFSET 0x24
#define CCM_CS1CDR_OFFSET 0x28
#define CCM_CS2CDR_OFFSET 0x2c
#define CCM_CDCDR_OFFSET 0x30
#define CCM_CHSCCDR_OFFSET 0x34
#define CCM_CSCDR2_OFFSET 0x38
#define CCM_CSCDR3_OFFSET 0x3c
#define CCM_CSCDR4_OFFSET 0x40
#define CCM_CWDR_OFFSET   0x44
#define CCM_CDHIPR_OFFSET 0x48
#define CCM_CDCR_OFFSET   0x4c
#define CCM_CTOR_OFFSET   0x50
#define CCM_CLPCR_OFFSET  0x54
#define CCM_CISR_OFFSET 0x58
#define CCM_CIMR_OFFSET 0x5c
#define CCM_CCOSR_OFFSET 0x60
#define CCM_CGPR_OFFSET 0x64
#define CCM_CCGR0_OFFSET 0x68
#define CCM_CCGR1_OFFSET 0x6c
#define CCM_CCGR2_OFFSET 0x70
#define CCM_CCGR3_OFFSET 0x74
#define CCM_CCGR4_OFFSET 0x78
#define CCM_CCGR5_OFFSET 0x7c
#define CCM_CCGR6_OFFSET 0x80
#define CCM_CCGR7_OFFSET 0x84
#define CCM_CMEOR_OFFSET 0x88

#define CCM_CCR     CCM_BASE_ADDR+CCM_CCR_OFFSET
#define CCM_CCDR    CCM_BASE_ADDR+CCM_CCDR_OFFSET
#define CCM_CSR     CCM_BASE_ADDR+CCM_CSR_OFFSET
#define CCM_CCSR    CCM_BASE_ADDR+CCM_CCSR_OFFSET
#define CCM_CACRR   CCM_BASE_ADDR+CCM_CACRR_OFFSET
#define CCM_CBCDR   CCM_BASE_ADDR+CCM_CBCDR_OFFSET
#define CCM_CBCMR   CCM_BASE_ADDR+CCM_CBCMR_OFFSET
#define CCM_CSCMR1  CCM_BASE_ADDR+CCM_CSCMR1_OFFSET
#define CCM_CSCMR2  CCM_BASE_ADDR+CCM_CSCMR2_OFFSET
#define CCM_CSCDR1  CCM_BASE_ADDR+CCM_CSCDR1_OFFSET
#define CCM_CS1CDR  CCM_BASE_ADDR+CCM_CS1CDR_OFFSET
#define CCM_CS2CDR  CCM_BASE_ADDR+CCM_CS2CDR_OFFSET
#define CCM_CDCDR   CCM_BASE_ADDR+CCM_CDCDR_OFFSET
#define CCM_CHSCCDR CCM_BASE_ADDR+CCM_CHSCCDR_OFFSET
#define CCM_CSCDR2  CCM_BASE_ADDR+CCM_CSCDR2_OFFSET
#define CCM_CSCDR3  CCM_BASE_ADDR+CCM_CSCDR3_OFFSET
#define CCM_CSCDR4  CCM_BASE_ADDR+CCM_CSCDR4_OFFSET
#define CCM_CWDR    CCM_BASE_ADDR+CCM_CWDR_OFFSET
#define CCM_CDHIPR  CCM_BASE_ADDR+CCM_CDHIPR_OFFSET
#define CCM_CDCR    CCM_BASE_ADDR+CCM_CDCR_OFFSET
#define CCM_CTOR    CCM_BASE_ADDR+CCM_CTOR_OFFSET
#define CCM_CLPCR   CCM_BASE_ADDR+CCM_CLPCR_OFFSET
#define CCM_CISR    CCM_BASE_ADDR+CCM_CISR_OFFSET
#define CCM_CIMR    CCM_BASE_ADDR+CCM_CIMR_OFFSET
#define CCM_CCOSR   CCM_BASE_ADDR+CCM_CCOSR_OFFSET
#define CCM_CGPR    CCM_BASE_ADDR+CCM_CGPR_OFFSET
#define CCM_CCGR0   CCM_BASE_ADDR+CCM_CCGR0_OFFSET
#define CCM_CCGR1   CCM_BASE_ADDR+CCM_CCGR1_OFFSET
#define CCM_CCGR2   CCM_BASE_ADDR+CCM_CCGR2_OFFSET
#define CCM_CCGR3   CCM_BASE_ADDR+CCM_CCGR3_OFFSET
#define CCM_CCGR4   CCM_BASE_ADDR+CCM_CCGR4_OFFSET
#define CCM_CCGR5   CCM_BASE_ADDR+CCM_CCGR5_OFFSET
#define CCM_CCGR6   CCM_BASE_ADDR+CCM_CCGR6_OFFSET
#define CCM_CCGR7   CCM_BASE_ADDR+CCM_CCGR7_OFFSET
#define CCM_CMEOR   CCM_BASE_ADDR+CCM_CMEOR_OFFSET

//#########################################
//# CCM peripheral defines used by prog_pll.c and hardware.c
//#########################################
#define CLKCTL_CCGR1        CCM_CCGR1_OFFSET
#define CLKCTL_CSCMR1       CCM_CSCMR1_OFFSET
#define CLKCTL_CSCDR1       CCM_CSCDR1_OFFSET
#define CLKCTL_CBCMR        CCM_CBCMR_OFFSET
#define CLKCTL_CBCDR        CCM_CBCDR_OFFSET
#define CLKCTL_CCSR         CCM_CCSR_OFFSET
#define CLKCTL_CDHIPR       CCM_CDHIPR_OFFSET
#define CLKCTL_CACRR        CCM_CACRR_OFFSET
#define CLKCTL_CSCDR2       CCM_CSCDR2_OFFSET
#define CLKCTL_CS1CDR       CCM_CS1CDR_OFFSET
#define CLKCTL_CS2CDR       CCM_CS2CDR_OFFSET

#define CLKCTL_CSCMR2       CCM_CSCMR2_OFFSET

#define PLL1_BASE_ADDR      DPLLIP1_BASE_ADDR
#define PLL2_BASE_ADDR      DPLLIP2_BASE_ADDR
#define PLL3_BASE_ADDR      DPLLIP3_BASE_ADDR
#define PLL4_BASE_ADDR      DPLLIP4_BASE_ADDR

#define PLL_DP_CTL          DPLLIP_DP_CTL_OFFSET
#define PLL_DP_CONFIG       DPLLIP_DP_CONFIG_OFFSET
#define PLL_DP_OP           DPLLIP_DP_OP_OFFSET
#define PLL_DP_MFD          DPLLIP_DP_MFD_OFFSET
#define PLL_DP_MFN          DPLLIP_DP_MFN_OFFSET
#define PLL_DP_MFNMINUS     DPLLIP_DP_MFNMINUS_OFFSET
#define PLL_DP_MFNPLUS      DPLLIP_DP_MFNPLUS_OFFSET
#define PLL_DP_HFS_OP       DPLLIP_DP_HFS_OP_OFFSET
#define PLL_DP_HFS_MFD      DPLLIP_DP_HFS_MFD_OFFSET
#define PLL_DP_HFS_MFN      DPLLIP_DP_HFS_MFN_OFFSET
#define PLL_DP_TOGC         DPLLIP_DP_MFN_TOGC_OFFSET
#define PLL_DP_DESTAT       DPLLIP_DP_DESTAT_OFFSET

#endif