/* * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ #ifndef HPM_TRGMMUX_SRC_H #define HPM_TRGMMUX_SRC_H /* trgm0_input mux definitions */ #define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) #define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) #define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x2UL) #define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x3UL) #define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x4UL) #define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x5UL) #define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x6UL) #define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x7UL) #define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x8UL) #define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x9UL) #define HPM_TRGM0_INPUT_SRC_TRGM0_P8 (0xAUL) #define HPM_TRGM0_INPUT_SRC_TRGM0_P9 (0xBUL) #define HPM_TRGM0_INPUT_SRC_TRGM0_P10 (0xCUL) #define HPM_TRGM0_INPUT_SRC_TRGM0_P11 (0xDUL) #define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX0 (0xEUL) #define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX1 (0xFUL) #define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX0 (0x10UL) #define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX1 (0x11UL) #define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX0 (0x12UL) #define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX1 (0x13UL) #define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x14UL) #define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x15UL) #define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x16UL) #define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x17UL) #define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x18UL) #define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x19UL) #define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x1AUL) #define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x1BUL) #define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x1CUL) #define HPM_TRGM0_INPUT_SRC_HALL0_TRGO (0x1DUL) #define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x1EUL) #define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x1FUL) #define HPM_TRGM0_INPUT_SRC_SYNT_CH0 (0x20UL) #define HPM_TRGM0_INPUT_SRC_SYNT_CH1 (0x21UL) #define HPM_TRGM0_INPUT_SRC_SYNT_CH2 (0x22UL) #define HPM_TRGM0_INPUT_SRC_SYNT_CH3 (0x23UL) #define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x24UL) #define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x25UL) #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x26UL) #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x27UL) #define HPM_TRGM0_INPUT_SRC_SDM_CMPL0 (0x28UL) #define HPM_TRGM0_INPUT_SRC_SDM_CMPL1 (0x29UL) #define HPM_TRGM0_INPUT_SRC_SDM_CMPL2 (0x2AUL) #define HPM_TRGM0_INPUT_SRC_SDM_CMPL3 (0x2BUL) #define HPM_TRGM0_INPUT_SRC_SDM_CMPH0 (0x2CUL) #define HPM_TRGM0_INPUT_SRC_SDM_CMPH1 (0x2DUL) #define HPM_TRGM0_INPUT_SRC_SDM_CMPH2 (0x2EUL) #define HPM_TRGM0_INPUT_SRC_SDM_CMPH3 (0x2FUL) #define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ0 (0x30UL) #define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ1 (0x31UL) #define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ2 (0x32UL) #define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ3 (0x33UL) #define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x34UL) #define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x35UL) #define HPM_TRGM0_INPUT_SRC_CMP2_OUT (0x36UL) #define HPM_TRGM0_INPUT_SRC_CMP3_OUT (0x37UL) #define HPM_TRGM0_INPUT_SRC_PLA0_OUT0 (0x38UL) #define HPM_TRGM0_INPUT_SRC_PLA0_OUT1 (0x39UL) #define HPM_TRGM0_INPUT_SRC_PLA0_OUT2 (0x3AUL) #define HPM_TRGM0_INPUT_SRC_PLA0_OUT3 (0x3BUL) #define HPM_TRGM0_INPUT_SRC_PLA0_OUT4 (0x3CUL) #define HPM_TRGM0_INPUT_SRC_PLA0_OUT5 (0x3DUL) #define HPM_TRGM0_INPUT_SRC_PLA0_OUT6 (0x3EUL) #define HPM_TRGM0_INPUT_SRC_PLA0_OUT7 (0x3FUL) /* trgm1_input mux definitions */ #define HPM_TRGM1_INPUT_SRC_VSS (0x0UL) #define HPM_TRGM1_INPUT_SRC_VDD (0x1UL) #define HPM_TRGM1_INPUT_SRC_TRGM1_P0 (0x2UL) #define HPM_TRGM1_INPUT_SRC_TRGM1_P1 (0x3UL) #define HPM_TRGM1_INPUT_SRC_TRGM1_P2 (0x4UL) #define HPM_TRGM1_INPUT_SRC_TRGM1_P3 (0x5UL) #define HPM_TRGM1_INPUT_SRC_TRGM1_P4 (0x6UL) #define HPM_TRGM1_INPUT_SRC_TRGM1_P5 (0x7UL) #define HPM_TRGM1_INPUT_SRC_TRGM1_P6 (0x8UL) #define HPM_TRGM1_INPUT_SRC_TRGM1_P7 (0x9UL) #define HPM_TRGM1_INPUT_SRC_TRGM1_P8 (0xAUL) #define HPM_TRGM1_INPUT_SRC_TRGM1_P9 (0xBUL) #define HPM_TRGM1_INPUT_SRC_TRGM1_P10 (0xCUL) #define HPM_TRGM1_INPUT_SRC_TRGM1_P11 (0xDUL) #define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX0 (0xEUL) #define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX1 (0xFUL) #define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX0 (0x10UL) #define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX1 (0x11UL) #define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX0 (0x12UL) #define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX1 (0x13UL) #define HPM_TRGM1_INPUT_SRC_PWM1_CH8REF (0x14UL) #define HPM_TRGM1_INPUT_SRC_PWM1_CH9REF (0x15UL) #define HPM_TRGM1_INPUT_SRC_PWM1_CH10REF (0x16UL) #define HPM_TRGM1_INPUT_SRC_PWM1_CH11REF (0x17UL) #define HPM_TRGM1_INPUT_SRC_PWM1_CH12REF (0x18UL) #define HPM_TRGM1_INPUT_SRC_PWM1_CH13REF (0x19UL) #define HPM_TRGM1_INPUT_SRC_PWM1_CH14REF (0x1AUL) #define HPM_TRGM1_INPUT_SRC_PWM1_CH15REF (0x1BUL) #define HPM_TRGM1_INPUT_SRC_QEI1_TRGO (0x1CUL) #define HPM_TRGM1_INPUT_SRC_HALL1_TRGO (0x1DUL) #define HPM_TRGM1_INPUT_SRC_PTPC_CMP0 (0x1EUL) #define HPM_TRGM1_INPUT_SRC_PTPC_CMP1 (0x1FUL) #define HPM_TRGM1_INPUT_SRC_SYNT_CH0 (0x20UL) #define HPM_TRGM1_INPUT_SRC_SYNT_CH1 (0x21UL) #define HPM_TRGM1_INPUT_SRC_SYNT_CH2 (0x22UL) #define HPM_TRGM1_INPUT_SRC_SYNT_CH3 (0x23UL) #define HPM_TRGM1_INPUT_SRC_USB0_SOF (0x24UL) #define HPM_TRGM1_INPUT_SRC_DEBUG_FLAG (0x25UL) #define HPM_TRGM1_INPUT_SRC_GPTMR1_OUT2 (0x26UL) #define HPM_TRGM1_INPUT_SRC_GPTMR1_OUT3 (0x27UL) #define HPM_TRGM1_INPUT_SRC_SDM_CMPL0 (0x28UL) #define HPM_TRGM1_INPUT_SRC_SDM_CMPL1 (0x29UL) #define HPM_TRGM1_INPUT_SRC_SDM_CMPL2 (0x2AUL) #define HPM_TRGM1_INPUT_SRC_SDM_CMPL3 (0x2BUL) #define HPM_TRGM1_INPUT_SRC_SDM_CMPH0 (0x2CUL) #define HPM_TRGM1_INPUT_SRC_SDM_CMPH1 (0x2DUL) #define HPM_TRGM1_INPUT_SRC_SDM_CMPH2 (0x2EUL) #define HPM_TRGM1_INPUT_SRC_SDM_CMPH3 (0x2FUL) #define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ0 (0x30UL) #define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ1 (0x31UL) #define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ2 (0x32UL) #define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ3 (0x33UL) #define HPM_TRGM1_INPUT_SRC_CMP0_OUT (0x34UL) #define HPM_TRGM1_INPUT_SRC_CMP1_OUT (0x35UL) #define HPM_TRGM1_INPUT_SRC_CMP2_OUT (0x36UL) #define HPM_TRGM1_INPUT_SRC_CMP3_OUT (0x37UL) #define HPM_TRGM1_INPUT_SRC_PLA1_OUT0 (0x38UL) #define HPM_TRGM1_INPUT_SRC_PLA1_OUT1 (0x39UL) #define HPM_TRGM1_INPUT_SRC_PLA1_OUT2 (0x3AUL) #define HPM_TRGM1_INPUT_SRC_PLA1_OUT3 (0x3BUL) #define HPM_TRGM1_INPUT_SRC_PLA1_OUT4 (0x3CUL) #define HPM_TRGM1_INPUT_SRC_PLA1_OUT5 (0x3DUL) #define HPM_TRGM1_INPUT_SRC_PLA1_OUT6 (0x3EUL) #define HPM_TRGM1_INPUT_SRC_PLA1_OUT7 (0x3FUL) /* trgm2_input mux definitions */ #define HPM_TRGM2_INPUT_SRC_VSS (0x0UL) #define HPM_TRGM2_INPUT_SRC_VDD (0x1UL) #define HPM_TRGM2_INPUT_SRC_TRGM2_P0 (0x2UL) #define HPM_TRGM2_INPUT_SRC_TRGM2_P1 (0x3UL) #define HPM_TRGM2_INPUT_SRC_TRGM2_P2 (0x4UL) #define HPM_TRGM2_INPUT_SRC_TRGM2_P3 (0x5UL) #define HPM_TRGM2_INPUT_SRC_TRGM2_P4 (0x6UL) #define HPM_TRGM2_INPUT_SRC_TRGM2_P5 (0x7UL) #define HPM_TRGM2_INPUT_SRC_TRGM2_P6 (0x8UL) #define HPM_TRGM2_INPUT_SRC_TRGM2_P7 (0x9UL) #define HPM_TRGM2_INPUT_SRC_TRGM2_P8 (0xAUL) #define HPM_TRGM2_INPUT_SRC_TRGM2_P9 (0xBUL) #define HPM_TRGM2_INPUT_SRC_TRGM2_P10 (0xCUL) #define HPM_TRGM2_INPUT_SRC_TRGM2_P11 (0xDUL) #define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX0 (0xEUL) #define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX1 (0xFUL) #define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX0 (0x10UL) #define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX1 (0x11UL) #define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX0 (0x12UL) #define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX1 (0x13UL) #define HPM_TRGM2_INPUT_SRC_PWM2_CH8REF (0x14UL) #define HPM_TRGM2_INPUT_SRC_PWM2_CH9REF (0x15UL) #define HPM_TRGM2_INPUT_SRC_PWM2_CH10REF (0x16UL) #define HPM_TRGM2_INPUT_SRC_PWM2_CH11REF (0x17UL) #define HPM_TRGM2_INPUT_SRC_PWM2_CH12REF (0x18UL) #define HPM_TRGM2_INPUT_SRC_PWM2_CH13REF (0x19UL) #define HPM_TRGM2_INPUT_SRC_PWM2_CH14REF (0x1AUL) #define HPM_TRGM2_INPUT_SRC_PWM2_CH15REF (0x1BUL) #define HPM_TRGM2_INPUT_SRC_QEI2_TRGO (0x1CUL) #define HPM_TRGM2_INPUT_SRC_HALL2_TRGO (0x1DUL) #define HPM_TRGM2_INPUT_SRC_PTPC_CMP0 (0x1EUL) #define HPM_TRGM2_INPUT_SRC_PTPC_CMP1 (0x1FUL) #define HPM_TRGM2_INPUT_SRC_SYNT_CH0 (0x20UL) #define HPM_TRGM2_INPUT_SRC_SYNT_CH1 (0x21UL) #define HPM_TRGM2_INPUT_SRC_SYNT_CH2 (0x22UL) #define HPM_TRGM2_INPUT_SRC_SYNT_CH3 (0x23UL) #define HPM_TRGM2_INPUT_SRC_USB0_SOF (0x24UL) #define HPM_TRGM2_INPUT_SRC_DEBUG_FLAG (0x25UL) #define HPM_TRGM2_INPUT_SRC_GPTMR2_OUT2 (0x26UL) #define HPM_TRGM2_INPUT_SRC_GPTMR2_OUT3 (0x27UL) #define HPM_TRGM2_INPUT_SRC_SDM_CMPL0 (0x28UL) #define HPM_TRGM2_INPUT_SRC_SDM_CMPL1 (0x29UL) #define HPM_TRGM2_INPUT_SRC_SDM_CMPL2 (0x2AUL) #define HPM_TRGM2_INPUT_SRC_SDM_CMPL3 (0x2BUL) #define HPM_TRGM2_INPUT_SRC_SDM_CMPH0 (0x2CUL) #define HPM_TRGM2_INPUT_SRC_SDM_CMPH1 (0x2DUL) #define HPM_TRGM2_INPUT_SRC_SDM_CMPH2 (0x2EUL) #define HPM_TRGM2_INPUT_SRC_SDM_CMPH3 (0x2FUL) #define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ0 (0x30UL) #define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ1 (0x31UL) #define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ2 (0x32UL) #define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ3 (0x33UL) #define HPM_TRGM2_INPUT_SRC_CMP0_OUT (0x34UL) #define HPM_TRGM2_INPUT_SRC_CMP1_OUT (0x35UL) #define HPM_TRGM2_INPUT_SRC_CMP2_OUT (0x36UL) #define HPM_TRGM2_INPUT_SRC_CMP3_OUT (0x37UL) /* trgm3_input mux definitions */ #define HPM_TRGM3_INPUT_SRC_VSS (0x0UL) #define HPM_TRGM3_INPUT_SRC_VDD (0x1UL) #define HPM_TRGM3_INPUT_SRC_TRGM3_P0 (0x2UL) #define HPM_TRGM3_INPUT_SRC_TRGM3_P1 (0x3UL) #define HPM_TRGM3_INPUT_SRC_TRGM3_P2 (0x4UL) #define HPM_TRGM3_INPUT_SRC_TRGM3_P3 (0x5UL) #define HPM_TRGM3_INPUT_SRC_TRGM3_P4 (0x6UL) #define HPM_TRGM3_INPUT_SRC_TRGM3_P5 (0x7UL) #define HPM_TRGM3_INPUT_SRC_TRGM3_P6 (0x8UL) #define HPM_TRGM3_INPUT_SRC_TRGM3_P7 (0x9UL) #define HPM_TRGM3_INPUT_SRC_TRGM3_P8 (0xAUL) #define HPM_TRGM3_INPUT_SRC_TRGM3_P9 (0xBUL) #define HPM_TRGM3_INPUT_SRC_TRGM3_P10 (0xCUL) #define HPM_TRGM3_INPUT_SRC_TRGM3_P11 (0xDUL) #define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX0 (0xEUL) #define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX1 (0xFUL) #define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX0 (0x10UL) #define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX1 (0x11UL) #define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX0 (0x12UL) #define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX1 (0x13UL) #define HPM_TRGM3_INPUT_SRC_PWM3_CH8REF (0x14UL) #define HPM_TRGM3_INPUT_SRC_PWM3_CH9REF (0x15UL) #define HPM_TRGM3_INPUT_SRC_PWM3_CH10REF (0x16UL) #define HPM_TRGM3_INPUT_SRC_PWM3_CH11REF (0x17UL) #define HPM_TRGM3_INPUT_SRC_PWM3_CH12REF (0x18UL) #define HPM_TRGM3_INPUT_SRC_PWM3_CH13REF (0x19UL) #define HPM_TRGM3_INPUT_SRC_PWM3_CH14REF (0x1AUL) #define HPM_TRGM3_INPUT_SRC_PWM3_CH15REF (0x1BUL) #define HPM_TRGM3_INPUT_SRC_QEI3_TRGO (0x1CUL) #define HPM_TRGM3_INPUT_SRC_HALL3_TRGO (0x1DUL) #define HPM_TRGM3_INPUT_SRC_PTPC_CMP0 (0x1EUL) #define HPM_TRGM3_INPUT_SRC_PTPC_CMP1 (0x1FUL) #define HPM_TRGM3_INPUT_SRC_SYNT_CH0 (0x20UL) #define HPM_TRGM3_INPUT_SRC_SYNT_CH1 (0x21UL) #define HPM_TRGM3_INPUT_SRC_SYNT_CH2 (0x22UL) #define HPM_TRGM3_INPUT_SRC_SYNT_CH3 (0x23UL) #define HPM_TRGM3_INPUT_SRC_USB0_SOF (0x24UL) #define HPM_TRGM3_INPUT_SRC_DEBUG_FLAG (0x25UL) #define HPM_TRGM3_INPUT_SRC_GPTMR3_OUT2 (0x26UL) #define HPM_TRGM3_INPUT_SRC_GPTMR3_OUT3 (0x27UL) #define HPM_TRGM3_INPUT_SRC_SDM_CMPL0 (0x28UL) #define HPM_TRGM3_INPUT_SRC_SDM_CMPL1 (0x29UL) #define HPM_TRGM3_INPUT_SRC_SDM_CMPL2 (0x2AUL) #define HPM_TRGM3_INPUT_SRC_SDM_CMPL3 (0x2BUL) #define HPM_TRGM3_INPUT_SRC_SDM_CMPH0 (0x2CUL) #define HPM_TRGM3_INPUT_SRC_SDM_CMPH1 (0x2DUL) #define HPM_TRGM3_INPUT_SRC_SDM_CMPH2 (0x2EUL) #define HPM_TRGM3_INPUT_SRC_SDM_CMPH3 (0x2FUL) #define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ0 (0x30UL) #define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ1 (0x31UL) #define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ2 (0x32UL) #define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ3 (0x33UL) #define HPM_TRGM3_INPUT_SRC_CMP0_OUT (0x34UL) #define HPM_TRGM3_INPUT_SRC_CMP1_OUT (0x35UL) #define HPM_TRGM3_INPUT_SRC_CMP2_OUT (0x36UL) #define HPM_TRGM3_INPUT_SRC_CMP3_OUT (0x37UL) /* trgm0_output mux definitions */ #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P0 (0x0UL) #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P1 (0x1UL) #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P2 (0x2UL) #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P3 (0x3UL) #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P4 (0x4UL) #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P5 (0x5UL) #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P6 (0x6UL) #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P7 (0x7UL) #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P8 (0x8UL) #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P9 (0x9UL) #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P10 (0xAUL) #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P11 (0xBUL) #define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX0 (0xCUL) #define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX1 (0xDUL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0xEUL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0xFUL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x10UL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x11UL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x12UL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x13UL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI2 (0x14UL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI3 (0x15UL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN8 (0x16UL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN9 (0x17UL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN10 (0x18UL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN11 (0x19UL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN12 (0x1AUL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN13 (0x1BUL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN14 (0x1CUL) #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN15 (0x1DUL) #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN0 (0x1EUL) #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN1 (0x1FUL) #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN2 (0x20UL) #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN3 (0x21UL) #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN4 (0x22UL) #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN5 (0x23UL) #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN6 (0x24UL) #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN7 (0x25UL) #define HPM_TRGM0_OUTPUT_SRC_QEI0_A (0x26UL) #define HPM_TRGM0_OUTPUT_SRC_QEI0_B (0x27UL) #define HPM_TRGM0_OUTPUT_SRC_QEI0_Z (0x28UL) #define HPM_TRGM0_OUTPUT_SRC_QEI0_H (0x29UL) #define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x2AUL) #define HPM_TRGM0_OUTPUT_SRC_QEI0_SNAPI (0x2BUL) #define HPM_TRGM0_OUTPUT_SRC_HALL0_U (0x2CUL) #define HPM_TRGM0_OUTPUT_SRC_HALL0_V (0x2DUL) #define HPM_TRGM0_OUTPUT_SRC_HALL0_W (0x2EUL) #define HPM_TRGM0_OUTPUT_SRC_HALL0_SNAPI (0x2FUL) #define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x30UL) #define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x31UL) #define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI (0x32UL) #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x34UL) #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x35UL) #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x36UL) #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x37UL) #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x38UL) #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x39UL) #define HPM_TRGM0_OUTPUT_SRC_DAC0_BUF_TRG (0x3AUL) #define HPM_TRGM0_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) #define HPM_TRGM0_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) #define HPM_TRGM0_OUTPUT_SRC_ACMP0_WIN (0x3DUL) #define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) #define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) #define HPM_TRGM0_OUTPUT_SRC_SDM_TRG0 (0x40UL) #define HPM_TRGM0_OUTPUT_SRC_SDM_TRG1 (0x41UL) #define HPM_TRGM0_OUTPUT_SRC_SDM_TRG2 (0x42UL) #define HPM_TRGM0_OUTPUT_SRC_SDM_TRG3 (0x43UL) /* trgm1_output mux definitions */ #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P0 (0x0UL) #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P1 (0x1UL) #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P2 (0x2UL) #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P3 (0x3UL) #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P4 (0x4UL) #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P5 (0x5UL) #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P6 (0x6UL) #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P7 (0x7UL) #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P8 (0x8UL) #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P9 (0x9UL) #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P10 (0xAUL) #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P11 (0xBUL) #define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX0 (0xCUL) #define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX1 (0xDUL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_SYNCI (0xEUL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCI (0xFUL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCSYNCI (0x10UL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x11UL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI0 (0x12UL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI1 (0x13UL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI2 (0x14UL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI3 (0x15UL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN8 (0x16UL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN9 (0x17UL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN10 (0x18UL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN11 (0x19UL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN12 (0x1AUL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN13 (0x1BUL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN14 (0x1CUL) #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN15 (0x1DUL) #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN0 (0x1EUL) #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN1 (0x1FUL) #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN2 (0x20UL) #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN3 (0x21UL) #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN4 (0x22UL) #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN5 (0x23UL) #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN6 (0x24UL) #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN7 (0x25UL) #define HPM_TRGM1_OUTPUT_SRC_QEI1_A (0x26UL) #define HPM_TRGM1_OUTPUT_SRC_QEI1_B (0x27UL) #define HPM_TRGM1_OUTPUT_SRC_QEI1_Z (0x28UL) #define HPM_TRGM1_OUTPUT_SRC_QEI1_H (0x29UL) #define HPM_TRGM1_OUTPUT_SRC_QEI1_PAUSE (0x2AUL) #define HPM_TRGM1_OUTPUT_SRC_QEI1_SNAPI (0x2BUL) #define HPM_TRGM1_OUTPUT_SRC_HALL1_U (0x2CUL) #define HPM_TRGM1_OUTPUT_SRC_HALL1_V (0x2DUL) #define HPM_TRGM1_OUTPUT_SRC_HALL1_W (0x2EUL) #define HPM_TRGM1_OUTPUT_SRC_HALL1_SNAPI (0x2FUL) #define HPM_TRGM1_OUTPUT_SRC_ADC0_STRGI (0x30UL) #define HPM_TRGM1_OUTPUT_SRC_ADC1_STRGI (0x31UL) #define HPM_TRGM1_OUTPUT_SRC_ADC2_STRGI (0x32UL) #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1A (0x34UL) #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1B (0x35UL) #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1C (0x36UL) #define HPM_TRGM1_OUTPUT_SRC_GPTMR1_SYNCI (0x37UL) #define HPM_TRGM1_OUTPUT_SRC_GPTMR1_IN2 (0x38UL) #define HPM_TRGM1_OUTPUT_SRC_GPTMR1_IN3 (0x39UL) #define HPM_TRGM1_OUTPUT_SRC_DAC1_BUF_TRG (0x3AUL) #define HPM_TRGM1_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) #define HPM_TRGM1_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) #define HPM_TRGM1_OUTPUT_SRC_ACMP1_WIN (0x3DUL) #define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) #define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) #define HPM_TRGM1_OUTPUT_SRC_SDM_TRG4 (0x40UL) #define HPM_TRGM1_OUTPUT_SRC_SDM_TRG5 (0x41UL) #define HPM_TRGM1_OUTPUT_SRC_SDM_TRG6 (0x42UL) #define HPM_TRGM1_OUTPUT_SRC_SDM_TRG7 (0x43UL) /* trgm2_output mux definitions */ #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P0 (0x0UL) #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P1 (0x1UL) #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P2 (0x2UL) #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P3 (0x3UL) #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P4 (0x4UL) #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P5 (0x5UL) #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P6 (0x6UL) #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P7 (0x7UL) #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P8 (0x8UL) #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P9 (0x9UL) #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P10 (0xAUL) #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P11 (0xBUL) #define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX0 (0xCUL) #define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX1 (0xDUL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_SYNCI (0xEUL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCI (0xFUL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCSYNCI (0x10UL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_SHRLDSYNCI (0x11UL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI0 (0x12UL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI1 (0x13UL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI2 (0x14UL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI3 (0x15UL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN8 (0x16UL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN9 (0x17UL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN10 (0x18UL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN11 (0x19UL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN12 (0x1AUL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN13 (0x1BUL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN14 (0x1CUL) #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN15 (0x1DUL) #define HPM_TRGM2_OUTPUT_SRC_QEI2_A (0x26UL) #define HPM_TRGM2_OUTPUT_SRC_QEI2_B (0x27UL) #define HPM_TRGM2_OUTPUT_SRC_QEI2_Z (0x28UL) #define HPM_TRGM2_OUTPUT_SRC_QEI2_H (0x29UL) #define HPM_TRGM2_OUTPUT_SRC_QEI2_PAUSE (0x2AUL) #define HPM_TRGM2_OUTPUT_SRC_QEI2_SNAPI (0x2BUL) #define HPM_TRGM2_OUTPUT_SRC_HALL2_U (0x2CUL) #define HPM_TRGM2_OUTPUT_SRC_HALL2_V (0x2DUL) #define HPM_TRGM2_OUTPUT_SRC_HALL2_W (0x2EUL) #define HPM_TRGM2_OUTPUT_SRC_HALL2_SNAPI (0x2FUL) #define HPM_TRGM2_OUTPUT_SRC_ADC0_STRGI (0x30UL) #define HPM_TRGM2_OUTPUT_SRC_ADC1_STRGI (0x31UL) #define HPM_TRGM2_OUTPUT_SRC_ADC2_STRGI (0x32UL) #define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2A (0x34UL) #define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2B (0x35UL) #define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2C (0x36UL) #define HPM_TRGM2_OUTPUT_SRC_GPTMR2_SYNCI (0x37UL) #define HPM_TRGM2_OUTPUT_SRC_GPTMR2_IN2 (0x38UL) #define HPM_TRGM2_OUTPUT_SRC_GPTMR2_IN3 (0x39UL) #define HPM_TRGM2_OUTPUT_SRC_DAC0_BUF_TRG (0x3AUL) #define HPM_TRGM2_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) #define HPM_TRGM2_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) #define HPM_TRGM2_OUTPUT_SRC_ACMP2_WIN (0x3DUL) #define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) #define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) #define HPM_TRGM2_OUTPUT_SRC_SDM_TRG8 (0x40UL) #define HPM_TRGM2_OUTPUT_SRC_SDM_TRG9 (0x41UL) #define HPM_TRGM2_OUTPUT_SRC_SDM_TRG10 (0x42UL) #define HPM_TRGM2_OUTPUT_SRC_SDM_TRG11 (0x43UL) /* trgm3_output mux definitions */ #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P0 (0x0UL) #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P1 (0x1UL) #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P2 (0x2UL) #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P3 (0x3UL) #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P4 (0x4UL) #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P5 (0x5UL) #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P6 (0x6UL) #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P7 (0x7UL) #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P8 (0x8UL) #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P9 (0x9UL) #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P10 (0xAUL) #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P11 (0xBUL) #define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX0 (0xCUL) #define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX1 (0xDUL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_SYNCI (0xEUL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCI (0xFUL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCSYNCI (0x10UL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_SHRLDSYNCI (0x11UL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI0 (0x12UL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI1 (0x13UL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI2 (0x14UL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI3 (0x15UL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN8 (0x16UL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN9 (0x17UL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN10 (0x18UL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN11 (0x19UL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN12 (0x1AUL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN13 (0x1BUL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN14 (0x1CUL) #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN15 (0x1DUL) #define HPM_TRGM3_OUTPUT_SRC_QEI3_A (0x26UL) #define HPM_TRGM3_OUTPUT_SRC_QEI3_B (0x27UL) #define HPM_TRGM3_OUTPUT_SRC_QEI3_Z (0x28UL) #define HPM_TRGM3_OUTPUT_SRC_QEI3_H (0x29UL) #define HPM_TRGM3_OUTPUT_SRC_QEI3_PAUSE (0x2AUL) #define HPM_TRGM3_OUTPUT_SRC_QEI3_SNAPI (0x2BUL) #define HPM_TRGM3_OUTPUT_SRC_HALL3_U (0x2CUL) #define HPM_TRGM3_OUTPUT_SRC_HALL3_V (0x2DUL) #define HPM_TRGM3_OUTPUT_SRC_HALL3_W (0x2EUL) #define HPM_TRGM3_OUTPUT_SRC_HALL3_SNAPI (0x2FUL) #define HPM_TRGM3_OUTPUT_SRC_ADC0_STRGI (0x30UL) #define HPM_TRGM3_OUTPUT_SRC_ADC1_STRGI (0x31UL) #define HPM_TRGM3_OUTPUT_SRC_ADC2_STRGI (0x32UL) #define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3A (0x34UL) #define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3B (0x35UL) #define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3C (0x36UL) #define HPM_TRGM3_OUTPUT_SRC_GPTMR3_SYNCI (0x37UL) #define HPM_TRGM3_OUTPUT_SRC_GPTMR3_IN2 (0x38UL) #define HPM_TRGM3_OUTPUT_SRC_GPTMR3_IN3 (0x39UL) #define HPM_TRGM3_OUTPUT_SRC_DAC1_BUF_TRG (0x3AUL) #define HPM_TRGM3_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) #define HPM_TRGM3_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) #define HPM_TRGM3_OUTPUT_SRC_ACMP3_WIN (0x3DUL) #define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) #define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) #define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG12 (0x40UL) #define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG13 (0x41UL) #define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG14 (0x42UL) #define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG15 (0x43UL) /* trgm0_filter mux definitions */ #define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) #define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) #define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) #define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) #define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) #define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) #define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) #define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) #define HPM_TRGM0_FILTER_SRC_TRGM0_IN0 (0x8UL) #define HPM_TRGM0_FILTER_SRC_TRGM0_IN1 (0x9UL) #define HPM_TRGM0_FILTER_SRC_TRGM0_IN2 (0xAUL) #define HPM_TRGM0_FILTER_SRC_TRGM0_IN3 (0xBUL) #define HPM_TRGM0_FILTER_SRC_TRGM0_IN4 (0xCUL) #define HPM_TRGM0_FILTER_SRC_TRGM0_IN5 (0xDUL) #define HPM_TRGM0_FILTER_SRC_TRGM0_IN6 (0xEUL) #define HPM_TRGM0_FILTER_SRC_TRGM0_IN7 (0xFUL) #define HPM_TRGM0_FILTER_SRC_TRGM0_IN8 (0x10UL) #define HPM_TRGM0_FILTER_SRC_TRGM0_IN9 (0x11UL) #define HPM_TRGM0_FILTER_SRC_TRGM0_IN10 (0x12UL) #define HPM_TRGM0_FILTER_SRC_TRGM0_IN11 (0x13UL) /* trgm1_filter mux definitions */ #define HPM_TRGM1_FILTER_SRC_PWM1_IN0 (0x0UL) #define HPM_TRGM1_FILTER_SRC_PWM1_IN1 (0x1UL) #define HPM_TRGM1_FILTER_SRC_PWM1_IN2 (0x2UL) #define HPM_TRGM1_FILTER_SRC_PWM1_IN3 (0x3UL) #define HPM_TRGM1_FILTER_SRC_PWM1_IN4 (0x4UL) #define HPM_TRGM1_FILTER_SRC_PWM1_IN5 (0x5UL) #define HPM_TRGM1_FILTER_SRC_PWM1_IN6 (0x6UL) #define HPM_TRGM1_FILTER_SRC_PWM1_IN7 (0x7UL) #define HPM_TRGM1_FILTER_SRC_TRGM1_IN0 (0x8UL) #define HPM_TRGM1_FILTER_SRC_TRGM1_IN1 (0x9UL) #define HPM_TRGM1_FILTER_SRC_TRGM1_IN2 (0xAUL) #define HPM_TRGM1_FILTER_SRC_TRGM1_IN3 (0xBUL) #define HPM_TRGM1_FILTER_SRC_TRGM1_IN4 (0xCUL) #define HPM_TRGM1_FILTER_SRC_TRGM1_IN5 (0xDUL) #define HPM_TRGM1_FILTER_SRC_TRGM1_IN6 (0xEUL) #define HPM_TRGM1_FILTER_SRC_TRGM1_IN7 (0xFUL) #define HPM_TRGM1_FILTER_SRC_TRGM1_IN8 (0x10UL) #define HPM_TRGM1_FILTER_SRC_TRGM1_IN9 (0x11UL) #define HPM_TRGM1_FILTER_SRC_TRGM1_IN10 (0x12UL) #define HPM_TRGM1_FILTER_SRC_TRGM1_IN11 (0x13UL) /* trgm2_filter mux definitions */ #define HPM_TRGM2_FILTER_SRC_PWM2_IN0 (0x0UL) #define HPM_TRGM2_FILTER_SRC_PWM2_IN1 (0x1UL) #define HPM_TRGM2_FILTER_SRC_PWM2_IN2 (0x2UL) #define HPM_TRGM2_FILTER_SRC_PWM2_IN3 (0x3UL) #define HPM_TRGM2_FILTER_SRC_PWM2_IN4 (0x4UL) #define HPM_TRGM2_FILTER_SRC_PWM2_IN5 (0x5UL) #define HPM_TRGM2_FILTER_SRC_PWM2_IN6 (0x6UL) #define HPM_TRGM2_FILTER_SRC_PWM2_IN7 (0x7UL) #define HPM_TRGM2_FILTER_SRC_TRGM2_IN0 (0x8UL) #define HPM_TRGM2_FILTER_SRC_TRGM2_IN1 (0x9UL) #define HPM_TRGM2_FILTER_SRC_TRGM2_IN2 (0xAUL) #define HPM_TRGM2_FILTER_SRC_TRGM2_IN3 (0xBUL) #define HPM_TRGM2_FILTER_SRC_TRGM2_IN4 (0xCUL) #define HPM_TRGM2_FILTER_SRC_TRGM2_IN5 (0xDUL) #define HPM_TRGM2_FILTER_SRC_TRGM2_IN6 (0xEUL) #define HPM_TRGM2_FILTER_SRC_TRGM2_IN7 (0xFUL) #define HPM_TRGM2_FILTER_SRC_TRGM2_IN8 (0x10UL) #define HPM_TRGM2_FILTER_SRC_TRGM2_IN9 (0x11UL) #define HPM_TRGM2_FILTER_SRC_TRGM2_IN10 (0x12UL) #define HPM_TRGM2_FILTER_SRC_TRGM2_IN11 (0x13UL) /* trgm3_filter mux definitions */ #define HPM_TRGM3_FILTER_SRC_PWM3_IN0 (0x0UL) #define HPM_TRGM3_FILTER_SRC_PWM3_IN1 (0x1UL) #define HPM_TRGM3_FILTER_SRC_PWM3_IN2 (0x2UL) #define HPM_TRGM3_FILTER_SRC_PWM3_IN3 (0x3UL) #define HPM_TRGM3_FILTER_SRC_PWM3_IN4 (0x4UL) #define HPM_TRGM3_FILTER_SRC_PWM3_IN5 (0x5UL) #define HPM_TRGM3_FILTER_SRC_PWM3_IN6 (0x6UL) #define HPM_TRGM3_FILTER_SRC_PWM3_IN7 (0x7UL) #define HPM_TRGM3_FILTER_SRC_TRGM3_IN0 (0x8UL) #define HPM_TRGM3_FILTER_SRC_TRGM3_IN1 (0x9UL) #define HPM_TRGM3_FILTER_SRC_TRGM3_IN2 (0xAUL) #define HPM_TRGM3_FILTER_SRC_TRGM3_IN3 (0xBUL) #define HPM_TRGM3_FILTER_SRC_TRGM3_IN4 (0xCUL) #define HPM_TRGM3_FILTER_SRC_TRGM3_IN5 (0xDUL) #define HPM_TRGM3_FILTER_SRC_TRGM3_IN6 (0xEUL) #define HPM_TRGM3_FILTER_SRC_TRGM3_IN7 (0xFUL) #define HPM_TRGM3_FILTER_SRC_TRGM3_IN8 (0x10UL) #define HPM_TRGM3_FILTER_SRC_TRGM3_IN9 (0x11UL) #define HPM_TRGM3_FILTER_SRC_TRGM3_IN10 (0x12UL) #define HPM_TRGM3_FILTER_SRC_TRGM3_IN11 (0x13UL) /* trgm0_dma mux definitions */ #define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) #define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) #define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) #define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) #define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) #define HPM_TRGM0_DMA_SRC_QEI0 (0x1BUL) #define HPM_TRGM0_DMA_SRC_HALL0 (0x1CUL) /* trgm1_dma mux definitions */ #define HPM_TRGM1_DMA_SRC_PWM1_CMP0 (0x0UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP1 (0x1UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP2 (0x2UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP3 (0x3UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP4 (0x4UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP5 (0x5UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP6 (0x6UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP7 (0x7UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP8 (0x8UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP9 (0x9UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP10 (0xAUL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP11 (0xBUL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP12 (0xCUL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP13 (0xDUL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP14 (0xEUL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP15 (0xFUL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP16 (0x10UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP17 (0x11UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP18 (0x12UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP19 (0x13UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP20 (0x14UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP21 (0x15UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP22 (0x16UL) #define HPM_TRGM1_DMA_SRC_PWM1_CMP23 (0x17UL) #define HPM_TRGM1_DMA_SRC_PWM1_RLD (0x18UL) #define HPM_TRGM1_DMA_SRC_PWM1_HALFRLD (0x19UL) #define HPM_TRGM1_DMA_SRC_PWM1_XRLD (0x1AUL) #define HPM_TRGM1_DMA_SRC_QEI1 (0x1BUL) #define HPM_TRGM1_DMA_SRC_HALL1 (0x1CUL) /* trgm2_dma mux definitions */ #define HPM_TRGM2_DMA_SRC_PWM2_CMP0 (0x0UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP1 (0x1UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP2 (0x2UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP3 (0x3UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP4 (0x4UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP5 (0x5UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP6 (0x6UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP7 (0x7UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP8 (0x8UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP9 (0x9UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP10 (0xAUL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP11 (0xBUL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP12 (0xCUL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP13 (0xDUL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP14 (0xEUL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP15 (0xFUL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP16 (0x10UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP17 (0x11UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP18 (0x12UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP19 (0x13UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP20 (0x14UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP21 (0x15UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP22 (0x16UL) #define HPM_TRGM2_DMA_SRC_PWM2_CMP23 (0x17UL) #define HPM_TRGM2_DMA_SRC_PWM2_RLD (0x18UL) #define HPM_TRGM2_DMA_SRC_PWM2_HALFRLD (0x19UL) #define HPM_TRGM2_DMA_SRC_PWM2_XRLD (0x1AUL) #define HPM_TRGM2_DMA_SRC_QEI2 (0x1BUL) #define HPM_TRGM2_DMA_SRC_HALL2 (0x1CUL) /* trgm3_dma mux definitions */ #define HPM_TRGM3_DMA_SRC_PWM3_CMP0 (0x0UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP1 (0x1UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP2 (0x2UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP3 (0x3UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP4 (0x4UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP5 (0x5UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP6 (0x6UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP7 (0x7UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP8 (0x8UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP9 (0x9UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP10 (0xAUL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP11 (0xBUL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP12 (0xCUL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP13 (0xDUL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP14 (0xEUL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP15 (0xFUL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP16 (0x10UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP17 (0x11UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP18 (0x12UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP19 (0x13UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP20 (0x14UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP21 (0x15UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP22 (0x16UL) #define HPM_TRGM3_DMA_SRC_PWM3_CMP23 (0x17UL) #define HPM_TRGM3_DMA_SRC_PWM3_RLD (0x18UL) #define HPM_TRGM3_DMA_SRC_PWM3_HALFRLD (0x19UL) #define HPM_TRGM3_DMA_SRC_PWM3_XRLD (0x1AUL) #define HPM_TRGM3_DMA_SRC_QEI3 (0x1BUL) #define HPM_TRGM3_DMA_SRC_HALL3 (0x1CUL) #endif /* HPM_TRGMMUX_SRC_H */