hw_ints.h 7.1 KB

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  1. //*****************************************************************************
  2. //
  3. // hw_ints.h - Macros that define the interrupt assignment on Stellaris.
  4. //
  5. // Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
  6. // Software License Agreement
  7. //
  8. // Texas Instruments (TI) is supplying this software for use solely and
  9. // exclusively on TI's microcontroller products. The software is owned by
  10. // TI and/or its suppliers, and is protected under applicable copyright
  11. // laws. You may not combine this software with "viral" open-source
  12. // software in order to form a larger program.
  13. //
  14. // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
  15. // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
  16. // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  17. // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
  18. // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
  19. // DAMAGES, FOR ANY REASON WHATSOEVER.
  20. //
  21. // This is part of revision 6459 of the Stellaris Firmware Development Package.
  22. //
  23. //*****************************************************************************
  24. #ifndef __HW_INTS_H__
  25. #define __HW_INTS_H__
  26. //*****************************************************************************
  27. //
  28. // The following are defines for the fault assignments.
  29. //
  30. //*****************************************************************************
  31. #define FAULT_NMI 2 // NMI fault
  32. #define FAULT_HARD 3 // Hard fault
  33. #define FAULT_MPU 4 // MPU fault
  34. #define FAULT_BUS 5 // Bus fault
  35. #define FAULT_USAGE 6 // Usage fault
  36. #define FAULT_SVCALL 11 // SVCall
  37. #define FAULT_DEBUG 12 // Debug monitor
  38. #define FAULT_PENDSV 14 // PendSV
  39. #define FAULT_SYSTICK 15 // System Tick
  40. //*****************************************************************************
  41. //
  42. // The following are defines for the interrupt assignments.
  43. //
  44. //*****************************************************************************
  45. #define INT_GPIOA 16 // GPIO Port A
  46. #define INT_GPIOB 17 // GPIO Port B
  47. #define INT_GPIOC 18 // GPIO Port C
  48. #define INT_GPIOD 19 // GPIO Port D
  49. #define INT_GPIOE 20 // GPIO Port E
  50. #define INT_UART0 21 // UART0 Rx and Tx
  51. #define INT_UART1 22 // UART1 Rx and Tx
  52. #define INT_SSI0 23 // SSI0 Rx and Tx
  53. #define INT_I2C0 24 // I2C0 Master and Slave
  54. #define INT_PWM_FAULT 25 // PWM Fault
  55. #define INT_PWM0 26 // PWM Generator 0
  56. #define INT_PWM1 27 // PWM Generator 1
  57. #define INT_PWM2 28 // PWM Generator 2
  58. #define INT_QEI0 29 // Quadrature Encoder 0
  59. #define INT_ADC0SS0 30 // ADC0 Sequence 0
  60. #define INT_ADC0SS1 31 // ADC0 Sequence 1
  61. #define INT_ADC0SS2 32 // ADC0 Sequence 2
  62. #define INT_ADC0SS3 33 // ADC0 Sequence 3
  63. #define INT_WATCHDOG 34 // Watchdog timer
  64. #define INT_TIMER0A 35 // Timer 0 subtimer A
  65. #define INT_TIMER0B 36 // Timer 0 subtimer B
  66. #define INT_TIMER1A 37 // Timer 1 subtimer A
  67. #define INT_TIMER1B 38 // Timer 1 subtimer B
  68. #define INT_TIMER2A 39 // Timer 2 subtimer A
  69. #define INT_TIMER2B 40 // Timer 2 subtimer B
  70. #define INT_COMP0 41 // Analog Comparator 0
  71. #define INT_COMP1 42 // Analog Comparator 1
  72. #define INT_COMP2 43 // Analog Comparator 2
  73. #define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
  74. #define INT_FLASH 45 // FLASH Control
  75. #define INT_GPIOF 46 // GPIO Port F
  76. #define INT_GPIOG 47 // GPIO Port G
  77. #define INT_GPIOH 48 // GPIO Port H
  78. #define INT_UART2 49 // UART2 Rx and Tx
  79. #define INT_SSI1 50 // SSI1 Rx and Tx
  80. #define INT_TIMER3A 51 // Timer 3 subtimer A
  81. #define INT_TIMER3B 52 // Timer 3 subtimer B
  82. #define INT_I2C1 53 // I2C1 Master and Slave
  83. #define INT_QEI1 54 // Quadrature Encoder 1
  84. #define INT_CAN0 55 // CAN0
  85. #define INT_CAN1 56 // CAN1
  86. #define INT_CAN2 57 // CAN2
  87. #define INT_ETH 58 // Ethernet
  88. #define INT_HIBERNATE 59 // Hibernation module
  89. #define INT_USB0 60 // USB 0 Controller
  90. #define INT_PWM3 61 // PWM Generator 3
  91. #define INT_UDMA 62 // uDMA controller
  92. #define INT_UDMAERR 63 // uDMA Error
  93. #define INT_ADC1SS0 64 // ADC1 Sequence 0
  94. #define INT_ADC1SS1 65 // ADC1 Sequence 1
  95. #define INT_ADC1SS2 66 // ADC1 Sequence 2
  96. #define INT_ADC1SS3 67 // ADC1 Sequence 3
  97. #define INT_I2S0 68 // I2S0
  98. #define INT_EPI0 69 // EPI0
  99. #define INT_GPIOJ 70 // GPIO Port J
  100. //*****************************************************************************
  101. //
  102. // The following are defines for the total number of interrupts.
  103. //
  104. //*****************************************************************************
  105. #define NUM_INTERRUPTS 71
  106. //*****************************************************************************
  107. //
  108. // The following are defines for the total number of priority levels.
  109. //
  110. //*****************************************************************************
  111. #define NUM_PRIORITY 8
  112. #define NUM_PRIORITY_BITS 3
  113. //*****************************************************************************
  114. //
  115. // The following definitions are deprecated.
  116. //
  117. //*****************************************************************************
  118. #ifndef DEPRECATED
  119. //*****************************************************************************
  120. //
  121. // The following are deprecated defines for the interrupt assignments.
  122. //
  123. //*****************************************************************************
  124. #define INT_SSI 23 // SSI Rx and Tx
  125. #define INT_I2C 24 // I2C Master and Slave
  126. #define INT_QEI 29 // Quadrature Encoder
  127. #define INT_ADC0 30 // ADC Sequence 0
  128. #define INT_ADC1 31 // ADC Sequence 1
  129. #define INT_ADC2 32 // ADC Sequence 2
  130. #define INT_ADC3 33 // ADC Sequence 3
  131. #endif
  132. #endif // __HW_INTS_H__