hw_udma.h 15 KB

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  1. //*****************************************************************************
  2. //
  3. // hw_udma.h - Macros for use in accessing the UDMA registers.
  4. //
  5. // Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved.
  6. // Software License Agreement
  7. //
  8. // Texas Instruments (TI) is supplying this software for use solely and
  9. // exclusively on TI's microcontroller products. The software is owned by
  10. // TI and/or its suppliers, and is protected under applicable copyright
  11. // laws. You may not combine this software with "viral" open-source
  12. // software in order to form a larger program.
  13. //
  14. // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
  15. // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
  16. // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  17. // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
  18. // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
  19. // DAMAGES, FOR ANY REASON WHATSOEVER.
  20. //
  21. // This is part of revision 6459 of the Stellaris Firmware Development Package.
  22. //
  23. //*****************************************************************************
  24. #ifndef __HW_UDMA_H__
  25. #define __HW_UDMA_H__
  26. //*****************************************************************************
  27. //
  28. // The following are defines for the Micro Direct Memory Access register
  29. // addresses.
  30. //
  31. //*****************************************************************************
  32. #define UDMA_STAT 0x400FF000 // DMA Status
  33. #define UDMA_CFG 0x400FF004 // DMA Configuration
  34. #define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer
  35. #define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control
  36. // Base Pointer
  37. #define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait-on-Request
  38. // Status
  39. #define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request
  40. #define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set
  41. #define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear
  42. #define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set
  43. #define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear
  44. #define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set
  45. #define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear
  46. #define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate
  47. // Set
  48. #define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate
  49. // Clear
  50. #define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set
  51. #define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear
  52. #define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear
  53. #define UDMA_CHALT 0x400FF500 // DMA Channel Alternate Select
  54. //*****************************************************************************
  55. //
  56. // The following are defines for the bit fields in the UDMA_STAT register.
  57. //
  58. //*****************************************************************************
  59. #define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1
  60. #define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status
  61. #define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
  62. #define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data
  63. #define UDMA_STAT_STATE_RD_SRCENDP \
  64. 0x00000020 // Reading source end pointer
  65. #define UDMA_STAT_STATE_RD_DSTENDP \
  66. 0x00000030 // Reading destination end pointer
  67. #define UDMA_STAT_STATE_RD_SRCDAT \
  68. 0x00000040 // Reading source data
  69. #define UDMA_STAT_STATE_WR_DSTDAT \
  70. 0x00000050 // Writing destination data
  71. #define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to
  72. // clear
  73. #define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data
  74. #define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
  75. #define UDMA_STAT_STATE_DONE 0x00000090 // Done
  76. #define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
  77. #define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status
  78. #define UDMA_STAT_DMACHANS_S 16
  79. //*****************************************************************************
  80. //
  81. // The following are defines for the bit fields in the UDMA_CFG register.
  82. //
  83. //*****************************************************************************
  84. #define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable
  85. //*****************************************************************************
  86. //
  87. // The following are defines for the bit fields in the UDMA_CTLBASE register.
  88. //
  89. //*****************************************************************************
  90. #define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address
  91. #define UDMA_CTLBASE_ADDR_S 10
  92. //*****************************************************************************
  93. //
  94. // The following are defines for the bit fields in the UDMA_ALTBASE register.
  95. //
  96. //*****************************************************************************
  97. #define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
  98. // Pointer
  99. #define UDMA_ALTBASE_ADDR_S 0
  100. //*****************************************************************************
  101. //
  102. // The following are defines for the bit fields in the UDMA_WAITSTAT register.
  103. //
  104. //*****************************************************************************
  105. #define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status
  106. //*****************************************************************************
  107. //
  108. // The following are defines for the bit fields in the UDMA_SWREQ register.
  109. //
  110. //*****************************************************************************
  111. #define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request
  112. //*****************************************************************************
  113. //
  114. // The following are defines for the bit fields in the UDMA_USEBURSTSET
  115. // register.
  116. //
  117. //*****************************************************************************
  118. #define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set
  119. //*****************************************************************************
  120. //
  121. // The following are defines for the bit fields in the UDMA_USEBURSTCLR
  122. // register.
  123. //
  124. //*****************************************************************************
  125. #define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear
  126. //*****************************************************************************
  127. //
  128. // The following are defines for the bit fields in the UDMA_REQMASKSET
  129. // register.
  130. //
  131. //*****************************************************************************
  132. #define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set
  133. //*****************************************************************************
  134. //
  135. // The following are defines for the bit fields in the UDMA_REQMASKCLR
  136. // register.
  137. //
  138. //*****************************************************************************
  139. #define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear
  140. //*****************************************************************************
  141. //
  142. // The following are defines for the bit fields in the UDMA_ENASET register.
  143. //
  144. //*****************************************************************************
  145. #define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set
  146. //*****************************************************************************
  147. //
  148. // The following are defines for the bit fields in the UDMA_ENACLR register.
  149. //
  150. //*****************************************************************************
  151. #define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear
  152. //*****************************************************************************
  153. //
  154. // The following are defines for the bit fields in the UDMA_ALTSET register.
  155. //
  156. //*****************************************************************************
  157. #define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set
  158. //*****************************************************************************
  159. //
  160. // The following are defines for the bit fields in the UDMA_ALTCLR register.
  161. //
  162. //*****************************************************************************
  163. #define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear
  164. //*****************************************************************************
  165. //
  166. // The following are defines for the bit fields in the UDMA_PRIOSET register.
  167. //
  168. //*****************************************************************************
  169. #define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set
  170. //*****************************************************************************
  171. //
  172. // The following are defines for the bit fields in the UDMA_PRIOCLR register.
  173. //
  174. //*****************************************************************************
  175. #define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear
  176. //*****************************************************************************
  177. //
  178. // The following are defines for the bit fields in the UDMA_ERRCLR register.
  179. //
  180. //*****************************************************************************
  181. #define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status
  182. //*****************************************************************************
  183. //
  184. // The following are defines for the bit fields in the UDMA_CHALT register.
  185. //
  186. //*****************************************************************************
  187. #define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment
  188. // Select
  189. //*****************************************************************************
  190. //
  191. // The following are defines for the Micro Direct Memory Access (uDMA) offsets.
  192. //
  193. //*****************************************************************************
  194. #define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
  195. // Pointer
  196. #define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
  197. // End Pointer
  198. #define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
  199. //*****************************************************************************
  200. //
  201. // The following are defines for the bit fields in the UDMA_O_SRCENDP register.
  202. //
  203. //*****************************************************************************
  204. #define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
  205. #define UDMA_SRCENDP_ADDR_S 0
  206. //*****************************************************************************
  207. //
  208. // The following are defines for the bit fields in the UDMA_O_DSTENDP register.
  209. //
  210. //*****************************************************************************
  211. #define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
  212. #define UDMA_DSTENDP_ADDR_S 0
  213. //*****************************************************************************
  214. //
  215. // The following are defines for the bit fields in the UDMA_O_CHCTL register.
  216. //
  217. //*****************************************************************************
  218. #define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
  219. #define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
  220. #define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
  221. #define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
  222. #define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
  223. #define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
  224. #define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
  225. #define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
  226. #define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
  227. #define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
  228. #define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
  229. #define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
  230. #define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
  231. #define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
  232. #define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
  233. #define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
  234. #define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
  235. #define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
  236. #define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
  237. #define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
  238. #define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
  239. #define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
  240. #define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
  241. #define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
  242. #define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
  243. #define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
  244. #define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
  245. #define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
  246. #define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
  247. #define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
  248. #define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
  249. #define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
  250. #define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
  251. #define UDMA_CHCTL_XFERMODE_STOP \
  252. 0x00000000 // Stop
  253. #define UDMA_CHCTL_XFERMODE_BASIC \
  254. 0x00000001 // Basic
  255. #define UDMA_CHCTL_XFERMODE_AUTO \
  256. 0x00000002 // Auto-Request
  257. #define UDMA_CHCTL_XFERMODE_PINGPONG \
  258. 0x00000003 // Ping-Pong
  259. #define UDMA_CHCTL_XFERMODE_MEM_SG \
  260. 0x00000004 // Memory Scatter-Gather
  261. #define UDMA_CHCTL_XFERMODE_MEM_SGA \
  262. 0x00000005 // Alternate Memory Scatter-Gather
  263. #define UDMA_CHCTL_XFERMODE_PER_SG \
  264. 0x00000006 // Peripheral Scatter-Gather
  265. #define UDMA_CHCTL_XFERMODE_PER_SGA \
  266. 0x00000007 // Alternate Peripheral
  267. // Scatter-Gather
  268. #define UDMA_CHCTL_XFERSIZE_S 4
  269. //*****************************************************************************
  270. //
  271. // The following definitions are deprecated.
  272. //
  273. //*****************************************************************************
  274. #ifndef DEPRECATED
  275. //*****************************************************************************
  276. //
  277. // The following are deprecated defines for the bit fields in the UDMA_ENASET
  278. // register.
  279. //
  280. //*****************************************************************************
  281. #define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set
  282. #endif
  283. #endif // __HW_UDMA_H__