context_gcc.S 4.1 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2013-07-05 Bernard the first version
  9. */
  10. #include "rtconfig.h"
  11. .section .text, "ax"
  12. #ifdef RT_USING_SMP
  13. #define rt_hw_interrupt_disable rt_hw_local_irq_disable
  14. #define rt_hw_interrupt_enable rt_hw_local_irq_enable
  15. #endif
  16. /*
  17. * rt_base_t rt_hw_interrupt_disable();
  18. */
  19. .globl rt_hw_interrupt_disable
  20. rt_hw_interrupt_disable:
  21. mrs r0, cpsr
  22. cpsid i
  23. bx lr
  24. /*
  25. * void rt_hw_interrupt_enable(rt_base_t level);
  26. */
  27. .globl rt_hw_interrupt_enable
  28. rt_hw_interrupt_enable:
  29. msr cpsr, r0
  30. bx lr
  31. /*
  32. * void rt_hw_context_switch_to(rt_uint32 to, struct rt_thread *to_thread);
  33. * r0 --> to (thread stack)
  34. * r1 --> to_thread
  35. */
  36. .globl rt_hw_context_switch_to
  37. rt_hw_context_switch_to:
  38. ldr sp, [r0] @ get new task stack pointer
  39. #ifdef RT_USING_SMP
  40. mov r0, r1
  41. bl rt_cpus_lock_status_restore
  42. #endif /*RT_USING_SMP*/
  43. b rt_hw_context_switch_exit
  44. .section .bss.share.isr
  45. _guest_switch_lvl:
  46. .word 0
  47. .globl vmm_virq_update
  48. .section .text.isr, "ax"
  49. /*
  50. * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to, struct rt_thread *to_thread);
  51. * r0 --> from (from_thread stack)
  52. * r1 --> to (to_thread stack)
  53. * r2 --> to_thread
  54. */
  55. .globl rt_hw_context_switch
  56. rt_hw_context_switch:
  57. stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC)
  58. stmfd sp!, {r0-r12, lr} @ push lr & register file
  59. mrs r4, cpsr
  60. tst lr, #0x01
  61. orrne r4, r4, #0x20 @ it's thumb code
  62. stmfd sp!, {r4} @ push cpsr
  63. #ifdef RT_USING_LWP
  64. stmfd sp, {r13, r14}^ @ push usr_sp usr_lr
  65. sub sp, #8
  66. #endif
  67. #ifdef RT_USING_FPU
  68. /* fpu context */
  69. vmrs r6, fpexc
  70. tst r6, #(1<<30)
  71. beq 1f
  72. vstmdb sp!, {d0-d15}
  73. vstmdb sp!, {d16-d31}
  74. vmrs r5, fpscr
  75. stmfd sp!, {r5}
  76. 1:
  77. stmfd sp!, {r6}
  78. #endif
  79. str sp, [r0] @ store sp in preempted tasks TCB
  80. ldr sp, [r1] @ get new task stack pointer
  81. #ifdef RT_USING_SMP
  82. mov r0, r2
  83. bl rt_cpus_lock_status_restore
  84. #endif /*RT_USING_SMP*/
  85. b rt_hw_context_switch_exit
  86. /*
  87. * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
  88. */
  89. .equ Mode_USR, 0x10
  90. .equ Mode_FIQ, 0x11
  91. .equ Mode_IRQ, 0x12
  92. .equ Mode_SVC, 0x13
  93. .equ Mode_ABT, 0x17
  94. .equ Mode_UND, 0x1B
  95. .equ Mode_SYS, 0x1F
  96. .equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
  97. .equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
  98. .globl rt_thread_switch_interrupt_flag
  99. .globl rt_interrupt_from_thread
  100. .globl rt_interrupt_to_thread
  101. .globl rt_hw_context_switch_interrupt
  102. rt_hw_context_switch_interrupt:
  103. #ifdef RT_USING_SMP
  104. /* r0 :svc_mod context
  105. * r1 :addr of from_thread's sp
  106. * r2 :addr of to_thread's sp
  107. * r3 :to_thread's tcb
  108. */
  109. str r0, [r1]
  110. ldr sp, [r2]
  111. mov r0, r3
  112. bl rt_cpus_lock_status_restore
  113. b rt_hw_context_switch_exit
  114. #else /*RT_USING_SMP*/
  115. ldr r2, =rt_thread_switch_interrupt_flag
  116. ldr r3, [r2]
  117. cmp r3, #1
  118. beq _reswitch
  119. ldr ip, =rt_interrupt_from_thread @ set rt_interrupt_from_thread
  120. mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1
  121. str r0, [ip]
  122. str r3, [r2]
  123. _reswitch:
  124. ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread
  125. str r1, [r2]
  126. bx lr
  127. #endif /*RT_USING_SMP*/
  128. .global rt_hw_context_switch_exit
  129. rt_hw_context_switch_exit:
  130. #ifdef RT_USING_SMP
  131. #ifdef RT_USING_SIGNALS
  132. mov r0, sp
  133. cps #Mode_IRQ
  134. bl rt_signal_check
  135. cps #Mode_SVC
  136. mov sp, r0
  137. #endif
  138. #endif
  139. #ifdef RT_USING_FPU
  140. /* fpu context */
  141. ldmfd sp!, {r6}
  142. vmsr fpexc, r6
  143. tst r6, #(1<<30)
  144. beq 1f
  145. ldmfd sp!, {r5}
  146. vmsr fpscr, r5
  147. vldmia sp!, {d16-d31}
  148. vldmia sp!, {d0-d15}
  149. 1:
  150. #endif
  151. #ifdef RT_USING_LWP
  152. ldmfd sp, {r13, r14}^ /* usr_sp, usr_lr */
  153. add sp, #8
  154. #endif
  155. ldmfd sp!, {r1}
  156. msr spsr_cxsf, r1 /* original mode */
  157. ldmfd sp!, {r0-r12,lr,pc}^ /* irq return */