drv_smc911x.c 15 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020/12/31 Bernard Add license info
  9. */
  10. #include <board.h>
  11. #include <rtthread.h>
  12. #include <netif/ethernetif.h>
  13. #include <lwipopts.h>
  14. #include <automac.h>
  15. #include "delay.h"
  16. #define MAX_ADDR_LEN 6
  17. #define SMC911X_EMAC_DEVICE(eth) (struct eth_device_smc911x*)(eth)
  18. #include "drv_smc911x.h"
  19. #define DRIVERNAME "EMAC"
  20. struct eth_device_smc911x
  21. {
  22. /* inherit from Ethernet device */
  23. struct eth_device parent;
  24. /* interface address info. */
  25. rt_uint8_t enetaddr[MAX_ADDR_LEN]; /* MAC address */
  26. uint32_t iobase;
  27. uint32_t irqno;
  28. };
  29. static struct eth_device_smc911x _emac;
  30. #if defined (CONFIG_SMC911X_32_BIT)
  31. rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
  32. {
  33. return *(volatile uint32_t *)(dev->iobase + offset);
  34. }
  35. rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
  36. {
  37. *(volatile uint32_t *)(dev->iobase + offset) = val;
  38. }
  39. #elif defined (CONFIG_SMC911X_16_BIT)
  40. rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
  41. {
  42. volatile uint16_t *addr_16 = (uint16_t *)(dev->iobase + offset);
  43. return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
  44. }
  45. rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
  46. {
  47. *(volatile uint16_t *)(dev->iobase + offset) = (uint16_t)val;
  48. *(volatile uint16_t *)(dev->iobase + offset + 2) = (uint16_t)(val >> 16);
  49. }
  50. #else
  51. #error "SMC911X: undefined bus width"
  52. #endif /* CONFIG_SMC911X_16_BIT */
  53. struct chip_id
  54. {
  55. uint16_t id;
  56. char *name;
  57. };
  58. static const struct chip_id chip_ids[] =
  59. {
  60. { LAN9118_ID_89218, "LAN89218" },
  61. { LAN9118_ID_9115, "LAN9115" },
  62. { LAN9118_ID_9116, "LAN9116" },
  63. { LAN9118_ID_9117, "LAN9117" },
  64. { LAN9118_ID_9118, "LAN9118" },
  65. { LAN9210_ID_9211, "LAN9211" },
  66. { LAN9218_ID_9215, "LAN9215" },
  67. { LAN9218_ID_9216, "LAN9216" },
  68. { LAN9218_ID_9217, "LAN9217" },
  69. { LAN9218_ID_9218, "LAN9218" },
  70. { LAN9220_ID_9220, "LAN9220" },
  71. { LAN9220_ID_9221, "LAN9221" },
  72. { 0, RT_NULL },
  73. };
  74. static uint32_t smc911x_get_mac_csr(struct eth_device_smc911x *dev, uint8_t reg)
  75. {
  76. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  77. smc911x_reg_write(dev, LAN9118_MAC_CSR_CMD, LAN9118_MAC_CSR_CMD_BUSY | LAN9118_MAC_CSR_CMD_R | reg);
  78. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  79. return smc911x_reg_read(dev, LAN9118_MAC_CSR_DATA);
  80. }
  81. static void smc911x_set_mac_csr(struct eth_device_smc911x *dev, uint8_t reg, uint32_t data)
  82. {
  83. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  84. smc911x_reg_write(dev, LAN9118_MAC_CSR_DATA, data);
  85. smc911x_reg_write(dev, LAN9118_MAC_CSR_CMD, LAN9118_MAC_CSR_CMD_BUSY | reg);
  86. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  87. }
  88. static int smc911x_detect_chip(struct eth_device_smc911x *dev)
  89. {
  90. unsigned long val, i;
  91. val = smc911x_reg_read(dev, LAN9118_BYTE_TEST);
  92. if (val == 0xffffffff)
  93. {
  94. /* Special case -- no chip present */
  95. return -1;
  96. }
  97. else if (val != 0x87654321)
  98. {
  99. rt_kprintf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
  100. return -1;
  101. }
  102. val = smc911x_reg_read(dev, LAN9118_ID_REV) >> 16;
  103. for (i = 0; chip_ids[i].id != 0; i++)
  104. {
  105. if (chip_ids[i].id == val) break;
  106. }
  107. if (!chip_ids[i].id)
  108. {
  109. rt_kprintf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
  110. return -1;
  111. }
  112. return 0;
  113. }
  114. static void smc911x_reset(struct eth_device_smc911x *dev)
  115. {
  116. int timeout;
  117. /*
  118. * Take out of PM setting first
  119. * Device is already wake up if LAN9118_PMT_CTRL_READY bit is set
  120. */
  121. if ((smc911x_reg_read(dev, LAN9118_PMT_CTRL) & LAN9118_PMT_CTRL_READY) == 0)
  122. {
  123. /* Write to the bytetest will take out of powerdown */
  124. smc911x_reg_write(dev, LAN9118_BYTE_TEST, 0x0);
  125. timeout = 10;
  126. while (timeout-- && !(smc911x_reg_read(dev, LAN9118_PMT_CTRL) & LAN9118_PMT_CTRL_READY))
  127. udelay(10);
  128. if (timeout < 0)
  129. {
  130. rt_kprintf(DRIVERNAME
  131. ": timeout waiting for PM restore\n");
  132. return;
  133. }
  134. }
  135. /* Disable interrupts */
  136. smc911x_reg_write(dev, LAN9118_INT_EN, 0);
  137. smc911x_reg_write(dev, LAN9118_HW_CFG, LAN9118_HW_CFG_SRST);
  138. timeout = 1000;
  139. while (timeout-- && smc911x_reg_read(dev, LAN9118_E2P_CMD) & LAN9118_E2P_CMD)
  140. udelay(10);
  141. if (timeout < 0)
  142. {
  143. rt_kprintf(DRIVERNAME ": reset timeout\n");
  144. return;
  145. }
  146. /* Reset the FIFO level and flow control settings */
  147. smc911x_set_mac_csr(dev, LAN9118_FLOW, LAN9118_FLOW_FCPT(0xffff) | LAN9118_FLOW_FCEN);
  148. smc911x_reg_write(dev, LAN9118_AFC_CFG, 0x0050287F);
  149. /* Set to LED outputs */
  150. smc911x_reg_write(dev, LAN9118_GPIO_CFG, 0x70070000);
  151. }
  152. static void smc911x_handle_mac_address(struct eth_device_smc911x *dev)
  153. {
  154. unsigned long addrh, addrl;
  155. uint8_t *m = dev->enetaddr;
  156. addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
  157. addrh = m[4] | (m[5] << 8);
  158. smc911x_set_mac_csr(dev, LAN9118_ADDRL, addrl);
  159. smc911x_set_mac_csr(dev, LAN9118_ADDRH, addrh);
  160. }
  161. static int smc911x_eth_phy_read(struct eth_device_smc911x *dev,
  162. uint8_t phy, uint8_t reg, uint16_t *val)
  163. {
  164. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY) ;
  165. smc911x_set_mac_csr(dev, LAN9118_MII_ACC, phy << 11 | reg << 6 | LAN9118_MII_ACC_MIIBZY);
  166. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY) ;
  167. *val = smc911x_get_mac_csr(dev, LAN9118_MII_DATA);
  168. return 0;
  169. }
  170. static int smc911x_eth_phy_write(struct eth_device_smc911x *dev,
  171. uint8_t phy, uint8_t reg, uint16_t val)
  172. {
  173. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY)
  174. ;
  175. smc911x_set_mac_csr(dev, LAN9118_MII_DATA, val);
  176. smc911x_set_mac_csr(dev, LAN9118_MII_ACC,
  177. phy << 11 | reg << 6 | LAN9118_MII_ACC_MIIBZY | LAN9118_MII_ACC_MIIWNR);
  178. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY)
  179. ;
  180. return 0;
  181. }
  182. static int smc911x_phy_reset(struct eth_device_smc911x *dev)
  183. {
  184. uint32_t reg;
  185. reg = smc911x_reg_read(dev, LAN9118_PMT_CTRL);
  186. reg &= ~0xfffff030;
  187. reg |= LAN9118_PMT_CTRL_PHY_RST;
  188. smc911x_reg_write(dev, LAN9118_PMT_CTRL, reg);
  189. mdelay(100);
  190. return 0;
  191. }
  192. static void smc911x_phy_configure(struct eth_device_smc911x *dev)
  193. {
  194. int timeout;
  195. uint16_t status;
  196. smc911x_phy_reset(dev);
  197. smc911x_eth_phy_write(dev, 1, LAN9118_MII_BMCR, LAN9118_BMCR_RESET);
  198. mdelay(1);
  199. smc911x_eth_phy_write(dev, 1, LAN9118_MII_ADVERTISE, 0x01e1);
  200. smc911x_eth_phy_write(dev, 1, LAN9118_MII_BMCR, LAN9118_BMCR_ANENABLE | LAN9118_BMCR_ANRESTART);
  201. timeout = 5000;
  202. do
  203. {
  204. mdelay(1);
  205. if ((timeout--) == 0)
  206. goto err_out;
  207. if (smc911x_eth_phy_read(dev, 1, LAN9118_MII_BMSR, &status) != 0)
  208. goto err_out;
  209. }
  210. while (!(status & LAN9118_BMSR_LSTATUS));
  211. return;
  212. err_out:
  213. rt_kprintf(DRIVERNAME ": autonegotiation timed out\n");
  214. }
  215. static void smc911x_enable(struct eth_device_smc911x *dev)
  216. {
  217. /* Enable TX */
  218. smc911x_reg_write(dev, LAN9118_HW_CFG, 8 << 16 | LAN9118_HW_CFG_SF);
  219. smc911x_reg_write(dev, LAN9118_GPT_CFG, LAN9118_GPT_CFG_TIMER_EN | 10000);
  220. smc911x_reg_write(dev, LAN9118_TX_CFG, LAN9118_TX_CFG_TX_ON);
  221. /* no padding to start of packets */
  222. smc911x_reg_write(dev, LAN9118_RX_CFG, 0);
  223. smc911x_set_mac_csr(dev, LAN9118_MAC_CR, LAN9118_MAC_CR_TXEN | LAN9118_MAC_CR_RXEN |
  224. LAN9118_MAC_CR_HBDIS);
  225. }
  226. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  227. /* wrapper for smc911x_eth_phy_read */
  228. static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
  229. int reg)
  230. {
  231. uint16_t val = 0;
  232. struct eth_device_smc911x *dev = eth_get_dev_by_name(bus->name);
  233. if (dev)
  234. {
  235. int retval = smc911x_eth_phy_read(dev, phy, reg, &val);
  236. if (retval < 0)
  237. return retval;
  238. return val;
  239. }
  240. return -ENODEV;
  241. }
  242. /* wrapper for smc911x_eth_phy_write */
  243. static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
  244. int reg, uint16_t val)
  245. {
  246. struct eth_device_smc911x *dev = eth_get_dev_by_name(bus->name);
  247. if (dev)
  248. return smc911x_eth_phy_write(dev, phy, reg, val);
  249. return -ENODEV;
  250. }
  251. #endif
  252. static void smc911x_isr(int vector, void *param)
  253. {
  254. uint32_t status;
  255. struct eth_device_smc911x *emac;
  256. emac = SMC911X_EMAC_DEVICE(param);
  257. status = smc911x_reg_read(emac, LAN9118_INT_STS);
  258. if (status & LAN9118_INT_STS_RSFL)
  259. {
  260. eth_device_ready(&emac->parent);
  261. }
  262. smc911x_reg_write(emac, LAN9118_INT_STS, status);
  263. return ;
  264. }
  265. static rt_err_t smc911x_emac_init(rt_device_t dev)
  266. {
  267. // uint32_t value;
  268. struct eth_device_smc911x *emac;
  269. emac = SMC911X_EMAC_DEVICE(dev);
  270. RT_ASSERT(emac != RT_NULL);
  271. smc911x_reset(emac);
  272. /* Configure the PHY, initialize the link state */
  273. smc911x_phy_configure(emac);
  274. smc911x_handle_mac_address(emac);
  275. /* Turn on Tx + Rx */
  276. smc911x_enable(emac);
  277. #if 1
  278. /* Interrupt on every received packet */
  279. smc911x_reg_write(emac, LAN9118_FIFO_INT, 0x01 << 8);
  280. smc911x_reg_write(emac, LAN9118_INT_EN, LAN9118_INT_EN_RDFL_EN | LAN9118_INT_RSFL);
  281. /* enable interrupt */
  282. smc911x_reg_write(emac, LAN9118_IRQ_CFG, LAN9118_IRQ_CFG_IRQ_EN | LAN9118_IRQ_CFG_IRQ_POL | LAN9118_IRQ_CFG_IRQ_TYPE);
  283. #else
  284. /* disable interrupt */
  285. smc911x_reg_write(emac, LAN9118_INT_EN, 0);
  286. value = smc911x_reg_read(emac, LAN9118_IRQ_CFG);
  287. value &= ~LAN9118_IRQ_CFG_IRQ_EN;
  288. smc911x_reg_write(emac, LAN9118_IRQ_CFG, value);
  289. #endif
  290. rt_hw_interrupt_install(emac->irqno, smc911x_isr, emac, "smc911x");
  291. rt_hw_interrupt_umask(emac->irqno);
  292. return RT_EOK;
  293. }
  294. static rt_err_t smc911x_emac_control(rt_device_t dev, int cmd, void *args)
  295. {
  296. struct eth_device_smc911x *emac;
  297. emac = SMC911X_EMAC_DEVICE(dev);
  298. RT_ASSERT(emac != RT_NULL);
  299. switch (cmd)
  300. {
  301. case NIOCTL_GADDR:
  302. /* get MAC address */
  303. if (args) rt_memcpy(args, emac->enetaddr, 6);
  304. else return -RT_ERROR;
  305. break;
  306. default :
  307. break;
  308. }
  309. return RT_EOK;
  310. }
  311. /* Ethernet device interface */
  312. /* transmit packet. */
  313. static uint8_t tx_buf[2048];
  314. rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf *p)
  315. {
  316. struct eth_device_smc911x *emac;
  317. uint32_t *data;
  318. uint32_t tmplen;
  319. uint32_t status;
  320. uint32_t length;
  321. emac = SMC911X_EMAC_DEVICE(dev);
  322. RT_ASSERT(emac != RT_NULL);
  323. /* copy pbuf to a whole ETH frame */
  324. pbuf_copy_partial(p, tx_buf, p->tot_len, 0);
  325. /* send it out */
  326. data = (uint32_t *)tx_buf;
  327. length = p->tot_len;
  328. smc911x_reg_write(emac, LAN9118_TXDFIFOP, LAN9118_TXC_A_FS | LAN9118_TXC_A_LS | length);
  329. smc911x_reg_write(emac, LAN9118_TXDFIFOP, length);
  330. tmplen = (length + 3) / 4;
  331. while (tmplen--)
  332. {
  333. smc911x_reg_write(emac, LAN9118_TXDFIFOP, *data++);
  334. }
  335. /* wait for transmission */
  336. while (!(LAN9118_TX_FIFO_INF_TXSUSED(smc911x_reg_read(emac, LAN9118_TX_FIFO_INF))));
  337. /* get status. Ignore 'no carrier' error, it has no meaning for
  338. * full duplex operation
  339. */
  340. status = smc911x_reg_read(emac, LAN9118_TXSFIFOP) &
  341. (LAN9118_TXS_LOC | LAN9118_TXS_LCOL | LAN9118_TXS_ECOL |
  342. LAN9118_TXS_ED | LAN9118_TX_STS_UNDERRUN);
  343. if (!status) return 0;
  344. rt_kprintf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
  345. status & LAN9118_TXS_LOC ? "LAN9118_TXS_LOC " : "",
  346. status & LAN9118_TXS_LCOL ? "LAN9118_TXS_LCOL " : "",
  347. status & LAN9118_TXS_ECOL ? "LAN9118_TXS_ECOL " : "",
  348. status & LAN9118_TXS_ED ? "LAN9118_TXS_ED " : "",
  349. status & LAN9118_TX_STS_UNDERRUN ? "LAN9118_TX_STS_UNDERRUN" : "");
  350. return -RT_EIO;
  351. }
  352. /* reception packet. */
  353. struct pbuf *smc911x_emac_rx(rt_device_t dev)
  354. {
  355. struct pbuf *p = RT_NULL;
  356. struct eth_device_smc911x *emac;
  357. emac = SMC911X_EMAC_DEVICE(dev);
  358. RT_ASSERT(emac != RT_NULL);
  359. /* take the emac buffer to the pbuf */
  360. if (LAN9118_RX_FIFO_INF_RXSUSED(smc911x_reg_read(emac, LAN9118_RX_FIFO_INF)))
  361. {
  362. uint32_t status;
  363. uint32_t pktlen, tmplen;
  364. status = smc911x_reg_read(emac, LAN9118_RXSFIFOP);
  365. /* get frame length */
  366. pktlen = (status & LAN9118_RX_STS_PKT_LEN) >> 16;
  367. smc911x_reg_write(emac, LAN9118_RX_CFG, 0);
  368. tmplen = (pktlen + 3) / 4;
  369. /* allocate pbuf */
  370. p = pbuf_alloc(PBUF_RAW, tmplen * 4, PBUF_RAM);
  371. if (p)
  372. {
  373. uint32_t *data = (uint32_t *)p->payload;
  374. while (tmplen--)
  375. {
  376. *data++ = smc911x_reg_read(emac, LAN9118_RXDFIFOP);
  377. }
  378. }
  379. if (status & LAN9118_RXS_ES)
  380. {
  381. rt_kprintf(DRIVERNAME ": dropped bad packet. Status: 0x%08x\n", status);
  382. }
  383. }
  384. return p;
  385. }
  386. #ifdef RT_USING_DEVICE_OPS
  387. const static struct rt_device_ops smc911x_emac_ops =
  388. {
  389. smc911x_emac_init,
  390. RT_NULL,
  391. RT_NULL,
  392. RT_NULL,
  393. RT_NULL,
  394. smc911x_emac_control
  395. };
  396. #endif
  397. int smc911x_emac_hw_init(void)
  398. {
  399. _emac.iobase = VEXPRESS_ETH_BASE;
  400. _emac.irqno = IRQ_VEXPRESS_A9_ETH;
  401. if (smc911x_detect_chip(&_emac))
  402. {
  403. rt_kprintf("no smc911x network interface found!\n");
  404. return -1;
  405. }
  406. /* set INT CFG */
  407. smc911x_reg_write(&_emac, LAN9118_IRQ_CFG, LAN9118_IRQ_CFG_IRQ_POL | LAN9118_IRQ_CFG_IRQ_TYPE);
  408. /* test MAC address */
  409. _emac.enetaddr[0] = AUTOMAC0;
  410. _emac.enetaddr[1] = AUTOMAC1;
  411. _emac.enetaddr[2] = AUTOMAC2;
  412. _emac.enetaddr[3] = AUTOMAC3;
  413. _emac.enetaddr[4] = AUTOMAC4;
  414. _emac.enetaddr[5] = AUTOMAC5;
  415. #ifdef RT_USING_DEVICE_OPS
  416. _emac.parent.parent.ops = &smc911x_emac_ops;
  417. #else
  418. _emac.parent.parent.init = smc911x_emac_init;
  419. _emac.parent.parent.open = RT_NULL;
  420. _emac.parent.parent.close = RT_NULL;
  421. _emac.parent.parent.read = RT_NULL;
  422. _emac.parent.parent.write = RT_NULL;
  423. _emac.parent.parent.control = smc911x_emac_control;
  424. #endif
  425. _emac.parent.parent.user_data = RT_NULL;
  426. _emac.parent.eth_rx = smc911x_emac_rx;
  427. _emac.parent.eth_tx = smc911x_emac_tx;
  428. /* register ETH device */
  429. eth_device_init(&(_emac.parent), "e0");
  430. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  431. {
  432. int retval;
  433. struct mii_dev *mdiodev = mdio_alloc();
  434. if (!mdiodev)
  435. return -ENOMEM;
  436. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  437. mdiodev->read = smc911x_miiphy_read;
  438. mdiodev->write = smc911x_miiphy_write;
  439. retval = mdio_register(mdiodev);
  440. if (retval < 0)
  441. return retval;
  442. }
  443. #endif
  444. eth_device_linkchange(&_emac.parent, RT_TRUE);
  445. return 0;
  446. }
  447. INIT_APP_EXPORT(smc911x_emac_hw_init);