pic.c 28 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292
  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-08-24 GuEe-GUI first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #define DBG_TAG "rtdm.pic"
  13. #define DBG_LVL DBG_INFO
  14. #include <rtdbg.h>
  15. #include <drivers/pic.h>
  16. #include <ktime.h>
  17. struct irq_traps
  18. {
  19. rt_list_t list;
  20. void *data;
  21. rt_bool_t (*handler)(void *);
  22. };
  23. static int _ipi_hash[] =
  24. {
  25. #ifdef RT_USING_SMP
  26. [RT_SCHEDULE_IPI] = RT_SCHEDULE_IPI,
  27. [RT_STOP_IPI] = RT_STOP_IPI,
  28. #endif
  29. };
  30. /* reserved ipi */
  31. static int _pirq_hash_idx = RT_ARRAY_SIZE(_ipi_hash);
  32. static struct rt_pic_irq _pirq_hash[MAX_HANDLERS] =
  33. {
  34. [0 ... MAX_HANDLERS - 1] =
  35. {
  36. .irq = -1,
  37. .hwirq = -1,
  38. .mode = RT_IRQ_MODE_NONE,
  39. .priority = RT_UINT32_MAX,
  40. .rw_lock = { },
  41. }
  42. };
  43. static struct rt_spinlock _pic_lock = { };
  44. static rt_size_t _pic_name_max = sizeof("PIC");
  45. static rt_list_t _pic_nodes = RT_LIST_OBJECT_INIT(_pic_nodes);
  46. static rt_list_t _traps_nodes = RT_LIST_OBJECT_INIT(_traps_nodes);
  47. static struct rt_pic_irq *irq2pirq(int irq)
  48. {
  49. struct rt_pic_irq *pirq = RT_NULL;
  50. if ((irq >= 0) && (irq < MAX_HANDLERS))
  51. {
  52. pirq = &_pirq_hash[irq];
  53. if (pirq->irq < 0)
  54. {
  55. pirq = RT_NULL;
  56. }
  57. }
  58. if (!pirq)
  59. {
  60. LOG_E("irq = %d is invalid", irq);
  61. }
  62. return pirq;
  63. }
  64. static void append_pic(struct rt_pic *pic)
  65. {
  66. int pic_name_len = rt_strlen(pic->ops->name);
  67. rt_list_insert_before(&_pic_nodes, &pic->list);
  68. if (pic_name_len > _pic_name_max)
  69. {
  70. _pic_name_max = pic_name_len;
  71. }
  72. }
  73. void rt_pic_default_name(struct rt_pic *pic)
  74. {
  75. if (pic)
  76. {
  77. #if RT_NAME_MAX > 0
  78. rt_strncpy(pic->parent.name, "PIC", RT_NAME_MAX - 1);
  79. pic->parent.name[RT_NAME_MAX - 1] = '\0';
  80. #else
  81. pic->parent.name = "PIC";
  82. #endif
  83. }
  84. }
  85. struct rt_pic *rt_pic_dynamic_cast(void *ptr)
  86. {
  87. struct rt_pic *pic = RT_NULL, *tmp = RT_NULL;
  88. if (ptr)
  89. {
  90. struct rt_object *obj = ptr;
  91. if (obj->type == RT_Object_Class_Unknown)
  92. {
  93. tmp = (void *)obj;
  94. }
  95. else if (obj->type == RT_Object_Class_Device)
  96. {
  97. tmp = (void *)obj + sizeof(struct rt_device);
  98. }
  99. else
  100. {
  101. tmp = (void *)obj + sizeof(struct rt_object);
  102. }
  103. if (tmp && !rt_strcmp(tmp->parent.name, "PIC"))
  104. {
  105. pic = tmp;
  106. }
  107. }
  108. return pic;
  109. }
  110. rt_err_t rt_pic_linear_irq(struct rt_pic *pic, rt_size_t irq_nr)
  111. {
  112. rt_err_t err = RT_EOK;
  113. if (pic && pic->ops && pic->ops->name)
  114. {
  115. rt_ubase_t level = rt_spin_lock_irqsave(&_pic_lock);
  116. if (_pirq_hash_idx + irq_nr <= RT_ARRAY_SIZE(_pirq_hash))
  117. {
  118. rt_list_init(&pic->list);
  119. rt_pic_default_name(pic);
  120. pic->parent.type = RT_Object_Class_Unknown;
  121. pic->irq_start = _pirq_hash_idx;
  122. pic->irq_nr = irq_nr;
  123. pic->pirqs = &_pirq_hash[_pirq_hash_idx];
  124. _pirq_hash_idx += irq_nr;
  125. append_pic(pic);
  126. LOG_D("%s alloc irqs ranges [%d, %d]", pic->ops->name,
  127. pic->irq_start, pic->irq_start + pic->irq_nr);
  128. }
  129. else
  130. {
  131. LOG_E("%s alloc %d irqs is overflow", pic->ops->name, irq_nr);
  132. err = -RT_EEMPTY;
  133. }
  134. rt_spin_unlock_irqrestore(&_pic_lock, level);
  135. }
  136. else
  137. {
  138. err = -RT_EINVAL;
  139. }
  140. return err;
  141. }
  142. static void config_pirq(struct rt_pic *pic, struct rt_pic_irq *pirq, int irq, int hwirq)
  143. {
  144. rt_ubase_t level = rt_spin_lock_irqsave(&pirq->rw_lock);
  145. if (pirq->irq < 0)
  146. {
  147. rt_list_init(&pirq->list);
  148. rt_list_init(&pirq->children_nodes);
  149. rt_list_init(&pirq->isr.list);
  150. }
  151. else if (pirq->pic != pic)
  152. {
  153. RT_ASSERT(rt_list_isempty(&pirq->list) == RT_TRUE);
  154. RT_ASSERT(rt_list_isempty(&pirq->children_nodes) == RT_TRUE);
  155. RT_ASSERT(rt_list_isempty(&pirq->isr.list) == RT_TRUE);
  156. }
  157. pirq->irq = irq;
  158. pirq->hwirq = hwirq;
  159. pirq->pic = pic;
  160. rt_spin_unlock_irqrestore(&pirq->rw_lock, level);
  161. }
  162. int rt_pic_config_ipi(struct rt_pic *pic, int ipi_index, int hwirq)
  163. {
  164. int ipi = ipi_index;
  165. struct rt_pic_irq *pirq;
  166. if (pic && ipi < RT_ARRAY_SIZE(_ipi_hash) && hwirq >= 0 && pic->ops->irq_send_ipi)
  167. {
  168. pirq = &_pirq_hash[ipi];
  169. config_pirq(pic, pirq, ipi, hwirq);
  170. for (int cpuid = 0; cpuid < RT_CPUS_NR; ++cpuid)
  171. {
  172. RT_IRQ_AFFINITY_SET(pirq->affinity, cpuid);
  173. }
  174. LOG_D("%s config %s %d to hwirq %d", pic->ops->name, "ipi", ipi, hwirq);
  175. }
  176. else
  177. {
  178. ipi = -RT_EINVAL;
  179. }
  180. return ipi;
  181. }
  182. int rt_pic_config_irq(struct rt_pic *pic, int irq_index, int hwirq)
  183. {
  184. int irq;
  185. if (pic && hwirq >= 0)
  186. {
  187. irq = pic->irq_start + irq_index;
  188. if (irq >= 0 && irq < MAX_HANDLERS)
  189. {
  190. config_pirq(pic, &_pirq_hash[irq], irq, hwirq);
  191. LOG_D("%s config %s %d to hwirq %d", pic->ops->name, "irq", irq, hwirq);
  192. }
  193. else
  194. {
  195. irq = -RT_ERROR;
  196. }
  197. }
  198. else
  199. {
  200. irq = -RT_EINVAL;
  201. }
  202. return irq;
  203. }
  204. struct rt_pic_irq *rt_pic_find_ipi(struct rt_pic *pic, int ipi_index)
  205. {
  206. struct rt_pic_irq *pirq = &_pirq_hash[ipi_index];
  207. RT_ASSERT(ipi_index < RT_ARRAY_SIZE(_ipi_hash));
  208. RT_ASSERT(pirq->pic == pic);
  209. return pirq;
  210. }
  211. struct rt_pic_irq *rt_pic_find_pirq(struct rt_pic *pic, int irq)
  212. {
  213. if (pic && irq >= pic->irq_start && irq <= pic->irq_start + pic->irq_nr)
  214. {
  215. return &pic->pirqs[irq - pic->irq_start];
  216. }
  217. return RT_NULL;
  218. }
  219. rt_err_t rt_pic_cascade(struct rt_pic_irq *pirq, int parent_irq)
  220. {
  221. rt_err_t err = RT_EOK;
  222. if (pirq && !pirq->parent && parent_irq >= 0)
  223. {
  224. struct rt_pic_irq *parent;
  225. rt_spin_lock(&pirq->rw_lock);
  226. parent = irq2pirq(parent_irq);
  227. if (parent)
  228. {
  229. pirq->parent = parent;
  230. pirq->priority = parent->priority;
  231. rt_memcpy(&pirq->affinity, &parent->affinity, sizeof(pirq->affinity));
  232. }
  233. rt_spin_unlock(&pirq->rw_lock);
  234. if (parent && pirq->pic->ops->flags & RT_PIC_F_IRQ_ROUTING)
  235. {
  236. rt_spin_lock(&parent->rw_lock);
  237. rt_list_insert_before(&parent->children_nodes, &pirq->list);
  238. rt_spin_unlock(&parent->rw_lock);
  239. }
  240. }
  241. else
  242. {
  243. err = -RT_EINVAL;
  244. }
  245. return err;
  246. }
  247. rt_err_t rt_pic_uncascade(struct rt_pic_irq *pirq)
  248. {
  249. rt_err_t err = RT_EOK;
  250. if (pirq && pirq->parent)
  251. {
  252. struct rt_pic_irq *parent;
  253. rt_spin_lock(&pirq->rw_lock);
  254. parent = pirq->parent;
  255. pirq->parent = RT_NULL;
  256. rt_spin_unlock(&pirq->rw_lock);
  257. if (parent && pirq->pic->ops->flags & RT_PIC_F_IRQ_ROUTING)
  258. {
  259. rt_spin_lock(&parent->rw_lock);
  260. rt_list_remove(&pirq->list);
  261. rt_spin_unlock(&parent->rw_lock);
  262. }
  263. }
  264. else
  265. {
  266. err = -RT_EINVAL;
  267. }
  268. return err;
  269. }
  270. rt_err_t rt_pic_attach_irq(int irq, rt_isr_handler_t handler, void *uid, const char *name, int flags)
  271. {
  272. rt_err_t err = -RT_EINVAL;
  273. struct rt_pic_irq *pirq;
  274. if (handler && name && (pirq = irq2pirq(irq)))
  275. {
  276. struct rt_pic_isr *isr = RT_NULL;
  277. rt_ubase_t level = rt_spin_lock_irqsave(&pirq->rw_lock);
  278. err = RT_EOK;
  279. if (!pirq->isr.action.handler)
  280. {
  281. /* first attach */
  282. isr = &pirq->isr;
  283. rt_list_init(&isr->list);
  284. }
  285. else
  286. {
  287. rt_spin_unlock_irqrestore(&pirq->rw_lock, level);
  288. if ((isr = rt_malloc(sizeof(*isr))))
  289. {
  290. rt_list_init(&isr->list);
  291. level = rt_spin_lock_irqsave(&pirq->rw_lock);
  292. rt_list_insert_after(&pirq->isr.list, &isr->list);
  293. }
  294. else
  295. {
  296. LOG_E("No memory to save '%s' isr", name);
  297. err = -RT_ERROR;
  298. }
  299. }
  300. if (!err)
  301. {
  302. isr->flags = flags;
  303. isr->action.handler = handler;
  304. isr->action.param = uid;
  305. #ifdef RT_USING_INTERRUPT_INFO
  306. isr->action.counter = 0;
  307. rt_strncpy(isr->action.name, name, RT_NAME_MAX - 1);
  308. isr->action.name[RT_NAME_MAX - 1] = '\0';
  309. #ifdef RT_USING_SMP
  310. rt_memset(isr->action.cpu_counter, 0, sizeof(isr->action.cpu_counter));
  311. #endif
  312. #endif
  313. rt_spin_unlock_irqrestore(&pirq->rw_lock, level);
  314. }
  315. }
  316. return err;
  317. }
  318. rt_err_t rt_pic_detach_irq(int irq, void *uid)
  319. {
  320. rt_err_t err = -RT_EINVAL;
  321. struct rt_pic_irq *pirq = irq2pirq(irq);
  322. if (pirq)
  323. {
  324. rt_bool_t will_free = RT_FALSE;
  325. struct rt_pic_isr *isr = RT_NULL;
  326. rt_ubase_t level = rt_spin_lock_irqsave(&pirq->rw_lock);
  327. isr = &pirq->isr;
  328. if (isr->action.param == uid)
  329. {
  330. if (rt_list_isempty(&isr->list))
  331. {
  332. isr->action.handler = RT_NULL;
  333. isr->action.param = RT_NULL;
  334. }
  335. else
  336. {
  337. struct rt_pic_isr *next_isr = rt_list_first_entry(&isr->list, struct rt_pic_isr, list);
  338. rt_list_remove(&next_isr->list);
  339. isr->action.handler = next_isr->action.handler;
  340. isr->action.param = next_isr->action.param;
  341. #ifdef RT_USING_INTERRUPT_INFO
  342. isr->action.counter = next_isr->action.counter;
  343. rt_strncpy(isr->action.name, next_isr->action.name, RT_NAME_MAX);
  344. #ifdef RT_USING_SMP
  345. rt_memcpy(isr->action.cpu_counter, next_isr->action.cpu_counter, sizeof(next_isr->action.cpu_counter));
  346. #endif
  347. #endif
  348. isr = next_isr;
  349. will_free = RT_TRUE;
  350. }
  351. err = RT_EOK;
  352. }
  353. else
  354. {
  355. rt_list_for_each_entry(isr, &pirq->isr.list, list)
  356. {
  357. if (isr->action.param == uid)
  358. {
  359. err = RT_EOK;
  360. will_free = RT_TRUE;
  361. rt_list_remove(&isr->list);
  362. break;
  363. }
  364. }
  365. }
  366. rt_spin_unlock_irqrestore(&pirq->rw_lock, level);
  367. if (will_free)
  368. {
  369. rt_free(isr);
  370. }
  371. }
  372. return err;
  373. }
  374. rt_err_t rt_pic_add_traps(rt_bool_t (*handler)(void *), void *data)
  375. {
  376. rt_err_t err = -RT_EINVAL;
  377. if (handler)
  378. {
  379. struct irq_traps *traps = rt_malloc(sizeof(*traps));
  380. if (traps)
  381. {
  382. rt_ubase_t level = rt_hw_interrupt_disable();
  383. rt_list_init(&traps->list);
  384. traps->data = data;
  385. traps->handler = handler;
  386. rt_list_insert_before(&_traps_nodes, &traps->list);
  387. err = RT_EOK;
  388. rt_hw_interrupt_enable(level);
  389. }
  390. else
  391. {
  392. LOG_E("No memory to save '%p' handler", handler);
  393. err = -RT_ENOMEM;
  394. }
  395. }
  396. return err;
  397. }
  398. rt_err_t rt_pic_do_traps(void)
  399. {
  400. rt_err_t err = -RT_ERROR;
  401. struct irq_traps *traps;
  402. rt_interrupt_enter();
  403. rt_list_for_each_entry(traps, &_traps_nodes, list)
  404. {
  405. if (traps->handler(traps->data))
  406. {
  407. err = RT_EOK;
  408. break;
  409. }
  410. }
  411. rt_interrupt_leave();
  412. return err;
  413. }
  414. rt_err_t rt_pic_handle_isr(struct rt_pic_irq *pirq)
  415. {
  416. rt_err_t err = -RT_EEMPTY;
  417. rt_list_t *handler_nodes;
  418. struct rt_irq_desc *action;
  419. #ifdef RT_USING_PIC_STATISTICS
  420. struct timespec ts;
  421. rt_ubase_t irq_time_ns;
  422. rt_ubase_t current_irq_begin;
  423. #endif
  424. RT_ASSERT(pirq != RT_NULL);
  425. RT_ASSERT(pirq->pic != RT_NULL);
  426. #ifdef RT_USING_PIC_STATISTICS
  427. rt_ktime_boottime_get_ns(&ts);
  428. current_irq_begin = ts.tv_sec * (1000UL * 1000 * 1000) + ts.tv_nsec;
  429. #endif
  430. handler_nodes = &pirq->isr.list;
  431. action = &pirq->isr.action;
  432. if (!rt_list_isempty(&pirq->children_nodes))
  433. {
  434. struct rt_pic_irq *child;
  435. rt_list_for_each_entry(child, &pirq->children_nodes, list)
  436. {
  437. if (child->pic->ops->irq_ack)
  438. {
  439. child->pic->ops->irq_ack(child);
  440. }
  441. err = rt_pic_handle_isr(child);
  442. if (child->pic->ops->irq_eoi)
  443. {
  444. child->pic->ops->irq_eoi(child);
  445. }
  446. }
  447. }
  448. if (action->handler)
  449. {
  450. action->handler(pirq->irq, action->param);
  451. #ifdef RT_USING_INTERRUPT_INFO
  452. action->counter++;
  453. #ifdef RT_USING_SMP
  454. action->cpu_counter[rt_hw_cpu_id()]++;
  455. #endif
  456. #endif
  457. if (!rt_list_isempty(handler_nodes))
  458. {
  459. struct rt_pic_isr *isr;
  460. rt_list_for_each_entry(isr, handler_nodes, list)
  461. {
  462. action = &isr->action;
  463. RT_ASSERT(action->handler != RT_NULL);
  464. action->handler(pirq->irq, action->param);
  465. #ifdef RT_USING_INTERRUPT_INFO
  466. action->counter++;
  467. #ifdef RT_USING_SMP
  468. action->cpu_counter[rt_hw_cpu_id()]++;
  469. #endif
  470. #endif
  471. }
  472. }
  473. err = RT_EOK;
  474. }
  475. #ifdef RT_USING_PIC_STATISTICS
  476. rt_ktime_boottime_get_ns(&ts);
  477. irq_time_ns = ts.tv_sec * (1000UL * 1000 * 1000) + ts.tv_nsec - current_irq_begin;
  478. pirq->stat.sum_irq_time_ns += irq_time_ns;
  479. if (irq_time_ns < pirq->stat.min_irq_time_ns || pirq->stat.min_irq_time_ns == 0)
  480. {
  481. pirq->stat.min_irq_time_ns = irq_time_ns;
  482. }
  483. if (irq_time_ns > pirq->stat.max_irq_time_ns)
  484. {
  485. pirq->stat.max_irq_time_ns = irq_time_ns;
  486. }
  487. #endif
  488. return err;
  489. }
  490. rt_weak rt_err_t rt_pic_user_extends(struct rt_pic *pic)
  491. {
  492. return -RT_ENOSYS;
  493. }
  494. rt_err_t rt_pic_irq_init(void)
  495. {
  496. rt_err_t err = RT_EOK;
  497. struct rt_pic *pic;
  498. rt_list_for_each_entry(pic, &_pic_nodes, list)
  499. {
  500. if (pic->ops->irq_init)
  501. {
  502. err = pic->ops->irq_init(pic);
  503. if (err)
  504. {
  505. LOG_E("PIC = %s init fail", pic->ops->name);
  506. break;
  507. }
  508. }
  509. }
  510. return err;
  511. }
  512. rt_err_t rt_pic_irq_finit(void)
  513. {
  514. rt_err_t err = RT_EOK;
  515. struct rt_pic *pic;
  516. rt_list_for_each_entry(pic, &_pic_nodes, list)
  517. {
  518. if (pic->ops->irq_finit)
  519. {
  520. err = pic->ops->irq_finit(pic);
  521. if (err)
  522. {
  523. LOG_E("PIC = %s finit fail", pic->ops->name);
  524. break;
  525. }
  526. }
  527. }
  528. return err;
  529. }
  530. void rt_pic_irq_enable(int irq)
  531. {
  532. struct rt_pic_irq *pirq = irq2pirq(irq);
  533. RT_ASSERT(pirq != RT_NULL);
  534. rt_hw_spin_lock(&pirq->rw_lock.lock);
  535. if (pirq->pic->ops->irq_enable)
  536. {
  537. pirq->pic->ops->irq_enable(pirq);
  538. }
  539. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  540. }
  541. void rt_pic_irq_disable(int irq)
  542. {
  543. struct rt_pic_irq *pirq = irq2pirq(irq);
  544. RT_ASSERT(pirq != RT_NULL);
  545. rt_hw_spin_lock(&pirq->rw_lock.lock);
  546. if (pirq->pic->ops->irq_disable)
  547. {
  548. pirq->pic->ops->irq_disable(pirq);
  549. }
  550. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  551. }
  552. void rt_pic_irq_ack(int irq)
  553. {
  554. struct rt_pic_irq *pirq = irq2pirq(irq);
  555. RT_ASSERT(pirq != RT_NULL);
  556. rt_hw_spin_lock(&pirq->rw_lock.lock);
  557. if (pirq->pic->ops->irq_ack)
  558. {
  559. pirq->pic->ops->irq_ack(pirq);
  560. }
  561. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  562. }
  563. void rt_pic_irq_mask(int irq)
  564. {
  565. struct rt_pic_irq *pirq = irq2pirq(irq);
  566. RT_ASSERT(pirq != RT_NULL);
  567. rt_hw_spin_lock(&pirq->rw_lock.lock);
  568. if (pirq->pic->ops->irq_mask)
  569. {
  570. pirq->pic->ops->irq_mask(pirq);
  571. }
  572. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  573. }
  574. void rt_pic_irq_unmask(int irq)
  575. {
  576. struct rt_pic_irq *pirq = irq2pirq(irq);
  577. RT_ASSERT(pirq != RT_NULL);
  578. rt_hw_spin_lock(&pirq->rw_lock.lock);
  579. if (pirq->pic->ops->irq_unmask)
  580. {
  581. pirq->pic->ops->irq_unmask(pirq);
  582. }
  583. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  584. }
  585. void rt_pic_irq_eoi(int irq)
  586. {
  587. struct rt_pic_irq *pirq = irq2pirq(irq);
  588. RT_ASSERT(pirq != RT_NULL);
  589. rt_hw_spin_lock(&pirq->rw_lock.lock);
  590. if (pirq->pic->ops->irq_eoi)
  591. {
  592. pirq->pic->ops->irq_eoi(pirq);
  593. }
  594. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  595. }
  596. rt_err_t rt_pic_irq_set_priority(int irq, rt_uint32_t priority)
  597. {
  598. rt_err_t err = -RT_EINVAL;
  599. struct rt_pic_irq *pirq = irq2pirq(irq);
  600. if (pirq)
  601. {
  602. rt_hw_spin_lock(&pirq->rw_lock.lock);
  603. if (pirq->pic->ops->irq_set_priority)
  604. {
  605. err = pirq->pic->ops->irq_set_priority(pirq, priority);
  606. if (!err)
  607. {
  608. pirq->priority = priority;
  609. }
  610. }
  611. else
  612. {
  613. err = -RT_ENOSYS;
  614. }
  615. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  616. }
  617. return err;
  618. }
  619. rt_uint32_t rt_pic_irq_get_priority(int irq)
  620. {
  621. rt_uint32_t priority = RT_UINT32_MAX;
  622. struct rt_pic_irq *pirq = irq2pirq(irq);
  623. if (pirq)
  624. {
  625. rt_hw_spin_lock(&pirq->rw_lock.lock);
  626. priority = pirq->priority;
  627. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  628. }
  629. return priority;
  630. }
  631. rt_err_t rt_pic_irq_set_affinity(int irq, rt_bitmap_t *affinity)
  632. {
  633. rt_err_t err = -RT_EINVAL;
  634. struct rt_pic_irq *pirq;
  635. if (affinity && (pirq = irq2pirq(irq)))
  636. {
  637. rt_hw_spin_lock(&pirq->rw_lock.lock);
  638. if (pirq->pic->ops->irq_set_affinity)
  639. {
  640. err = pirq->pic->ops->irq_set_affinity(pirq, affinity);
  641. if (!err)
  642. {
  643. rt_memcpy(pirq->affinity, affinity, sizeof(pirq->affinity));
  644. }
  645. }
  646. else
  647. {
  648. err = -RT_ENOSYS;
  649. }
  650. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  651. }
  652. return err;
  653. }
  654. rt_err_t rt_pic_irq_get_affinity(int irq, rt_bitmap_t *out_affinity)
  655. {
  656. rt_err_t err = -RT_EINVAL;
  657. struct rt_pic_irq *pirq;
  658. if (out_affinity && (pirq = irq2pirq(irq)))
  659. {
  660. rt_hw_spin_lock(&pirq->rw_lock.lock);
  661. rt_memcpy(out_affinity, pirq->affinity, sizeof(pirq->affinity));
  662. err = RT_EOK;
  663. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  664. }
  665. return err;
  666. }
  667. rt_err_t rt_pic_irq_set_triger_mode(int irq, rt_uint32_t mode)
  668. {
  669. rt_err_t err = -RT_EINVAL;
  670. struct rt_pic_irq *pirq;
  671. if ((~mode & RT_IRQ_MODE_MASK) && (pirq = irq2pirq(irq)))
  672. {
  673. rt_hw_spin_lock(&pirq->rw_lock.lock);
  674. if (pirq->pic->ops->irq_set_triger_mode)
  675. {
  676. err = pirq->pic->ops->irq_set_triger_mode(pirq, mode);
  677. if (!err)
  678. {
  679. pirq->mode = mode;
  680. }
  681. }
  682. else
  683. {
  684. err = -RT_ENOSYS;
  685. }
  686. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  687. }
  688. return err;
  689. }
  690. rt_uint32_t rt_pic_irq_get_triger_mode(int irq)
  691. {
  692. rt_uint32_t mode = RT_UINT32_MAX;
  693. struct rt_pic_irq *pirq = irq2pirq(irq);
  694. if (pirq)
  695. {
  696. rt_hw_spin_lock(&pirq->rw_lock.lock);
  697. mode = pirq->mode;
  698. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  699. }
  700. return mode;
  701. }
  702. void rt_pic_irq_send_ipi(int irq, rt_bitmap_t *cpumask)
  703. {
  704. struct rt_pic_irq *pirq;
  705. if (cpumask && (pirq = irq2pirq(irq)))
  706. {
  707. rt_hw_spin_lock(&pirq->rw_lock.lock);
  708. if (pirq->pic->ops->irq_send_ipi)
  709. {
  710. pirq->pic->ops->irq_send_ipi(pirq, cpumask);
  711. }
  712. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  713. }
  714. }
  715. rt_err_t rt_pic_irq_set_state_raw(struct rt_pic *pic, int hwirq, int type, rt_bool_t state)
  716. {
  717. rt_err_t err;
  718. if (pic && hwirq >= 0)
  719. {
  720. if (pic->ops->irq_set_state)
  721. {
  722. err = pic->ops->irq_set_state(pic, hwirq, type, state);
  723. }
  724. else
  725. {
  726. err = -RT_ENOSYS;
  727. }
  728. }
  729. else
  730. {
  731. err = -RT_EINVAL;
  732. }
  733. return err;
  734. }
  735. rt_err_t rt_pic_irq_get_state_raw(struct rt_pic *pic, int hwirq, int type, rt_bool_t *out_state)
  736. {
  737. rt_err_t err;
  738. if (pic && hwirq >= 0)
  739. {
  740. if (pic->ops->irq_get_state)
  741. {
  742. rt_bool_t state;
  743. if (!(err = pic->ops->irq_get_state(pic, hwirq, type, &state)) && out_state)
  744. {
  745. *out_state = state;
  746. }
  747. }
  748. else
  749. {
  750. err = -RT_ENOSYS;
  751. }
  752. }
  753. else
  754. {
  755. err = -RT_EINVAL;
  756. }
  757. return err;
  758. }
  759. rt_err_t rt_pic_irq_set_state(int irq, int type, rt_bool_t state)
  760. {
  761. rt_err_t err;
  762. struct rt_pic_irq *pirq = irq2pirq(irq);
  763. RT_ASSERT(pirq != RT_NULL);
  764. rt_hw_spin_lock(&pirq->rw_lock.lock);
  765. err = rt_pic_irq_set_state_raw(pirq->pic, pirq->hwirq, type, state);
  766. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  767. return err;
  768. }
  769. rt_err_t rt_pic_irq_get_state(int irq, int type, rt_bool_t *out_state)
  770. {
  771. rt_err_t err;
  772. struct rt_pic_irq *pirq = irq2pirq(irq);
  773. RT_ASSERT(pirq != RT_NULL);
  774. rt_hw_spin_lock(&pirq->rw_lock.lock);
  775. err = rt_pic_irq_get_state_raw(pirq->pic, pirq->hwirq, type, out_state);
  776. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  777. return err;
  778. }
  779. void rt_pic_irq_parent_enable(struct rt_pic_irq *pirq)
  780. {
  781. RT_ASSERT(pirq != RT_NULL);
  782. pirq = pirq->parent;
  783. if (pirq->pic->ops->irq_enable)
  784. {
  785. pirq->pic->ops->irq_enable(pirq);
  786. }
  787. }
  788. void rt_pic_irq_parent_disable(struct rt_pic_irq *pirq)
  789. {
  790. RT_ASSERT(pirq != RT_NULL);
  791. pirq = pirq->parent;
  792. if (pirq->pic->ops->irq_disable)
  793. {
  794. pirq->pic->ops->irq_disable(pirq);
  795. }
  796. }
  797. void rt_pic_irq_parent_ack(struct rt_pic_irq *pirq)
  798. {
  799. RT_ASSERT(pirq != RT_NULL);
  800. pirq = pirq->parent;
  801. if (pirq->pic->ops->irq_ack)
  802. {
  803. pirq->pic->ops->irq_ack(pirq);
  804. }
  805. }
  806. void rt_pic_irq_parent_mask(struct rt_pic_irq *pirq)
  807. {
  808. RT_ASSERT(pirq != RT_NULL);
  809. pirq = pirq->parent;
  810. if (pirq->pic->ops->irq_mask)
  811. {
  812. pirq->pic->ops->irq_mask(pirq);
  813. }
  814. }
  815. void rt_pic_irq_parent_unmask(struct rt_pic_irq *pirq)
  816. {
  817. RT_ASSERT(pirq != RT_NULL);
  818. pirq = pirq->parent;
  819. if (pirq->pic->ops->irq_unmask)
  820. {
  821. pirq->pic->ops->irq_unmask(pirq);
  822. }
  823. }
  824. void rt_pic_irq_parent_eoi(struct rt_pic_irq *pirq)
  825. {
  826. RT_ASSERT(pirq != RT_NULL);
  827. pirq = pirq->parent;
  828. if (pirq->pic->ops->irq_eoi)
  829. {
  830. pirq->pic->ops->irq_eoi(pirq);
  831. }
  832. }
  833. rt_err_t rt_pic_irq_parent_set_priority(struct rt_pic_irq *pirq, rt_uint32_t priority)
  834. {
  835. rt_err_t err = -RT_ENOSYS;
  836. RT_ASSERT(pirq != RT_NULL);
  837. pirq = pirq->parent;
  838. if (pirq->pic->ops->irq_set_priority)
  839. {
  840. if (!(err = pirq->pic->ops->irq_set_priority(pirq, priority)))
  841. {
  842. pirq->priority = priority;
  843. }
  844. }
  845. return err;
  846. }
  847. rt_err_t rt_pic_irq_parent_set_affinity(struct rt_pic_irq *pirq, rt_bitmap_t *affinity)
  848. {
  849. rt_err_t err = -RT_ENOSYS;
  850. RT_ASSERT(pirq != RT_NULL);
  851. pirq = pirq->parent;
  852. if (pirq->pic->ops->irq_set_affinity)
  853. {
  854. if (!(err = pirq->pic->ops->irq_set_affinity(pirq, affinity)))
  855. {
  856. rt_memcpy(pirq->affinity, affinity, sizeof(pirq->affinity));
  857. }
  858. }
  859. return err;
  860. }
  861. rt_err_t rt_pic_irq_parent_set_triger_mode(struct rt_pic_irq *pirq, rt_uint32_t mode)
  862. {
  863. rt_err_t err = -RT_ENOSYS;
  864. RT_ASSERT(pirq != RT_NULL);
  865. pirq = pirq->parent;
  866. if (pirq->pic->ops->irq_set_triger_mode)
  867. {
  868. if (!(err = pirq->pic->ops->irq_set_triger_mode(pirq, mode)))
  869. {
  870. pirq->mode = mode;
  871. }
  872. }
  873. return err;
  874. }
  875. #ifdef RT_USING_OFW
  876. RT_OFW_STUB_RANGE_EXPORT(pic, _pic_ofw_start, _pic_ofw_end);
  877. static rt_err_t ofw_pic_init(void)
  878. {
  879. struct rt_ofw_node *ic_np;
  880. rt_ofw_foreach_node_by_prop(ic_np, "interrupt-controller")
  881. {
  882. rt_ofw_stub_probe_range(ic_np, &_pic_ofw_start, &_pic_ofw_end);
  883. }
  884. return RT_EOK;
  885. }
  886. #else
  887. static rt_err_t ofw_pic_init(void)
  888. {
  889. return RT_EOK;
  890. }
  891. #endif /* !RT_USING_OFW */
  892. rt_err_t rt_pic_init(void)
  893. {
  894. rt_err_t err;
  895. LOG_D("init start");
  896. err = ofw_pic_init();
  897. LOG_D("init end");
  898. return err;
  899. }
  900. #if defined(RT_USING_CONSOLE) && defined(RT_USING_MSH)
  901. static int list_irq(int argc, char**argv)
  902. {
  903. rt_size_t irq_nr = 0;
  904. rt_bool_t dump_all = RT_FALSE;
  905. const char *const irq_modes[] =
  906. {
  907. [RT_IRQ_MODE_NONE] = "None",
  908. [RT_IRQ_MODE_EDGE_RISING] = "Edge-Rising",
  909. [RT_IRQ_MODE_EDGE_FALLING] = "Edge-Falling",
  910. [RT_IRQ_MODE_EDGE_BOTH] = "Edge-Both",
  911. [RT_IRQ_MODE_LEVEL_HIGH] = "Level-High",
  912. [RT_IRQ_MODE_LEVEL_LOW] = "Level-Low",
  913. };
  914. static char info[RT_CONSOLEBUF_SIZE];
  915. #ifdef RT_USING_SMP
  916. static char cpumask[RT_CPUS_NR + 1] = { [RT_CPUS_NR] = '\0' };
  917. #endif
  918. if (argc > 1)
  919. {
  920. if (!rt_strcmp(argv[1], "all"))
  921. {
  922. dump_all = RT_TRUE;
  923. }
  924. }
  925. rt_kprintf("%-*.s %-*.s %s %-*.s %-*.s %-*.s %-*.sUsers%-*.s",
  926. 6, "IRQ",
  927. 6, "HW-IRQ",
  928. "MSI",
  929. _pic_name_max, "PIC",
  930. 12, "Mode",
  931. #ifdef RT_USING_SMP
  932. RT_CPUS_NR, "CPUs",
  933. #else
  934. 0, 0,
  935. #endif
  936. #ifdef RT_USING_INTERRUPT_INFO
  937. 11, "Count",
  938. 5, ""
  939. #else
  940. 0, 0,
  941. 10, "-Number"
  942. #endif
  943. );
  944. #if defined(RT_USING_SMP) && defined(RT_USING_INTERRUPT_INFO)
  945. for (int i = 0; i < RT_CPUS_NR; i++)
  946. {
  947. rt_kprintf(" cpu%2d ", i);
  948. }
  949. #endif
  950. #ifdef RT_USING_PIC_STATISTICS
  951. rt_kprintf(" max/ns avg/ns min/ns");
  952. #endif
  953. rt_kputs("\n");
  954. for (int i = 0; i < RT_ARRAY_SIZE(_pirq_hash); ++i)
  955. {
  956. struct rt_pic_irq *pirq = &_pirq_hash[i];
  957. if (!pirq->pic || !(dump_all || pirq->isr.action.handler))
  958. {
  959. continue;
  960. }
  961. rt_snprintf(info, sizeof(info), "%-6d %-6d %c %-*.s %-*.s ",
  962. pirq->irq,
  963. pirq->hwirq,
  964. pirq->msi_desc ? 'Y' : 'N',
  965. _pic_name_max, pirq->pic->ops->name,
  966. 12, irq_modes[pirq->mode]);
  967. #ifdef RT_USING_SMP
  968. for (int group = 0, id = 0; group < RT_ARRAY_SIZE(pirq->affinity); ++group)
  969. {
  970. rt_bitmap_t mask = pirq->affinity[group];
  971. for (int idx = 0; id < RT_CPUS_NR && idx < RT_BITMAP_BIT_LEN(1); ++idx, ++id)
  972. {
  973. cpumask[RT_ARRAY_SIZE(cpumask) - id - 2] = '0' + ((mask >> idx) & 1);
  974. }
  975. }
  976. #endif /* RT_USING_SMP */
  977. rt_kputs(info);
  978. #ifdef RT_USING_SMP
  979. rt_kputs(cpumask);
  980. #endif
  981. #ifdef RT_USING_INTERRUPT_INFO
  982. rt_kprintf(" %-10d ", pirq->isr.action.counter);
  983. rt_kprintf("%-*.s", 10, pirq->isr.action.name);
  984. #ifdef RT_USING_SMP
  985. for (int cpuid = 0; cpuid < RT_CPUS_NR; cpuid++)
  986. {
  987. rt_kprintf(" %-10d", pirq->isr.action.cpu_counter[cpuid]);
  988. }
  989. #endif
  990. #ifdef RT_USING_PIC_STATISTICS
  991. rt_kprintf(" %-10d %-10d %-10d", pirq->stat.max_irq_time_ns, pirq->stat.sum_irq_time_ns/pirq->isr.action.counter, pirq->stat.min_irq_time_ns);
  992. #endif
  993. rt_kputs("\n");
  994. if (!rt_list_isempty(&pirq->isr.list))
  995. {
  996. struct rt_pic_isr *repeat_isr;
  997. rt_list_for_each_entry(repeat_isr, &pirq->isr.list, list)
  998. {
  999. rt_kputs(info);
  1000. #ifdef RT_USING_SMP
  1001. rt_kputs(cpumask);
  1002. #endif
  1003. rt_kprintf("%-10d ", repeat_isr->action.counter);
  1004. rt_kprintf("%-*.s", 10, repeat_isr->action.name);
  1005. #ifdef RT_USING_SMP
  1006. for (int cpuid = 0; cpuid < RT_CPUS_NR; cpuid++)
  1007. {
  1008. rt_kprintf(" %-10d", repeat_isr->action.cpu_counter[cpuid]);
  1009. }
  1010. #endif
  1011. #ifdef RT_USING_PIC_STATISTICS
  1012. rt_kprintf(" --- --- ---");
  1013. #endif
  1014. rt_kputs("\n");
  1015. }
  1016. }
  1017. #else
  1018. rt_kprintf(" %d\n", rt_list_len(&pirq->isr.list));
  1019. #endif
  1020. ++irq_nr;
  1021. }
  1022. rt_kprintf("%d IRQs found\n", irq_nr);
  1023. return 0;
  1024. }
  1025. MSH_CMD_EXPORT(list_irq, dump using or args = all of irq information);
  1026. #endif /* RT_USING_CONSOLE && RT_USING_MSH */