drv_sdio.c 16 KB

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  1. /*
  2. * Copyright (c) 2020-2021, Bluetrum Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-11-30 greedyhao first version
  9. */
  10. #include "drv_sdio.h"
  11. #include "interrupt.h"
  12. #include <rthw.h>
  13. #ifdef BSP_USING_SDIO
  14. // #define DRV_DEBUG
  15. #define LOG_TAG "drv.sdio"
  16. #include <drv_log.h>
  17. #define SDIO_USING_1_BIT
  18. static struct ab32_sdio_config sdio_config[] =
  19. {
  20. {.instance = SDMMC0_BASE,
  21. },
  22. };
  23. static struct rt_mmcsd_host *host = RT_NULL;
  24. #define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&(_sdio)->mutex, RT_WAITING_FOREVER)
  25. #define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&(_sdio)->mutex);
  26. struct sdio_pkg
  27. {
  28. struct rt_mmcsd_cmd *cmd;
  29. void *buff;
  30. rt_uint32_t flag;
  31. rt_uint32_t xfer_blks;
  32. };
  33. struct rthw_sdio
  34. {
  35. struct rt_mmcsd_host *host;
  36. struct ab32_sdio_des sdio_des;
  37. struct rt_event event;
  38. struct rt_mutex mutex;
  39. struct sdio_pkg *pkg;
  40. };
  41. rt_align(SDIO_ALIGN_LEN)
  42. static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
  43. static rt_uint8_t sd_baud = 119;
  44. rt_uint8_t sysclk_update_baud(rt_uint8_t baud);
  45. static rt_uint32_t ab32_sdio_clk_get(hal_sfr_t hw_sdio)
  46. {
  47. return (get_sysclk_nhz() / (sd_baud+1));
  48. }
  49. /**
  50. * @brief This function get order from sdio.
  51. * @param data
  52. * @retval sdio order
  53. */
  54. static int get_order(rt_uint32_t data)
  55. {
  56. int order = 0;
  57. switch (data)
  58. {
  59. case 1:
  60. order = 0;
  61. break;
  62. case 2:
  63. order = 1;
  64. break;
  65. case 4:
  66. order = 2;
  67. break;
  68. case 8:
  69. order = 3;
  70. break;
  71. case 16:
  72. order = 4;
  73. break;
  74. case 32:
  75. order = 5;
  76. break;
  77. case 64:
  78. order = 6;
  79. break;
  80. case 128:
  81. order = 7;
  82. break;
  83. case 256:
  84. order = 8;
  85. break;
  86. case 512:
  87. order = 9;
  88. break;
  89. case 1024:
  90. order = 10;
  91. break;
  92. case 2048:
  93. order = 11;
  94. break;
  95. case 4096:
  96. order = 12;
  97. break;
  98. case 8192:
  99. order = 13;
  100. break;
  101. case 16384:
  102. order = 14;
  103. break;
  104. default :
  105. order = 0;
  106. break;
  107. }
  108. return order;
  109. }
  110. /**
  111. * @brief This function wait sdio completed.
  112. * @param sdio rthw_sdio
  113. * @retval None
  114. */
  115. static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
  116. {
  117. rt_uint32_t status = 0;
  118. struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
  119. struct rt_mmcsd_data *data = cmd->data;
  120. hal_sfr_t hw_sdio = sdio->sdio_des.hw_sdio;
  121. rt_err_t tx_finish = -RT_ERROR;
  122. if (rt_event_recv(&sdio->event, 0xFFFFFFFF & ~HW_SDIO_CON_DFLAG, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
  123. rt_tick_from_millisecond(5000), &status) != RT_EOK)
  124. {
  125. LOG_E("wait completed timeout");
  126. cmd->err = -RT_ETIMEOUT;
  127. return;
  128. }
  129. if (sdio->pkg == RT_NULL)
  130. {
  131. return;
  132. }
  133. cmd->resp[0] = hw_sdio[SDxARG3];
  134. cmd->resp[1] = hw_sdio[SDxARG2];
  135. cmd->resp[2] = hw_sdio[SDxARG1];
  136. cmd->resp[3] = hw_sdio[SDxARG0];
  137. if (!(status & HW_SDIO_CON_NRPS)) {
  138. cmd->err = RT_EOK;
  139. LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
  140. } else {
  141. cmd->err = -RT_ERROR;
  142. }
  143. }
  144. /**
  145. * @brief This function transfer data by dma.
  146. * @param sdio rthw_sdio
  147. * @param pkg sdio package
  148. * @retval None
  149. */
  150. static void rthw_sdio_transfer_by_dma(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
  151. {
  152. struct rt_mmcsd_data *data;
  153. int size;
  154. void *buff;
  155. hal_sfr_t hw_sdio = sdio->sdio_des.hw_sdio;
  156. if ((RT_NULL == pkg) || (RT_NULL == sdio))
  157. {
  158. LOG_E("rthw_sdio_transfer_by_dma invalid args");
  159. return;
  160. }
  161. data = pkg->cmd->data;
  162. if (RT_NULL == data)
  163. {
  164. LOG_E("rthw_sdio_transfer_by_dma invalid args");
  165. return;
  166. }
  167. buff = pkg->buff;
  168. if (RT_NULL == buff)
  169. {
  170. LOG_E("rthw_sdio_transfer_by_dma invalid args");
  171. return;
  172. }
  173. hw_sdio = sdio->sdio_des.hw_sdio;
  174. size = data->blks * data->blksize;
  175. if (data->flags & DATA_DIR_WRITE)
  176. {
  177. LOG_D("DATA_DIR_WRITE %d", pkg->xfer_blks);
  178. sdio->sdio_des.txconfig((rt_uint32_t *)((rt_uint8_t *)buff + (pkg->xfer_blks * data->blksize)), 512);
  179. }
  180. else if (data->flags & DATA_DIR_READ)
  181. {
  182. LOG_D("DATA_DIR_WRITE %d", pkg->xfer_blks);
  183. sdio->sdio_des.rxconfig((rt_uint32_t *)((rt_uint8_t *)buff + (pkg->xfer_blks * data->blksize)), data->blksize);
  184. }
  185. }
  186. /**
  187. * @brief This function send command.
  188. * @param sdio rthw_sdio
  189. * @param pkg sdio package
  190. * @retval None
  191. */
  192. static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
  193. {
  194. struct rt_mmcsd_cmd *cmd = pkg->cmd;
  195. struct rt_mmcsd_data *data = cmd->data;
  196. hal_sfr_t hw_sdio = sdio->sdio_des.hw_sdio;
  197. rt_uint32_t reg_cmd = 0;
  198. rt_uint32_t data_flag = 0;
  199. /* save pkg */
  200. sdio->pkg = pkg;
  201. #define CK8E BIT(11) //在命令/数据包后加上8CLK
  202. #define CBUSY BIT(10) //Busy Check
  203. #define CLRSP BIT(9) //17Byte Long Rsp
  204. #define CRSP BIT(8) //Need Rsp
  205. /* config cmd reg */
  206. if (cmd->cmd_code != 18) {
  207. reg_cmd = cmd->cmd_code | 0x40 | CK8E;
  208. } else {
  209. reg_cmd = cmd->cmd_code | 0x40;
  210. }
  211. switch (resp_type(cmd))
  212. {
  213. case RESP_R1B:
  214. reg_cmd |= CBUSY | CRSP;
  215. break;
  216. case RESP_R2:
  217. reg_cmd |= CLRSP | CRSP;
  218. break;
  219. default:
  220. reg_cmd |= CRSP;
  221. break;
  222. }
  223. LOG_D("CMD:%d 0x%04X ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d",
  224. cmd->cmd_code,
  225. reg_cmd,
  226. cmd->arg,
  227. resp_type(cmd) == RESP_NONE ? "NONE" : "",
  228. resp_type(cmd) == RESP_R1 ? "R1" : "",
  229. resp_type(cmd) == RESP_R1B ? "R1B" : "",
  230. resp_type(cmd) == RESP_R2 ? "R2" : "",
  231. resp_type(cmd) == RESP_R3 ? "R3" : "",
  232. resp_type(cmd) == RESP_R4 ? "R4" : "",
  233. resp_type(cmd) == RESP_R5 ? "R5" : "",
  234. resp_type(cmd) == RESP_R6 ? "R6" : "",
  235. resp_type(cmd) == RESP_R7 ? "R7" : "",
  236. data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
  237. data ? data->blks * data->blksize : 0,
  238. data ? data->blksize : 0
  239. );
  240. /* config data reg */
  241. if (data != RT_NULL)
  242. {
  243. rt_uint32_t dir = 0;
  244. rt_uint32_t size = data->blks * data->blksize;
  245. int order;
  246. order = get_order(data->blksize);
  247. dir = (data->flags & DATA_DIR_READ) ? HW_SDIO_TO_HOST : 0;
  248. data_flag = data->flags;
  249. }
  250. /* transfer config */
  251. if (data_flag & DATA_DIR_READ)
  252. {
  253. rthw_sdio_transfer_by_dma(sdio, pkg);
  254. }
  255. /* send cmd */
  256. hw_sdio[SDxARG3] = cmd->arg;
  257. hw_sdio[SDxCMD] = reg_cmd;
  258. /* wait cmd completed */
  259. rthw_sdio_wait_completed(sdio);
  260. /* transfer config */
  261. if (data != RT_NULL)
  262. {
  263. do {
  264. if ((data_flag & DATA_DIR_WRITE) || ((data_flag & DATA_DIR_READ) && (pkg->xfer_blks != 0))) {
  265. rthw_sdio_transfer_by_dma(sdio, pkg);
  266. }
  267. rt_uint32_t status = 0;
  268. if (rt_event_recv(&sdio->event, 0xFFFFFFFF & ~HW_SDIO_CON_DFLAG, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
  269. rt_tick_from_millisecond(5000), &status) != RT_EOK)
  270. {
  271. LOG_E("wait completed timeout");
  272. LOG_E("SDxCON=0x%X SDxCMD=0x%X\n", hw_sdio[SDxCON], hw_sdio[SDxCMD]);
  273. cmd->err = -RT_ETIMEOUT;
  274. }
  275. if (data_flag & DATA_DIR_WRITE) {
  276. if (((hw_sdio[SDxCON] & HW_SDIO_CON_CRCS) >> 17) != 2) {
  277. LOG_E("Write CRC error!");
  278. cmd->err = -RT_ERROR;
  279. hw_sdio[SDxCPND] = HW_SDIO_CON_DFLAG;
  280. }
  281. }
  282. } while(++pkg->xfer_blks != data->blks);
  283. }
  284. /* clear pkg */
  285. sdio->pkg = RT_NULL;
  286. }
  287. /**
  288. * @brief This function send sdio request.
  289. * @param host rt_mmcsd_host
  290. * @param req request
  291. * @retval None
  292. */
  293. static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
  294. {
  295. struct sdio_pkg pkg;
  296. struct rthw_sdio *sdio = host->private_data;
  297. struct rt_mmcsd_data *data;
  298. RTHW_SDIO_LOCK(sdio);
  299. if (req->cmd != RT_NULL)
  300. {
  301. rt_memset(&pkg, 0, sizeof(pkg));
  302. data = req->cmd->data;
  303. pkg.cmd = req->cmd;
  304. if (data != RT_NULL)
  305. {
  306. rt_uint32_t size = data->blks * data->blksize;
  307. RT_ASSERT(size <= SDIO_BUFF_SIZE);
  308. pkg.buff = data->buf;
  309. if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))
  310. {
  311. pkg.buff = cache_buf;
  312. if (data->flags & DATA_DIR_WRITE)
  313. {
  314. rt_memcpy(cache_buf, data->buf, size);
  315. }
  316. }
  317. }
  318. rthw_sdio_send_command(sdio, &pkg);
  319. if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)))
  320. {
  321. rt_memcpy(data->buf, cache_buf, data->blksize * data->blks);
  322. }
  323. }
  324. if (req->stop != RT_NULL)
  325. {
  326. rt_memset(&pkg, 0, sizeof(pkg));
  327. pkg.cmd = req->stop;
  328. rthw_sdio_send_command(sdio, &pkg);
  329. }
  330. RTHW_SDIO_UNLOCK(sdio);
  331. mmcsd_req_complete(sdio->host);
  332. }
  333. /**
  334. * @brief This function config sdio.
  335. * @param host rt_mmcsd_host
  336. * @param io_cfg rt_mmcsd_io_cfg
  337. * @retval None
  338. */
  339. static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
  340. {
  341. rt_uint32_t clkcr, div, clk_src;
  342. rt_uint32_t clk = io_cfg->clock;
  343. struct rthw_sdio *sdio = host->private_data;
  344. hal_sfr_t hw_sdio = sdio->sdio_des.hw_sdio;
  345. clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio);
  346. if (clk_src < 240 * 1000)
  347. {
  348. LOG_E("The clock rate is too low! rata:%d", clk_src);
  349. return;
  350. }
  351. if (clk > host->freq_max) clk = host->freq_max;
  352. if (clk > clk_src)
  353. {
  354. // LOG_W("Setting rate(%d) is greater than clock source rate(%d).", clk, clk_src);
  355. // clk = clk_src;
  356. }
  357. LOG_D("clk:%d width:%s%s%s power:%s%s%s",
  358. clk,
  359. io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "",
  360. io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "",
  361. io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "",
  362. io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "",
  363. io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "",
  364. io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""
  365. );
  366. RTHW_SDIO_LOCK(sdio);
  367. switch (io_cfg->power_mode)
  368. {
  369. case MMCSD_POWER_OFF:
  370. hw_sdio[SDxCON] &= ~BIT(0);
  371. break;
  372. case MMCSD_POWER_UP:
  373. sd_baud = 199;
  374. hw_sdio[SDxCON] = 0;
  375. rt_thread_mdelay(1);
  376. hw_sdio[SDxCON] |= BIT(0); /* SD control enable */
  377. hw_sdio[SDxBAUD] = sysclk_update_baud(sd_baud);
  378. hw_sdio[SDxCON] |= BIT(3); /* Keep clock output */
  379. hw_sdio[SDxCON] |= BIT(4);
  380. hw_sdio[SDxCON] |= BIT(5); /* Data interrupt enable */
  381. hal_mdelay(40);
  382. break;
  383. case MMCSD_POWER_ON:
  384. if (clk == SDIO_MAX_FREQ) {
  385. hw_sdio[SDxCON] &= ~BIT(3);
  386. sd_baud = 3;
  387. hw_sdio[SDxBAUD] = sysclk_update_baud(sd_baud);
  388. }
  389. break;
  390. default:
  391. LOG_W("unknown power_mode %d", io_cfg->power_mode);
  392. break;
  393. }
  394. RTHW_SDIO_UNLOCK(sdio);
  395. }
  396. /**
  397. * @brief This function update sdio interrupt.
  398. * @param host rt_mmcsd_host
  399. * @param enable
  400. * @retval None
  401. */
  402. void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable)
  403. {
  404. struct rthw_sdio *sdio = host->private_data;
  405. hal_sfr_t hw_sdio = sdio->sdio_des.hw_sdio;
  406. if (enable)
  407. {
  408. LOG_D("enable sdio irq");
  409. rt_hw_irq_enable(IRQ_SD_VECTOR);
  410. }
  411. else
  412. {
  413. LOG_D("disable sdio irq");
  414. rt_hw_irq_disable(IRQ_SD_VECTOR);
  415. }
  416. }
  417. /**
  418. * @brief This function detect sdcard.
  419. * @param host rt_mmcsd_host
  420. * @retval 0x01
  421. */
  422. static rt_int32_t rthw_sd_detect(struct rt_mmcsd_host *host)
  423. {
  424. LOG_D("try to detect device");
  425. return 0x01;
  426. }
  427. /**
  428. * @brief This function interrupt process function.
  429. * @param host rt_mmcsd_host
  430. * @retval None
  431. */
  432. rt_section(".irq.sdio")
  433. void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
  434. {
  435. int complete = 0;
  436. struct rthw_sdio *sdio = host->private_data;
  437. hal_sfr_t hw_sdio = sdio->sdio_des.hw_sdio;
  438. rt_uint32_t intstatus = hw_sdio[SDxCON];
  439. /* clear flag */
  440. if (intstatus & HW_SDIO_CON_CFLAG) {
  441. complete = 1;
  442. hw_sdio[SDxCPND] = HW_SDIO_CON_CFLAG;
  443. }
  444. if (intstatus & HW_SDIO_CON_DFLAG) {
  445. complete = 1;
  446. hw_sdio[SDxCPND] = HW_SDIO_CON_DFLAG;
  447. }
  448. if (complete)
  449. {
  450. rt_event_send(&sdio->event, intstatus);
  451. }
  452. }
  453. static const struct rt_mmcsd_host_ops ab32_sdio_ops =
  454. {
  455. rthw_sdio_request,
  456. rthw_sdio_iocfg,
  457. rthw_sd_detect,
  458. rthw_sdio_irq_update,
  459. };
  460. /**
  461. * @brief This function create mmcsd host.
  462. * @param sdio_des ab32_sdio_des
  463. * @retval rt_mmcsd_host
  464. */
  465. struct rt_mmcsd_host *sdio_host_create(struct ab32_sdio_des *sdio_des)
  466. {
  467. struct rt_mmcsd_host *host;
  468. struct rthw_sdio *sdio = RT_NULL;
  469. if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL))
  470. {
  471. LOG_E("L:%d F:%s %s %s %s",
  472. (sdio_des == RT_NULL ? "sdio_des is NULL" : ""),
  473. (sdio_des ? (sdio_des->txconfig ? "txconfig is NULL" : "") : ""),
  474. (sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : "")
  475. );
  476. return RT_NULL;
  477. }
  478. sdio = rt_malloc(sizeof(struct rthw_sdio));
  479. if (sdio == RT_NULL)
  480. {
  481. LOG_E("L:%d F:%s malloc rthw_sdio fail");
  482. return RT_NULL;
  483. }
  484. rt_memset(sdio, 0, sizeof(struct rthw_sdio));
  485. host = mmcsd_alloc_host();
  486. if (host == RT_NULL)
  487. {
  488. LOG_E("L:%d F:%s mmcsd alloc host fail");
  489. rt_free(sdio);
  490. return RT_NULL;
  491. }
  492. rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct ab32_sdio_des));
  493. sdio->sdio_des.hw_sdio = (sdio_des->hw_sdio == RT_NULL ? SDMMC0_BASE : sdio_des->hw_sdio);
  494. sdio->sdio_des.clk_get = (sdio_des->clk_get == RT_NULL ? ab32_sdio_clk_get : sdio_des->clk_get);
  495. rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
  496. rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_PRIO);
  497. /* set host defautl attributes */
  498. host->ops = &ab32_sdio_ops;
  499. host->freq_min = 240 * 1000;
  500. host->freq_max = SDIO_MAX_FREQ;
  501. host->valid_ocr = 0X00FFFF80;/* The voltage range supported is 1.65v-3.6v */
  502. #ifndef SDIO_USING_1_BIT
  503. host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
  504. #else
  505. host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
  506. #endif
  507. host->max_seg_size = SDIO_BUFF_SIZE;
  508. host->max_dma_segs = 1;
  509. host->max_blk_size = 512;
  510. host->max_blk_count = 512;
  511. /* link up host and sdio */
  512. sdio->host = host;
  513. host->private_data = sdio;
  514. rthw_sdio_irq_update(host, 1);
  515. /* ready to change */
  516. mmcsd_change(host);
  517. return host;
  518. }
  519. static rt_err_t _dma_txconfig(rt_uint32_t *src, int Size)
  520. {
  521. hal_sfr_t sdiox = sdio_config->instance;
  522. sdiox[SDxDMAADR] = DMA_ADR(src);
  523. sdiox[SDxDMACNT] = BIT(18) | BIT(17) | BIT(16) | Size;
  524. return RT_EOK;
  525. }
  526. static rt_err_t _dma_rxconfig(rt_uint32_t *dst, int Size)
  527. {
  528. hal_sfr_t sdiox = sdio_config->instance;
  529. sdiox[SDxDMAADR] = DMA_ADR(dst);
  530. sdiox[SDxDMACNT] = (Size);
  531. return RT_EOK;
  532. }
  533. rt_section(".irq.sdio")
  534. void sdio_isr(int vector, void *param)
  535. {
  536. /* enter interrupt */
  537. rt_interrupt_enter();
  538. /* Process All SDIO Interrupt Sources */
  539. rthw_sdio_irq_process(host);
  540. /* leave interrupt */
  541. rt_interrupt_leave();
  542. }
  543. int rt_hw_sdio_init(void)
  544. {
  545. struct ab32_sdio_des sdio_des = {0};
  546. struct sd_handle hsd = {0};
  547. rt_uint8_t param = 0;
  548. hsd.instance = SDMMC0_BASE;
  549. hal_rcu_periph_clk_enable(RCU_SD0);
  550. hal_sd_mspinit(&hsd);
  551. rt_hw_interrupt_install(IRQ_SD_VECTOR, sdio_isr, &param, "sd_isr");
  552. sdio_des.clk_get = ab32_sdio_clk_get;
  553. sdio_des.hw_sdio = SDMMC0_BASE;
  554. sdio_des.rxconfig = _dma_rxconfig;
  555. sdio_des.txconfig = _dma_txconfig;
  556. host = sdio_host_create(&sdio_des);
  557. return 0;
  558. }
  559. INIT_DEVICE_EXPORT(rt_hw_sdio_init);
  560. void ab32_mmcsd_change(void)
  561. {
  562. mmcsd_change(host);
  563. }
  564. #endif // 0