Home Explore Help
Register Sign In
lqb
/
rt-thread
mirror of https://gitee.com/rtthread/rt-thread.git
1
0
Fork 0
Files Issues 0 Wiki
Tree: 05699d63d5
Branches Tags
rt-thread
/
bsp
/
bluetrum
/
libraries
/
hal_libraries
/
bmsis
/
include
/
ab32vg1.h

ab32vg1.h 15 KB
History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346 
  1. /*
    2. 

  2.  * Copyright (c) 2020-2020, BLUETRUM Development Team
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: Apache-2.0
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef AB32VG1_H__
    8. 

  8. #define AB32VG1_H__
    9. 

  9. 

  10. #ifndef __ASSEMBLER__
    11. 

  11. #include <stdint.h>
    12. 

  12. #include "system_ab32vgx.h"
    13. 

  13. 

  14. /*!< Interrupt Number Definition */
    15. 

  15. typedef enum
    16. 

  16. {
    17. 

  17.     IRQ_SW_VECTOR                   = 2,
    18. 

  18.     IRQ_TMR0_VECTOR                 = 3,
    19. 

  19.     IRQ_TMR1_VECTOR                 = 4,
    20. 

  20.     IRQ_TMR2_4_5_VECTOR             = 5,    /*!< Timer 2, 4 and 5 Interrupt         */
    21. 

  21.     IRQ_IRRX_VECTOR                 = 6,    /*!< Timer 3 and IR receiver Interrupt  */
    22. 

  22.     IRQ_USB_VECTOR                  = 7,
    23. 

  23.     IRQ_SD_VECTOR                   = 8,
    24. 

  24.     IRQ_AUBUF0_1_VECTOR             = 9,    /*!< Audio buffer 0 and 1 Interrupt     */
    25. 

  25.     IRQ_SDADC_VECTOR                = 10,
    26. 

  26.     IRQ_AUDEC_VECTOR                = 11,   /*!< Audio codec, SBC encode and AEC FFT Interrupt */
    27. 

  27.     IRQ_SRC_VECTOR                  = 12,   /*!< SRC, PLC and CVSD Interrupt        */
    28. 

  28.     IRQ_FM_SPDIF_VECTOR             = 13,   /*!< FM TX, RX and SPDIF RX Interrupt   */
    29. 

  29.     IRQ_UART0_2_VECTOR              = 14,   /*!< UART 0 to 2 Interrupt              */
    30. 

  30.     IRQ_HSUART_VECTOR               = 15,
    31. 

  31.     IRQ_RTC_VECTOR                  = 16,   /*!< RTC, LVD and WDT Interrupt         */
    32. 

  32.     IRQ_I2S_VECTOR                  = 17,
    33. 

  33.     IRQ_GPIO_IRQ                    = 18,
    34. 

  34.     IRQ_TOTAL_NUM                   = 23,
    35. 

  35. } irq_type;
    36. 

  36. #endif // __ASSEMBLER__
    37. 

  37. 

  38. #ifndef __ASSEMBLER__
    39. 

  39. #define SFR_RO *(volatile unsigned long const *)
    40. 

  40. #define SFR_WO *(volatile unsigned long*)
    41. 

  41. #define SFR_RW *(volatile unsigned long*)
    42. 

  42. #define SWINT() asm(".long 0xb0030057")
    43. 

  43. #define EEBREAKINT() asm(".long 0xb0040057")
    44. 

  44. #else
    45. 

  45. #define SFR_RO
    46. 

  46. #define SFR_WO
    47. 

  47. #define SFR_RW
    48. 

  48. #define SWINT      .long 0xb0030057
    49. 

  49. #define EEBREAKINT .long 0xb0040057
    50. 

  50. #endif
    51. 

  51. 

  52. #define SFR_BASE   0x00000000
    53. 

  53. #define SFR0_BASE  (0x00000000 + 0x000)
    54. 

  54. #define SFR1_BASE  (0x00000000 + 0x100)
    55. 

  55. #define SFR2_BASE  (0x00000000 + 0x200)
    56. 

  56. #define SFR3_BASE  (0x00000000 + 0x300)
    57. 

  57. #define SFR4_BASE  (0x00000000 + 0x400)
    58. 

  58. #define SFR5_BASE  (0x00000000 + 0x500)
    59. 

  59. #define SFR6_BASE  (0x00000000 + 0x600)
    60. 

  60. #define SFR7_BASE  (0x00000000 + 0x700)
    61. 

  61. #define SFR8_BASE  (0x00000000 + 0x800)
    62. 

  62. #define SFR9_BASE  (0x00000000 + 0x900)
    63. 

  63. #define SFR10_BASE (0x00000000 + 0xa00)
    64. 

  64. #define SFR11_BASE (0x00000000 + 0xb00)
    65. 

  65. #define SFR12_BASE (0x00000000 + 0xc00)
    66. 

  66. #define SFR13_BASE (0x00000000 + 0xd00)
    67. 

  67. #define SFR14_BASE (0x00000000 + 0xe00)
    68. 

  68. #define SFR15_BASE (0x00000000 + 0xf00)
    69. 

  69. 

  70. #define RTC_WR          0x200
    71. 

  71. #define RTC_RD          0x100
    72. 

  72. 

  73. #define RTCCNT_CMD      0x01
    74. 

  74. #define RTCALM_CMD      0x02
    75. 

  75. #define RTCRAM_CMD      0x03
    76. 

  76. #define RTCCON0_CMD     0x04
    77. 

  77. #define RTCCON1_CMD     0x05
    78. 

  78. #define RTCCON2_CMD     0x06
    79. 

  79. #define RTCCON3_CMD     0x07
    80. 

  80. #define RTCCON4_CMD     0x08
    81. 

  81. #define RTCCON5_CMD     0x09
    82. 

  82. #define RTCCON6_CMD     0x0a
    83. 

  83. #define RTCCON7_CMD     0x0b
    84. 

  84. #define RTCCON8_CMD     0x0c
    85. 

  85. #define RTCCON9_CMD     0x0d
    86. 

  86. #define RTCCON10_CMD    0x0e
    87. 

  87. 

  88. #define FUNCMCON0         SFR_RW (SFR0_BASE + 0x07*4)
    89. 

  89. #define FUNCMCON1         SFR_RW (SFR0_BASE + 0x08*4)
    90. 

  90. #define FUNCMCON2         SFR_RW (SFR0_BASE + 0x09*4)
    91. 

  91. 

  92. #define UART0CON          SFR_RW (SFR0_BASE + 0x10*4)
    93. 

  93. #define UART0CPND         SFR_WO (SFR0_BASE + 0x11*4)
    94. 

  94. #define UART0BAUD         SFR_RW (SFR0_BASE + 0x12*4)
    95. 

  95. #define UART0DATA         SFR_RW (SFR0_BASE + 0x13*4)
    96. 

  96. #define TMR0CON           SFR_RW (SFR0_BASE + 0x14*4)
    97. 

  97. #define TMR0CPND          SFR_RW (SFR0_BASE + 0x15*4)
    98. 

  98. #define TMR0CNT           SFR_RW (SFR0_BASE + 0x16*4)
    99. 

  99. #define TMR0PR            SFR_RW (SFR0_BASE + 0x17*4)
    100. 

  100. #define CLKCON0           SFR_RW (SFR0_BASE + 0x19*4)
    101. 

  101. #define WDTCON            SFR_RW (SFR0_BASE + 0x1a*4)
    102. 

  102. #define RTCCON            SFR_RW (SFR0_BASE + 0x1b*4)
    103. 

  103. #define RTCDAT            SFR_RW (SFR0_BASE + 0x1c*4)
    104. 

  104. #define CLKCON1           SFR_RW (SFR0_BASE + 0x1d*4)
    105. 

  105. #define RTCCPND           SFR_WO (SFR0_BASE + 0x1e*4)
    106. 

  106. 

  107. #define SD0CON            SFR_RW (SFR0_BASE + 0x20*4)
    108. 

  108. #define SD0CPND           SFR_WO (SFR0_BASE + 0x21*4)
    109. 

  109. #define SD0BAUD           SFR_RW (SFR0_BASE + 0x22*4)
    110. 

  110. #define SD0CMD            SFR_RW (SFR0_BASE + 0x23*4)
    111. 

  111. #define SD0ARG3           SFR_RW (SFR0_BASE + 0x24*4)
    112. 

  112. #define SD0ARG2           SFR_RW (SFR0_BASE + 0x25*4)
    113. 

  113. #define SD0ARG1           SFR_RW (SFR0_BASE + 0x26*4)
    114. 

  114. #define SD0ARG0           SFR_RW (SFR0_BASE + 0x27*4)
    115. 

  115. #define SD0DMAADR         SFR_RW (SFR0_BASE + 0x28*4)
    116. 

  116. #define SD0DMACNT         SFR_RW (SFR0_BASE + 0x29*4)
    117. 

  117. #define SPI0CON           SFR_RW (SFR0_BASE + 0x2a*4)
    118. 

  118. #define SPI0BUF           SFR_RW (SFR0_BASE + 0x2b*4)
    119. 

  119. #define SPI0BAUD          SFR_RW (SFR0_BASE + 0x2c*4)
    120. 

  120. #define SPI0CPND          SFR_RW (SFR0_BASE + 0x2d*4)
    121. 

  121. #define SPI0DMACNT        SFR_RW (SFR0_BASE + 0x2e*4)
    122. 

  122. #define SPI0DMAADR        SFR_RW (SFR0_BASE + 0x2f*4)
    123. 

  123. 

  124. #define UART1CON          SFR_RW (SFR0_BASE + 0x30*4)
    125. 

  125. #define UART1CPND         SFR_WO (SFR0_BASE + 0x31*4)
    126. 

  126. #define UART1BAUD         SFR_RW (SFR0_BASE + 0x32*4)
    127. 

  127. #define UART1DATA         SFR_RW (SFR0_BASE + 0x33*4)
    128. 

  128. #define TMR1CON           SFR_RW (SFR0_BASE + 0x35*4)
    129. 

  129. #define TMR1CPND          SFR_RW (SFR0_BASE + 0x36*4)
    130. 

  130. #define TMR1CNT           SFR_RW (SFR0_BASE + 0x37*4)
    131. 

  131. #define TMR1PR            SFR_RW (SFR0_BASE + 0x38*4)
    132. 

  132. #define TMR2CON           SFR_RW (SFR0_BASE + 0x3a*4)
    133. 

  133. #define TMR2CPND          SFR_RW (SFR0_BASE + 0x3b*4)
    134. 

  134. #define TMR2CNT           SFR_RW (SFR0_BASE + 0x3c*4)
    135. 

  135. #define TMR2PR            SFR_RW (SFR0_BASE + 0x3d*4)
    136. 

  136. 

  137. //------------------------- SFR Group1 ---------------------------------------//
    138. 

  138. #define AUBUFDATA       SFR_RW (SFR1_BASE + 0x01*4)
    139. 

  139. #define AUBUFCON        SFR_RW (SFR1_BASE + 0x02*4)
    140. 

  140. #define AUBUFSTARTADDR  SFR_RW (SFR1_BASE + 0x03*4)
    141. 

  141. #define AUBUFSIZE       SFR_RW (SFR1_BASE + 0x04*4)
    142. 

  142. #define AUBUFFIFOCNT    SFR_RW (SFR1_BASE + 0x05*4)
    143. 

  143. #define AUBUF1DATA      SFR_RW (SFR1_BASE + 0x06*4)
    144. 

  144. #define AUBUF1CON       SFR_RW (SFR1_BASE + 0x07*4)
    145. 

  145. #define AUBUF1STARTADDR SFR_RW (SFR1_BASE + 0x08*4)
    146. 

  146. #define AUBUF1SIZE      SFR_RW (SFR1_BASE + 0x09*4)
    147. 

  147. #define AUBUF1FIFOCNT   SFR_RW (SFR1_BASE + 0x0a*4)
    148. 

  148. 

  149. #define DACDIGCON0      SFR_RW (SFR1_BASE + 0x10*4)
    150. 

  150. #define DACVOLCON       SFR_RW (SFR1_BASE + 0x11*4)
    151. 

  151. #define AU0LMIXCOEF     SFR_RW (SFR1_BASE + 0x12*4)
    152. 

  152. #define AU0RMIXCOEF     SFR_RW (SFR1_BASE + 0x13*4)
    153. 

  153. #define AU1LMIXCOEF     SFR_RW (SFR1_BASE + 0x14*4)
    154. 

  154. #define AU1RMIXCOEF     SFR_RW (SFR1_BASE + 0x15*4)
    155. 

  155. 

  156. #define AUANGCON0       SFR_RW (SFR1_BASE + 0x3c*4)
    157. 

  157. #define AUANGCON1       SFR_RW (SFR1_BASE + 0x3d*4)
    158. 

  158. #define AUANGCON2       SFR_RW (SFR1_BASE + 0x3e*4)
    159. 

  159. #define AUANGCON3       SFR_RW (SFR1_BASE + 0x3f*4)
    160. 

  160. 

  161. #define USBCON0         SFR_RW (SFR3_BASE + 0x00*4)
    162. 

  162. #define USBCON1         SFR_RW (SFR3_BASE + 0x01*4)
    163. 

  163. #define USBCON2         SFR_RW (SFR3_BASE + 0x02*4)
    164. 

  164. 

  165. #define PWRCON0         SFR_RW (SFR3_BASE + 0x1d*4)
    166. 

  166. #define LVDCON          SFR_RW (SFR3_BASE + 0x1e*4)
    167. 

  167. #define CHAGCON         SFR_RW (SFR3_BASE + 0x1f*4)
    168. 

  168. 

  169. #define PLL0DIV         SFR_RW (SFR3_BASE + 0x23*4)
    170. 

  170. #define PLL1DIV         SFR_RW (SFR3_BASE + 0x24*4)
    171. 

  171. #define PLL0CON         SFR_RW (SFR3_BASE + 0x26*4)
    172. 

  172. #define PLL1CON         SFR_RW (SFR3_BASE + 0x27*4)
    173. 

  173. #define PLL2CON         SFR_RW (SFR3_BASE + 0x28*4)
    174. 

  174. #define XO26MCON        SFR_RW (SFR3_BASE + 0x29*4)
    175. 

  175. #define CLKCON2         SFR_RW (SFR3_BASE + 0x2a*4)
    176. 

  176. #define CLKGAT0         SFR_RW (SFR3_BASE + 0x2c*4)
    177. 

  177. #define LPMCON          SFR_RW (SFR3_BASE + 0x2d*4)
    178. 

  178. #define MEMCON          SFR_RW (SFR3_BASE + 0x2e*4)
    179. 

  179. #define CLKCON3         SFR_RW (SFR3_BASE + 0x2f*4)
    180. 

  180. #define CLKGAT1         SFR_RW (SFR3_BASE + 0x3f*4)
    181. 

  181. 

  182. #define PWMCON          SFR_RW (SFR4_BASE + 0x20*4)
    183. 

  183. #define PWMPRCON        SFR_RW (SFR4_BASE + 0x21*4)
    184. 

  184. #define PWM01DUTY       SFR_RW (SFR4_BASE + 0x22*4)
    185. 

  185. #define PWM23DUTY       SFR_RW (SFR4_BASE + 0x23*4)
    186. 

  186. #define PWMCYCNUM       SFR_RW (SFR4_BASE + 0x24*4)
    187. 

  187. #define PWMSTEP         SFR_RW (SFR4_BASE + 0x25*4)
    188. 

  188. 

  189. //0x00~0x1f reserve for CPU
    190. 

  190. #define PICCONCLR       SFR_WO (SFR5_BASE + 0x0c*4)
    191. 

  191. #define PICCONSET       SFR_WO (SFR5_BASE + 0x0d*4)
    192. 

  192. #define PICENCLR        SFR_WO (SFR5_BASE + 0x0e*4)
    193. 

  193. #define PICENSET        SFR_WO (SFR5_BASE + 0x0f*4)
    194. 

  194. 

  195. #define PICCON          SFR_RW (SFR5_BASE + 0x10*4)
    196. 

  196. #define PICEN           SFR_RW (SFR5_BASE + 0x11*4)
    197. 

  197. #define PICPR           SFR_RW (SFR5_BASE + 0x12*4)
    198. 

  198. #define PICADR          SFR_RW (SFR5_BASE + 0x13*4)
    199. 

  199. #define PICPND          SFR_RW (SFR5_BASE + 0x14*4)
    200. 

  200. #define EPICCON         SFR_RW (SFR5_BASE + 0x1e*4)
    201. 

  201. #define EPC             SFR_RW (SFR5_BASE + 0x1f*4)
    202. 

  202. 

  203. #define SADCDAT0        SFR_RO (SFR5_BASE + 0x20*4)
    204. 

  204. #define SADCDAT1        SFR_RO (SFR5_BASE + 0x21*4)
    205. 

  205. #define SADCDAT2        SFR_RO (SFR5_BASE + 0x22*4)
    206. 

  206. #define SADCDAT3        SFR_RO (SFR5_BASE + 0x23*4)
    207. 

  207. #define SADCDAT4        SFR_RO (SFR5_BASE + 0x24*4)
    208. 

  208. #define SADCDAT5        SFR_RO (SFR5_BASE + 0x25*4)
    209. 

  209. #define SADCDAT6        SFR_RO (SFR5_BASE + 0x26*4)
    210. 

  210. #define SADCDAT7        SFR_RO (SFR5_BASE + 0x27*4)
    211. 

  211. #define SADCDAT8        SFR_RO (SFR5_BASE + 0x28*4)
    212. 

  212. #define SADCDAT9        SFR_RO (SFR5_BASE + 0x29*4)
    213. 

  213. #define SADCDAT10       SFR_RO (SFR5_BASE + 0x2a*4)
    214. 

  214. #define SADCDAT11       SFR_RO (SFR5_BASE + 0x2b*4)
    215. 

  215. #define SADCDAT12       SFR_RO (SFR5_BASE + 0x2c*4)
    216. 

  216. #define SADCDAT13       SFR_RO (SFR5_BASE + 0x2d*4)
    217. 

  217. #define SADCDAT14       SFR_RO (SFR5_BASE + 0x2e*4)
    218. 

  218. #define SADCDAT15       SFR_RO (SFR5_BASE + 0x2f*4)
    219. 

  219. 

  220. #define AUANGCON1       SFR_RW (SFR1_BASE + 0x3d*4)
    221. 

  221. 

  222. #define WKUPCON         SFR_WO (SFR5_BASE + 0x39*4)
    223. 

  223. #define WKUPEDG         SFR_WO (SFR5_BASE + 0x3a*4)
    224. 

  224. #define WKUPCPND        SFR_WO (SFR5_BASE + 0x3b*4)
    225. 

  225. 

  226. //------------------------- SFR Group6 ---------------------------------------//
    227. 

  227. #define GPIOASET        SFR_RW (SFR6_BASE + 0x00*4)
    228. 

  228. #define GPIOACLR        SFR_RW (SFR6_BASE + 0x01*4)
    229. 

  229. #define GPIOA           SFR_RW (SFR6_BASE + 0x02*4)
    230. 

  230. #define GPIOADIR        SFR_RW (SFR6_BASE + 0x03*4)
    231. 

  231. #define GPIOADE         SFR_RW (SFR6_BASE + 0x04*4)
    232. 

  232. #define GPIOAFEN        SFR_RW (SFR6_BASE + 0x05*4)
    233. 

  233. #define GPIOADRV        SFR_RW (SFR6_BASE + 0x06*4)
    234. 

  234. #define GPIOAPU         SFR_RW (SFR6_BASE + 0x07*4)
    235. 

  235. #define GPIOAPD         SFR_RW (SFR6_BASE + 0x08*4)
    236. 

  236. #define GPIOAPU200K     SFR_RW (SFR6_BASE + 0x09*4)
    237. 

  237. #define GPIOAPD200K     SFR_RW (SFR6_BASE + 0x0a*4)
    238. 

  238. #define GPIOAPU300      SFR_RW (SFR6_BASE + 0x0b*4)
    239. 

  239. #define GPIOAPD300      SFR_RW (SFR6_BASE + 0x0c*4)
    240. 

  240. 

  241. #define GPIOBSET        SFR_RW (SFR6_BASE + 0x10*4)
    242. 

  242. #define GPIOBCLR        SFR_RW (SFR6_BASE + 0x11*4)
    243. 

  243. #define GPIOB           SFR_RW (SFR6_BASE + 0x12*4)
    244. 

  244. #define GPIOBDIR        SFR_RW (SFR6_BASE + 0x13*4)
    245. 

  245. #define GPIOBDE         SFR_RW (SFR6_BASE + 0x14*4)
    246. 

  246. #define GPIOBFEN        SFR_RW (SFR6_BASE + 0x15*4)
    247. 

  247. #define GPIOBDRV        SFR_RW (SFR6_BASE + 0x16*4)
    248. 

  248. #define GPIOBPU         SFR_RW (SFR6_BASE + 0x17*4)
    249. 

  249. #define GPIOBPD         SFR_RW (SFR6_BASE + 0x18*4)
    250. 

  250. #define GPIOBPU200K     SFR_RW (SFR6_BASE + 0x19*4)
    251. 

  251. #define GPIOBPD200K     SFR_RW (SFR6_BASE + 0x1a*4)
    252. 

  252. #define GPIOBPU300      SFR_RW (SFR6_BASE + 0x1b*4)
    253. 

  253. #define GPIOBPD300      SFR_RW (SFR6_BASE + 0x1c*4)
    254. 

  254. 

  255. #define GPIOESET        SFR_RW (SFR6_BASE + 0x20*4)
    256. 

  256. #define GPIOECLR        SFR_RW (SFR6_BASE + 0x21*4)
    257. 

  257. #define GPIOE           SFR_RW (SFR6_BASE + 0x22*4)
    258. 

  258. #define GPIOEDIR        SFR_RW (SFR6_BASE + 0x23*4)
    259. 

  259. #define GPIOEDE         SFR_RW (SFR6_BASE + 0x24*4)
    260. 

  260. #define GPIOEFEN        SFR_RW (SFR6_BASE + 0x25*4)
    261. 

  261. #define GPIOEDRV        SFR_RW (SFR6_BASE + 0x26*4)
    262. 

  262. #define GPIOEPU         SFR_RW (SFR6_BASE + 0x27*4)
    263. 

  263. #define GPIOEPD         SFR_RW (SFR6_BASE + 0x28*4)
    264. 

  264. #define GPIOEPU200K     SFR_RW (SFR6_BASE + 0x29*4)
    265. 

  265. #define GPIOEPD200K     SFR_RW (SFR6_BASE + 0x2a*4)
    266. 

  266. #define GPIOEPU300      SFR_RW (SFR6_BASE + 0x2b*4)
    267. 

  267. #define GPIOEPD300      SFR_RW (SFR6_BASE + 0x2c*4)
    268. 

  268. 

  269. #define GPIOFSET        SFR_RW (SFR6_BASE + 0x30*4)
    270. 

  270. #define GPIOFCLR        SFR_RW (SFR6_BASE + 0x31*4)
    271. 

  271. #define GPIOF           SFR_RW (SFR6_BASE + 0x32*4)
    272. 

  272. #define GPIOFDIR        SFR_RW (SFR6_BASE + 0x33*4)
    273. 

  273. #define GPIOFDE         SFR_RW (SFR6_BASE + 0x34*4)
    274. 

  274. #define GPIOFFEN        SFR_RW (SFR6_BASE + 0x35*4)
    275. 

  275. #define GPIOFDRV        SFR_RW (SFR6_BASE + 0x36*4)
    276. 

  276. #define GPIOFPU         SFR_RW (SFR6_BASE + 0x37*4)
    277. 

  277. #define GPIOFPD         SFR_RW (SFR6_BASE + 0x38*4)
    278. 

  278. #define GPIOFPU200K     SFR_RW (SFR6_BASE + 0x39*4)
    279. 

  279. #define GPIOFPD200K     SFR_RW (SFR6_BASE + 0x3a*4)
    280. 

  280. #define GPIOFPU300      SFR_RW (SFR6_BASE + 0x3b*4)
    281. 

  281. #define GPIOFPD300      SFR_RW (SFR6_BASE + 0x3c*4)
    282. 

  282. 

  283. #define GPIOGSET        SFR_RW (SFR7_BASE + 0x00*4)
    284. 

  284. #define GPIOGCLR        SFR_RW (SFR7_BASE + 0x01*4)
    285. 

  285. #define GPIOG           SFR_RW (SFR7_BASE + 0x02*4)
    286. 

  286. #define GPIOGDIR        SFR_RW (SFR7_BASE + 0x03*4)
    287. 

  287. #define GPIOGDE         SFR_RW (SFR7_BASE + 0x04*4)
    288. 

  288. #define GPIOGFEN        SFR_RW (SFR7_BASE + 0x05*4)
    289. 

  289. #define GPIOGDRV        SFR_RW (SFR7_BASE + 0x06*4)
    290. 

  290. #define GPIOGPU         SFR_RW (SFR7_BASE + 0x07*4)
    291. 

  291. #define GPIOGPD         SFR_RW (SFR7_BASE + 0x08*4)
    292. 

  292. #define GPIOGPU200K     SFR_RW (SFR7_BASE + 0x09*4)
    293. 

  293. #define GPIOGPD200K     SFR_RW (SFR7_BASE + 0x0a*4)
    294. 

  294. #define GPIOGPU300      SFR_RW (SFR7_BASE + 0x0b*4)
    295. 

  295. #define GPIOGPD300      SFR_RW (SFR7_BASE + 0x0c*4)
    296. 

  296. 

  297. #define IRRXCON         SFR_RW (SFR8_BASE + 0x1b*4)
    298. 

  298. #define IRRXDAT         SFR_RW (SFR8_BASE + 0x1c*4)
    299. 

  299. #define IRRXCPND        SFR_WO (SFR8_BASE + 0x1d*4)
    300. 

  300. #define IRRXERR0        SFR_WO (SFR8_BASE + 0x1e*4)
    301. 

  301. #define IRRXERR1        SFR_WO (SFR8_BASE + 0x1f*4)
    302. 

  302. 

  303. #define USERKEY         SFR_RW (SFR8_BASE + 0x20*4)
    304. 

  304. #define PROTCON1        SFR_RW (SFR8_BASE + 0x21*4)
    305. 

  305. #define FMAMFDTCON      SFR_WO (SFR8_BASE + 0x29*4)
    306. 

  306. 

  307. #define TMR3CON         SFR_RW (SFR9_BASE + 0x00*4)
    308. 

  308. #define TMR3CPND        SFR_WO (SFR9_BASE + 0x01*4)
    309. 

  309. #define TMR3CNT         SFR_RW (SFR9_BASE + 0x02*4)
    310. 

  310. #define TMR3PR          SFR_RW (SFR9_BASE + 0x03*4)
    311. 

  311. #define TMR3CPT         SFR_RO (SFR9_BASE + 0x04*4)
    312. 

  312. #define TMR3DUTY0       SFR_WO (SFR9_BASE + 0x05*4)
    313. 

  313. #define TMR3DUTY1       SFR_WO (SFR9_BASE + 0x06*4)
    314. 

  314. #define TMR3DUTY2       SFR_WO (SFR9_BASE + 0x07*4)
    315. 

  315. #define TMR4CON         SFR_RW (SFR9_BASE + 0x08*4)
    316. 

  316. #define TMR4CPND        SFR_WO (SFR9_BASE + 0x09*4)
    317. 

  317. #define TMR4CNT         SFR_RW (SFR9_BASE + 0x0a*4)
    318. 

  318. #define TMR4PR          SFR_RW (SFR9_BASE + 0x0b*4)
    319. 

  319. #define TMR4CPT         SFR_RO (SFR9_BASE + 0x0c*4)
    320. 

  320. #define TMR4DUTY0       SFR_WO (SFR9_BASE + 0x0d*4)
    321. 

  321. #define TMR4DUTY1       SFR_WO (SFR9_BASE + 0x0e*4)
    322. 

  322. #define TMR4DUTY2       SFR_WO (SFR9_BASE + 0x0f*4)
    323. 

  323. 

  324. #define TMR5CON         SFR_RW (SFR9_BASE + 0x10*4)
    325. 

  325. #define TMR5CPND        SFR_WO (SFR9_BASE + 0x11*4)
    326. 

  326. #define TMR5CNT         SFR_RW (SFR9_BASE + 0x12*4)
    327. 

  327. #define TMR5PR          SFR_RW (SFR9_BASE + 0x13*4)
    328. 

  328. #define TMR5CPT         SFR_RO (SFR9_BASE + 0x14*4)
    329. 

  329. #define TMR5DUTY0       SFR_WO (SFR9_BASE + 0x15*4)
    330. 

  330. #define TMR5DUTY1       SFR_WO (SFR9_BASE + 0x16*4)
    331. 

  331. #define TMR5DUTY2       SFR_WO (SFR9_BASE + 0x17*4)
    332. 

  332. #define UART2CON        SFR_RW (SFR9_BASE + 0x18*4)
    333. 

  333. #define UART2CPND       SFR_WO (SFR9_BASE + 0x19*4)
    334. 

  334. #define UART2BAUD       SFR_RW (SFR9_BASE + 0x1a*4)
    335. 

  335. #define UART2DATA       SFR_RW (SFR9_BASE + 0x1b*4)
    336. 

  336. #define PORTINTEDG      SFR_RW (SFR9_BASE + 0x1e*4)
    337. 

  337. #define PORTINTEN       SFR_RW (SFR9_BASE + 0x1f*4)
    338. 

  338. 

  339. #define SPI1CON         SFR_RW (SFR9_BASE + 0x20*4)
    340. 

  340. #define SPI1BUF         SFR_RW (SFR9_BASE + 0x21*4)
    341. 

  341. #define SPI1BAUD        SFR_RW (SFR9_BASE + 0x22*4)
    342. 

  342. #define SPI1CPND        SFR_RW (SFR9_BASE + 0x23*4)
    343. 

  343. #define SPI1DMACNT      SFR_RW (SFR9_BASE + 0x24*4)
    344. 

  344. #define SPI1DMAADR      SFR_RW (SFR9_BASE + 0x25*4)
    345. 

  345. 

  346. #endif
    347.