board.c 4.3 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2019-07-29 zdzn first version
  9. * 2021-12-28 GuEe-GUI add smp support
  10. */
  11. #include <rthw.h>
  12. #include <rtthread.h>
  13. #include "board.h"
  14. #include "drv_uart.h"
  15. #include "drv_timer.h"
  16. #include "gtimer.h"
  17. #include "cpuport.h"
  18. #include "interrupt.h"
  19. #include "mmu.h"
  20. #include "raspi.h"
  21. struct mem_desc platform_mem_desc[] =
  22. {
  23. {0, 0x6400000, 0, NORMAL_MEM},
  24. {0xc00000, 0xc01000, 0xc00000, DEVICE_MEM}, /* mbox */
  25. {0x3f000000, 0x3f200000, 0x3f000000, DEVICE_MEM}, /* timer */
  26. {0x3f200000, 0x3f216000, 0x3f200000, DEVICE_MEM}, /* uart */
  27. {0x40000000, 0x40200000, 0x40000000, DEVICE_MEM}, /* core timer */
  28. {0x3F300000, 0x3F301000, 0x3F300000, DEVICE_MEM}, /* sdio */
  29. {0x3f804000, 0x3f805000, 0x3f804000, DEVICE_MEM}, /* i2c0 */
  30. {0x3f205000, 0x3f206000, 0x3f205000, DEVICE_MEM}, /* i2c1 */
  31. };
  32. const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]);
  33. #if defined(BSP_USING_CORETIMER) || defined(RT_USING_SMP)
  34. static volatile rt_uint64_t timer_step;
  35. #define BSP_USING_CORETIMER
  36. #endif
  37. void rt_hw_timer_isr(int vector, void *parameter)
  38. {
  39. #ifdef BSP_USING_CORETIMER
  40. rt_hw_set_gtimer_val(timer_step);
  41. #else
  42. ARM_TIMER_IRQCLR = 0;
  43. #endif
  44. rt_tick_increase();
  45. }
  46. void rt_hw_timer_init(void)
  47. {
  48. rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
  49. rt_hw_interrupt_umask(IRQ_ARM_TIMER);
  50. #ifdef BSP_USING_CORETIMER
  51. __ISB();
  52. timer_step = rt_hw_get_gtimer_frq();
  53. __DSB();
  54. timer_step /= RT_TICK_PER_SECOND;
  55. rt_hw_gtimer_enable();
  56. rt_hw_set_gtimer_val(timer_step);
  57. #ifdef RT_USING_SMP
  58. core_timer_enable(rt_hw_cpu_id());
  59. #else
  60. core_timer_enable(0);
  61. #endif
  62. #else
  63. __DSB();
  64. /* timer_clock = apb_clock/(pre_divider + 1) */
  65. ARM_TIMER_PREDIV = (250 - 1);
  66. ARM_TIMER_RELOAD = 0;
  67. ARM_TIMER_LOAD = 0;
  68. ARM_TIMER_IRQCLR = 0;
  69. ARM_TIMER_CTRL = 0;
  70. ARM_TIMER_RELOAD = 10000;
  71. ARM_TIMER_LOAD = 10000;
  72. /* 23-bit counter, enable interrupt, enable timer */
  73. ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7);
  74. #endif
  75. }
  76. void idle_wfi(void)
  77. {
  78. asm volatile ("wfi");
  79. }
  80. /**
  81. * Initialize the Hardware related stuffs. Called from rtthread_startup()
  82. * after interrupt disabled.
  83. */
  84. void rt_hw_board_init(void)
  85. {
  86. rt_hw_init_mmu_table(platform_mem_desc, platform_mem_desc_size);
  87. rt_hw_mmu_init();
  88. /* initialize hardware interrupt */
  89. rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
  90. /* initialize uart */
  91. rt_hw_uart_init(); // driver/drv_uart.c
  92. /* initialize timer for os tick */
  93. rt_hw_timer_init();
  94. rt_thread_idle_sethook(idle_wfi);
  95. #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
  96. /* set console device */
  97. rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
  98. #endif
  99. #ifdef RT_USING_HEAP
  100. /* initialize memory system */
  101. rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
  102. rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
  103. #endif
  104. #ifdef RT_USING_COMPONENTS_INIT
  105. rt_components_board_init();
  106. #endif
  107. #ifdef RT_USING_SMP
  108. /* install IPI handle */
  109. rt_hw_ipi_handler_install(IRQ_ARM_MAILBOX, rt_scheduler_ipi_handler);
  110. rt_hw_interrupt_umask(IRQ_ARM_MAILBOX);
  111. enable_cpu_ipi_intr(0);
  112. #endif
  113. }
  114. #ifdef RT_USING_SMP
  115. static unsigned long cpu_release_paddr[] =
  116. {
  117. [0] = 0xd8,
  118. [1] = 0xe0,
  119. [2] = 0xe8,
  120. [3] = 0xf0,
  121. [4] = 0
  122. };
  123. void rt_hw_secondary_cpu_up(void)
  124. {
  125. int i;
  126. extern void secondary_cpu_start(void);
  127. for (i = 1; i < RT_CPUS_NR && cpu_release_paddr[i]; ++i)
  128. {
  129. __asm__ volatile ("str %0, [%1]"::"rZ"((unsigned long)secondary_cpu_start), "r"(cpu_release_paddr[i]));
  130. rt_hw_dcache_flush_range(cpu_release_paddr[i], sizeof(cpu_release_paddr[i]));
  131. __DSB();
  132. __SEV();
  133. }
  134. }
  135. void secondary_cpu_c_start(void)
  136. {
  137. int id = rt_hw_cpu_id();
  138. rt_hw_mmu_init();
  139. rt_hw_spin_lock(&_cpus_lock);
  140. rt_hw_vector_init();
  141. rt_hw_timer_init();
  142. enable_cpu_ipi_intr(id);
  143. rt_kprintf("\rcall cpu %d on success\n", id);
  144. rt_system_scheduler_start();
  145. }
  146. void rt_hw_secondary_cpu_idle_exec(void)
  147. {
  148. __WFE();
  149. }
  150. #endif