jz47xx.h 3.0 KB

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  1. #ifndef __JZ47XX_H__
  2. #define __JZ47XX_H__
  3. #define __REG8(addr) *((volatile unsigned char *)(addr))
  4. #define __REG16(addr) *((volatile unsigned short *)(addr))
  5. #define __REG32(addr) *((volatile unsigned int *)(addr))
  6. #define HARB_BASE 0xB3000000
  7. #define EMC_BASE 0xB3010000
  8. #define DMAC_BASE 0xB3020000
  9. #define UHC_BASE 0xB3030000
  10. #define UDC_BASE 0xB3040000
  11. #define LCD_BASE 0xB3050000
  12. #define CIM_BASE 0xB3060000
  13. #define ETH_BASE 0xB3100000
  14. #define NBM_BASE 0xB3F00000
  15. #define CPM_BASE 0xB0000000
  16. #define INTC_BASE 0xB0001000
  17. #define OST_BASE 0xB0002000
  18. #define RTC_BASE 0xB0003000
  19. #define WDT_BASE 0xB0004000
  20. #define GPIO_BASE 0xB0010000
  21. #define AIC_BASE 0xB0020000
  22. #define MSC_BASE 0xB0021000
  23. #define UART0_BASE 0xB0030000
  24. #define UART1_BASE 0xB0031000
  25. #define UART2_BASE 0xB0032000
  26. #define UART3_BASE 0xB0033000
  27. #define FIR_BASE 0xB0040000
  28. #define SCC_BASE 0xB0041000
  29. #define SCC0_BASE 0xB0041000
  30. #define I2C_BASE 0xB0042000
  31. #define SSI_BASE 0xB0043000
  32. #define SCC1_BASE 0xB0044000
  33. #define PWM0_BASE 0xB0050000
  34. #define PWM1_BASE 0xB0051000
  35. #define DES_BASE 0xB0060000
  36. #define UPRT_BASE 0xB0061000
  37. #define KBC_BASE 0xB0062000
  38. /* uart offset */
  39. #define UART_RDR(base) __REG8((base) + 0x00) /* R 8b H'xx */
  40. #define UART_TDR(base) __REG8((base) + 0x00) /* W 8b H'xx */
  41. #define UART_DLLR(base) __REG8((base) + 0x00) /* RW 8b H'00 */
  42. #define UART_DLHR(base) __REG8((base) + 0x04) /* RW 8b H'00 */
  43. #define UART_IER(base) __REG8((base) + 0x04) /* RW 8b H'00 */
  44. #define UART_ISR(base) __REG8((base) + 0x08) /* R 8b H'01 */
  45. #define UART_FCR(base) __REG8((base) + 0x08) /* W 8b H'00 */
  46. #define UART_LCR(base) __REG8((base) + 0x0C) /* RW 8b H'00 */
  47. #define UART_MCR(base) __REG8((base) + 0x10) /* RW 8b H'00 */
  48. #define UART_LSR(base) __REG8((base) + 0x14) /* R 8b H'00 */
  49. #define UART_MSR(base) __REG8((base) + 0x18) /* R 8b H'00 */
  50. #define UART_SPR(base) __REG8((base) + 0x1C) /* RW 8b H'00 */
  51. #define UART_MCR(base) __REG8((base) + 0x10) /* RW 8b H'00 */
  52. #define UART_SIRCR(base) __REG8((base) + 0x20) /* RW 8b H'00 */
  53. /* interrupt controller */
  54. #define INTC_ISR __REG32(INTC_BASE + 0x00)
  55. #define INTC_IMR __REG32(INTC_BASE + 0x04)
  56. #define INTC_IMSR __REG32(INTC_BASE + 0x08)
  57. #define INTC_IMCR __REG32(INTC_BASE + 0x0c)
  58. #define INTC_IPR __REG32(INTC_BASE + 0x10)
  59. #define IRQ_I2C 1
  60. #define IRQ_PS2 2
  61. #define IRQ_UPRT 3
  62. #define IRQ_CORE 4
  63. #define IRQ_UART3 6
  64. #define IRQ_UART2 7
  65. #define IRQ_UART1 8
  66. #define IRQ_UART0 9
  67. #define IRQ_SCC1 10
  68. #define IRQ_SCC0 11
  69. #define IRQ_UDC 12
  70. #define IRQ_UHC 13
  71. #define IRQ_MSC 14
  72. #define IRQ_RTC 15
  73. #define IRQ_FIR 16
  74. #define IRQ_SSI 17
  75. #define IRQ_CIM 18
  76. #define IRQ_ETH 19
  77. #define IRQ_AIC 20
  78. #define IRQ_DMAC 21
  79. #define IRQ_OST2 22
  80. #define IRQ_OST1 23
  81. #define IRQ_OST0 24
  82. #define IRQ_GPIO3 25
  83. #define IRQ_GPIO2 26
  84. #define IRQ_GPIO1 27
  85. #define IRQ_GPIO0 28
  86. #define IRQ_LCD 30
  87. #define SYSTEM_STACK 0x8000ffe8 /* the kernel system stack address */
  88. #endif