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spi_flash_w25qxx.c 12 KB

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  1. /*
  2. * File : spi_flash_w25qxx.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along
  17. * with this program; if not, write to the Free Software Foundation, Inc.,
  18. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19. *
  20. * Change Logs:
  21. * Date Author Notes
  22. * 2011-12-16 aozima the first version
  23. * 2012-05-06 aozima can page write.
  24. * 2012-08-23 aozima add flash lock.
  25. * 2012-08-24 aozima fixed write status register BUG.
  26. */
  27. #include <stdint.h>
  28. #include <rtdevice.h>
  29. #include "spi_flash.h"
  30. #include "spi_flash_w25qxx.h"
  31. #define FLASH_DEBUG
  32. #ifdef FLASH_DEBUG
  33. #define FLASH_TRACE rt_kprintf
  34. #else
  35. #define FLASH_TRACE(...)
  36. #endif /* #ifdef FLASH_DEBUG */
  37. #define PAGE_SIZE 4096
  38. /* JEDEC Manufacturer��s ID */
  39. #define MF_ID (0xEF)
  40. /* JEDEC Device ID: Memory type and Capacity */
  41. #define MTC_W25Q80_BV (0x4014) /* W25Q80BV */
  42. #define MTC_W25Q16_BV_CL_CV (0x4015) /* W25Q16BV W25Q16CL W25Q16CV */
  43. #define MTC_W25Q16_DW (0x6015) /* W25Q16DW */
  44. #define MTC_W25Q32_BV (0x4016) /* W25Q32BV */
  45. #define MTC_W25Q32_DW (0x6016) /* W25Q32DW */
  46. #define MTC_W25Q64_BV_CV (0x4017) /* W25Q64BV W25Q64CV */
  47. #define MTC_W25Q64_DW (0x4017) /* W25Q64DW */
  48. #define MTC_W25Q128_BV (0x4018) /* W25Q128BV */
  49. #define MTC_W25Q256_FV (TBD) /* W25Q256FV */
  50. /* command list */
  51. #define CMD_WRSR (0x01) /* Write Status Register */
  52. #define CMD_PP (0x02) /* Page Program */
  53. #define CMD_READ (0x03) /* Read Data */
  54. #define CMD_WRDI (0x04) /* Write Disable */
  55. #define CMD_RDSR1 (0x05) /* Read Status Register-1 */
  56. #define CMD_WREN (0x06) /* Write Enable */
  57. #define CMD_FAST_READ (0x0B) /* Fast Read */
  58. #define CMD_ERASE_4K (0x20) /* Sector Erase:4K */
  59. #define CMD_RDSR2 (0x35) /* Read Status Register-2 */
  60. #define CMD_ERASE_32K (0x52) /* 32KB Block Erase */
  61. #define CMD_JEDEC_ID (0x9F) /* Read JEDEC ID */
  62. #define CMD_ERASE_full (0xC7) /* Chip Erase */
  63. #define CMD_ERASE_64K (0xD8) /* 64KB Block Erase */
  64. #define DUMMY (0xFF)
  65. static struct spi_flash_device spi_flash_device;
  66. static void flash_lock(struct spi_flash_device * flash_device)
  67. {
  68. rt_mutex_take(&flash_device->lock, RT_WAITING_FOREVER);
  69. }
  70. static void flash_unlock(struct spi_flash_device * flash_device)
  71. {
  72. rt_mutex_release(&flash_device->lock);
  73. }
  74. static uint8_t w25qxx_read_status(void)
  75. {
  76. return rt_spi_sendrecv8(spi_flash_device.rt_spi_device, CMD_RDSR1);
  77. }
  78. static void w25qxx_wait_busy(void)
  79. {
  80. while( w25qxx_read_status() & (0x01));
  81. }
  82. /** \brief read [size] byte from [offset] to [buffer]
  83. *
  84. * \param offset uint32_t unit : byte
  85. * \param buffer uint8_t*
  86. * \param size uint32_t unit : byte
  87. * \return uint32_t byte for read
  88. *
  89. */
  90. static uint32_t w25qxx_read(uint32_t offset, uint8_t * buffer, uint32_t size)
  91. {
  92. uint8_t send_buffer[4];
  93. send_buffer[0] = CMD_WRDI;
  94. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  95. send_buffer[0] = CMD_READ;
  96. send_buffer[1] = (uint8_t)(offset>>16);
  97. send_buffer[2] = (uint8_t)(offset>>8);
  98. send_buffer[3] = (uint8_t)(offset);
  99. rt_spi_send_then_recv(spi_flash_device.rt_spi_device,
  100. send_buffer, 4,
  101. buffer, size);
  102. return size;
  103. }
  104. /** \brief write N page on [page]
  105. *
  106. * \param page_addr uint32_t unit : byte (4096 * N,1 page = 4096byte)
  107. * \param buffer const uint8_t*
  108. * \return uint32_t
  109. *
  110. */
  111. uint32_t w25qxx_page_write(uint32_t page_addr, const uint8_t* buffer)
  112. {
  113. uint32_t index;
  114. uint8_t send_buffer[4];
  115. RT_ASSERT((page_addr&0xFF) == 0); /* page addr must align to 256byte. */
  116. send_buffer[0] = CMD_WREN;
  117. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  118. send_buffer[0] = CMD_ERASE_4K;
  119. send_buffer[1] = (page_addr >> 16);
  120. send_buffer[2] = (page_addr >> 8);
  121. send_buffer[3] = (page_addr);
  122. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 4);
  123. w25qxx_wait_busy(); // wait erase done.
  124. for(index=0; index < (PAGE_SIZE / 256); index++)
  125. {
  126. send_buffer[0] = CMD_WREN;
  127. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  128. send_buffer[0] = CMD_PP;
  129. send_buffer[1] = (uint8_t)(page_addr >> 16);
  130. send_buffer[2] = (uint8_t)(page_addr >> 8);
  131. send_buffer[3] = (uint8_t)(page_addr);
  132. rt_spi_send_then_send(spi_flash_device.rt_spi_device,
  133. send_buffer,
  134. 4,
  135. buffer,
  136. 256);
  137. buffer += 256;
  138. page_addr += 256;
  139. w25qxx_wait_busy();
  140. }
  141. send_buffer[0] = CMD_WRDI;
  142. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  143. return PAGE_SIZE;
  144. }
  145. /* RT-Thread device interface */
  146. static rt_err_t w25qxx_flash_init(rt_device_t dev)
  147. {
  148. return RT_EOK;
  149. }
  150. static rt_err_t w25qxx_flash_open(rt_device_t dev, rt_uint16_t oflag)
  151. {
  152. uint8_t send_buffer[3];
  153. flash_lock((struct spi_flash_device *)dev);
  154. send_buffer[0] = CMD_WREN;
  155. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  156. send_buffer[0] = CMD_WRSR;
  157. send_buffer[1] = 0;
  158. send_buffer[2] = 0;
  159. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 3);
  160. w25qxx_wait_busy();
  161. flash_unlock((struct spi_flash_device *)dev);
  162. return RT_EOK;
  163. }
  164. static rt_err_t w25qxx_flash_close(rt_device_t dev)
  165. {
  166. return RT_EOK;
  167. }
  168. static rt_err_t w25qxx_flash_control(rt_device_t dev, rt_uint8_t cmd, void *args)
  169. {
  170. RT_ASSERT(dev != RT_NULL);
  171. if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
  172. {
  173. struct rt_device_blk_geometry *geometry;
  174. geometry = (struct rt_device_blk_geometry *)args;
  175. if (geometry == RT_NULL) return -RT_ERROR;
  176. geometry->bytes_per_sector = spi_flash_device.geometry.bytes_per_sector;
  177. geometry->sector_count = spi_flash_device.geometry.sector_count;
  178. geometry->block_size = spi_flash_device.geometry.block_size;
  179. }
  180. return RT_EOK;
  181. }
  182. static rt_size_t w25qxx_flash_read(rt_device_t dev,
  183. rt_off_t pos,
  184. void* buffer,
  185. rt_size_t size)
  186. {
  187. flash_lock((struct spi_flash_device *)dev);
  188. w25qxx_read(pos*spi_flash_device.geometry.bytes_per_sector,
  189. buffer,
  190. size*spi_flash_device.geometry.bytes_per_sector);
  191. flash_unlock((struct spi_flash_device *)dev);
  192. return size;
  193. }
  194. static rt_size_t w25qxx_flash_write(rt_device_t dev,
  195. rt_off_t pos,
  196. const void* buffer,
  197. rt_size_t size)
  198. {
  199. rt_size_t i = 0;
  200. rt_size_t block = size;
  201. const uint8_t * ptr = buffer;
  202. flash_lock((struct spi_flash_device *)dev);
  203. while(block--)
  204. {
  205. w25qxx_page_write((pos + i)*spi_flash_device.geometry.bytes_per_sector,
  206. ptr);
  207. ptr += PAGE_SIZE;
  208. i++;
  209. }
  210. flash_unlock((struct spi_flash_device *)dev);
  211. return size;
  212. }
  213. rt_err_t w25qxx_init(const char * flash_device_name, const char * spi_device_name)
  214. {
  215. struct rt_spi_device * rt_spi_device;
  216. /* initialize mutex */
  217. if (rt_mutex_init(&spi_flash_device.lock, spi_device_name, RT_IPC_FLAG_FIFO) != RT_EOK)
  218. {
  219. rt_kprintf("init sd lock mutex failed\n");
  220. return -RT_ENOSYS;
  221. }
  222. rt_spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
  223. if(rt_spi_device == RT_NULL)
  224. {
  225. FLASH_TRACE("spi device %s not found!\r\n", spi_device_name);
  226. return -RT_ENOSYS;
  227. }
  228. spi_flash_device.rt_spi_device = rt_spi_device;
  229. /* config spi */
  230. {
  231. struct rt_spi_configuration cfg;
  232. cfg.data_width = 8;
  233. cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible: Mode 0 and Mode 3 */
  234. cfg.max_hz = 50 * 1000 * 1000; /* 50M */
  235. rt_spi_configure(spi_flash_device.rt_spi_device, &cfg);
  236. }
  237. /* init flash */
  238. {
  239. rt_uint8_t cmd;
  240. rt_uint8_t id_recv[3];
  241. uint16_t memory_type_capacity;
  242. flash_lock(&spi_flash_device);
  243. cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */
  244. rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
  245. cmd = CMD_WRDI;
  246. rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
  247. /* read flash id */
  248. cmd = CMD_JEDEC_ID;
  249. rt_spi_send_then_recv(spi_flash_device.rt_spi_device, &cmd, 1, id_recv, 3);
  250. flash_unlock(&spi_flash_device);
  251. if(id_recv[0] != MF_ID)
  252. {
  253. FLASH_TRACE("Manufacturers ID error!\r\n");
  254. FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]);
  255. return -RT_ENOSYS;
  256. }
  257. spi_flash_device.geometry.bytes_per_sector = 4096;
  258. spi_flash_device.geometry.block_size = 4096; /* block erase: 4k */
  259. /* get memory type and capacity */
  260. memory_type_capacity = id_recv[1];
  261. memory_type_capacity = (memory_type_capacity << 8) | id_recv[2];
  262. if(memory_type_capacity == MTC_W25Q128_BV)
  263. {
  264. FLASH_TRACE("W25Q128BV detection\r\n");
  265. spi_flash_device.geometry.sector_count = 4096;
  266. }
  267. else if(memory_type_capacity == MTC_W25Q64_BV_CV)
  268. {
  269. FLASH_TRACE("W25Q64BV or W25Q64CV detection\r\n");
  270. spi_flash_device.geometry.sector_count = 2048;
  271. }
  272. else if(memory_type_capacity == MTC_W25Q64_DW)
  273. {
  274. FLASH_TRACE("W25Q64DW detection\r\n");
  275. spi_flash_device.geometry.sector_count = 2048;
  276. }
  277. else if(memory_type_capacity == MTC_W25Q32_BV)
  278. {
  279. FLASH_TRACE("W25Q32BV detection\r\n");
  280. spi_flash_device.geometry.sector_count = 1024;
  281. }
  282. else if(memory_type_capacity == MTC_W25Q32_DW)
  283. {
  284. FLASH_TRACE("W25Q32DW detection\r\n");
  285. spi_flash_device.geometry.sector_count = 1024;
  286. }
  287. else if(memory_type_capacity == MTC_W25Q16_BV_CL_CV)
  288. {
  289. FLASH_TRACE("W25Q16BV or W25Q16CL or W25Q16CV detection\r\n");
  290. spi_flash_device.geometry.sector_count = 512;
  291. }
  292. else if(memory_type_capacity == MTC_W25Q16_DW)
  293. {
  294. FLASH_TRACE("W25Q16DW detection\r\n");
  295. spi_flash_device.geometry.sector_count = 512;
  296. }
  297. else if(memory_type_capacity == MTC_W25Q80_BV)
  298. {
  299. FLASH_TRACE("W25Q80BV detection\r\n");
  300. spi_flash_device.geometry.sector_count = 256;
  301. }
  302. else
  303. {
  304. FLASH_TRACE("Memory Capacity error!\r\n");
  305. return -RT_ENOSYS;
  306. }
  307. }
  308. /* register device */
  309. spi_flash_device.flash_device.type = RT_Device_Class_Block;
  310. spi_flash_device.flash_device.init = w25qxx_flash_init;
  311. spi_flash_device.flash_device.open = w25qxx_flash_open;
  312. spi_flash_device.flash_device.close = w25qxx_flash_close;
  313. spi_flash_device.flash_device.read = w25qxx_flash_read;
  314. spi_flash_device.flash_device.write = w25qxx_flash_write;
  315. spi_flash_device.flash_device.control = w25qxx_flash_control;
  316. /* no private */
  317. spi_flash_device.flash_device.user_data = RT_NULL;
  318. rt_device_register(&spi_flash_device.flash_device, flash_device_name,
  319. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
  320. return RT_EOK;
  321. }