drv_spi.c 11 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-03-06 BalanceTWK first version
  9. * 2022-04-16 wolfJane fix spixfer, add time out check
  10. */
  11. #include <board.h>
  12. #include <rtthread.h>
  13. #include <rtdevice.h>
  14. #ifdef RT_USING_SPI
  15. #ifdef BSP_USING_SPI
  16. #if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6)
  17. #include "drv_spi.h"
  18. #define DRV_DEBUG
  19. #define LOG_TAG "drv.spi"
  20. #include <drv_log.h>
  21. #define SPI_TIME_OUT (1000)
  22. enum
  23. {
  24. #ifdef BSP_USING_SPI1
  25. SPI1_INDEX,
  26. #endif
  27. #ifdef BSP_USING_SPI2
  28. SPI2_INDEX,
  29. #endif
  30. #ifdef BSP_USING_SPI3
  31. SPI3_INDEX,
  32. #endif
  33. #ifdef BSP_USING_SPI4
  34. SPI4_INDEX,
  35. #endif
  36. #ifdef BSP_USING_SPI5
  37. SPI5_INDEX,
  38. #endif
  39. #ifdef BSP_USING_SPI6
  40. SPI6_INDEX,
  41. #endif
  42. };
  43. struct n32_spi_config
  44. {
  45. SPI_Module *module;
  46. char *bus_name;
  47. };
  48. /* n32 spi dirver class */
  49. struct n32_spi
  50. {
  51. SPI_InitType SPI_InitStructure;
  52. struct n32_spi_config *config;
  53. struct rt_spi_configuration *cfg;
  54. struct rt_spi_bus spi_bus;
  55. };
  56. static struct n32_spi_config spi_config[] =
  57. {
  58. #ifdef BSP_USING_SPI1
  59. {
  60. .module = SPI1,
  61. .bus_name = "spi1",
  62. },
  63. #endif
  64. #ifdef BSP_USING_SPI2
  65. {
  66. .module = SPI2,
  67. .bus_name = "spi2",
  68. },
  69. #endif
  70. #ifdef BSP_USING_SPI3
  71. {
  72. .module = SPI3,
  73. .bus_name = "spi3",
  74. },
  75. #endif
  76. };
  77. static struct n32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0};
  78. static rt_err_t n32_spi_init(struct n32_spi *spi_drv, struct rt_spi_configuration *cfg)
  79. {
  80. RT_ASSERT(spi_drv != RT_NULL);
  81. RT_ASSERT(cfg != RT_NULL);
  82. SPI_InitType *SPI_InitStructure = &spi_drv->SPI_InitStructure;
  83. SPI_Module *spi_handle = spi_drv->config->module;
  84. /* GPIO configuration ------------------------------------------------------*/
  85. n32_msp_spi_init(spi_drv->config->module);
  86. if (cfg->mode & RT_SPI_SLAVE)
  87. {
  88. /* SPI_InitStructure->SpiMode = SPI_MODE_SLAVE; */
  89. return -RT_ERROR;
  90. }
  91. else
  92. {
  93. SPI_InitStructure->SpiMode = SPI_MODE_MASTER;
  94. }
  95. if (cfg->mode & RT_SPI_3WIRE)
  96. {
  97. SPI_InitStructure->DataDirection = SPI_DIR_SINGLELINE_TX;
  98. }
  99. else
  100. {
  101. SPI_InitStructure->DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX;
  102. }
  103. if (cfg->data_width == 8)
  104. {
  105. SPI_InitStructure->DataLen = SPI_DATA_SIZE_8BITS;
  106. }
  107. else if (cfg->data_width == 16)
  108. {
  109. SPI_InitStructure->DataLen = SPI_DATA_SIZE_16BITS;
  110. }
  111. else
  112. {
  113. return -RT_EIO;
  114. }
  115. if (cfg->mode & RT_SPI_CPHA)
  116. {
  117. SPI_InitStructure->CLKPHA = SPI_CLKPHA_SECOND_EDGE;
  118. }
  119. else
  120. {
  121. SPI_InitStructure->CLKPHA = SPI_CLKPHA_FIRST_EDGE;
  122. }
  123. if (cfg->mode & RT_SPI_CPOL)
  124. {
  125. SPI_InitStructure->CLKPOL = SPI_CLKPOL_HIGH;
  126. }
  127. else
  128. {
  129. SPI_InitStructure->CLKPOL = SPI_CLKPOL_LOW;
  130. }
  131. if (cfg->mode & RT_SPI_NO_CS)
  132. {
  133. SPI_InitStructure->NSS = SPI_NSS_HARD;
  134. }
  135. else
  136. {
  137. SPI_InitStructure->NSS = SPI_NSS_SOFT;
  138. }
  139. RCC_ClocksType RCC_Clock;
  140. RCC_GetClocksFreqValue(&RCC_Clock);
  141. rt_uint64_t SPI_APB_CLOCK;
  142. if (SPI1 == spi_handle)
  143. {
  144. SPI_APB_CLOCK = RCC_Clock.Pclk1Freq;
  145. }
  146. else if (SPI2 == spi_handle || SPI3 == spi_handle)
  147. {
  148. SPI_APB_CLOCK = RCC_Clock.Pclk2Freq;
  149. }
  150. if (cfg->max_hz >= SPI_APB_CLOCK / 2)
  151. {
  152. SPI_InitStructure->BaudRatePres = SPI_BR_PRESCALER_2;
  153. }
  154. else if (cfg->max_hz >= SPI_APB_CLOCK / 4)
  155. {
  156. SPI_InitStructure->BaudRatePres = SPI_BR_PRESCALER_4;
  157. }
  158. else if (cfg->max_hz >= SPI_APB_CLOCK / 8)
  159. {
  160. SPI_InitStructure->BaudRatePres = SPI_BR_PRESCALER_8;
  161. }
  162. else if (cfg->max_hz >= SPI_APB_CLOCK / 16)
  163. {
  164. SPI_InitStructure->BaudRatePres = SPI_BR_PRESCALER_16;
  165. }
  166. else if (cfg->max_hz >= SPI_APB_CLOCK / 32)
  167. {
  168. SPI_InitStructure->BaudRatePres = SPI_BR_PRESCALER_32;
  169. }
  170. else if (cfg->max_hz >= SPI_APB_CLOCK / 64)
  171. {
  172. SPI_InitStructure->BaudRatePres = SPI_BR_PRESCALER_64;
  173. }
  174. else if (cfg->max_hz >= SPI_APB_CLOCK / 128)
  175. {
  176. SPI_InitStructure->BaudRatePres = SPI_BR_PRESCALER_128;
  177. }
  178. else
  179. {
  180. SPI_InitStructure->BaudRatePres = SPI_BR_PRESCALER_256;
  181. }
  182. if (cfg->mode & RT_SPI_MSB)
  183. {
  184. SPI_InitStructure->FirstBit = SPI_FB_MSB;
  185. }
  186. else
  187. {
  188. SPI_InitStructure->FirstBit = SPI_FB_LSB;
  189. }
  190. SPI_InitStructure->CRCPoly = 7;
  191. SPI_Init(spi_handle, SPI_InitStructure);
  192. /* Enable SPI_MASTER TXE interrupt */
  193. SPI_I2S_EnableInt(spi_handle, SPI_I2S_INT_TE, ENABLE);
  194. /* Enable SPI_MASTER */
  195. SPI_Enable(spi_handle, ENABLE);
  196. return RT_EOK;
  197. }
  198. static rt_err_t spi_configure(struct rt_spi_device *device,
  199. struct rt_spi_configuration *configuration)
  200. {
  201. RT_ASSERT(device != RT_NULL);
  202. RT_ASSERT(configuration != RT_NULL);
  203. struct n32_spi *spi_drv = rt_container_of(device->bus, struct n32_spi, spi_bus);
  204. spi_drv->cfg = configuration;
  205. return n32_spi_init(spi_drv, configuration);
  206. }
  207. static rt_ssize_t _spi_recv(SPI_Module *hspi,
  208. uint8_t *tx_buff,
  209. uint8_t *rx_buff,
  210. uint32_t length,
  211. uint32_t timeout)
  212. {
  213. /* Init tickstart for timeout management*/
  214. uint32_t tickstart = rt_tick_get();
  215. uint8_t dat = 0;
  216. if ((tx_buff == RT_NULL) && (rx_buff == RT_NULL) || (length == 0))
  217. {
  218. return -RT_EIO;
  219. }
  220. while (length--)
  221. {
  222. while (SPI_I2S_GetStatus(hspi, SPI_I2S_TE_FLAG) == RESET)
  223. {
  224. if ((rt_tick_get() - tickstart) > timeout)
  225. {
  226. return RT_ETIMEOUT;
  227. }
  228. }
  229. SPI_I2S_TransmitData(hspi, *tx_buff++);
  230. while (SPI_I2S_GetStatus(hspi, SPI_I2S_RNE_FLAG) == RESET)
  231. {
  232. if ((rt_tick_get() - tickstart) > timeout)
  233. {
  234. return RT_ETIMEOUT;
  235. }
  236. }
  237. dat = SPI_I2S_ReceiveData(hspi);
  238. if (rx_buff)
  239. {
  240. *rx_buff++ = dat;
  241. }
  242. }
  243. return RT_EOK;
  244. }
  245. static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  246. {
  247. rt_size_t send_length;
  248. rt_uint8_t *recv_buf;
  249. const rt_uint8_t *send_buf;
  250. rt_ssize_t stat = RT_EOK;
  251. /* Check Direction parameter */
  252. RT_ASSERT(device != RT_NULL);
  253. RT_ASSERT(device->bus != RT_NULL);
  254. RT_ASSERT(device->bus->parent.user_data != RT_NULL);
  255. RT_ASSERT(message != RT_NULL);
  256. struct n32_spi *spi_drv = rt_container_of(device->bus, struct n32_spi, spi_bus);
  257. struct n32_hw_spi_cs *cs = device->parent.user_data;
  258. SPI_Module *spi_handle = spi_drv->config->module;
  259. if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS))
  260. {
  261. if (device->config.mode & RT_SPI_CS_HIGH)
  262. {
  263. GPIO_SetBits(cs->module, cs->pin);
  264. }
  265. else
  266. {
  267. GPIO_ResetBits(cs->module, cs->pin);
  268. }
  269. }
  270. send_length = message->length;
  271. recv_buf = message->recv_buf;
  272. send_buf = message->send_buf;
  273. /* start once data exchange in DMA mode */
  274. if (message->send_buf && message->recv_buf)
  275. {
  276. LOG_D("%s:%d", __FUNCTION__, __LINE__);
  277. stat = -RT_EIO;
  278. }
  279. else if (message->send_buf)
  280. {
  281. stat = _spi_recv(spi_handle,
  282. (uint8_t *)send_buf,
  283. RT_NULL,
  284. send_length,
  285. SPI_TIME_OUT);
  286. }
  287. else
  288. {
  289. rt_memset(recv_buf, 0xff, send_length);
  290. stat = _spi_recv(spi_handle,
  291. (uint8_t *)recv_buf,
  292. (uint8_t *)recv_buf,
  293. send_length,
  294. SPI_TIME_OUT);
  295. }
  296. if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS))
  297. {
  298. if (device->config.mode & RT_SPI_CS_HIGH)
  299. {
  300. GPIO_ResetBits(cs->module, cs->pin);
  301. }
  302. else
  303. {
  304. GPIO_SetBits(cs->module, cs->pin);
  305. }
  306. }
  307. if (stat != RT_EOK)
  308. {
  309. send_length = 0;
  310. }
  311. return send_length;
  312. }
  313. static const struct rt_spi_ops n32_spi_ops =
  314. {
  315. .configure = spi_configure,
  316. .xfer = spixfer,
  317. };
  318. static int rt_hw_spi_bus_init(void)
  319. {
  320. rt_err_t result;
  321. for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
  322. {
  323. spi_bus_obj[i].config = &spi_config[i];
  324. spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
  325. result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &n32_spi_ops);
  326. RT_ASSERT(result == RT_EOK);
  327. LOG_D("%s bus init done", spi_config[i].bus_name);
  328. }
  329. return result;
  330. }
  331. int rt_hw_spi_init(void)
  332. {
  333. /* TODO: n32_get_dma_info(); */
  334. return rt_hw_spi_bus_init();
  335. }
  336. INIT_BOARD_EXPORT(rt_hw_spi_init);
  337. /**
  338. * Attach the spi device to SPI bus, this function must be used after initialization.
  339. */
  340. rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_Module *cs_gpiox, uint32_t cs_gpio_pin)
  341. {
  342. rt_err_t result;
  343. struct rt_spi_device *spi_device;
  344. struct n32_hw_spi_cs *cs_pin;
  345. GPIO_InitType GPIO_InitStructure;
  346. RT_ASSERT(bus_name != RT_NULL);
  347. RT_ASSERT(device_name != RT_NULL);
  348. /* Enable the GPIO Clock */
  349. if (cs_gpiox == GPIOA)
  350. {
  351. RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
  352. }
  353. else if (cs_gpiox == GPIOB)
  354. {
  355. RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
  356. }
  357. else if (cs_gpiox == GPIOC)
  358. {
  359. RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
  360. }
  361. else if (cs_gpiox == GPIOD)
  362. {
  363. RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOD, ENABLE);
  364. }
  365. else if (cs_gpiox == GPIOE)
  366. {
  367. RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOE, ENABLE);
  368. }
  369. else if (cs_gpiox == GPIOF)
  370. {
  371. RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOF, ENABLE);
  372. }
  373. else if (cs_gpiox == GPIOG)
  374. {
  375. RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOG, ENABLE);
  376. }
  377. /* Configure the GPIO pin */
  378. if (cs_gpio_pin <= GPIO_PIN_ALL)
  379. {
  380. GPIO_InitStructure.Pin = cs_gpio_pin;
  381. GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
  382. GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  383. GPIO_InitPeripheral(cs_gpiox, &GPIO_InitStructure);
  384. }
  385. /* attach the device to spi bus*/
  386. spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  387. RT_ASSERT(spi_device != RT_NULL);
  388. cs_pin = (struct n32_hw_spi_cs *)rt_malloc(sizeof(struct n32_hw_spi_cs));
  389. RT_ASSERT(cs_pin != RT_NULL);
  390. cs_pin->module = cs_gpiox;
  391. cs_pin->pin = cs_gpio_pin;
  392. result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
  393. if (result != RT_EOK)
  394. {
  395. LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
  396. }
  397. RT_ASSERT(result == RT_EOK);
  398. LOG_D("%s attach to %s done", device_name, bus_name);
  399. return result;
  400. }
  401. #endif /* BSP_USING_SPIx */
  402. #endif /* BSP_USING_SPI */
  403. #endif /* RT_USING_SPI */