drv_sdmmc.c 19 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-05-23 liuduanfei first version
  9. * 2020-08-25 wanghaijing add sdmmmc2
  10. * 2023-03-26 wdfk-prog Distinguish between SDMMC and SDIO drivers
  11. */
  12. #include "board.h"
  13. #ifdef RT_USING_SDIO
  14. #if !defined(BSP_USING_SDIO1) && !defined(BSP_USING_SDIO2)
  15. #error "Please define at least one BSP_USING_SDIOx"
  16. #endif
  17. #include "drv_sdmmc.h"
  18. #define DBG_TAG "drv.sdmmc"
  19. #ifdef DRV_DEBUG
  20. #define DBG_LVL DBG_LOG
  21. #else
  22. #define DBG_LVL DBG_INFO
  23. #endif /* DRV_DEBUG */
  24. #include <rtdbg.h>
  25. static struct stm32_sdio_class sdio_obj;
  26. static struct rt_mmcsd_host *host1;
  27. static struct rt_mmcsd_host *host2;
  28. #define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (1000000)
  29. #define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
  30. #define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex);
  31. struct sdio_pkg
  32. {
  33. struct rt_mmcsd_cmd *cmd;
  34. void *buff;
  35. rt_uint32_t flag;
  36. };
  37. struct rthw_sdio
  38. {
  39. struct rt_mmcsd_host *host;
  40. struct stm32_sdio_des sdio_des;
  41. struct rt_event event;
  42. struct rt_mutex mutex;
  43. struct sdio_pkg *pkg;
  44. };
  45. rt_align(SDIO_ALIGN_LEN)
  46. static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
  47. /**
  48. * @brief This function get order from sdio.
  49. * @param data
  50. * @retval sdio order
  51. */
  52. static int get_order(rt_uint32_t data)
  53. {
  54. int order = 0;
  55. switch (data)
  56. {
  57. case 1:
  58. order = 0;
  59. break;
  60. case 2:
  61. order = 1;
  62. break;
  63. case 4:
  64. order = 2;
  65. break;
  66. case 8:
  67. order = 3;
  68. break;
  69. case 16:
  70. order = 4;
  71. break;
  72. case 32:
  73. order = 5;
  74. break;
  75. case 64:
  76. order = 6;
  77. break;
  78. case 128:
  79. order = 7;
  80. break;
  81. case 256:
  82. order = 8;
  83. break;
  84. case 512:
  85. order = 9;
  86. break;
  87. case 1024:
  88. order = 10;
  89. break;
  90. case 2048:
  91. order = 11;
  92. break;
  93. case 4096:
  94. order = 12;
  95. break;
  96. case 8192:
  97. order = 13;
  98. break;
  99. case 16384:
  100. order = 14;
  101. break;
  102. default :
  103. order = 0;
  104. break;
  105. }
  106. return order;
  107. }
  108. /**
  109. * @brief This function wait sdio cmd completed.
  110. * @param sdio rthw_sdio
  111. * @retval None
  112. */
  113. static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
  114. {
  115. rt_uint32_t status;
  116. struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
  117. struct rt_mmcsd_data *data = cmd->data;
  118. SD_TypeDef *hsd = sdio->sdio_des.hw_sdio.Instance;
  119. if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
  120. rt_tick_from_millisecond(5000), &status) != RT_EOK)
  121. {
  122. LOG_E("wait cmd completed timeout");
  123. cmd->err = -RT_ETIMEOUT;
  124. return;
  125. }
  126. if (sdio->pkg == RT_NULL)
  127. {
  128. return;
  129. }
  130. /* Get Card Specific Data */
  131. cmd->resp[0] = hsd->RESP1;
  132. if (resp_type(cmd) == RESP_R2)
  133. {
  134. cmd->resp[1] = hsd->RESP2;
  135. cmd->resp[2] = hsd->RESP3;
  136. cmd->resp[3] = hsd->RESP4;
  137. }
  138. /* Check for error conditions */
  139. if (status & SDIO_ERRORS)
  140. {
  141. if ((status & SDMMC_STA_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4)))
  142. {
  143. cmd->err = RT_EOK;
  144. }
  145. else
  146. {
  147. cmd->err = -RT_ERROR;
  148. }
  149. }
  150. else
  151. {
  152. cmd->err = RT_EOK;
  153. }
  154. if (status & SDMMC_IT_CTIMEOUT)
  155. {
  156. cmd->err = -RT_ETIMEOUT;
  157. }
  158. if (status & SDMMC_IT_DCRCFAIL)
  159. {
  160. data->err = -RT_ERROR;
  161. }
  162. if (status & SDMMC_IT_DTIMEOUT)
  163. {
  164. data->err = -RT_ETIMEOUT;
  165. }
  166. if (cmd->err == RT_EOK)
  167. {
  168. LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
  169. }
  170. else
  171. {
  172. LOG_D("err:0x%08x, %s%s%s%s%s%s%s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d",
  173. status,
  174. status & HW_SDIO_IT_CCRCFAIL ? "CCRCFAIL " : "",
  175. status & HW_SDIO_IT_DCRCFAIL ? "DCRCFAIL " : "",
  176. status & HW_SDIO_IT_CTIMEOUT ? "CTIMEOUT " : "",
  177. status & HW_SDIO_IT_DTIMEOUT ? "DTIMEOUT " : "",
  178. status & HW_SDIO_IT_TXUNDERR ? "TXUNDERR " : "",
  179. status & HW_SDIO_IT_RXOVERR ? "RXOVERR " : "",
  180. status == 0 ? "NULL" : "",
  181. cmd->cmd_code,
  182. cmd->arg,
  183. data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
  184. data ? data->blks * data->blksize : 0,
  185. data ? data->blksize : 0
  186. );
  187. }
  188. }
  189. /**
  190. * @brief This function send command.
  191. * @param sdio rthw_sdio
  192. * @param pkg sdio package
  193. * @retval None
  194. */
  195. static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
  196. {
  197. struct rt_mmcsd_cmd *cmd = pkg->cmd;
  198. struct rt_mmcsd_data *data = cmd->data;
  199. SD_TypeDef *hsd = sdio->sdio_des.hw_sdio.Instance;
  200. rt_uint32_t reg_cmd;
  201. rt_event_control(&sdio->event, RT_IPC_CMD_RESET, RT_NULL);
  202. /* save pkg */
  203. sdio->pkg = pkg;
  204. LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d\n",
  205. cmd->cmd_code,
  206. cmd->arg,
  207. resp_type(cmd) == RESP_NONE ? "NONE" : "",
  208. resp_type(cmd) == RESP_R1 ? "R1" : "",
  209. resp_type(cmd) == RESP_R1B ? "R1B" : "",
  210. resp_type(cmd) == RESP_R2 ? "R2" : "",
  211. resp_type(cmd) == RESP_R3 ? "R3" : "",
  212. resp_type(cmd) == RESP_R4 ? "R4" : "",
  213. resp_type(cmd) == RESP_R5 ? "R5" : "",
  214. resp_type(cmd) == RESP_R6 ? "R6" : "",
  215. resp_type(cmd) == RESP_R7 ? "R7" : "",
  216. data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
  217. data ? data->blks * data->blksize : 0,
  218. data ? data->blksize : 0
  219. );
  220. /* open irq */
  221. __HAL_SD_ENABLE_IT(&sdio->sdio_des.hw_sdio, SDIO_MASKR_ALL);
  222. reg_cmd = cmd->cmd_code | SDMMC_CMD_CPSMEN;
  223. /* data pre configuration */
  224. if (data != RT_NULL)
  225. {
  226. SCB_CleanInvalidateDCache();
  227. reg_cmd |= SDMMC_CMD_CMDTRANS;
  228. __HAL_SD_DISABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_MASK_CMDRENDIE | SDMMC_MASK_CMDSENTIE);
  229. hsd->DTIMER = HW_SDIO_DATATIMEOUT;
  230. hsd->DLEN = data->blks * data->blksize;
  231. hsd->DCTRL = (get_order(data->blksize) << 4) | (data->flags & DATA_DIR_READ ? SDMMC_DCTRL_DTDIR : 0);
  232. #ifndef SOC_SERIES_STM32H7RS
  233. hsd->IDMABASE0 = (rt_uint32_t)cache_buf;
  234. #else
  235. hsd->IDMABASER = (rt_uint32_t)cache_buf;
  236. #endif
  237. hsd->IDMACTRL = SDMMC_IDMA_IDMAEN;
  238. }
  239. /* config cmd reg */
  240. if (resp_type(cmd) == RESP_NONE)
  241. reg_cmd |= SDMMC_RESPONSE_NO;
  242. else if (resp_type(cmd) == RESP_R2)
  243. reg_cmd |= SDMMC_RESPONSE_LONG;
  244. else
  245. reg_cmd |= SDMMC_RESPONSE_SHORT;
  246. hsd->ARG = cmd->arg;
  247. hsd->CMD = reg_cmd;
  248. /* wait completed */
  249. rthw_sdio_wait_completed(sdio);
  250. /* Waiting for data to be sent to completion */
  251. if (data != RT_NULL)
  252. {
  253. volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS;
  254. while (count && (hsd->STA & SDMMC_STA_DPSMACT))
  255. {
  256. count--;
  257. }
  258. if ((count == 0) || (hsd->STA & SDIO_ERRORS))
  259. {
  260. cmd->err = -RT_ERROR;
  261. }
  262. }
  263. /* data post configuration */
  264. if (data != RT_NULL)
  265. {
  266. if (data->flags & DATA_DIR_READ)
  267. {
  268. rt_memcpy(data->buf, cache_buf, data->blks * data->blksize);
  269. SCB_CleanInvalidateDCache();
  270. }
  271. }
  272. }
  273. /**
  274. * @brief This function send sdio request.
  275. * @param sdio rthw_sdio
  276. * @param req request
  277. * @retval None
  278. */
  279. static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
  280. {
  281. struct sdio_pkg pkg;
  282. struct rthw_sdio *sdio = host->private_data;
  283. struct rt_mmcsd_data *data;
  284. RTHW_SDIO_LOCK(sdio);
  285. if (req->cmd != RT_NULL)
  286. {
  287. rt_memset(&pkg, 0, sizeof(pkg));
  288. data = req->cmd->data;
  289. pkg.cmd = req->cmd;
  290. if (data != RT_NULL)
  291. {
  292. rt_uint32_t size = data->blks * data->blksize;
  293. RT_ASSERT(size <= SDIO_BUFF_SIZE);
  294. if (data->flags & DATA_DIR_WRITE)
  295. {
  296. rt_memcpy(cache_buf, data->buf, size);
  297. }
  298. }
  299. rthw_sdio_send_command(sdio, &pkg);
  300. }
  301. if (req->stop != RT_NULL)
  302. {
  303. rt_memset(&pkg, 0, sizeof(pkg));
  304. pkg.cmd = req->stop;
  305. rthw_sdio_send_command(sdio, &pkg);
  306. }
  307. RTHW_SDIO_UNLOCK(sdio);
  308. mmcsd_req_complete(sdio->host);
  309. }
  310. /**
  311. * @brief This function config sdio.
  312. * @param host rt_mmcsd_host
  313. * @param io_cfg rt_mmcsd_io_cfg
  314. * @retval None
  315. */
  316. static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
  317. {
  318. rt_uint32_t temp, clk_src;
  319. rt_uint32_t clk = io_cfg->clock;
  320. struct rthw_sdio *sdio = host->private_data;
  321. SD_HandleTypeDef *hsd = &sdio->sdio_des.hw_sdio;
  322. SDMMC_InitTypeDef Init = {0};
  323. rt_uint32_t sdmmc_clk = sdio->sdio_des.clk_get();
  324. if (sdmmc_clk < 400 * 1000)
  325. {
  326. LOG_E("The clock rate is too low! rata:%d", sdmmc_clk);
  327. return;
  328. }
  329. if (clk > host->freq_max)
  330. clk = host->freq_max;
  331. if (clk > sdmmc_clk)
  332. {
  333. LOG_W("Setting rate is greater than clock source rate.");
  334. clk = sdmmc_clk;
  335. }
  336. LOG_D("clk:%dK width:%s%s%s power:%s%s%s",
  337. clk / 1000,
  338. io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "",
  339. io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "",
  340. io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "",
  341. io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "",
  342. io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "",
  343. io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""
  344. );
  345. if (sdmmc_clk != 0U)
  346. {
  347. hsd->Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ);
  348. /* Configure the SDMMC peripheral */
  349. Init.ClockEdge = hsd->Init.ClockEdge;
  350. Init.ClockPowerSave = hsd->Init.ClockPowerSave;
  351. if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
  352. {
  353. Init.BusWide = SDMMC_BUS_WIDE_4B;
  354. }
  355. else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
  356. {
  357. Init.BusWide = SDMMC_BUS_WIDE_8B;
  358. }
  359. else
  360. {
  361. Init.BusWide = SDMMC_BUS_WIDE_1B;
  362. }
  363. Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
  364. /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
  365. if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ)))
  366. {
  367. Init.ClockDiv = hsd->Init.ClockDiv;
  368. }
  369. //CARD_ULTRA_HIGH_SPEED :UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards and <104Mo/s for SDR104, Spec version 3.01
  370. else if (MMCSD_TIMING_UHS_SDR50 <= io_cfg->timing && io_cfg->timing <= MMCSD_TIMING_UHS_DDR50)
  371. {
  372. /* UltraHigh speed SD card,user Clock div */
  373. Init.ClockDiv = hsd->Init.ClockDiv;
  374. }
  375. //CARD_HIGH_SPEED: High Speed Card <25Mo/s , Spec version 2.00
  376. else if (io_cfg->timing == MMCSD_TIMING_SD_HS)
  377. {
  378. /* High speed SD card, Max Frequency = 50Mhz */
  379. if (hsd->Init.ClockDiv == 0U)
  380. {
  381. if (sdmmc_clk > SD_HIGH_SPEED_FREQ)
  382. {
  383. Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
  384. }
  385. else
  386. {
  387. Init.ClockDiv = hsd->Init.ClockDiv;
  388. }
  389. }
  390. else
  391. {
  392. if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ)
  393. {
  394. Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
  395. }
  396. else
  397. {
  398. Init.ClockDiv = hsd->Init.ClockDiv;
  399. }
  400. }
  401. }
  402. //CARD_NORMAL_SPEED: Normal Speed Card <12.5Mo/s , Spec Version 1.01
  403. else if (io_cfg->timing == MMCSD_TIMING_LEGACY)
  404. {
  405. /* No High speed SD card, Max Frequency = 25Mhz */
  406. if (hsd->Init.ClockDiv == 0U)
  407. {
  408. if (sdmmc_clk > SD_NORMAL_SPEED_FREQ)
  409. {
  410. Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
  411. }
  412. else
  413. {
  414. Init.ClockDiv = hsd->Init.ClockDiv;
  415. }
  416. }
  417. else
  418. {
  419. if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ)
  420. {
  421. Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
  422. }
  423. else
  424. {
  425. Init.ClockDiv = hsd->Init.ClockDiv;
  426. }
  427. }
  428. }
  429. (void)SDMMC_Init(hsd->Instance, Init);
  430. }
  431. switch ((io_cfg->power_mode)&0X03)
  432. {
  433. case MMCSD_POWER_OFF:
  434. /* Set Power State to OFF */
  435. (void)SDMMC_PowerState_OFF(hsd->Instance);
  436. break;
  437. case MMCSD_POWER_UP:
  438. /* In F4 series chips, 0X01 is reserved bit and has no practical effect.
  439. For F7 series chips, 0X01 is power-on after power-off,The SDMMC disables the function and the card clock stops.
  440. For H7 series chips, 0X03 is the power-on function.
  441. */
  442. case MMCSD_POWER_ON:
  443. /* Set Power State to ON */
  444. (void)SDMMC_PowerState_ON(hsd->Instance);
  445. break;
  446. default:
  447. LOG_W("unknown power mode %d", io_cfg->power_mode);
  448. break;
  449. }
  450. }
  451. /**
  452. * @brief This function update sdio interrupt.
  453. * @param host rt_mmcsd_host
  454. * @param enable
  455. * @retval None
  456. */
  457. void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable)
  458. {
  459. struct rthw_sdio *sdio = host->private_data;
  460. if (enable)
  461. {
  462. LOG_D("enable sdio irq");
  463. __HAL_SD_ENABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_IT_SDIOIT);
  464. }
  465. else
  466. {
  467. LOG_D("disable sdio irq");
  468. __HAL_SD_ENABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_IT_SDIOIT);
  469. }
  470. }
  471. /**
  472. * @brief This function detect sdcard.
  473. * @param host rt_mmcsd_host
  474. * @retval 0x01
  475. */
  476. static rt_int32_t rthw_sd_detect(struct rt_mmcsd_host *host)
  477. {
  478. LOG_D("try to detect device");
  479. return 0x01;
  480. }
  481. /**
  482. * @brief This function interrupt process function.
  483. * @param host rt_mmcsd_host
  484. * @retval None
  485. */
  486. void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
  487. {
  488. struct rthw_sdio *sdio = host->private_data;
  489. rt_uint32_t intstatus = sdio->sdio_des.hw_sdio.Instance->STA;
  490. /* clear irq flag*/
  491. __HAL_SD_CLEAR_FLAG(&sdio->sdio_des.hw_sdio, intstatus);
  492. rt_event_send(&sdio->event, intstatus);
  493. }
  494. static const struct rt_mmcsd_host_ops ops =
  495. {
  496. rthw_sdio_request,
  497. rthw_sdio_iocfg,
  498. rthw_sd_detect,
  499. rthw_sdio_irq_update,
  500. };
  501. /**
  502. * @brief This function create mmcsd host.
  503. * @param sdio_des stm32_sdio_des
  504. * @retval rt_mmcsd_host
  505. */
  506. struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des)
  507. {
  508. struct rt_mmcsd_host *host;
  509. struct rthw_sdio *sdio = RT_NULL;
  510. if (sdio_des == RT_NULL)
  511. {
  512. LOG_E("L:%d F:%s",(sdio_des == RT_NULL ? "sdio_des is NULL" : ""));
  513. return RT_NULL;
  514. }
  515. sdio = rt_malloc(sizeof(struct rthw_sdio));
  516. if (sdio == RT_NULL)
  517. {
  518. LOG_E("L:%d F:%s malloc rthw_sdio fail");
  519. return RT_NULL;
  520. }
  521. rt_memset(sdio, 0, sizeof(struct rthw_sdio));
  522. host = mmcsd_alloc_host();
  523. if (host == RT_NULL)
  524. {
  525. LOG_E("L:%d F:%s mmcsd alloc host fail");
  526. rt_free(sdio);
  527. return RT_NULL;
  528. }
  529. rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des));
  530. #ifdef BSP_USING_SDIO1
  531. if(sdio_des->hw_sdio.Instance == SDMMC1)
  532. {
  533. rt_event_init(&sdio->event, "sdio1", RT_IPC_FLAG_FIFO);
  534. rt_mutex_init(&sdio->mutex, "sdio1", RT_IPC_FLAG_PRIO);
  535. }
  536. #endif /* BSP_USING_SDIO1 */
  537. #ifdef BSP_USING_SDIO2
  538. if(sdio_des->hw_sdio.Instance == SDMMC2)
  539. {
  540. rt_event_init(&sdio->event, "sdio2", RT_IPC_FLAG_FIFO);
  541. rt_mutex_init(&sdio->mutex, "sdio2", RT_IPC_FLAG_PRIO);
  542. }
  543. #endif /* BSP_USING_SDIO2 */
  544. /* set host default attributes */
  545. host->ops = &ops;
  546. host->freq_min = 400 * 1000;
  547. host->freq_max = SDIO_MAX_FREQ;
  548. host->valid_ocr = 0X00FFFF80;/* The voltage range supported is 1.65v-3.6v */
  549. #ifndef SDIO_USING_1_BIT
  550. host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED;
  551. #else
  552. host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
  553. #endif
  554. host->max_seg_size = SDIO_BUFF_SIZE;
  555. host->max_dma_segs = 1;
  556. host->max_blk_size = 512;
  557. host->max_blk_count = 512;
  558. /* link up host and sdio */
  559. sdio->host = host;
  560. host->private_data = sdio;
  561. rthw_sdio_irq_update(host, 1);
  562. /* ready to change */
  563. mmcsd_change(host);
  564. return host;
  565. }
  566. /**
  567. * @brief This function get stm32 sdio clock.
  568. * @param hw_sdio: stm32_sdio
  569. * @retval PCLK2Freq
  570. */
  571. static rt_uint32_t stm32_sdio_clock_get(void)
  572. {
  573. #ifndef SOC_SERIES_STM32H7RS
  574. return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
  575. #else
  576. return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC12);
  577. #endif
  578. }
  579. void SDMMC1_IRQHandler(void)
  580. {
  581. /* enter interrupt */
  582. rt_interrupt_enter();
  583. /* Process All SDIO Interrupt Sources */
  584. rthw_sdio_irq_process(host1);
  585. /* leave interrupt */
  586. rt_interrupt_leave();
  587. }
  588. void SDMMC2_IRQHandler(void)
  589. {
  590. /* enter interrupt */
  591. rt_interrupt_enter();
  592. /* Process All SDIO Interrupt Sources */
  593. rthw_sdio_irq_process(host2);
  594. /* leave interrupt */
  595. rt_interrupt_leave();
  596. }
  597. int rt_hw_sdio_init(void)
  598. {
  599. #ifdef BSP_USING_SDIO1
  600. struct stm32_sdio_des sdio_des1 = {0};
  601. sdio_des1.hw_sdio.Instance = SDMMC1;
  602. HAL_SD_MspInit(&sdio_des1.hw_sdio);
  603. HAL_NVIC_SetPriority(SDMMC1_IRQn, 2, 0);
  604. HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
  605. sdio_des1.clk_get = stm32_sdio_clock_get;
  606. host1 = sdio_host_create(&sdio_des1);
  607. if (host1 == RT_NULL)
  608. {
  609. LOG_E("host1 create fail");
  610. return -RT_ERROR;
  611. }
  612. #endif /* BSP_USING_SDIO1 */
  613. #ifdef BSP_USING_SDIO2
  614. struct stm32_sdio_des sdio_des2 = {0};
  615. sdio_des2.hw_sdio.Instance = SDMMC2;
  616. HAL_SD_MspInit(&sdio_des2.hw_sdio);
  617. HAL_NVIC_SetPriority(SDMMC2_IRQn, 2, 0);
  618. HAL_NVIC_EnableIRQ(SDMMC2_IRQn);
  619. sdio_des2.clk_get = stm32_sdio_clock_get;
  620. host2 = sdio_host_create(&sdio_des2);
  621. if (host2 == RT_NULL)
  622. {
  623. LOG_E("host2 create fail");
  624. return -RT_ERROR;
  625. }
  626. #endif /* BSP_USING_SDIO2 */
  627. return RT_EOK;
  628. }
  629. INIT_DEVICE_EXPORT(rt_hw_sdio_init);
  630. void stm32_mmcsd_change(void)
  631. {
  632. #ifdef BSP_USING_SDIO1
  633. mmcsd_change(host1);
  634. #endif /* BSP_USING_SDIO2 */
  635. #ifdef BSP_USING_SDIO2
  636. mmcsd_change(host2);
  637. #endif /* BSP_USING_SDIO2 */
  638. }
  639. #endif /* RT_USING_SDIO */