reg_pmm.h 2.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778
  1. /** @file reg_pmm.h
  2. * @brief PMM Register Layer Header File
  3. * @date 29.May.2013
  4. * @version 03.05.02
  5. *
  6. * This file contains:
  7. * - Definitions
  8. * - Types
  9. * .
  10. * which are relevant for the PMM driver.
  11. */
  12. /* (c) Texas Instruments 2009-2013, All rights reserved. */
  13. #ifndef __REG_PMM_H__
  14. #define __REG_PMM_H__
  15. #include "sys_common.h"
  16. /* USER CODE BEGIN (0) */
  17. /* USER CODE END */
  18. /* Pmm Register Frame Definition */
  19. /** @struct pmmBase
  20. * @brief Pmm Register Frame Definition
  21. *
  22. * This type is used to access the Pmm Registers.
  23. */
  24. /** @typedef pmmBase_t
  25. * @brief Pmm Register Frame Type Definition
  26. *
  27. * This type is used to access the Pmm Registers.
  28. */
  29. typedef volatile struct pmmBase
  30. {
  31. uint32 LOGICPDPWRCTRL0; /**< 0x0000: Logic Power Domain Control Register 0 */
  32. uint32 rsvd1[3U]; /**< 0x0004: Reserved*/
  33. uint32 MEMPDPWRCTRL0; /**< 0x0010: Memory Power Domain Control Register 0 */
  34. uint32 rsvd2[3U]; /**< 0x0014: Reserved*/
  35. uint32 PDCLKDISREG; /**< 0x0020: Power Domain Clock Disable Register */
  36. uint32 PDCLKDISSETREG; /**< 0x0024: Power Domain Clock Disable Set Register */
  37. uint32 PDCLKDISCLRREG; /**< 0x0028: Power Domain Clock Disable Clear Register */
  38. uint32 rsvd3[5U]; /**< 0x002C: Reserved */
  39. uint32 LOGICPDPWRSTAT[4U]; /**< 0x0040, 0x0044, 0x0048, 0x004C: Logic Power Domain Power Status Register
  40. - 0: PD2
  41. - 1: PD3
  42. - 2: PD4
  43. - 3: PD5 */
  44. uint32 rsvd4[12U]; /**< 0x0050: Reserved*/
  45. uint32 MEMPDPWRSTAT[3U]; /**< 0x0080, 0x0084, 0x0088: Memory Power Domain Power Status Register
  46. - 0: RAM_PD1
  47. - 1: RAM_PD2
  48. - 2: RAM_PD3 */
  49. uint32 rsvd5[5U]; /**< 0x008C: Reserved */
  50. uint32 GLOBALCTRL1; /**< 0x00A0: Global Control Register 1 */
  51. uint32 rsvd6; /**< 0x00A4: Reserved */
  52. uint32 GLOBALSTAT; /**< 0x00A8: Global Status Register */
  53. uint32 PRCKEYREG; /**< 0x00AC: PSCON Diagnostic Compare Key Register */
  54. uint32 LPDDCSTAT1; /**< 0x00B0: LogicPD PSCON Diagnostic Compare Status Register 1 */
  55. uint32 LPDDCSTAT2; /**< 0x00B4: LogicPD PSCON Diagnostic Compare Status Register 2 */
  56. uint32 MPDDCSTAT1; /**< 0x00B8: Memory PD PSCON Diagnostic Compare Status Register 1 */
  57. uint32 MPDDCSTAT2; /**< 0x00BC: Memory PD PSCON Diagnostic Compare Status Register 2 */
  58. uint32 ISODIAGSTAT; /**< 0x00C0: Isolation Diagnostic Status Register */
  59. }pmmBase_t;
  60. /** @def pmmREG
  61. * @brief Pmm Register Frame Pointer
  62. *
  63. * This pointer is used by the Pmm driver to access the Pmm registers.
  64. */
  65. #define pmmREG ((pmmBase_t *)0xFFFF0000U)
  66. /* USER CODE BEGIN (1) */
  67. /* USER CODE END */
  68. #endif