gd32vf103_exmc.c 7.2 KB

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  1. /*!
  2. \file gd32vf103_exmc.c
  3. \brief EXMC driver
  4. \version 2019-6-5, V1.0.0, firmware for GD32VF103
  5. */
  6. /*
  7. Copyright (c) 2019, GigaDevice Semiconductor Inc.
  8. Redistribution and use in source and binary forms, with or without modification,
  9. are permitted provided that the following conditions are met:
  10. 1. Redistributions of source code must retain the above copyright notice, this
  11. list of conditions and the following disclaimer.
  12. 2. Redistributions in binary form must reproduce the above copyright notice,
  13. this list of conditions and the following disclaimer in the documentation
  14. and/or other materials provided with the distribution.
  15. 3. Neither the name of the copyright holder nor the names of its contributors
  16. may be used to endorse or promote products derived from this software without
  17. specific prior written permission.
  18. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  19. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  20. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  22. INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23. NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  24. PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  25. WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  27. OF SUCH DAMAGE.
  28. */
  29. #include "gd32vf103_exmc.h"
  30. /* EXMC bank0 register reset value */
  31. #define BANK0_SNCTL0_REGION_RESET ((uint32_t)0x000030DAU)
  32. #define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU)
  33. /* EXMC register bit offset */
  34. #define SNCTL_NRMUX_OFFSET ((uint32_t)1U)
  35. #define SNCTL_WREN_OFFSET ((uint32_t)12U)
  36. #define SNCTL_NRWTEN_OFFSET ((uint32_t)13U)
  37. #define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U)
  38. #define SNTCFG_AHLD_OFFSET ((uint32_t)4U)
  39. #define SNTCFG_DSET_OFFSET ((uint32_t)8U)
  40. #define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U)
  41. /*!
  42. \brief deinitialize EXMC NOR/SRAM region
  43. \param[in] norsram_region: select the region of bank0
  44. \arg EXMC_BANK0_NORSRAM_REGIONx(x=0)
  45. \param[out] none
  46. \retval none
  47. */
  48. void exmc_norsram_deinit(uint32_t norsram_region)
  49. {
  50. /* reset the registers */
  51. if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){
  52. EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET;
  53. }
  54. EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET;
  55. }
  56. /*!
  57. \brief initialize the structure exmc_norsram_parameter_struct
  58. \param[in] none
  59. \param[out] exmc_norsram_init_struct: the initialized structure exmc_norsram_parameter_struct pointer
  60. \retval none
  61. */
  62. void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
  63. {
  64. /* configure the structure with default value */
  65. exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0;
  66. exmc_norsram_init_struct->address_data_mux = ENABLE;
  67. exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM;
  68. exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_16B;
  69. exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW;
  70. exmc_norsram_init_struct->memory_write = ENABLE;
  71. exmc_norsram_init_struct->nwait_signal = ENABLE;
  72. exmc_norsram_init_struct->asyn_wait = DISABLE;
  73. /* read/write timing configure */
  74. exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU;
  75. exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU;
  76. exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU;
  77. exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU;
  78. }
  79. /*!
  80. \brief initialize EXMC NOR/SRAM region
  81. \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter
  82. norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0
  83. asyn_wait: ENABLE or DISABLE
  84. nwait_signal: ENABLE or DISABLE
  85. memory_write: ENABLE or DISABLE
  86. nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH
  87. databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B
  88. memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR
  89. address_data_mux: ENABLE
  90. read_write_timing: structure exmc_norsram_timing_parameter_struct set the time
  91. \param[out] none
  92. \retval none
  93. */
  94. void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
  95. {
  96. uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U;
  97. /* get the register value */
  98. snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region);
  99. /* clear relative bits */
  100. snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_NRWTPOL |
  101. EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_NRMUX));
  102. snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) |
  103. exmc_norsram_init_struct->memory_type |
  104. exmc_norsram_init_struct->databus_width |
  105. exmc_norsram_init_struct->nwait_polarity |
  106. (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) |
  107. (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) |
  108. (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET);
  109. sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )|
  110. (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) |
  111. (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) |
  112. (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT );
  113. /* nor flash access enable */
  114. if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){
  115. snctl |= (uint32_t)EXMC_SNCTL_NREN;
  116. }
  117. /* configure the registers */
  118. EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl;
  119. EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg;
  120. }
  121. /*!
  122. \brief enable EXMC NOR/PSRAM bank region
  123. \param[in] norsram_region: specify the region of NOR/PSRAM bank
  124. \arg EXMC_BANK0_NORSRAM_REGIONx(x=0)
  125. \param[out] none
  126. \retval none
  127. */
  128. void exmc_norsram_enable(uint32_t norsram_region)
  129. {
  130. EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN;
  131. }
  132. /*!
  133. \brief disable EXMC NOR/PSRAM bank region
  134. \param[in] norsram_region: specify the region of NOR/PSRAM bank
  135. \arg EXMC_BANK0_NORSRAM_REGIONx(x=0)
  136. \param[out] none
  137. \retval none
  138. */
  139. void exmc_norsram_disable(uint32_t norsram_region)
  140. {
  141. EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN;
  142. }