drv_smc911x.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569
  1. /*
  2. * Copyright (c) 2006-2020, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020/12/31 Bernard Add license info
  9. */
  10. #include <board.h>
  11. #include <rtthread.h>
  12. #include <netif/ethernetif.h>
  13. #include <lwipopts.h>
  14. #include <automac.h>
  15. #define MAX_ADDR_LEN 6
  16. #define SMC911X_EMAC_DEVICE(eth) (struct eth_device_smc911x*)(eth)
  17. #include "drv_smc911x.h"
  18. #define DRIVERNAME "EMAC"
  19. struct eth_device_smc911x
  20. {
  21. /* inherit from Ethernet device */
  22. struct eth_device parent;
  23. /* interface address info. */
  24. rt_uint8_t enetaddr[MAX_ADDR_LEN]; /* MAC address */
  25. uint32_t iobase;
  26. uint32_t irqno;
  27. };
  28. static struct eth_device_smc911x _emac;
  29. int udelay(int value)
  30. {
  31. return 0;
  32. }
  33. int mdelay(int value)
  34. {
  35. return 0;
  36. }
  37. #if defined (CONFIG_SMC911X_32_BIT)
  38. rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
  39. {
  40. return *(volatile uint32_t*)(dev->iobase + offset);
  41. }
  42. rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
  43. {
  44. *(volatile uint32_t*)(dev->iobase + offset) = val;
  45. }
  46. #elif defined (CONFIG_SMC911X_16_BIT)
  47. rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
  48. {
  49. volatile uint16_t *addr_16 = (uint16_t *)(dev->iobase + offset);
  50. return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
  51. }
  52. rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
  53. {
  54. *(volatile uint16_t *)(dev->iobase + offset) = (uint16_t)val;
  55. *(volatile uint16_t *)(dev->iobase + offset + 2) = (uint16_t)(val >> 16);
  56. }
  57. #else
  58. #error "SMC911X: undefined bus width"
  59. #endif /* CONFIG_SMC911X_16_BIT */
  60. struct chip_id
  61. {
  62. uint16_t id;
  63. char *name;
  64. };
  65. static const struct chip_id chip_ids[] =
  66. {
  67. { CHIP_89218,"LAN89218" },
  68. { CHIP_9115, "LAN9115" },
  69. { CHIP_9116, "LAN9116" },
  70. { CHIP_9117, "LAN9117" },
  71. { CHIP_9118, "LAN9118" },
  72. { CHIP_9211, "LAN9211" },
  73. { CHIP_9215, "LAN9215" },
  74. { CHIP_9216, "LAN9216" },
  75. { CHIP_9217, "LAN9217" },
  76. { CHIP_9218, "LAN9218" },
  77. { CHIP_9220, "LAN9220" },
  78. { CHIP_9221, "LAN9221" },
  79. { 0, RT_NULL },
  80. };
  81. static uint32_t smc911x_get_mac_csr(struct eth_device_smc911x *dev, uint8_t reg)
  82. {
  83. while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
  84. smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
  85. while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
  86. return smc911x_reg_read(dev, MAC_CSR_DATA);
  87. }
  88. static void smc911x_set_mac_csr(struct eth_device_smc911x *dev, uint8_t reg, uint32_t data)
  89. {
  90. while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
  91. smc911x_reg_write(dev, MAC_CSR_DATA, data);
  92. smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
  93. while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
  94. }
  95. static int smc911x_detect_chip(struct eth_device_smc911x *dev)
  96. {
  97. unsigned long val, i;
  98. val = smc911x_reg_read(dev, BYTE_TEST);
  99. if (val == 0xffffffff)
  100. {
  101. /* Special case -- no chip present */
  102. return -1;
  103. }
  104. else if (val != 0x87654321)
  105. {
  106. rt_kprintf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
  107. return -1;
  108. }
  109. val = smc911x_reg_read(dev, ID_REV) >> 16;
  110. for (i = 0; chip_ids[i].id != 0; i++)
  111. {
  112. if (chip_ids[i].id == val) break;
  113. }
  114. if (!chip_ids[i].id)
  115. {
  116. rt_kprintf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
  117. return -1;
  118. }
  119. return 0;
  120. }
  121. static void smc911x_reset(struct eth_device_smc911x *dev)
  122. {
  123. int timeout;
  124. /*
  125. * Take out of PM setting first
  126. * Device is already wake up if PMT_CTRL_READY bit is set
  127. */
  128. if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0)
  129. {
  130. /* Write to the bytetest will take out of powerdown */
  131. smc911x_reg_write(dev, BYTE_TEST, 0x0);
  132. timeout = 10;
  133. while (timeout-- && !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
  134. udelay(10);
  135. if (timeout < 0)
  136. {
  137. rt_kprintf(DRIVERNAME
  138. ": timeout waiting for PM restore\n");
  139. return;
  140. }
  141. }
  142. /* Disable interrupts */
  143. smc911x_reg_write(dev, INT_EN, 0);
  144. smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
  145. timeout = 1000;
  146. while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
  147. udelay(10);
  148. if (timeout < 0)
  149. {
  150. rt_kprintf(DRIVERNAME ": reset timeout\n");
  151. return;
  152. }
  153. /* Reset the FIFO level and flow control settings */
  154. smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
  155. smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
  156. /* Set to LED outputs */
  157. smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
  158. }
  159. static void smc911x_handle_mac_address(struct eth_device_smc911x *dev)
  160. {
  161. unsigned long addrh, addrl;
  162. uint8_t *m = dev->enetaddr;
  163. addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
  164. addrh = m[4] | (m[5] << 8);
  165. smc911x_set_mac_csr(dev, ADDRL, addrl);
  166. smc911x_set_mac_csr(dev, ADDRH, addrh);
  167. }
  168. static int smc911x_eth_phy_read(struct eth_device_smc911x *dev,
  169. uint8_t phy, uint8_t reg, uint16_t *val)
  170. {
  171. while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) ;
  172. smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY);
  173. while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) ;
  174. *val = smc911x_get_mac_csr(dev, MII_DATA);
  175. return 0;
  176. }
  177. static int smc911x_eth_phy_write(struct eth_device_smc911x *dev,
  178. uint8_t phy, uint8_t reg, uint16_t val)
  179. {
  180. while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
  181. ;
  182. smc911x_set_mac_csr(dev, MII_DATA, val);
  183. smc911x_set_mac_csr(dev, MII_ACC,
  184. phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
  185. while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
  186. ;
  187. return 0;
  188. }
  189. static int smc911x_phy_reset(struct eth_device_smc911x *dev)
  190. {
  191. uint32_t reg;
  192. reg = smc911x_reg_read(dev, PMT_CTRL);
  193. reg &= ~0xfffff030;
  194. reg |= PMT_CTRL_PHY_RST;
  195. smc911x_reg_write(dev, PMT_CTRL, reg);
  196. mdelay(100);
  197. return 0;
  198. }
  199. static void smc911x_phy_configure(struct eth_device_smc911x *dev)
  200. {
  201. int timeout;
  202. uint16_t status;
  203. smc911x_phy_reset(dev);
  204. smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET);
  205. mdelay(1);
  206. smc911x_eth_phy_write(dev, 1, MII_ADVERTISE, 0x01e1);
  207. smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
  208. timeout = 5000;
  209. do
  210. {
  211. mdelay(1);
  212. if ((timeout--) == 0)
  213. goto err_out;
  214. if (smc911x_eth_phy_read(dev, 1, MII_BMSR, &status) != 0)
  215. goto err_out;
  216. }
  217. while (!(status & BMSR_LSTATUS));
  218. return;
  219. err_out:
  220. rt_kprintf(DRIVERNAME ": autonegotiation timed out\n");
  221. }
  222. static void smc911x_enable(struct eth_device_smc911x *dev)
  223. {
  224. /* Enable TX */
  225. smc911x_reg_write(dev, HW_CFG, 8 << 16 | HW_CFG_SF);
  226. smc911x_reg_write(dev, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
  227. smc911x_reg_write(dev, TX_CFG, TX_CFG_TX_ON);
  228. /* no padding to start of packets */
  229. smc911x_reg_write(dev, RX_CFG, 0);
  230. smc911x_set_mac_csr(dev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
  231. MAC_CR_HBDIS);
  232. }
  233. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  234. /* wrapper for smc911x_eth_phy_read */
  235. static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
  236. int reg)
  237. {
  238. uint16_t val = 0;
  239. struct eth_device_smc911x *dev = eth_get_dev_by_name(bus->name);
  240. if (dev)
  241. {
  242. int retval = smc911x_eth_phy_read(dev, phy, reg, &val);
  243. if (retval < 0)
  244. return retval;
  245. return val;
  246. }
  247. return -ENODEV;
  248. }
  249. /* wrapper for smc911x_eth_phy_write */
  250. static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
  251. int reg, uint16_t val)
  252. {
  253. struct eth_device_smc911x *dev = eth_get_dev_by_name(bus->name);
  254. if (dev)
  255. return smc911x_eth_phy_write(dev, phy, reg, val);
  256. return -ENODEV;
  257. }
  258. #endif
  259. static void smc911x_isr(int vector, void *param)
  260. {
  261. uint32_t status;
  262. struct eth_device_smc911x *emac;
  263. emac = SMC911X_EMAC_DEVICE(param);
  264. status = smc911x_reg_read(emac, INT_STS);
  265. if (status & INT_STS_RSFL)
  266. {
  267. eth_device_ready(&emac->parent);
  268. }
  269. smc911x_reg_write(emac, INT_STS, status);
  270. return ;
  271. }
  272. static rt_err_t smc911x_emac_init(rt_device_t dev)
  273. {
  274. // uint32_t value;
  275. struct eth_device_smc911x *emac;
  276. emac = SMC911X_EMAC_DEVICE(dev);
  277. RT_ASSERT(emac != RT_NULL);
  278. smc911x_reset(emac);
  279. /* Configure the PHY, initialize the link state */
  280. smc911x_phy_configure(emac);
  281. smc911x_handle_mac_address(emac);
  282. /* Turn on Tx + Rx */
  283. smc911x_enable(emac);
  284. #if 1
  285. /* Interrupt on every received packet */
  286. smc911x_reg_write(emac, FIFO_INT, 0x01 << 8);
  287. smc911x_reg_write(emac, INT_EN, INT_EN_RDFL_EN | INT_EN_RSFL_EN);
  288. /* enable interrupt */
  289. smc911x_reg_write(emac, INT_CFG, INT_CFG_IRQ_EN | INT_CFG_IRQ_POL | INT_CFG_IRQ_TYPE);
  290. #else
  291. /* disable interrupt */
  292. smc911x_reg_write(emac, INT_EN, 0);
  293. value = smc911x_reg_read(emac, INT_CFG);
  294. value &= ~INT_CFG_IRQ_EN;
  295. smc911x_reg_write(emac, INT_CFG, value);
  296. #endif
  297. rt_hw_interrupt_install(emac->irqno, smc911x_isr, emac, "smc911x");
  298. rt_hw_interrupt_umask(emac->irqno);
  299. return RT_EOK;
  300. }
  301. static rt_err_t smc911x_emac_control(rt_device_t dev, int cmd, void *args)
  302. {
  303. struct eth_device_smc911x *emac;
  304. emac = SMC911X_EMAC_DEVICE(dev);
  305. RT_ASSERT(emac != RT_NULL);
  306. switch(cmd)
  307. {
  308. case NIOCTL_GADDR:
  309. /* get MAC address */
  310. if(args) rt_memcpy(args, emac->enetaddr, 6);
  311. else return -RT_ERROR;
  312. break;
  313. default :
  314. break;
  315. }
  316. return RT_EOK;
  317. }
  318. /* Ethernet device interface */
  319. /* transmit packet. */
  320. static uint8_t tx_buf[2048];
  321. rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf* p)
  322. {
  323. struct eth_device_smc911x *emac;
  324. uint32_t *data;
  325. uint32_t tmplen;
  326. uint32_t status;
  327. uint32_t length;
  328. emac = SMC911X_EMAC_DEVICE(dev);
  329. RT_ASSERT(emac != RT_NULL);
  330. /* copy pbuf to a whole ETH frame */
  331. pbuf_copy_partial(p, tx_buf, p->tot_len, 0);
  332. /* send it out */
  333. data = (uint32_t*)tx_buf;
  334. length = p->tot_len;
  335. smc911x_reg_write(emac, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length);
  336. smc911x_reg_write(emac, TX_DATA_FIFO, length);
  337. tmplen = (length + 3) / 4;
  338. while (tmplen--)
  339. {
  340. smc911x_reg_write(emac, TX_DATA_FIFO, *data++);
  341. }
  342. /* wait for transmission */
  343. while (!((smc911x_reg_read(emac, TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16));
  344. /* get status. Ignore 'no carrier' error, it has no meaning for
  345. * full duplex operation
  346. */
  347. status = smc911x_reg_read(emac, TX_STATUS_FIFO) &
  348. (TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL |
  349. TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
  350. if (!status) return 0;
  351. rt_kprintf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
  352. status & TX_STS_LOC ? "TX_STS_LOC " : "",
  353. status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "",
  354. status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "",
  355. status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "",
  356. status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : "");
  357. return -RT_EIO;
  358. }
  359. /* reception packet. */
  360. struct pbuf *smc911x_emac_rx(rt_device_t dev)
  361. {
  362. struct pbuf* p = RT_NULL;
  363. struct eth_device_smc911x *emac;
  364. emac = SMC911X_EMAC_DEVICE(dev);
  365. RT_ASSERT(emac != RT_NULL);
  366. /* take the emac buffer to the pbuf */
  367. if ((smc911x_reg_read(emac, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16)
  368. {
  369. uint32_t status;
  370. uint32_t pktlen, tmplen;
  371. status = smc911x_reg_read(emac, RX_STATUS_FIFO);
  372. /* get frame length */
  373. pktlen = (status & RX_STS_PKT_LEN) >> 16;
  374. smc911x_reg_write(emac, RX_CFG, 0);
  375. tmplen = (pktlen + 3) / 4;
  376. /* allocate pbuf */
  377. p = pbuf_alloc(PBUF_RAW, tmplen * 4, PBUF_RAM);
  378. if (p)
  379. {
  380. uint32_t *data = (uint32_t *)p->payload;
  381. while (tmplen--)
  382. {
  383. *data++ = smc911x_reg_read(emac, RX_DATA_FIFO);
  384. }
  385. }
  386. if (status & RX_STS_ES)
  387. {
  388. rt_kprintf(DRIVERNAME ": dropped bad packet. Status: 0x%08x\n", status);
  389. }
  390. }
  391. return p;
  392. }
  393. #ifdef RT_USING_DEVICE_OPS
  394. const static struct rt_device_ops smc911x_emac_ops =
  395. {
  396. smc911x_emac_init,
  397. RT_NULL,
  398. RT_NULL,
  399. RT_NULL,
  400. RT_NULL,
  401. smc911x_emac_control
  402. };
  403. #endif
  404. int smc911x_emac_hw_init(void)
  405. {
  406. _emac.iobase = VEXPRESS_ETH_BASE;
  407. _emac.irqno = IRQ_VEXPRESS_A9_ETH;
  408. if (smc911x_detect_chip(&_emac))
  409. {
  410. rt_kprintf("no smc911x network interface found!\n");
  411. return -1;
  412. }
  413. /* set INT CFG */
  414. smc911x_reg_write(&_emac, INT_CFG, INT_CFG_IRQ_POL | INT_CFG_IRQ_TYPE);
  415. /* test MAC address */
  416. _emac.enetaddr[0] = AUTOMAC0;
  417. _emac.enetaddr[1] = AUTOMAC1;
  418. _emac.enetaddr[2] = AUTOMAC2;
  419. _emac.enetaddr[3] = AUTOMAC3;
  420. _emac.enetaddr[4] = AUTOMAC4;
  421. _emac.enetaddr[5] = AUTOMAC5;
  422. #ifdef RT_USING_DEVICE_OPS
  423. _emac.parent.parent.ops = &smc911x_emac_ops;
  424. #else
  425. _emac.parent.parent.init = smc911x_emac_init;
  426. _emac.parent.parent.open = RT_NULL;
  427. _emac.parent.parent.close = RT_NULL;
  428. _emac.parent.parent.read = RT_NULL;
  429. _emac.parent.parent.write = RT_NULL;
  430. _emac.parent.parent.control = smc911x_emac_control;
  431. #endif
  432. _emac.parent.parent.user_data = RT_NULL;
  433. _emac.parent.eth_rx = smc911x_emac_rx;
  434. _emac.parent.eth_tx = smc911x_emac_tx;
  435. /* register ETH device */
  436. eth_device_init(&(_emac.parent), "e0");
  437. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  438. {
  439. int retval;
  440. struct mii_dev *mdiodev = mdio_alloc();
  441. if (!mdiodev)
  442. return -ENOMEM;
  443. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  444. mdiodev->read = smc911x_miiphy_read;
  445. mdiodev->write = smc911x_miiphy_write;
  446. retval = mdio_register(mdiodev);
  447. if (retval < 0)
  448. return retval;
  449. }
  450. #endif
  451. eth_device_linkchange(&_emac.parent, RT_TRUE);
  452. return 0;
  453. }
  454. INIT_APP_EXPORT(smc911x_emac_hw_init);