system_at32f4xx.c 95 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-04-13 shelton first version
  9. */
  10. /** @addtogroup CMSIS
  11. * @{
  12. */
  13. /** @addtogroup at32f4xx_system
  14. * @{
  15. */
  16. /** @addtogroup at32f4xx_System_Private_Includes
  17. * @{
  18. */
  19. #include "at32f4xx.h"
  20. /**
  21. * @}
  22. */
  23. /** @addtogroup at32f4xx_System_Private_TypesDefinitions
  24. * @{
  25. */
  26. /**
  27. * @}
  28. */
  29. /** @addtogroup at32f4xx_System_Private_Defines
  30. * @{
  31. */
  32. /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
  33. frequency (after reset the HSI is used as SYSCLK source)
  34. IMPORTANT NOTE:
  35. ==============
  36. 1. After each device reset the HSI is used as System clock source.
  37. 2. Please make sure that the selected System clock doesn't exceed your device's
  38. maximum frequency.
  39. 3. If none of the define below is enabled, the HSI is used as System clock
  40. source.
  41. 4. The System clock configuration functions provided within this file assume that:
  42. - For at32f4xx devices, an external 8MHz crystal is used to drive the System clock.
  43. If you are using different crystal you have to adapt those functions accordingly.
  44. Clock (MHz)
  45. PLL from HSE or HSI
  46. SYSCLK HCLK PCLK2 PCLK1
  47. 24 24 24 24
  48. 36 36 36 36
  49. 48 48 48 24
  50. 56 56 56 28
  51. 72 72 72 36
  52. 96 96 48 48
  53. 108 108 54 54
  54. 120 120 60 60
  55. 144 144 72 72
  56. 150 150 75 75
  57. 168 168 84 84
  58. 176 176 88 88
  59. 192 192 96 96
  60. 200 200 100 100
  61. 224 224 112 112
  62. 240 240 120 120
  63. */
  64. #if defined (AT32F403xx) || defined (AT32F413xx) || \
  65. defined (AT32F415xx) || defined (AT32F403Axx)|| \
  66. defined (AT32F407xx)
  67. /* #define SYSCLK_FREQ_HSE HSE_VALUE */
  68. /* #define SYSCLK_FREQ_24MHz 24000000 */
  69. /* #define SYSCLK_FREQ_36MHz 36000000 */
  70. /* #define SYSCLK_FREQ_48MHz 48000000 */
  71. /* #define SYSCLK_FREQ_56MHz 56000000 */
  72. /* #define SYSCLK_FREQ_72MHz 72000000 */
  73. /* #define SYSCLK_FREQ_96MHz 96000000 */
  74. /* #define SYSCLK_FREQ_108MHz 108000000 */
  75. /* #define SYSCLK_FREQ_120MHz 120000000 */
  76. /* #define SYSCLK_FREQ_144MHz 144000000 */
  77. /* #define SYSCLK_FREQ_24MHz_HSI 24000000 */
  78. /* #define SYSCLK_FREQ_36MHz_HSI 36000000 */
  79. /* #define SYSCLK_FREQ_48MHz_HSI 48000000 */
  80. /* #define SYSCLK_FREQ_56MHz_HSI 56000000 */
  81. /* #define SYSCLK_FREQ_72MHz_HSI 72000000 */
  82. /* #define SYSCLK_FREQ_96MHz_HSI 96000000 */
  83. /* #define SYSCLK_FREQ_108MHz_HSI 108000000 */
  84. /* #define SYSCLK_FREQ_120MHz_HSI 120000000 */
  85. /* #define SYSCLK_FREQ_144MHz_HSI 144000000 */
  86. #endif
  87. #if defined (AT32F415xx)
  88. /* #define SYSCLK_FREQ_150MHz 150000000 */
  89. /* #define SYSCLK_FREQ_150MHz_HSI 150000000 */
  90. #endif
  91. #if defined (AT32F403xx) || defined (AT32F413xx) || \
  92. defined (AT32F403Axx)|| defined (AT32F407xx)
  93. /* #define SYSCLK_FREQ_168MHz 168000000 */
  94. /* #define SYSCLK_FREQ_176MHz 176000000 */
  95. /* #define SYSCLK_FREQ_192MHz 192000000 */
  96. /* #define SYSCLK_FREQ_200MHz 200000000 */
  97. /* #define SYSCLK_FREQ_168MHz_HSI 168000000 */
  98. /* #define SYSCLK_FREQ_176MHz_HSI 176000000 */
  99. /* #define SYSCLK_FREQ_192MHz_HSI 192000000 */
  100. /* #define SYSCLK_FREQ_200MHz_HSI 200000000 */
  101. #endif
  102. #if defined (AT32F403Axx)|| defined (AT32F407xx)
  103. /* #define SYSCLK_FREQ_224MHz 224000000 */
  104. #define SYSCLK_FREQ_240MHz 240000000
  105. /* #define SYSCLK_FREQ_224MHz_HSI 224000000 */
  106. /* #define SYSCLK_FREQ_240MHz_HSI 240000000 */
  107. #endif
  108. /*!< Uncomment the following line if you need to use external SRAM mounted
  109. (AT32 High density and XL-density devices) as data memory */
  110. /* #define DATA_IN_ExtSRAM */
  111. /*!< Uncomment the following line if you need to relocate your vector Table in
  112. Internal SRAM. */
  113. /* #define VECT_TAB_SRAM */
  114. #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
  115. This value must be a multiple of 0x200. */
  116. /**
  117. * @}
  118. */
  119. /** @addtogroup at32f4xx_System_Private_Macros
  120. * @{
  121. */
  122. /**
  123. * @}
  124. */
  125. /** @addtogroup at32f4xx_System_Private_Variables
  126. * @{
  127. */
  128. /*******************************************************************************
  129. * Clock Definitions
  130. *******************************************************************************/
  131. #ifdef SYSCLK_FREQ_HSE
  132. uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
  133. #elif defined SYSCLK_FREQ_24MHz
  134. uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
  135. #elif defined SYSCLK_FREQ_36MHz
  136. uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
  137. #elif defined SYSCLK_FREQ_48MHz
  138. uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
  139. #elif defined SYSCLK_FREQ_56MHz
  140. uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
  141. #elif defined SYSCLK_FREQ_72MHz
  142. uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
  143. #elif defined SYSCLK_FREQ_96MHz
  144. uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz; /*!< System Clock Frequency (Core Clock) */
  145. #elif defined SYSCLK_FREQ_108MHz
  146. uint32_t SystemCoreClock = SYSCLK_FREQ_108MHz; /*!< System Clock Frequency (Core Clock) */
  147. #elif defined SYSCLK_FREQ_120MHz
  148. uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz; /*!< System Clock Frequency (Core Clock) */
  149. #elif defined SYSCLK_FREQ_144MHz
  150. uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz; /*!< System Clock Frequency (Core Clock) */
  151. #elif defined SYSCLK_FREQ_150MHz
  152. uint32_t SystemCoreClock = SYSCLK_FREQ_150MHz; /*!< System Clock Frequency (Core Clock) */
  153. #elif defined SYSCLK_FREQ_168MHz
  154. uint32_t SystemCoreClock = SYSCLK_FREQ_168MHz; /*!< System Clock Frequency (Core Clock) */
  155. #elif defined SYSCLK_FREQ_176MHz
  156. uint32_t SystemCoreClock = SYSCLK_FREQ_176MHz; /*!< System Clock Frequency (Core Clock) */
  157. #elif defined SYSCLK_FREQ_192MHz
  158. uint32_t SystemCoreClock = SYSCLK_FREQ_192MHz; /*!< System Clock Frequency (Core Clock) */
  159. #elif defined SYSCLK_FREQ_200MHz
  160. uint32_t SystemCoreClock = SYSCLK_FREQ_200MHz; /*!< System Clock Frequency (Core Clock) */
  161. #elif defined SYSCLK_FREQ_224MHz
  162. uint32_t SystemCoreClock = SYSCLK_FREQ_224MHz; /*!< System Clock Frequency (Core Clock) */
  163. #elif defined SYSCLK_FREQ_240MHz
  164. uint32_t SystemCoreClock = SYSCLK_FREQ_240MHz; /*!< System Clock Frequency (Core Clock) */
  165. #elif defined SYSCLK_FREQ_24MHz_HSI
  166. uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  167. #elif defined SYSCLK_FREQ_36MHz_HSI
  168. uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  169. #elif defined SYSCLK_FREQ_48MHz_HSI
  170. uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  171. #elif defined SYSCLK_FREQ_56MHz_HSI
  172. uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  173. #elif defined SYSCLK_FREQ_72MHz_HSI
  174. uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  175. #elif defined SYSCLK_FREQ_96MHz_HSI
  176. uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  177. #elif defined SYSCLK_FREQ_108MHz_HSI
  178. uint32_t SystemCoreClock = SYSCLK_FREQ_108MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  179. #elif defined SYSCLK_FREQ_120MHz_HSI
  180. uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  181. #elif defined SYSCLK_FREQ_144MHz_HSI
  182. uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  183. #elif defined SYSCLK_FREQ_150MHz_HSI
  184. uint32_t SystemCoreClock = SYSCLK_FREQ_150MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  185. #elif defined SYSCLK_FREQ_168MHz_HSI
  186. uint32_t SystemCoreClock = SYSCLK_FREQ_168MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  187. #elif defined SYSCLK_FREQ_176MHz_HSI
  188. uint32_t SystemCoreClock = SYSCLK_FREQ_176MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  189. #elif defined SYSCLK_FREQ_192MHz_HSI
  190. uint32_t SystemCoreClock = SYSCLK_FREQ_192MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  191. #elif defined SYSCLK_FREQ_200MHz_HSI
  192. uint32_t SystemCoreClock = SYSCLK_FREQ_200MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  193. #elif defined SYSCLK_FREQ_224MHz_HSI
  194. uint32_t SystemCoreClock = SYSCLK_FREQ_224MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  195. #elif defined SYSCLK_FREQ_240MHz_HSI
  196. uint32_t SystemCoreClock = SYSCLK_FREQ_240MHz_HSI; /*!< System Clock Frequency (Core Clock) */
  197. #else /*!< HSI Selected as System Clock source */
  198. #define SYSCLK_FREQ_HSI HSI_VALUE
  199. uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
  200. #endif
  201. __I uint8_t AHBPscTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
  202. /**
  203. * @}
  204. */
  205. /** @addtogroup at32f4xx_System_Private_FunctionPrototypes
  206. * @{
  207. */
  208. static void SetSysClock(void);
  209. #ifdef SYSCLK_FREQ_HSE
  210. static void SetSysClockToHSE(void);
  211. #elif defined SYSCLK_FREQ_24MHz
  212. static void SetSysClockTo24M(void);
  213. #elif defined SYSCLK_FREQ_36MHz
  214. static void SetSysClockTo36M(void);
  215. #elif defined SYSCLK_FREQ_48MHz
  216. static void SetSysClockTo48M(void);
  217. #elif defined SYSCLK_FREQ_56MHz
  218. static void SetSysClockTo56M(void);
  219. #elif defined SYSCLK_FREQ_72MHz
  220. static void SetSysClockTo72M(void);
  221. #elif defined SYSCLK_FREQ_96MHz
  222. static void SetSysClockTo96M(void);
  223. #elif defined SYSCLK_FREQ_108MHz
  224. static void SetSysClockTo108M(void);
  225. #elif defined SYSCLK_FREQ_120MHz
  226. static void SetSysClockTo120M(void);
  227. #elif defined SYSCLK_FREQ_144MHz
  228. static void SetSysClockTo144M(void);
  229. #elif defined SYSCLK_FREQ_150MHz
  230. static void SetSysClockTo150M(void);
  231. #elif defined SYSCLK_FREQ_168MHz
  232. static void SetSysClockTo168M(void);
  233. #elif defined SYSCLK_FREQ_176MHz
  234. static void SetSysClockTo176M(void);
  235. #elif defined SYSCLK_FREQ_192MHz
  236. static void SetSysClockTo192M(void);
  237. #elif defined SYSCLK_FREQ_200MHz
  238. static void SetSysClockTo200M(void);
  239. #elif defined SYSCLK_FREQ_224MHz
  240. static void SetSysClockTo224M(void);
  241. #elif defined SYSCLK_FREQ_240MHz
  242. static void SetSysClockTo240M(void);
  243. #elif defined SYSCLK_FREQ_24MHz_HSI
  244. static void SetSysClockTo24MHSI(void);
  245. #elif defined SYSCLK_FREQ_36MHz_HSI
  246. static void SetSysClockTo36MHSI(void);
  247. #elif defined SYSCLK_FREQ_48MHz_HSI
  248. static void SetSysClockTo48MHSI(void);
  249. #elif defined SYSCLK_FREQ_56MHz_HSI
  250. static void SetSysClockTo56MHSI(void);
  251. #elif defined SYSCLK_FREQ_72MHz_HSI
  252. static void SetSysClockTo72MHSI(void);
  253. #elif defined SYSCLK_FREQ_96MHz_HSI
  254. static void SetSysClockTo96MHSI(void);
  255. #elif defined SYSCLK_FREQ_108MHz_HSI
  256. static void SetSysClockTo108MHSI(void);
  257. #elif defined SYSCLK_FREQ_120MHz_HSI
  258. static void SetSysClockTo120MHSI(void);
  259. #elif defined SYSCLK_FREQ_144MHz_HSI
  260. static void SetSysClockTo144MHSI(void);
  261. #elif defined SYSCLK_FREQ_150MHz_HSI
  262. static void SetSysClockTo150MHSI(void);
  263. #elif defined SYSCLK_FREQ_168MHz_HSI
  264. static void SetSysClockTo168MHSI(void);
  265. #elif defined SYSCLK_FREQ_176MHz_HSI
  266. static void SetSysClockTo176MHSI(void);
  267. #elif defined SYSCLK_FREQ_192MHz_HSI
  268. static void SetSysClockTo192MHSI(void);
  269. #elif defined SYSCLK_FREQ_200MHz_HSI
  270. static void SetSysClockTo200MHSI(void);
  271. #elif defined SYSCLK_FREQ_224MHz_HSI
  272. static void SetSysClockTo224MHSI(void);
  273. #elif defined SYSCLK_FREQ_240MHz_HSI
  274. static void SetSysClockTo240MHSI(void);
  275. #endif
  276. #ifdef DATA_IN_ExtSRAM
  277. static void SystemInit_ExtMemCtrl(void);
  278. #endif /* DATA_IN_ExtSRAM */
  279. /**
  280. * @}
  281. */
  282. /** @addtogroup at32f4xx_System_Private_Functions
  283. * @{
  284. */
  285. /**
  286. * @brief Setup the microcontroller system
  287. * Initialize the Embedded Flash Interface, the PLL and update the
  288. * SystemCoreClock variable.
  289. * @note This function should be used only after reset.
  290. * @param None
  291. * @retval None
  292. */
  293. void SystemInit (void)
  294. {
  295. #if defined (AT32F415xx)
  296. /* Enable low power mode, 0x40007050[bit2] */
  297. RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_PWR, ENABLE);
  298. *(volatile uint8_t *)(0x40007050) |= (uint8_t)(0x1 << 2);
  299. RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_PWR, DISABLE);
  300. #endif
  301. #if defined (__FPU_USED) && (__FPU_USED == 1U)
  302. SCB->CPACR |= ((3U << 10U * 2U) | /* set CP10 Full Access */
  303. (3U << 11U * 2U) ); /* set CP11 Full Access */
  304. #endif
  305. /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
  306. /* Set HSIEN bit */
  307. BIT_SET(RCC->CTRL, RCC_CTRL_HSIEN);
  308. /* Reset SW, AHBPSC, APB1PSC, APB2PSC, ADCPSC and CLKOUT bits */
  309. BIT_CLEAR(RCC->CFG, RCC_CFG_SYSCLKSEL | RCC_CFG_AHBPSC | \
  310. RCC_CFG_APB1PSC | RCC_CFG_APB2PSC | \
  311. RCC_CFG_ADCPSC | RCC_CFG_CLKOUT);
  312. /* Reset HSEEN, HSECFDEN and PLLEN bits */
  313. BIT_CLEAR(RCC->CTRL, RCC_CTRL_HSEEN | RCC_CTRL_HSECFDEN | \
  314. RCC_CTRL_PLLEN);
  315. /* Reset HSEBYPS bit */
  316. BIT_CLEAR(RCC->CTRL, RCC_CTRL_HSEBYPS);
  317. /* Reset PLLRC, PLLHSEPSC, PLLMUL, USBPSC and PLLRANGE bits */
  318. BIT_CLEAR(RCC->CFG, RCC_CFG_PLLRC | RCC_CFG_PLLHSEPSC | \
  319. RCC_CFG_PLLMULT | RCC_CFG_USBPSC | RCC_CFG_PLLRANGE);
  320. /* Reset USB768B, CLKOUT[3], HSICAL_KEY[7:0] */
  321. BIT_CLEAR(RCC->MISC, 0x010100FF);
  322. /* Disable all interrupts and clear pending bits */
  323. RCC->CLKINT = RCC_CLKINT_LSISTBLFC | RCC_CLKINT_LSESTBLFC | \
  324. RCC_CLKINT_HSISTBLFC | RCC_CLKINT_HSESTBLFC | \
  325. RCC_CLKINT_PLLSTBLFC | RCC_CLKINT_HSECFDFC;
  326. #ifdef DATA_IN_ExtSRAM
  327. SystemInit_ExtMemCtrl();
  328. #endif /* DATA_IN_ExtSRAM */
  329. /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
  330. /* Configure the Flash Latency cycles and enable prefetch buffer */
  331. SetSysClock();
  332. #ifdef VECT_TAB_SRAM
  333. SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
  334. #else
  335. SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
  336. #endif
  337. }
  338. /**
  339. * @brief Update SystemCoreClock variable according to Clock Register Values.
  340. * The SystemCoreClock variable contains the core clock (HCLK), it can
  341. * be used by the user application to setup the SysTick timer or configure
  342. * other parameters.
  343. *
  344. * @note Each time the core clock (HCLK) changes, this function must be called
  345. * to update SystemCoreClock variable value. Otherwise, any configuration
  346. * based on this variable will be incorrect.
  347. *
  348. * @note - The system frequency computed by this function is not the real
  349. * frequency in the chip. It is calculated based on the predefined
  350. * constant and the selected clock source:
  351. *
  352. * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
  353. *
  354. * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
  355. *
  356. * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
  357. * or HSI_VALUE(*) multiplied by the PLL factors.
  358. *
  359. * (*) HSI_VALUE is a constant defined in at32f4xx.h file (default value
  360. * 8 MHz) but the real value may vary depending on the variations
  361. * in voltage and temperature.
  362. *
  363. * (**) HSE_VALUE is a constant defined in at32f4xx.h file (default value
  364. * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
  365. * that HSE_VALUE is same as the real frequency of the crystal used.
  366. * Otherwise, this function may have wrong result.
  367. *
  368. * - The result of this function could be not correct when using fractional
  369. * value for HSE crystal.
  370. * @param None
  371. * @retval None
  372. */
  373. void SystemCoreClockUpdate (void)
  374. {
  375. uint32_t tmp = 0, pllmult = 0, pllrefclk = 0, tempcfg = 0;
  376. /* Get SYSCLK source -------------------------------------------------------*/
  377. tmp = RCC->CFG & RCC_CFG_SYSCLKSTS;
  378. switch (tmp)
  379. {
  380. case RCC_CFG_SYSCLKSTS_HSI: /* HSI used as system clock */
  381. SystemCoreClock = HSI_VALUE;
  382. break;
  383. case RCC_CFG_SYSCLKSTS_HSE: /* HSE used as system clock */
  384. SystemCoreClock = HSE_VALUE;
  385. break;
  386. case RCC_CFG_SYSCLKSTS_PLL: /* PLL used as system clock */
  387. /* Get PLL clock source and multiplication factor ----------------------*/
  388. pllrefclk = RCC->CFG & RCC_CFG_PLLRC;
  389. tempcfg = RCC->CFG;
  390. pllmult = RCC_GET_PLLMULT(tempcfg);
  391. if (pllrefclk == RCC_PLLRefClk_HSI_Div2)
  392. {
  393. /* HSI oscillator clock divided by 2 selected as PLL clock entry */
  394. SystemCoreClock = (HSI_VALUE >> 1) * pllmult;
  395. }
  396. else
  397. {
  398. /* HSE selected as PLL clock entry */
  399. if ((RCC->CFG & RCC_CFG_PLLHSEPSC) != (uint32_t)RESET)
  400. {
  401. /* HSE oscillator clock divided by 2 */
  402. SystemCoreClock = (HSE_VALUE >> 1) * pllmult;
  403. }
  404. else
  405. {
  406. SystemCoreClock = HSE_VALUE * pllmult;
  407. }
  408. }
  409. break;
  410. default:
  411. SystemCoreClock = HSI_VALUE;
  412. break;
  413. }
  414. /* Compute HCLK clock frequency ----------------*/
  415. /* Get HCLK prescaler */
  416. tmp = AHBPscTable[((RCC->CFG & RCC_CFG_AHBPSC) >> 4)];
  417. /* HCLK clock frequency */
  418. SystemCoreClock >>= tmp;
  419. }
  420. /**
  421. * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
  422. * @param None
  423. * @retval None
  424. */
  425. static void SetSysClock(void)
  426. {
  427. #ifdef SYSCLK_FREQ_HSE
  428. SetSysClockToHSE();
  429. #elif defined SYSCLK_FREQ_24MHz
  430. SetSysClockTo24M();
  431. #elif defined SYSCLK_FREQ_36MHz
  432. SetSysClockTo36M();
  433. #elif defined SYSCLK_FREQ_48MHz
  434. SetSysClockTo48M();
  435. #elif defined SYSCLK_FREQ_56MHz
  436. SetSysClockTo56M();
  437. #elif defined SYSCLK_FREQ_72MHz
  438. SetSysClockTo72M();
  439. #elif defined SYSCLK_FREQ_96MHz
  440. SetSysClockTo96M();
  441. #elif defined SYSCLK_FREQ_108MHz
  442. SetSysClockTo108M();
  443. #elif defined SYSCLK_FREQ_120MHz
  444. SetSysClockTo120M();
  445. #elif defined SYSCLK_FREQ_144MHz
  446. SetSysClockTo144M();
  447. #elif defined SYSCLK_FREQ_150MHz
  448. SetSysClockTo150M();
  449. #elif defined SYSCLK_FREQ_168MHz
  450. SetSysClockTo168M();
  451. #elif defined SYSCLK_FREQ_176MHz
  452. SetSysClockTo176M();
  453. #elif defined SYSCLK_FREQ_192MHz
  454. SetSysClockTo192M();
  455. #elif defined SYSCLK_FREQ_200MHz
  456. SetSysClockTo200M();
  457. #elif defined SYSCLK_FREQ_224MHz
  458. SetSysClockTo224M();
  459. #elif defined SYSCLK_FREQ_240MHz
  460. SetSysClockTo240M();
  461. #elif defined SYSCLK_FREQ_24MHz_HSI
  462. SetSysClockTo24MHSI();
  463. #elif defined SYSCLK_FREQ_36MHz_HSI
  464. SetSysClockTo36MHSI();
  465. #elif defined SYSCLK_FREQ_48MHz_HSI
  466. SetSysClockTo48MHSI();
  467. #elif defined SYSCLK_FREQ_56MHz_HSI
  468. SetSysClockTo56MHSI();
  469. #elif defined SYSCLK_FREQ_72MHz_HSI
  470. SetSysClockTo72MHSI();
  471. #elif defined SYSCLK_FREQ_96MHz_HSI
  472. SetSysClockTo96MHSI();
  473. #elif defined SYSCLK_FREQ_108MHz_HSI
  474. SetSysClockTo108MHSI();
  475. #elif defined SYSCLK_FREQ_120MHz_HSI
  476. SetSysClockTo120MHSI();
  477. #elif defined SYSCLK_FREQ_144MHz_HSI
  478. SetSysClockTo144MHSI();
  479. #elif defined SYSCLK_FREQ_150MHz_HSI
  480. SetSysClockTo150MHSI();
  481. #elif defined SYSCLK_FREQ_168MHz_HSI
  482. SetSysClockTo168MHSI();
  483. #elif defined SYSCLK_FREQ_176MHz_HSI
  484. SetSysClockTo176MHSI();
  485. #elif defined SYSCLK_FREQ_192MHz_HSI
  486. SetSysClockTo192MHSI();
  487. #elif defined SYSCLK_FREQ_200MHz_HSI
  488. SetSysClockTo200MHSI();
  489. #elif defined SYSCLK_FREQ_224MHz_HSI
  490. SetSysClockTo224MHSI();
  491. #elif defined SYSCLK_FREQ_240MHz_HSI
  492. SetSysClockTo240MHSI();
  493. #endif
  494. /* If none of the define above is enabled, the HSI is used as System clock
  495. source (default after reset) */
  496. }
  497. /**
  498. * @brief Setup the external memory controller. Called in startup_at32f4xx.s
  499. * before jump to __main
  500. * @param None
  501. * @retval None
  502. */
  503. #ifdef DATA_IN_ExtSRAM
  504. /**
  505. * @brief Setup the external memory controller.
  506. * Called in startup_at32f4xx_xx.s/.c before jump to main.
  507. * This function configures the external SRAM mounted
  508. * (AT32 High density devices). This SRAM will be used as program
  509. * data memory (including heap and stack).
  510. * @param None
  511. * @retval None
  512. */
  513. void SystemInit_ExtMemCtrl(void)
  514. {
  515. /* Enable XMC clock */
  516. RCC->AHBEN = RCC_AHBEN_SRAMEN | RCC_AHBEN_FLASHEN | RCC_AHBEN_XMCEN;
  517. /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
  518. RCC->APB2EN = RCC_APB2EN_GPIODEN | RCC_APB2EN_GPIOEEN | RCC_APB2EN_GPIOFEN | RCC_APB2EN_GPIOGEN;
  519. /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
  520. /*---------------- SRAM Address lines configuration -------------------------*/
  521. /*---------------- NOE and NWE configuration --------------------------------*/
  522. /*---------------- NE3 configuration ----------------------------------------*/
  523. /*---------------- NBL0, NBL1 configuration ---------------------------------*/
  524. GPIOD->CTRLL = 0x44BB44BB;
  525. GPIOD->CTRLH = 0xBBBBBBBB;
  526. GPIOE->CTRLL = 0xB44444BB;
  527. GPIOE->CTRLH = 0xBBBBBBBB;
  528. GPIOF->CTRLL = 0x44BBBBBB;
  529. GPIOF->CTRLH = 0xBBBB4444;
  530. GPIOG->CTRLL = 0x44BBBBBB;
  531. GPIOG->CTRLH = 0x44444B44;
  532. /*---------------- XMC Configuration ---------------------------------------*/
  533. /*---------------- Enable XMC Bank1_SRAM Bank ------------------------------*/
  534. XMC_Bank1->BK1CTRLR[4] = 0x00001011;
  535. XMC_Bank1->BK1CTRLR[5] = 0x00000200;
  536. }
  537. #endif /* DATA_IN_ExtSRAM */
  538. #ifndef SYSCLK_FREQ_HSI
  539. #ifdef AT32F403xx
  540. /**
  541. * @brief Delay to wait for HSE stable.
  542. * @note This function should be used before reading the HSESTBL flag.
  543. * @param None
  544. * @retval None
  545. */
  546. static void WaitHseStbl(uint32_t delay)
  547. {
  548. uint32_t i;
  549. for(i = 0; i < delay; i++)
  550. ;
  551. }
  552. #endif
  553. #endif /* SYSCLK_FREQ_HSI */
  554. #ifdef SYSCLK_FREQ_HSE
  555. /**
  556. * @brief Selects HSE as System clock source and configure HCLK, PCLK2
  557. * and PCLK1 prescalers.
  558. * @note This function should be used only after reset.
  559. * @param None
  560. * @retval None
  561. */
  562. static void SetSysClockToHSE(void)
  563. {
  564. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  565. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  566. /* Enable HSE */
  567. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  568. /* Wait till HSE is ready and if Time out is reached exit */
  569. do
  570. {
  571. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  572. StartUpCounter++;
  573. }
  574. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  575. #ifdef AT32F403xx
  576. WaitHseStbl(HSE_STABLE_DELAY);
  577. #endif
  578. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  579. {
  580. HSEStatus = (uint32_t)0x01;
  581. }
  582. else
  583. {
  584. HSEStatus = (uint32_t)0x00;
  585. }
  586. if (HSEStatus == (uint32_t)0x01)
  587. {
  588. #if defined (AT32F415xx)
  589. /* Enable Prefetch Buffer */
  590. FLASH->ACR |= FLASH_ACR_PRFTBE;
  591. /* Flash 1 wait state */
  592. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  593. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
  594. #endif
  595. /* HCLK = SYSCLK */
  596. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  597. /* PCLK2 = HCLK */
  598. RCC->CFG &= 0xFFFFC7FF;
  599. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
  600. /* PCLK1 = HCLK */
  601. RCC->CFG &= 0xFFFFF8FF;
  602. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1;
  603. /* Select HSE as system clock source */
  604. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  605. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_HSE;
  606. /* Wait till HSE is used as system clock source */
  607. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != (uint32_t)0x04)
  608. {
  609. }
  610. }
  611. else
  612. {
  613. /* If HSE fails to start-up, the application will have wrong clock
  614. configuration. User can add here some code to deal with this error */
  615. }
  616. }
  617. #elif defined SYSCLK_FREQ_24MHz
  618. /**
  619. * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
  620. * and PCLK1 prescalers.
  621. * @note This function should be used only after reset.
  622. * @param None
  623. * @retval None
  624. */
  625. static void SetSysClockTo24M(void)
  626. {
  627. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  628. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  629. /* Enable HSE */
  630. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  631. /* Wait till HSE is ready and if Time out is reached exit */
  632. do
  633. {
  634. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  635. StartUpCounter++;
  636. }
  637. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  638. #ifdef AT32F403xx
  639. WaitHseStbl(HSE_STABLE_DELAY);
  640. #endif
  641. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  642. {
  643. HSEStatus = (uint32_t)0x01;
  644. }
  645. else
  646. {
  647. HSEStatus = (uint32_t)0x00;
  648. }
  649. if (HSEStatus == (uint32_t)0x01)
  650. {
  651. #if defined (AT32F415xx)
  652. /* Enable Prefetch Buffer */
  653. FLASH->ACR |= FLASH_ACR_PRFTBE;
  654. /* Flash 1 wait state */
  655. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  656. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
  657. #endif
  658. /* HCLK = SYSCLK */
  659. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  660. /* PCLK2 = HCLK */
  661. RCC->CFG &= 0xFFFFC7FF;
  662. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
  663. /* PCLK1 = HCLK */
  664. RCC->CFG &= 0xFFFFF8FF;
  665. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1;
  666. /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
  667. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  668. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT6);
  669. /* Enable PLL */
  670. RCC->CTRL |= RCC_CTRL_PLLEN;
  671. /* Wait till PLL is ready */
  672. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  673. {
  674. }
  675. /* Select PLL as system clock source */
  676. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  677. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  678. /* Wait till PLL is used as system clock source */
  679. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  680. {
  681. }
  682. #ifdef AT32F403xx
  683. WaitHseStbl(PLL_STABLE_DELAY);
  684. #endif
  685. }
  686. else
  687. {
  688. /* If HSE fails to start-up, the application will have wrong clock
  689. configuration. User can add here some code to deal with this error */
  690. }
  691. }
  692. #elif defined SYSCLK_FREQ_36MHz
  693. /**
  694. * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
  695. * and PCLK1 prescalers.
  696. * @note This function should be used only after reset.
  697. * @param None
  698. * @retval None
  699. */
  700. static void SetSysClockTo36M(void)
  701. {
  702. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  703. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  704. /* Enable HSE */
  705. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  706. /* Wait till HSE is ready and if Time out is reached exit */
  707. do
  708. {
  709. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  710. StartUpCounter++;
  711. }
  712. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  713. #ifdef AT32F403xx
  714. WaitHseStbl(HSE_STABLE_DELAY);
  715. #endif
  716. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  717. {
  718. HSEStatus = (uint32_t)0x01;
  719. }
  720. else
  721. {
  722. HSEStatus = (uint32_t)0x00;
  723. }
  724. if (HSEStatus == (uint32_t)0x01)
  725. {
  726. #if defined (AT32F415xx)
  727. /* Enable Prefetch Buffer */
  728. FLASH->ACR |= FLASH_ACR_PRFTBE;
  729. /* Flash 1 wait state */
  730. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  731. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
  732. #endif
  733. /* HCLK = SYSCLK */
  734. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  735. /* PCLK2 = HCLK */
  736. RCC->CFG &= 0xFFFFC7FF;
  737. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
  738. /* PCLK1 = HCLK */
  739. RCC->CFG &= 0xFFFFF8FF;
  740. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1;
  741. /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
  742. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  743. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT9);
  744. /* Enable PLL */
  745. RCC->CTRL |= RCC_CTRL_PLLEN;
  746. /* Wait till PLL is ready */
  747. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  748. {
  749. }
  750. /* Select PLL as system clock source */
  751. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  752. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  753. /* Wait till PLL is used as system clock source */
  754. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  755. {
  756. }
  757. #ifdef AT32F403xx
  758. WaitHseStbl(PLL_STABLE_DELAY);
  759. #endif
  760. }
  761. else
  762. {
  763. /* If HSE fails to start-up, the application will have wrong clock
  764. configuration. User can add here some code to deal with this error */
  765. }
  766. }
  767. #elif defined SYSCLK_FREQ_48MHz
  768. /**
  769. * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
  770. * and PCLK1 prescalers.
  771. * @note This function should be used only after reset.
  772. * @param None
  773. * @retval None
  774. */
  775. static void SetSysClockTo48M(void)
  776. {
  777. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  778. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  779. /* Enable HSE */
  780. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  781. /* Wait till HSE is ready and if Time out is reached exit */
  782. do
  783. {
  784. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  785. StartUpCounter++;
  786. }
  787. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  788. #ifdef AT32F403xx
  789. WaitHseStbl(HSE_STABLE_DELAY);
  790. #endif
  791. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  792. {
  793. HSEStatus = (uint32_t)0x01;
  794. }
  795. else
  796. {
  797. HSEStatus = (uint32_t)0x00;
  798. }
  799. if (HSEStatus == (uint32_t)0x01)
  800. {
  801. #if defined (AT32F415xx)
  802. /* Enable Prefetch Buffer */
  803. FLASH->ACR |= FLASH_ACR_PRFTBE;
  804. /* Flash 1 wait state */
  805. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  806. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
  807. #endif
  808. /* HCLK = SYSCLK */
  809. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  810. /* PCLK2 = HCLK */
  811. RCC->CFG &= 0xFFFFC7FF;
  812. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
  813. /* PCLK1 = HCLK/2 */
  814. RCC->CFG &= 0xFFFFF8FF;
  815. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  816. /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
  817. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  818. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT6);
  819. /* Enable PLL */
  820. RCC->CTRL |= RCC_CTRL_PLLEN;
  821. /* Wait till PLL is ready */
  822. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  823. {
  824. }
  825. /* Select PLL as system clock source */
  826. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  827. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  828. /* Wait till PLL is used as system clock source */
  829. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  830. {
  831. }
  832. #ifdef AT32F403xx
  833. WaitHseStbl(PLL_STABLE_DELAY);
  834. #endif
  835. }
  836. else
  837. {
  838. /* If HSE fails to start-up, the application will have wrong clock
  839. configuration. User can add here some code to deal with this error */
  840. }
  841. }
  842. #elif defined SYSCLK_FREQ_56MHz
  843. /**
  844. * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
  845. * and PCLK1 prescalers.
  846. * @note This function should be used only after reset.
  847. * @param None
  848. * @retval None
  849. */
  850. static void SetSysClockTo56M(void)
  851. {
  852. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  853. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  854. /* Enable HSE */
  855. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  856. /* Wait till HSE is ready and if Time out is reached exit */
  857. do
  858. {
  859. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  860. StartUpCounter++;
  861. }
  862. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  863. #ifdef AT32F403xx
  864. WaitHseStbl(HSE_STABLE_DELAY);
  865. #endif
  866. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  867. {
  868. HSEStatus = (uint32_t)0x01;
  869. }
  870. else
  871. {
  872. HSEStatus = (uint32_t)0x00;
  873. }
  874. if (HSEStatus == (uint32_t)0x01)
  875. {
  876. #if defined (AT32F415xx)
  877. /* Enable Prefetch Buffer */
  878. FLASH->ACR |= FLASH_ACR_PRFTBE;
  879. /* Flash 1 wait state */
  880. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  881. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
  882. #endif
  883. /* HCLK = SYSCLK */
  884. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  885. /* PCLK2 = HCLK */
  886. RCC->CFG &= 0xFFFFC7FF;
  887. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
  888. /* PCLK1 = HCLK/2 */
  889. RCC->CFG &= 0xFFFFF8FF;
  890. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  891. /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
  892. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  893. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT7);
  894. /* Enable PLL */
  895. RCC->CTRL |= RCC_CTRL_PLLEN;
  896. /* Wait till PLL is ready */
  897. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  898. {
  899. }
  900. /* Select PLL as system clock source */
  901. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  902. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  903. /* Wait till PLL is used as system clock source */
  904. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  905. {
  906. }
  907. #ifdef AT32F403xx
  908. WaitHseStbl(PLL_STABLE_DELAY);
  909. #endif
  910. }
  911. else
  912. {
  913. /* If HSE fails to start-up, the application will have wrong clock
  914. configuration. User can add here some code to deal with this error */
  915. }
  916. }
  917. #elif defined SYSCLK_FREQ_72MHz
  918. /**
  919. * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
  920. * and PCLK1 prescalers.
  921. * @note This function should be used only after reset.
  922. * @param None
  923. * @retval None
  924. */
  925. static void SetSysClockTo72M(void)
  926. {
  927. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  928. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  929. /* Enable HSE */
  930. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  931. /* Wait till HSE is ready and if Time out is reached exit */
  932. do
  933. {
  934. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  935. StartUpCounter++;
  936. }
  937. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  938. #ifdef AT32F403xx
  939. WaitHseStbl(HSE_STABLE_DELAY);
  940. #endif
  941. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  942. {
  943. HSEStatus = (uint32_t)0x01;
  944. }
  945. else
  946. {
  947. HSEStatus = (uint32_t)0x00;
  948. }
  949. if (HSEStatus == (uint32_t)0x01)
  950. {
  951. #if defined (AT32F415xx)
  952. /* Enable Prefetch Buffer */
  953. FLASH->ACR |= FLASH_ACR_PRFTBE;
  954. /* Flash 1 wait state */
  955. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  956. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
  957. #endif
  958. /* HCLK = SYSCLK */
  959. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  960. /* PCLK2 = HCLK */
  961. RCC->CFG &= 0xFFFFC7FF;
  962. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
  963. /* PCLK1 = HCLK/2 */
  964. RCC->CFG &= 0xFFFFF8FF;
  965. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  966. /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
  967. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  968. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT9);
  969. /* Enable PLL */
  970. RCC->CTRL |= RCC_CTRL_PLLEN;
  971. /* Wait till PLL is ready */
  972. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  973. {
  974. }
  975. /* Select PLL as system clock source */
  976. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  977. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  978. /* Wait till PLL is used as system clock source */
  979. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  980. {
  981. }
  982. #ifdef AT32F403xx
  983. WaitHseStbl(PLL_STABLE_DELAY);
  984. #endif
  985. }
  986. else
  987. {
  988. /* If HSE fails to start-up, the application will have wrong clock
  989. configuration. User can add here some code to deal with this error */
  990. }
  991. }
  992. #elif defined SYSCLK_FREQ_96MHz
  993. /**
  994. * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2
  995. * and PCLK1 prescalers.
  996. * @note This function should be used only after reset.
  997. * @param None
  998. * @retval None
  999. */
  1000. static void SetSysClockTo96M(void)
  1001. {
  1002. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  1003. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  1004. /* Enable HSE */
  1005. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  1006. /* Wait till HSE is ready and if Time out is reached exit */
  1007. do
  1008. {
  1009. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  1010. StartUpCounter++;
  1011. }
  1012. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  1013. #ifdef AT32F403xx
  1014. WaitHseStbl(HSE_STABLE_DELAY);
  1015. #endif
  1016. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  1017. {
  1018. HSEStatus = (uint32_t)0x01;
  1019. }
  1020. else
  1021. {
  1022. HSEStatus = (uint32_t)0x00;
  1023. }
  1024. if (HSEStatus == (uint32_t)0x01)
  1025. {
  1026. #if defined (AT32F415xx)
  1027. /* Enable Prefetch Buffer */
  1028. FLASH->ACR |= FLASH_ACR_PRFTBE;
  1029. /* Flash 1 wait state */
  1030. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  1031. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
  1032. #endif
  1033. /* HCLK = SYSCLK */
  1034. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  1035. /* PCLK2 = HCLK/2 */
  1036. RCC->CFG &= 0xFFFFC7FF;
  1037. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  1038. /* PCLK1 = HCLK/2 */
  1039. RCC->CFG &= 0xFFFFF8FF;
  1040. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  1041. /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
  1042. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  1043. #if defined (AT32F415xx)
  1044. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT12);
  1045. #else
  1046. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT12 | RCC_CFG_PLLRANGE_GT72MHZ);
  1047. #endif
  1048. /* Enable PLL */
  1049. RCC->CTRL |= RCC_CTRL_PLLEN;
  1050. /* Wait till PLL is ready */
  1051. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  1052. {
  1053. }
  1054. /* Select PLL as system clock source */
  1055. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  1056. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  1057. /* Wait till PLL is used as system clock source */
  1058. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  1059. {
  1060. }
  1061. #ifdef AT32F403xx
  1062. WaitHseStbl(PLL_STABLE_DELAY);
  1063. #endif
  1064. }
  1065. else
  1066. {
  1067. /* If HSE fails to start-up, the application will have wrong clock
  1068. configuration. User can add here some code to deal with this error */
  1069. }
  1070. }
  1071. #elif defined SYSCLK_FREQ_108MHz
  1072. /**
  1073. * @brief Sets System clock frequency to 108MHz and configure HCLK, PCLK2
  1074. * and PCLK1 prescalers.
  1075. * @note This function should be used only after reset.
  1076. * @param None
  1077. * @retval None
  1078. */
  1079. static void SetSysClockTo108M(void)
  1080. {
  1081. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  1082. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  1083. /* Enable HSE */
  1084. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  1085. /* Wait till HSE is ready and if Time out is reached exit */
  1086. do
  1087. {
  1088. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  1089. StartUpCounter++;
  1090. }
  1091. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  1092. #ifdef AT32F403xx
  1093. WaitHseStbl(HSE_STABLE_DELAY);
  1094. #endif
  1095. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  1096. {
  1097. HSEStatus = (uint32_t)0x01;
  1098. }
  1099. else
  1100. {
  1101. HSEStatus = (uint32_t)0x00;
  1102. }
  1103. if (HSEStatus == (uint32_t)0x01)
  1104. {
  1105. #if defined (AT32F415xx)
  1106. /* Enable Prefetch Buffer */
  1107. FLASH->ACR |= FLASH_ACR_PRFTBE;
  1108. /* Flash 1 wait state */
  1109. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  1110. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
  1111. #endif
  1112. /* HCLK = SYSCLK */
  1113. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  1114. /* PCLK2 = HCLK/2 */
  1115. RCC->CFG &= 0xFFFFC7FF;
  1116. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  1117. /* PCLK1 = HCLK/2 */
  1118. RCC->CFG &= 0xFFFFF8FF;
  1119. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  1120. /* PLL configuration: PLLCLK = (HSE/2) * 27 = 108 MHz */
  1121. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  1122. #if defined (AT32F415xx)
  1123. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT27);
  1124. #else
  1125. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT27 \
  1126. | RCC_CFG_PLLRANGE_GT72MHZ);
  1127. #endif
  1128. /* Enable PLL */
  1129. RCC->CTRL |= RCC_CTRL_PLLEN;
  1130. /* Wait till PLL is ready */
  1131. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  1132. {
  1133. }
  1134. /* Select PLL as system clock source */
  1135. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  1136. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  1137. /* Wait till PLL is used as system clock source */
  1138. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  1139. {
  1140. }
  1141. #ifdef AT32F403xx
  1142. WaitHseStbl(PLL_STABLE_DELAY);
  1143. #endif
  1144. }
  1145. else
  1146. {
  1147. /* If HSE fails to start-up, the application will have wrong clock
  1148. configuration. User can add here some code to deal with this error */
  1149. }
  1150. }
  1151. #elif defined SYSCLK_FREQ_120MHz
  1152. /**
  1153. * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2
  1154. * and PCLK1 prescalers.
  1155. * @note This function should be used only after reset.
  1156. * @param None
  1157. * @retval None
  1158. */
  1159. static void SetSysClockTo120M(void)
  1160. {
  1161. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  1162. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  1163. /* Enable HSE */
  1164. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  1165. /* Wait till HSE is ready and if Time out is reached exit */
  1166. do
  1167. {
  1168. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  1169. StartUpCounter++;
  1170. }
  1171. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  1172. #ifdef AT32F403xx
  1173. WaitHseStbl(HSE_STABLE_DELAY);
  1174. #endif
  1175. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  1176. {
  1177. HSEStatus = (uint32_t)0x01;
  1178. }
  1179. else
  1180. {
  1181. HSEStatus = (uint32_t)0x00;
  1182. }
  1183. if (HSEStatus == (uint32_t)0x01)
  1184. {
  1185. #if defined (AT32F415xx)
  1186. /* Enable Prefetch Buffer */
  1187. FLASH->ACR |= FLASH_ACR_PRFTBE;
  1188. /* Flash 1 wait state */
  1189. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  1190. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
  1191. #endif
  1192. /* HCLK = SYSCLK */
  1193. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  1194. /* PCLK2 = HCLK/2 */
  1195. RCC->CFG &= 0xFFFFC7FF;
  1196. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  1197. /* PCLK1 = HCLK/2 */
  1198. RCC->CFG &= 0xFFFFF8FF;
  1199. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  1200. /* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
  1201. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  1202. #if defined (AT32F415xx)
  1203. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT15);
  1204. #else
  1205. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT15 | RCC_CFG_PLLRANGE_GT72MHZ);
  1206. #endif
  1207. /* Enable PLL */
  1208. RCC->CTRL |= RCC_CTRL_PLLEN;
  1209. /* Wait till PLL is ready */
  1210. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  1211. {
  1212. }
  1213. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1214. defined (AT32F407xx) || defined (AT32F415xx)
  1215. RCC_StepModeCmd(ENABLE);
  1216. #endif
  1217. /* Select PLL as system clock source */
  1218. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  1219. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  1220. /* Wait till PLL is used as system clock source */
  1221. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  1222. {
  1223. }
  1224. #ifdef AT32F403xx
  1225. WaitHseStbl(PLL_STABLE_DELAY);
  1226. #endif
  1227. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1228. defined (AT32F407xx) || defined (AT32F415xx)
  1229. RCC_StepModeCmd(DISABLE);
  1230. #endif
  1231. }
  1232. else
  1233. {
  1234. /* If HSE fails to start-up, the application will have wrong clock
  1235. configuration. User can add here some code to deal with this error */
  1236. }
  1237. }
  1238. #elif defined SYSCLK_FREQ_144MHz
  1239. /**
  1240. * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2
  1241. * and PCLK1 prescalers.
  1242. * @note This function should be used only after reset.
  1243. * @param None
  1244. * @retval None
  1245. */
  1246. static void SetSysClockTo144M(void)
  1247. {
  1248. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  1249. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  1250. /* Enable HSE */
  1251. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  1252. /* Wait till HSE is ready and if Time out is reached exit */
  1253. do
  1254. {
  1255. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  1256. StartUpCounter++;
  1257. }
  1258. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  1259. #ifdef AT32F403xx
  1260. WaitHseStbl(HSE_STABLE_DELAY);
  1261. #endif
  1262. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  1263. {
  1264. HSEStatus = (uint32_t)0x01;
  1265. }
  1266. else
  1267. {
  1268. HSEStatus = (uint32_t)0x00;
  1269. }
  1270. if (HSEStatus == (uint32_t)0x01)
  1271. {
  1272. #if defined (AT32F415xx)
  1273. /* Enable Prefetch Buffer */
  1274. FLASH->ACR |= FLASH_ACR_PRFTBE;
  1275. /* Flash 1 wait state */
  1276. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  1277. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
  1278. #endif
  1279. /* HCLK = SYSCLK */
  1280. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  1281. /* PCLK2 = HCLK/2 */
  1282. RCC->CFG &= 0xFFFFC7FF;
  1283. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  1284. /* PCLK1 = HCLK/2 */
  1285. RCC->CFG &= 0xFFFFF8FF;
  1286. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  1287. /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
  1288. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  1289. #if defined (AT32F415xx)
  1290. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18);
  1291. #else
  1292. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18 | RCC_CFG_PLLRANGE_GT72MHZ);
  1293. #endif
  1294. /* Enable PLL */
  1295. RCC->CTRL |= RCC_CTRL_PLLEN;
  1296. /* Wait till PLL is ready */
  1297. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  1298. {
  1299. }
  1300. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1301. defined (AT32F407xx) || defined (AT32F415xx)
  1302. RCC_StepModeCmd(ENABLE);
  1303. #endif
  1304. /* Select PLL as system clock source */
  1305. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  1306. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  1307. /* Wait till PLL is used as system clock source */
  1308. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  1309. {
  1310. }
  1311. #ifdef AT32F403xx
  1312. WaitHseStbl(PLL_STABLE_DELAY);
  1313. #endif
  1314. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1315. defined (AT32F407xx) || defined (AT32F415xx)
  1316. RCC_StepModeCmd(DISABLE);
  1317. #endif
  1318. }
  1319. else
  1320. {
  1321. /* If HSE fails to start-up, the application will have wrong clock
  1322. configuration. User can add here some code to deal with this error */
  1323. }
  1324. }
  1325. #elif defined SYSCLK_FREQ_150MHz
  1326. /**
  1327. * @brief Sets System clock frequency to 150MHz and configure HCLK, PCLK2
  1328. * and PCLK1 prescalers.
  1329. * @note This function should be used only after reset.
  1330. * @param None
  1331. * @retval None
  1332. */
  1333. static void SetSysClockTo150M(void)
  1334. {
  1335. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  1336. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  1337. /* Enable HSE */
  1338. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  1339. /* Wait till HSE is ready and if Time out is reached exit */
  1340. do
  1341. {
  1342. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  1343. StartUpCounter++;
  1344. }
  1345. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  1346. #ifdef AT32F403xx
  1347. WaitHseStbl(HSE_STABLE_DELAY);
  1348. #endif
  1349. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  1350. {
  1351. HSEStatus = (uint32_t)0x01;
  1352. }
  1353. else
  1354. {
  1355. HSEStatus = (uint32_t)0x00;
  1356. }
  1357. if (HSEStatus == (uint32_t)0x01)
  1358. {
  1359. #if defined (AT32F415xx)
  1360. /* Enable Prefetch Buffer */
  1361. FLASH->ACR |= FLASH_ACR_PRFTBE;
  1362. /* Flash 1 wait state */
  1363. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  1364. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
  1365. #endif
  1366. /* HCLK = SYSCLK */
  1367. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  1368. /* PCLK2 = HCLK/2 */
  1369. RCC->CFG &= 0xFFFFC7FF;
  1370. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  1371. /* PCLK1 = HCLK/2 */
  1372. RCC->CFG &= 0xFFFFF8FF;
  1373. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  1374. /* PLL configuration: PLLCLK = (HSE * 75) / (1 * 4) = 150 MHz */
  1375. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  1376. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE);
  1377. RCC_PLLconfig2(PLL_FREF_8M, 75, 1, PLL_FR_4);
  1378. /* Enable PLL */
  1379. RCC->CTRL |= RCC_CTRL_PLLEN;
  1380. /* Wait till PLL is ready */
  1381. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  1382. {
  1383. }
  1384. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1385. defined (AT32F407xx) || defined (AT32F415xx)
  1386. RCC_StepModeCmd(ENABLE);
  1387. #endif
  1388. /* Select PLL as system clock source */
  1389. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  1390. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  1391. /* Wait till PLL is used as system clock source */
  1392. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  1393. {
  1394. }
  1395. #ifdef AT32F403xx
  1396. WaitHseStbl(PLL_STABLE_DELAY);
  1397. #endif
  1398. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1399. defined (AT32F407xx) || defined (AT32F415xx)
  1400. RCC_StepModeCmd(DISABLE);
  1401. #endif
  1402. }
  1403. else
  1404. {
  1405. /* If HSE fails to start-up, the application will have wrong clock
  1406. configuration. User can add here some code to deal with this error */
  1407. }
  1408. }
  1409. #elif defined SYSCLK_FREQ_168MHz
  1410. /**
  1411. * @brief Sets System clock frequency to 168MHz and configure HCLK, PCLK2
  1412. * and PCLK1 prescalers.
  1413. * @note This function should be used only after reset.
  1414. * @param None
  1415. * @retval None
  1416. */
  1417. static void SetSysClockTo168M(void)
  1418. {
  1419. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  1420. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  1421. /* Enable HSE */
  1422. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  1423. /* Wait till HSE is ready and if Time out is reached exit */
  1424. do
  1425. {
  1426. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  1427. StartUpCounter++;
  1428. }
  1429. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  1430. #ifdef AT32F403xx
  1431. WaitHseStbl(HSE_STABLE_DELAY);
  1432. #endif
  1433. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  1434. {
  1435. HSEStatus = (uint32_t)0x01;
  1436. }
  1437. else
  1438. {
  1439. HSEStatus = (uint32_t)0x00;
  1440. }
  1441. if (HSEStatus == (uint32_t)0x01)
  1442. {
  1443. /* HCLK = SYSCLK */
  1444. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  1445. /* PCLK2 = HCLK/2 */
  1446. RCC->CFG &= 0xFFFFC7FF;
  1447. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  1448. /* PCLK1 = HCLK/2 */
  1449. RCC->CFG &= 0xFFFFF8FF;
  1450. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  1451. /* PLL configuration: PLLCLK = HSE * 21 = 168 MHz */
  1452. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  1453. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT21 | RCC_CFG_PLLRANGE_GT72MHZ);
  1454. /* Enable PLL */
  1455. RCC->CTRL |= RCC_CTRL_PLLEN;
  1456. /* Wait till PLL is ready */
  1457. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  1458. {
  1459. }
  1460. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1461. defined (AT32F407xx)
  1462. RCC_StepModeCmd(ENABLE);
  1463. #endif
  1464. /* Select PLL as system clock source */
  1465. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  1466. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  1467. /* Wait till PLL is used as system clock source */
  1468. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  1469. {
  1470. }
  1471. #ifdef AT32F403xx
  1472. WaitHseStbl(PLL_STABLE_DELAY);
  1473. #endif
  1474. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1475. defined (AT32F407xx)
  1476. RCC_StepModeCmd(DISABLE);
  1477. #endif
  1478. }
  1479. else
  1480. {
  1481. /* If HSE fails to start-up, the application will have wrong clock
  1482. configuration. User can add here some code to deal with this error */
  1483. }
  1484. }
  1485. #elif defined SYSCLK_FREQ_176MHz
  1486. /**
  1487. * @brief Sets System clock frequency to 176MHz and configure HCLK, PCLK2
  1488. * and PCLK1 prescalers.
  1489. * @note This function should be used only after reset.
  1490. * @param None
  1491. * @retval None
  1492. */
  1493. static void SetSysClockTo176M(void)
  1494. {
  1495. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  1496. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  1497. /* Enable HSE */
  1498. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  1499. /* Wait till HSE is ready and if Time out is reached exit */
  1500. do
  1501. {
  1502. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  1503. StartUpCounter++;
  1504. }
  1505. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  1506. #ifdef AT32F403xx
  1507. WaitHseStbl(HSE_STABLE_DELAY);
  1508. #endif
  1509. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  1510. {
  1511. HSEStatus = (uint32_t)0x01;
  1512. }
  1513. else
  1514. {
  1515. HSEStatus = (uint32_t)0x00;
  1516. }
  1517. if (HSEStatus == (uint32_t)0x01)
  1518. {
  1519. /* HCLK = SYSCLK */
  1520. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  1521. /* PCLK2 = HCLK/2 */
  1522. RCC->CFG &= 0xFFFFC7FF;
  1523. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  1524. /* PCLK1 = HCLK/2 */
  1525. RCC->CFG &= 0xFFFFF8FF;
  1526. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  1527. /* PLL configuration: PLLCLK = HSE * 22 = 176 MHz */
  1528. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  1529. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT22 | RCC_CFG_PLLRANGE_GT72MHZ);
  1530. /* Enable PLL */
  1531. RCC->CTRL |= RCC_CTRL_PLLEN;
  1532. /* Wait till PLL is ready */
  1533. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  1534. {
  1535. }
  1536. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1537. defined (AT32F407xx)
  1538. RCC_StepModeCmd(ENABLE);
  1539. #endif
  1540. /* Select PLL as system clock source */
  1541. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  1542. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  1543. /* Wait till PLL is used as system clock source */
  1544. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  1545. {
  1546. }
  1547. #ifdef AT32F403xx
  1548. WaitHseStbl(PLL_STABLE_DELAY);
  1549. #endif
  1550. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1551. defined (AT32F407xx)
  1552. RCC_StepModeCmd(DISABLE);
  1553. #endif
  1554. }
  1555. else
  1556. {
  1557. /* If HSE fails to start-up, the application will have wrong clock
  1558. configuration. User can add here some code to deal with this error */
  1559. }
  1560. }
  1561. #elif defined SYSCLK_FREQ_192MHz
  1562. /**
  1563. * @brief Sets System clock frequency to 192MHz and configure HCLK, PCLK2
  1564. * and PCLK1 prescalers.
  1565. * @note This function should be used only after reset.
  1566. * @param None
  1567. * @retval None
  1568. */
  1569. static void SetSysClockTo192M(void)
  1570. {
  1571. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  1572. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  1573. /* Enable HSE */
  1574. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  1575. /* Wait till HSE is ready and if Time out is reached exit */
  1576. do
  1577. {
  1578. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  1579. StartUpCounter++;
  1580. }
  1581. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  1582. #ifdef AT32F403xx
  1583. WaitHseStbl(HSE_STABLE_DELAY);
  1584. #endif
  1585. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  1586. {
  1587. HSEStatus = (uint32_t)0x01;
  1588. }
  1589. else
  1590. {
  1591. HSEStatus = (uint32_t)0x00;
  1592. }
  1593. if (HSEStatus == (uint32_t)0x01)
  1594. {
  1595. /* HCLK = SYSCLK */
  1596. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  1597. /* PCLK2 = HCLK/2 */
  1598. RCC->CFG &= 0xFFFFC7FF;
  1599. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  1600. /* PCLK1 = HCLK/2 */
  1601. RCC->CFG &= 0xFFFFF8FF;
  1602. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  1603. /* PLL configuration: PLLCLK = HSE * 24 = 192 MHz */
  1604. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  1605. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT24 | RCC_CFG_PLLRANGE_GT72MHZ);
  1606. /* Enable PLL */
  1607. RCC->CTRL |= RCC_CTRL_PLLEN;
  1608. /* Wait till PLL is ready */
  1609. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  1610. {
  1611. }
  1612. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1613. defined (AT32F407xx)
  1614. RCC_StepModeCmd(ENABLE);
  1615. #endif
  1616. /* Select PLL as system clock source */
  1617. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  1618. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  1619. /* Wait till PLL is used as system clock source */
  1620. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  1621. {
  1622. }
  1623. #ifdef AT32F403xx
  1624. WaitHseStbl(PLL_STABLE_DELAY);
  1625. #endif
  1626. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1627. defined (AT32F407xx)
  1628. RCC_StepModeCmd(DISABLE);
  1629. #endif
  1630. }
  1631. else
  1632. {
  1633. /* If HSE fails to start-up, the application will have wrong clock
  1634. configuration. User can add here some code to deal with this error */
  1635. }
  1636. }
  1637. #elif defined SYSCLK_FREQ_200MHz
  1638. /**
  1639. * @brief Sets System clock frequency to 200MHz and configure HCLK, PCLK2
  1640. * and PCLK1 prescalers.
  1641. * @note This function should be used only after reset.
  1642. * @param None
  1643. * @retval None
  1644. */
  1645. static void SetSysClockTo200M(void)
  1646. {
  1647. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  1648. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  1649. /* Enable HSE */
  1650. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  1651. /* Wait till HSE is ready and if Time out is reached exit */
  1652. do
  1653. {
  1654. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  1655. StartUpCounter++;
  1656. }
  1657. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  1658. #ifdef AT32F403xx
  1659. WaitHseStbl(HSE_STABLE_DELAY);
  1660. #endif
  1661. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  1662. {
  1663. HSEStatus = (uint32_t)0x01;
  1664. }
  1665. else
  1666. {
  1667. HSEStatus = (uint32_t)0x00;
  1668. }
  1669. if (HSEStatus == (uint32_t)0x01)
  1670. {
  1671. /* HCLK = SYSCLK */
  1672. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  1673. /* PCLK2 = HCLK/2 */
  1674. RCC->CFG &= 0xFFFFC7FF;
  1675. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  1676. /* PCLK1 = HCLK/2 */
  1677. RCC->CFG &= 0xFFFFF8FF;
  1678. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  1679. /* PLL configuration: PLLCLK = HSE * 25 = 200 MHz */
  1680. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  1681. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT25 | RCC_CFG_PLLRANGE_GT72MHZ);
  1682. /* Enable PLL */
  1683. RCC->CTRL |= RCC_CTRL_PLLEN;
  1684. /* Wait till PLL is ready */
  1685. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  1686. {
  1687. }
  1688. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1689. defined (AT32F407xx)
  1690. RCC_StepModeCmd(ENABLE);
  1691. #endif
  1692. /* Select PLL as system clock source */
  1693. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  1694. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  1695. /* Wait till PLL is used as system clock source */
  1696. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  1697. {
  1698. }
  1699. #ifdef AT32F403xx
  1700. WaitHseStbl(PLL_STABLE_DELAY);
  1701. #endif
  1702. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1703. defined (AT32F407xx)
  1704. RCC_StepModeCmd(DISABLE);
  1705. #endif
  1706. }
  1707. else
  1708. {
  1709. /* If HSE fails to start-up, the application will have wrong clock
  1710. configuration. User can add here some code to deal with this error */
  1711. }
  1712. }
  1713. #elif defined SYSCLK_FREQ_224MHz
  1714. /**
  1715. * @brief Sets System clock frequency to 224MHz and configure HCLK, PCLK2
  1716. * and PCLK1 prescalers.
  1717. * @note This function should be used only after reset.
  1718. * @param None
  1719. * @retval None
  1720. */
  1721. static void SetSysClockTo224M(void)
  1722. {
  1723. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  1724. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  1725. /* Enable HSE */
  1726. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  1727. /* Wait till HSE is ready and if Time out is reached exit */
  1728. do
  1729. {
  1730. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  1731. StartUpCounter++;
  1732. }
  1733. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  1734. #ifdef AT32F403xx
  1735. WaitHseStbl(HSE_STABLE_DELAY);
  1736. #endif
  1737. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  1738. {
  1739. HSEStatus = (uint32_t)0x01;
  1740. }
  1741. else
  1742. {
  1743. HSEStatus = (uint32_t)0x00;
  1744. }
  1745. if (HSEStatus == (uint32_t)0x01)
  1746. {
  1747. /* HCLK = SYSCLK */
  1748. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  1749. /* PCLK2 = HCLK/2 */
  1750. RCC->CFG &= 0xFFFFC7FF;
  1751. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  1752. /* PCLK1 = HCLK/2 */
  1753. RCC->CFG &= 0xFFFFF8FF;
  1754. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  1755. /* PLL configuration: PLLCLK = HSE * 28 = 224 MHz */
  1756. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  1757. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT28 | RCC_CFG_PLLRANGE_GT72MHZ);
  1758. /* Enable PLL */
  1759. RCC->CTRL |= RCC_CTRL_PLLEN;
  1760. /* Wait till PLL is ready */
  1761. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  1762. {
  1763. }
  1764. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1765. defined (AT32F407xx)
  1766. RCC_StepModeCmd(ENABLE);
  1767. #endif
  1768. /* Select PLL as system clock source */
  1769. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  1770. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  1771. /* Wait till PLL is used as system clock source */
  1772. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  1773. {
  1774. }
  1775. #ifdef AT32F403xx
  1776. WaitHseStbl(PLL_STABLE_DELAY);
  1777. #endif
  1778. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1779. defined (AT32F407xx)
  1780. RCC_StepModeCmd(DISABLE);
  1781. #endif
  1782. }
  1783. else
  1784. {
  1785. /* If HSE fails to start-up, the application will have wrong clock
  1786. configuration. User can add here some code to deal with this error */
  1787. }
  1788. }
  1789. #elif defined SYSCLK_FREQ_240MHz
  1790. /**
  1791. * @brief Sets System clock frequency to 240MHz and configure HCLK, PCLK2
  1792. * and PCLK1 prescalers.
  1793. * @note This function should be used only after reset.
  1794. * @param None
  1795. * @retval None
  1796. */
  1797. static void SetSysClockTo240M(void)
  1798. {
  1799. __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  1800. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  1801. /* Enable HSE */
  1802. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
  1803. /* Wait till HSE is ready and if Time out is reached exit */
  1804. do
  1805. {
  1806. HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
  1807. StartUpCounter++;
  1808. }
  1809. while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
  1810. #ifdef AT32F403xx
  1811. WaitHseStbl(HSE_STABLE_DELAY);
  1812. #endif
  1813. if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
  1814. {
  1815. HSEStatus = (uint32_t)0x01;
  1816. }
  1817. else
  1818. {
  1819. HSEStatus = (uint32_t)0x00;
  1820. }
  1821. if (HSEStatus == (uint32_t)0x01)
  1822. {
  1823. /* HCLK = SYSCLK */
  1824. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  1825. /* PCLK2 = HCLK/2 */
  1826. RCC->CFG &= 0xFFFFC7FF;
  1827. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  1828. /* PCLK1 = HCLK/2 */
  1829. RCC->CFG &= 0xFFFFF8FF;
  1830. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  1831. /* PLL configuration: PLLCLK = HSE * 30 = 240 MHz */
  1832. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  1833. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT30 | RCC_CFG_PLLRANGE_GT72MHZ);
  1834. /* Enable PLL */
  1835. RCC->CTRL |= RCC_CTRL_PLLEN;
  1836. /* Wait till PLL is ready */
  1837. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  1838. {
  1839. }
  1840. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1841. defined (AT32F407xx)
  1842. RCC_StepModeCmd(ENABLE);
  1843. #endif
  1844. /* Select PLL as system clock source */
  1845. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  1846. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  1847. /* Wait till PLL is used as system clock source */
  1848. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  1849. {
  1850. }
  1851. #ifdef AT32F403xx
  1852. WaitHseStbl(PLL_STABLE_DELAY);
  1853. #endif
  1854. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  1855. defined (AT32F407xx)
  1856. RCC_StepModeCmd(DISABLE);
  1857. #endif
  1858. }
  1859. else
  1860. {
  1861. /* If HSE fails to start-up, the application will have wrong clock
  1862. configuration. User can add here some code to deal with this error */
  1863. }
  1864. }
  1865. #elif defined SYSCLK_FREQ_24MHz_HSI
  1866. /**
  1867. * @brief Sets System clock frequency to 24MHz from HSI and configure HCLK, PCLK2
  1868. * and PCLK1 prescalers.
  1869. * @note This function should be used only after reset.
  1870. * @param None
  1871. * @retval None
  1872. */
  1873. static void SetSysClockTo24MHSI(void)
  1874. {
  1875. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  1876. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  1877. /* Enable HSI */
  1878. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  1879. /* Wait till HSI is ready and if Time out is reached exit */
  1880. do
  1881. {
  1882. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  1883. StartUpCounter++;
  1884. }
  1885. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  1886. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  1887. {
  1888. HSIStatus = (uint32_t)0x01;
  1889. }
  1890. else
  1891. {
  1892. HSIStatus = (uint32_t)0x00;
  1893. }
  1894. if (HSIStatus == (uint32_t)0x01)
  1895. {
  1896. #if defined (AT32F415xx)
  1897. /* Enable Prefetch Buffer */
  1898. FLASH->ACR |= FLASH_ACR_PRFTBE;
  1899. /* Flash 1 wait state */
  1900. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  1901. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
  1902. #endif
  1903. /* HCLK = SYSCLK */
  1904. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  1905. /* PCLK2 = HCLK */
  1906. RCC->CFG &= 0xFFFFC7FF;
  1907. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
  1908. /* PCLK1 = HCLK */
  1909. RCC->CFG &= 0xFFFFF8FF;
  1910. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1;
  1911. /* PLL configuration: PLLCLK = (HSI/2) * 6 = 24 MHz */
  1912. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  1913. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT6);
  1914. /* Enable PLL */
  1915. RCC->CTRL |= RCC_CTRL_PLLEN;
  1916. /* Wait till PLL is ready */
  1917. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  1918. {
  1919. }
  1920. /* Select PLL as system clock source */
  1921. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  1922. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  1923. /* Wait till PLL is used as system clock source */
  1924. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  1925. {
  1926. }
  1927. #ifdef AT32F403xx
  1928. WaitHseStbl(PLL_STABLE_DELAY);
  1929. #endif
  1930. }
  1931. }
  1932. #elif defined SYSCLK_FREQ_36MHz_HSI
  1933. /**
  1934. * @brief Sets System clock frequency to 36MHz from HSI and configure HCLK, PCLK2
  1935. * and PCLK1 prescalers.
  1936. * @note This function should be used only after reset.
  1937. * @param None
  1938. * @retval None
  1939. */
  1940. static void SetSysClockTo36MHSI(void)
  1941. {
  1942. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  1943. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  1944. /* Enable HSI */
  1945. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  1946. /* Wait till HSI is ready and if Time out is reached exit */
  1947. do
  1948. {
  1949. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  1950. StartUpCounter++;
  1951. }
  1952. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  1953. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  1954. {
  1955. HSIStatus = (uint32_t)0x01;
  1956. }
  1957. else
  1958. {
  1959. HSIStatus = (uint32_t)0x00;
  1960. }
  1961. if (HSIStatus == (uint32_t)0x01)
  1962. {
  1963. #if defined (AT32F415xx)
  1964. /* Enable Prefetch Buffer */
  1965. FLASH->ACR |= FLASH_ACR_PRFTBE;
  1966. /* Flash 1 wait state */
  1967. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  1968. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
  1969. #endif
  1970. /* HCLK = SYSCLK */
  1971. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  1972. /* PCLK2 = HCLK */
  1973. RCC->CFG &= 0xFFFFC7FF;
  1974. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
  1975. /* PCLK1 = HCLK */
  1976. RCC->CFG &= 0xFFFFF8FF;
  1977. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1;
  1978. /* PLL configuration: PLLCLK = (HSI/2) * 9 = 36 MHz */
  1979. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  1980. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT9);
  1981. /* Enable PLL */
  1982. RCC->CTRL |= RCC_CTRL_PLLEN;
  1983. /* Wait till PLL is ready */
  1984. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  1985. {
  1986. }
  1987. /* Select PLL as system clock source */
  1988. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  1989. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  1990. /* Wait till PLL is used as system clock source */
  1991. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  1992. {
  1993. }
  1994. #ifdef AT32F403xx
  1995. WaitHseStbl(PLL_STABLE_DELAY);
  1996. #endif
  1997. }
  1998. }
  1999. #elif defined SYSCLK_FREQ_48MHz_HSI
  2000. /**
  2001. * @brief Sets System clock frequency to 48MHz from HSI and configure HCLK, PCLK2
  2002. * and PCLK1 prescalers.
  2003. * @note This function should be used only after reset.
  2004. * @param None
  2005. * @retval None
  2006. */
  2007. static void SetSysClockTo48MHSI(void)
  2008. {
  2009. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  2010. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  2011. /* Enable HSI */
  2012. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  2013. /* Wait till HSI is ready and if Time out is reached exit */
  2014. do
  2015. {
  2016. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  2017. StartUpCounter++;
  2018. }
  2019. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  2020. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  2021. {
  2022. HSIStatus = (uint32_t)0x01;
  2023. }
  2024. else
  2025. {
  2026. HSIStatus = (uint32_t)0x00;
  2027. }
  2028. if (HSIStatus == (uint32_t)0x01)
  2029. {
  2030. #if defined (AT32F415xx)
  2031. /* Enable Prefetch Buffer */
  2032. FLASH->ACR |= FLASH_ACR_PRFTBE;
  2033. /* Flash 1 wait state */
  2034. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  2035. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
  2036. #endif
  2037. /* HCLK = SYSCLK */
  2038. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  2039. /* PCLK2 = HCLK */
  2040. RCC->CFG &= 0xFFFFC7FF;
  2041. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
  2042. /* PCLK1 = HCLK/2 */
  2043. RCC->CFG &= 0xFFFFF8FF;
  2044. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  2045. /* PLL configuration: PLLCLK = (HSI/2) * 12 = 48 MHz */
  2046. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  2047. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT12);
  2048. /* Enable PLL */
  2049. RCC->CTRL |= RCC_CTRL_PLLEN;
  2050. /* Wait till PLL is ready */
  2051. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  2052. {
  2053. }
  2054. /* Select PLL as system clock source */
  2055. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  2056. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  2057. /* Wait till PLL is used as system clock source */
  2058. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  2059. {
  2060. }
  2061. #ifdef AT32F403xx
  2062. WaitHseStbl(PLL_STABLE_DELAY);
  2063. #endif
  2064. }
  2065. }
  2066. #elif defined SYSCLK_FREQ_56MHz_HSI
  2067. /**
  2068. * @brief Sets System clock frequency to 56MHz from HSI and configure HCLK, PCLK2
  2069. * and PCLK1 prescalers.
  2070. * @note This function should be used only after reset.
  2071. * @param None
  2072. * @retval None
  2073. */
  2074. static void SetSysClockTo56MHSI(void)
  2075. {
  2076. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  2077. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  2078. /* Enable HSI */
  2079. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  2080. /* Wait till HSI is ready and if Time out is reached exit */
  2081. do
  2082. {
  2083. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  2084. StartUpCounter++;
  2085. }
  2086. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  2087. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  2088. {
  2089. HSIStatus = (uint32_t)0x01;
  2090. }
  2091. else
  2092. {
  2093. HSIStatus = (uint32_t)0x00;
  2094. }
  2095. if (HSIStatus == (uint32_t)0x01)
  2096. {
  2097. #if defined (AT32F415xx)
  2098. /* Enable Prefetch Buffer */
  2099. FLASH->ACR |= FLASH_ACR_PRFTBE;
  2100. /* Flash 1 wait state */
  2101. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  2102. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
  2103. #endif
  2104. /* HCLK = SYSCLK */
  2105. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  2106. /* PCLK2 = HCLK */
  2107. RCC->CFG &= 0xFFFFC7FF;
  2108. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
  2109. /* PCLK1 = HCLK/2 */
  2110. RCC->CFG &= 0xFFFFF8FF;
  2111. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  2112. /* PLL configuration: PLLCLK = (HSI/2) * 14 = 56 MHz */
  2113. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  2114. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT14);
  2115. /* Enable PLL */
  2116. RCC->CTRL |= RCC_CTRL_PLLEN;
  2117. /* Wait till PLL is ready */
  2118. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  2119. {
  2120. }
  2121. /* Select PLL as system clock source */
  2122. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  2123. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  2124. /* Wait till PLL is used as system clock source */
  2125. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  2126. {
  2127. }
  2128. #ifdef AT32F403xx
  2129. WaitHseStbl(PLL_STABLE_DELAY);
  2130. #endif
  2131. }
  2132. }
  2133. #elif defined SYSCLK_FREQ_72MHz_HSI
  2134. /**
  2135. * @brief Sets System clock frequency to 72MHz from HSI and configure HCLK, PCLK2
  2136. * and PCLK1 prescalers.
  2137. * @note This function should be used only after reset.
  2138. * @param None
  2139. * @retval None
  2140. */
  2141. static void SetSysClockTo72MHSI(void)
  2142. {
  2143. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  2144. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  2145. /* Enable HSI */
  2146. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  2147. /* Wait till HSI is ready and if Time out is reached exit */
  2148. do
  2149. {
  2150. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  2151. StartUpCounter++;
  2152. }
  2153. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  2154. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  2155. {
  2156. HSIStatus = (uint32_t)0x01;
  2157. }
  2158. else
  2159. {
  2160. HSIStatus = (uint32_t)0x00;
  2161. }
  2162. if (HSIStatus == (uint32_t)0x01)
  2163. {
  2164. #if defined (AT32F415xx)
  2165. /* Enable Prefetch Buffer */
  2166. FLASH->ACR |= FLASH_ACR_PRFTBE;
  2167. /* Flash 1 wait state */
  2168. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  2169. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
  2170. #endif
  2171. /* HCLK = SYSCLK */
  2172. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  2173. /* PCLK2 = HCLK */
  2174. RCC->CFG &= 0xFFFFC7FF;
  2175. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
  2176. /* PCLK1 = HCLK/2 */
  2177. RCC->CFG &= 0xFFFFF8FF;
  2178. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  2179. /* PLL configuration: PLLCLK = (HSI/2) * 18 = 72 MHz */
  2180. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  2181. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT18);
  2182. /* Enable PLL */
  2183. RCC->CTRL |= RCC_CTRL_PLLEN;
  2184. /* Wait till PLL is ready */
  2185. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  2186. {
  2187. }
  2188. /* Select PLL as system clock source */
  2189. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  2190. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  2191. /* Wait till PLL is used as system clock source */
  2192. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  2193. {
  2194. }
  2195. #ifdef AT32F403xx
  2196. WaitHseStbl(PLL_STABLE_DELAY);
  2197. #endif
  2198. }
  2199. }
  2200. #elif defined SYSCLK_FREQ_96MHz_HSI
  2201. /**
  2202. * @brief Sets System clock frequency to 96MHz from HSI and configure HCLK, PCLK2
  2203. * and PCLK1 prescalers.
  2204. * @note This function should be used only after reset.
  2205. * @param None
  2206. * @retval None
  2207. */
  2208. static void SetSysClockTo96MHSI(void)
  2209. {
  2210. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  2211. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  2212. /* Enable HSI */
  2213. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  2214. /* Wait till HSI is ready and if Time out is reached exit */
  2215. do
  2216. {
  2217. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  2218. StartUpCounter++;
  2219. }
  2220. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  2221. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  2222. {
  2223. HSIStatus = (uint32_t)0x01;
  2224. }
  2225. else
  2226. {
  2227. HSIStatus = (uint32_t)0x00;
  2228. }
  2229. if (HSIStatus == (uint32_t)0x01)
  2230. {
  2231. #if defined (AT32F415xx)
  2232. /* Enable Prefetch Buffer */
  2233. FLASH->ACR |= FLASH_ACR_PRFTBE;
  2234. /* Flash 1 wait state */
  2235. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  2236. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
  2237. #endif
  2238. /* HCLK = SYSCLK */
  2239. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  2240. /* PCLK2 = HCLK/2 */
  2241. RCC->CFG &= 0xFFFFC7FF;
  2242. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  2243. /* PCLK1 = HCLK/2 */
  2244. RCC->CFG &= 0xFFFFF8FF;
  2245. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  2246. /* PLL configuration: PLLCLK = (HSI/2) * 24 = 96 MHz */
  2247. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  2248. #if defined (AT32F415xx)
  2249. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT24);
  2250. #else
  2251. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT24 | RCC_CFG_PLLRANGE_GT72MHZ);
  2252. #endif
  2253. /* Enable PLL */
  2254. RCC->CTRL |= RCC_CTRL_PLLEN;
  2255. /* Wait till PLL is ready */
  2256. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  2257. {
  2258. }
  2259. /* Select PLL as system clock source */
  2260. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  2261. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  2262. /* Wait till PLL is used as system clock source */
  2263. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  2264. {
  2265. }
  2266. #ifdef AT32F403xx
  2267. WaitHseStbl(PLL_STABLE_DELAY);
  2268. #endif
  2269. }
  2270. }
  2271. #elif defined SYSCLK_FREQ_108MHz_HSI
  2272. /**
  2273. * @brief Sets System clock frequency to 108MHz from HSI and configure HCLK, PCLK2
  2274. * and PCLK1 prescalers.
  2275. * @note This function should be used only after reset.
  2276. * @param None
  2277. * @retval None
  2278. */
  2279. static void SetSysClockTo108MHSI(void)
  2280. {
  2281. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  2282. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  2283. /* Enable HSI */
  2284. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  2285. /* Wait till HSI is ready and if Time out is reached exit */
  2286. do
  2287. {
  2288. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  2289. StartUpCounter++;
  2290. }
  2291. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  2292. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  2293. {
  2294. HSIStatus = (uint32_t)0x01;
  2295. }
  2296. else
  2297. {
  2298. HSIStatus = (uint32_t)0x00;
  2299. }
  2300. if (HSIStatus == (uint32_t)0x01)
  2301. {
  2302. #if defined (AT32F415xx)
  2303. /* Enable Prefetch Buffer */
  2304. FLASH->ACR |= FLASH_ACR_PRFTBE;
  2305. /* Flash 1 wait state */
  2306. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  2307. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
  2308. #endif
  2309. /* HCLK = SYSCLK */
  2310. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  2311. /* PCLK2 = HCLK/2 */
  2312. RCC->CFG &= 0xFFFFC7FF;
  2313. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  2314. /* PCLK1 = HCLK/2 */
  2315. RCC->CFG &= 0xFFFFF8FF;
  2316. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  2317. /* PLL configuration: PLLCLK = (HSI/2) * 27 = 108 MHz */
  2318. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  2319. #if defined (AT32F415xx)
  2320. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT27);
  2321. #else
  2322. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT27 | RCC_CFG_PLLRANGE_GT72MHZ);
  2323. #endif
  2324. /* Enable PLL */
  2325. RCC->CTRL |= RCC_CTRL_PLLEN;
  2326. /* Wait till PLL is ready */
  2327. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  2328. {
  2329. }
  2330. /* Select PLL as system clock source */
  2331. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  2332. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  2333. /* Wait till PLL is used as system clock source */
  2334. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  2335. {
  2336. }
  2337. #ifdef AT32F403xx
  2338. WaitHseStbl(PLL_STABLE_DELAY);
  2339. #endif
  2340. }
  2341. }
  2342. #elif defined SYSCLK_FREQ_120MHz_HSI
  2343. /**
  2344. * @brief Sets System clock frequency to 120MHz from HSI and configure HCLK, PCLK2
  2345. * and PCLK1 prescalers.
  2346. * @note This function should be used only after reset.
  2347. * @param None
  2348. * @retval None
  2349. */
  2350. static void SetSysClockTo120MHSI(void)
  2351. {
  2352. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  2353. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  2354. /* Enable HSI */
  2355. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  2356. /* Wait till HSI is ready and if Time out is reached exit */
  2357. do
  2358. {
  2359. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  2360. StartUpCounter++;
  2361. }
  2362. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  2363. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  2364. {
  2365. HSIStatus = (uint32_t)0x01;
  2366. }
  2367. else
  2368. {
  2369. HSIStatus = (uint32_t)0x00;
  2370. }
  2371. if (HSIStatus == (uint32_t)0x01)
  2372. {
  2373. #if defined (AT32F415xx)
  2374. /* Enable Prefetch Buffer */
  2375. FLASH->ACR |= FLASH_ACR_PRFTBE;
  2376. /* Flash 1 wait state */
  2377. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  2378. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
  2379. #endif
  2380. /* HCLK = SYSCLK */
  2381. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  2382. /* PCLK2 = HCLK/2 */
  2383. RCC->CFG &= 0xFFFFC7FF;
  2384. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  2385. /* PCLK1 = HCLK/2 */
  2386. RCC->CFG &= 0xFFFFF8FF;
  2387. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  2388. /* PLL configuration: PLLCLK = (HSI/2) * 30 = 120 MHz */
  2389. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  2390. #if defined (AT32F415xx)
  2391. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT30);
  2392. #else
  2393. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT30 | RCC_CFG_PLLRANGE_GT72MHZ);
  2394. #endif
  2395. /* Enable PLL */
  2396. RCC->CTRL |= RCC_CTRL_PLLEN;
  2397. /* Wait till PLL is ready */
  2398. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  2399. {
  2400. }
  2401. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2402. defined (AT32F407xx) || defined (AT32F415xx)
  2403. RCC_StepModeCmd(ENABLE);
  2404. #endif
  2405. /* Select PLL as system clock source */
  2406. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  2407. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  2408. /* Wait till PLL is used as system clock source */
  2409. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  2410. {
  2411. }
  2412. #ifdef AT32F403xx
  2413. WaitHseStbl(PLL_STABLE_DELAY);
  2414. #endif
  2415. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2416. defined (AT32F407xx) || defined (AT32F415xx)
  2417. RCC_StepModeCmd(DISABLE);
  2418. #endif
  2419. }
  2420. }
  2421. #elif defined SYSCLK_FREQ_144MHz_HSI
  2422. /**
  2423. * @brief Sets System clock frequency to 144MHz from HSI and configure HCLK, PCLK2
  2424. * and PCLK1 prescalers.
  2425. * @note This function should be used only after reset.
  2426. * @param None
  2427. * @retval None
  2428. */
  2429. static void SetSysClockTo144MHSI(void)
  2430. {
  2431. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  2432. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  2433. /* Enable HSI */
  2434. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  2435. /* Wait till HSI is ready and if Time out is reached exit */
  2436. do
  2437. {
  2438. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  2439. StartUpCounter++;
  2440. }
  2441. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  2442. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  2443. {
  2444. HSIStatus = (uint32_t)0x01;
  2445. }
  2446. else
  2447. {
  2448. HSIStatus = (uint32_t)0x00;
  2449. }
  2450. if (HSIStatus == (uint32_t)0x01)
  2451. {
  2452. #if defined (AT32F415xx)
  2453. /* Enable Prefetch Buffer */
  2454. FLASH->ACR |= FLASH_ACR_PRFTBE;
  2455. /* Flash 1 wait state */
  2456. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  2457. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
  2458. #endif
  2459. /* HCLK = SYSCLK */
  2460. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  2461. /* PCLK2 = HCLK/2 */
  2462. RCC->CFG &= 0xFFFFC7FF;
  2463. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  2464. /* PCLK1 = HCLK/2 */
  2465. RCC->CFG &= 0xFFFFF8FF;
  2466. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  2467. /* PLL configuration: PLLCLK = (HSI/2) * 36 = 144 MHz */
  2468. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  2469. #if defined (AT32F415xx)
  2470. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT36);
  2471. #else
  2472. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT36 | RCC_CFG_PLLRANGE_GT72MHZ);
  2473. #endif
  2474. /* Enable PLL */
  2475. RCC->CTRL |= RCC_CTRL_PLLEN;
  2476. /* Wait till PLL is ready */
  2477. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  2478. {
  2479. }
  2480. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2481. defined (AT32F407xx) || defined (AT32F415xx)
  2482. RCC_StepModeCmd(ENABLE);
  2483. #endif
  2484. /* Select PLL as system clock source */
  2485. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  2486. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  2487. /* Wait till PLL is used as system clock source */
  2488. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  2489. {
  2490. }
  2491. #ifdef AT32F403xx
  2492. WaitHseStbl(PLL_STABLE_DELAY);
  2493. #endif
  2494. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2495. defined (AT32F407xx) || defined (AT32F415xx)
  2496. RCC_StepModeCmd(DISABLE);
  2497. #endif
  2498. }
  2499. }
  2500. #elif defined SYSCLK_FREQ_150MHz_HSI
  2501. /**
  2502. * @brief Sets System clock frequency to 150MHz from HSI and configure HCLK, PCLK2
  2503. * and PCLK1 prescalers.
  2504. * @note This function should be used only after reset.
  2505. * @param None
  2506. * @retval None
  2507. */
  2508. static void SetSysClockTo150MHSI(void)
  2509. {
  2510. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  2511. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  2512. /* Enable HSI */
  2513. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  2514. /* Wait till HSI is ready and if Time out is reached exit */
  2515. do
  2516. {
  2517. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  2518. StartUpCounter++;
  2519. }
  2520. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  2521. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  2522. {
  2523. HSIStatus = (uint32_t)0x01;
  2524. }
  2525. else
  2526. {
  2527. HSIStatus = (uint32_t)0x00;
  2528. }
  2529. if (HSIStatus == (uint32_t)0x01)
  2530. {
  2531. #if defined (AT32F415xx)
  2532. /* Enable Prefetch Buffer */
  2533. FLASH->ACR |= FLASH_ACR_PRFTBE;
  2534. /* Flash 1 wait state */
  2535. FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
  2536. FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
  2537. #endif
  2538. /* HCLK = SYSCLK */
  2539. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  2540. /* PCLK2 = HCLK/2 */
  2541. RCC->CFG &= 0xFFFFC7FF;
  2542. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  2543. /* PCLK1 = HCLK/2 */
  2544. RCC->CFG &= 0xFFFFF8FF;
  2545. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  2546. /* PLL configuration: PLLCLK = ((HSI/2) * 150) / (1 * 4) = 150 MHz */
  2547. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  2548. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2);
  2549. RCC_PLLconfig2(PLL_FREF_4M, 150, 1, PLL_FR_4);
  2550. /* Enable PLL */
  2551. RCC->CTRL |= RCC_CTRL_PLLEN;
  2552. /* Wait till PLL is ready */
  2553. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  2554. {
  2555. }
  2556. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2557. defined (AT32F407xx) || defined (AT32F415xx)
  2558. RCC_StepModeCmd(ENABLE);
  2559. #endif
  2560. /* Select PLL as system clock source */
  2561. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  2562. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  2563. /* Wait till PLL is used as system clock source */
  2564. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  2565. {
  2566. }
  2567. #ifdef AT32F403xx
  2568. WaitHseStbl(PLL_STABLE_DELAY);
  2569. #endif
  2570. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2571. defined (AT32F407xx) || defined (AT32F415xx)
  2572. RCC_StepModeCmd(DISABLE);
  2573. #endif
  2574. }
  2575. }
  2576. #elif defined SYSCLK_FREQ_168MHz_HSI
  2577. /**
  2578. * @brief Sets System clock frequency to 168MHz from HSI and configure HCLK, PCLK2
  2579. * and PCLK1 prescalers.
  2580. * @note This function should be used only after reset.
  2581. * @param None
  2582. * @retval None
  2583. */
  2584. static void SetSysClockTo168MHSI(void)
  2585. {
  2586. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  2587. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  2588. /* Enable HSI */
  2589. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  2590. /* Wait till HSI is ready and if Time out is reached exit */
  2591. do
  2592. {
  2593. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  2594. StartUpCounter++;
  2595. }
  2596. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  2597. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  2598. {
  2599. HSIStatus = (uint32_t)0x01;
  2600. }
  2601. else
  2602. {
  2603. HSIStatus = (uint32_t)0x00;
  2604. }
  2605. if (HSIStatus == (uint32_t)0x01)
  2606. {
  2607. /* HCLK = SYSCLK */
  2608. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  2609. /* PCLK2 = HCLK/2 */
  2610. RCC->CFG &= 0xFFFFC7FF;
  2611. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  2612. /* PCLK1 = HCLK/2 */
  2613. RCC->CFG &= 0xFFFFF8FF;
  2614. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  2615. /* PLL configuration: PLLCLK = (HSI/2) * 42 = 168 MHz */
  2616. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  2617. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT42 | RCC_CFG_PLLRANGE_GT72MHZ);
  2618. /* Enable PLL */
  2619. RCC->CTRL |= RCC_CTRL_PLLEN;
  2620. /* Wait till PLL is ready */
  2621. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  2622. {
  2623. }
  2624. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2625. defined (AT32F407xx)
  2626. RCC_StepModeCmd(ENABLE);
  2627. #endif
  2628. /* Select PLL as system clock source */
  2629. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  2630. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  2631. /* Wait till PLL is used as system clock source */
  2632. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  2633. {
  2634. }
  2635. #ifdef AT32F403xx
  2636. WaitHseStbl(PLL_STABLE_DELAY);
  2637. #endif
  2638. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2639. defined (AT32F407xx)
  2640. RCC_StepModeCmd(DISABLE);
  2641. #endif
  2642. }
  2643. }
  2644. #elif defined SYSCLK_FREQ_176MHz_HSI
  2645. /**
  2646. * @brief Sets System clock frequency to 176MHz from HSI and configure HCLK, PCLK2
  2647. * and PCLK1 prescalers.
  2648. * @note This function should be used only after reset.
  2649. * @param None
  2650. * @retval None
  2651. */
  2652. static void SetSysClockTo176MHSI(void)
  2653. {
  2654. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  2655. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  2656. /* Enable HSI */
  2657. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  2658. /* Wait till HSI is ready and if Time out is reached exit */
  2659. do
  2660. {
  2661. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  2662. StartUpCounter++;
  2663. }
  2664. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  2665. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  2666. {
  2667. HSIStatus = (uint32_t)0x01;
  2668. }
  2669. else
  2670. {
  2671. HSIStatus = (uint32_t)0x00;
  2672. }
  2673. if (HSIStatus == (uint32_t)0x01)
  2674. {
  2675. /* HCLK = SYSCLK */
  2676. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  2677. /* PCLK2 = HCLK/2 */
  2678. RCC->CFG &= 0xFFFFC7FF;
  2679. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  2680. /* PCLK1 = HCLK/2 */
  2681. RCC->CFG &= 0xFFFFF8FF;
  2682. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  2683. /* PLL configuration: PLLCLK = (HSI/2) * 44 = 176 MHz */
  2684. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  2685. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT44 | RCC_CFG_PLLRANGE_GT72MHZ);
  2686. /* Enable PLL */
  2687. RCC->CTRL |= RCC_CTRL_PLLEN;
  2688. /* Wait till PLL is ready */
  2689. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  2690. {
  2691. }
  2692. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2693. defined (AT32F407xx)
  2694. RCC_StepModeCmd(ENABLE);
  2695. #endif
  2696. /* Select PLL as system clock source */
  2697. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  2698. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  2699. /* Wait till PLL is used as system clock source */
  2700. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  2701. {
  2702. }
  2703. #ifdef AT32F403xx
  2704. WaitHseStbl(PLL_STABLE_DELAY);
  2705. #endif
  2706. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2707. defined (AT32F407xx)
  2708. RCC_StepModeCmd(DISABLE);
  2709. #endif
  2710. }
  2711. }
  2712. #elif defined SYSCLK_FREQ_192MHz_HSI
  2713. /**
  2714. * @brief Sets System clock frequency to 192MHz from HSI and configure HCLK, PCLK2
  2715. * and PCLK1 prescalers.
  2716. * @note This function should be used only after reset.
  2717. * @param None
  2718. * @retval None
  2719. */
  2720. static void SetSysClockTo192MHSI(void)
  2721. {
  2722. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  2723. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  2724. /* Enable HSI */
  2725. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  2726. /* Wait till HSI is ready and if Time out is reached exit */
  2727. do
  2728. {
  2729. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  2730. StartUpCounter++;
  2731. }
  2732. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  2733. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  2734. {
  2735. HSIStatus = (uint32_t)0x01;
  2736. }
  2737. else
  2738. {
  2739. HSIStatus = (uint32_t)0x00;
  2740. }
  2741. if (HSIStatus == (uint32_t)0x01)
  2742. {
  2743. /* HCLK = SYSCLK */
  2744. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  2745. /* PCLK2 = HCLK/2 */
  2746. RCC->CFG &= 0xFFFFC7FF;
  2747. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  2748. /* PCLK1 = HCLK/2 */
  2749. RCC->CFG &= 0xFFFFF8FF;
  2750. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  2751. /* PLL configuration: PLLCLK = (HSI/2) * 48 = 192 MHz */
  2752. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  2753. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT48 | RCC_CFG_PLLRANGE_GT72MHZ);
  2754. /* Enable PLL */
  2755. RCC->CTRL |= RCC_CTRL_PLLEN;
  2756. /* Wait till PLL is ready */
  2757. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  2758. {
  2759. }
  2760. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2761. defined (AT32F407xx)
  2762. RCC_StepModeCmd(ENABLE);
  2763. #endif
  2764. /* Select PLL as system clock source */
  2765. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  2766. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  2767. /* Wait till PLL is used as system clock source */
  2768. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  2769. {
  2770. }
  2771. #ifdef AT32F403xx
  2772. WaitHseStbl(PLL_STABLE_DELAY);
  2773. #endif
  2774. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2775. defined (AT32F407xx)
  2776. RCC_StepModeCmd(DISABLE);
  2777. #endif
  2778. }
  2779. }
  2780. #elif defined SYSCLK_FREQ_200MHz_HSI
  2781. /**
  2782. * @brief Sets System clock frequency to 200MHz from HSI and configure HCLK, PCLK2
  2783. * and PCLK1 prescalers.
  2784. * @note This function should be used only after reset.
  2785. * @param None
  2786. * @retval None
  2787. */
  2788. static void SetSysClockTo200MHSI(void)
  2789. {
  2790. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  2791. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  2792. /* Enable HSI */
  2793. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  2794. /* Wait till HSI is ready and if Time out is reached exit */
  2795. do
  2796. {
  2797. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  2798. StartUpCounter++;
  2799. }
  2800. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  2801. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  2802. {
  2803. HSIStatus = (uint32_t)0x01;
  2804. }
  2805. else
  2806. {
  2807. HSIStatus = (uint32_t)0x00;
  2808. }
  2809. if (HSIStatus == (uint32_t)0x01)
  2810. {
  2811. /* HCLK = SYSCLK */
  2812. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  2813. /* PCLK2 = HCLK/2 */
  2814. RCC->CFG &= 0xFFFFC7FF;
  2815. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  2816. /* PCLK1 = HCLK/2 */
  2817. RCC->CFG &= 0xFFFFF8FF;
  2818. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  2819. /* PLL configuration: PLLCLK = (HSI/2) * 50 = 200 MHz */
  2820. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  2821. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT50 | RCC_CFG_PLLRANGE_GT72MHZ);
  2822. /* Enable PLL */
  2823. RCC->CTRL |= RCC_CTRL_PLLEN;
  2824. /* Wait till PLL is ready */
  2825. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  2826. {
  2827. }
  2828. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2829. defined (AT32F407xx)
  2830. RCC_StepModeCmd(ENABLE);
  2831. #endif
  2832. /* Select PLL as system clock source */
  2833. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  2834. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  2835. /* Wait till PLL is used as system clock source */
  2836. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  2837. {
  2838. }
  2839. #ifdef AT32F403xx
  2840. WaitHseStbl(PLL_STABLE_DELAY);
  2841. #endif
  2842. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2843. defined (AT32F407xx)
  2844. RCC_StepModeCmd(DISABLE);
  2845. #endif
  2846. }
  2847. }
  2848. #elif defined SYSCLK_FREQ_224MHz_HSI
  2849. /**
  2850. * @brief Sets System clock frequency to 224MHz from HSI and configure HCLK, PCLK2
  2851. * and PCLK1 prescalers.
  2852. * @note This function should be used only after reset.
  2853. * @param None
  2854. * @retval None
  2855. */
  2856. static void SetSysClockTo224MHSI(void)
  2857. {
  2858. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  2859. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  2860. /* Enable HSI */
  2861. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  2862. /* Wait till HSI is ready and if Time out is reached exit */
  2863. do
  2864. {
  2865. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  2866. StartUpCounter++;
  2867. }
  2868. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  2869. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  2870. {
  2871. HSIStatus = (uint32_t)0x01;
  2872. }
  2873. else
  2874. {
  2875. HSIStatus = (uint32_t)0x00;
  2876. }
  2877. if (HSIStatus == (uint32_t)0x01)
  2878. {
  2879. /* HCLK = SYSCLK */
  2880. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  2881. /* PCLK2 = HCLK/2 */
  2882. RCC->CFG &= 0xFFFFC7FF;
  2883. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  2884. /* PCLK1 = HCLK/2 */
  2885. RCC->CFG &= 0xFFFFF8FF;
  2886. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  2887. /* PLL configuration: PLLCLK = (HSI/2) * 56 = 224 MHz */
  2888. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  2889. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT56 | RCC_CFG_PLLRANGE_GT72MHZ);
  2890. /* Enable PLL */
  2891. RCC->CTRL |= RCC_CTRL_PLLEN;
  2892. /* Wait till PLL is ready */
  2893. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  2894. {
  2895. }
  2896. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2897. defined (AT32F407xx)
  2898. RCC_StepModeCmd(ENABLE);
  2899. #endif
  2900. /* Select PLL as system clock source */
  2901. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  2902. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  2903. /* Wait till PLL is used as system clock source */
  2904. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  2905. {
  2906. }
  2907. #ifdef AT32F403xx
  2908. WaitHseStbl(PLL_STABLE_DELAY);
  2909. #endif
  2910. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2911. defined (AT32F407xx)
  2912. RCC_StepModeCmd(DISABLE);
  2913. #endif
  2914. }
  2915. }
  2916. #elif defined SYSCLK_FREQ_240MHz_HSI
  2917. /**
  2918. * @brief Sets System clock frequency to 240MHz from HSI and configure HCLK, PCLK2
  2919. * and PCLK1 prescalers.
  2920. * @note This function should be used only after reset.
  2921. * @param None
  2922. * @retval None
  2923. */
  2924. static void SetSysClockTo240MHSI(void)
  2925. {
  2926. __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  2927. /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  2928. /* Enable HSI */
  2929. RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
  2930. /* Wait till HSI is ready and if Time out is reached exit */
  2931. do
  2932. {
  2933. HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
  2934. StartUpCounter++;
  2935. }
  2936. while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
  2937. if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
  2938. {
  2939. HSIStatus = (uint32_t)0x01;
  2940. }
  2941. else
  2942. {
  2943. HSIStatus = (uint32_t)0x00;
  2944. }
  2945. if (HSIStatus == (uint32_t)0x01)
  2946. {
  2947. /* HCLK = SYSCLK */
  2948. RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
  2949. /* PCLK2 = HCLK/2 */
  2950. RCC->CFG &= 0xFFFFC7FF;
  2951. RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
  2952. /* PCLK1 = HCLK/2 */
  2953. RCC->CFG &= 0xFFFFF8FF;
  2954. RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
  2955. /* PLL configuration: PLLCLK = (HSI/2) * 60 = 240 MHz */
  2956. RCC->CFG &= RCC_CFG_PLLCFG_MASK;
  2957. RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT60 | RCC_CFG_PLLRANGE_GT72MHZ);
  2958. /* Enable PLL */
  2959. RCC->CTRL |= RCC_CTRL_PLLEN;
  2960. /* Wait till PLL is ready */
  2961. while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
  2962. {
  2963. }
  2964. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2965. defined (AT32F407xx)
  2966. RCC_StepModeCmd(ENABLE);
  2967. #endif
  2968. /* Select PLL as system clock source */
  2969. RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
  2970. RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
  2971. /* Wait till PLL is used as system clock source */
  2972. while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
  2973. {
  2974. }
  2975. #ifdef AT32F403xx
  2976. WaitHseStbl(PLL_STABLE_DELAY);
  2977. #endif
  2978. #if defined (AT32F413xx) || defined (AT32F403Axx)|| \
  2979. defined (AT32F407xx)
  2980. RCC_StepModeCmd(DISABLE);
  2981. #endif
  2982. }
  2983. }
  2984. #endif
  2985. /**
  2986. * @}
  2987. */
  2988. /**
  2989. * @}
  2990. */
  2991. /**
  2992. * @}
  2993. */
  2994. /******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/