start_gcc.S 10 KB

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  1. /*
  2. * Copyright (c) 2006-2019, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2013-07-05 Bernard the first version
  9. * 2019-07-28 zdzn add smp support
  10. */
  11. #include "../rtconfig.h"
  12. .equ Mode_USR, 0x10
  13. .equ Mode_FIQ, 0x11
  14. .equ Mode_IRQ, 0x12
  15. .equ Mode_SVC, 0x13
  16. .equ Mode_ABT, 0x17
  17. .equ Mode_UND, 0x1B
  18. .equ Mode_SYS, 0x1F
  19. .equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
  20. .equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
  21. #ifdef RT_USING_FPU
  22. .equ UND_Stack_Size, 0x00000400
  23. #else
  24. .equ UND_Stack_Size, 0x00000000
  25. #endif
  26. .equ SVC_Stack_Size, 0x00000400
  27. .equ ABT_Stack_Size, 0x00000000
  28. .equ RT_FIQ_STACK_PGSZ, 0x00000000
  29. .equ RT_IRQ_STACK_PGSZ, 0x00000800
  30. .equ USR_Stack_Size, 0x00000400
  31. #define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
  32. RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
  33. .section .data.share.isr
  34. /* stack */
  35. #ifdef RT_USING_SMP
  36. .globl stack_start0
  37. .globl stack_top0
  38. .globl stack_start1
  39. .globl stack_top1
  40. .globl stack_start2
  41. .globl stack_top2
  42. .globl stack_start3
  43. .globl stack_top3
  44. stack_start0:
  45. .rept ISR_Stack_Size
  46. .byte 0
  47. .endr
  48. stack_top0:
  49. stack_start1:
  50. .rept ISR_Stack_Size
  51. .byte 0
  52. .endr
  53. stack_top1:
  54. stack_start2:
  55. .rept ISR_Stack_Size
  56. .byte 0
  57. .endr
  58. stack_top2:
  59. stack_start3:
  60. .rept ISR_Stack_Size
  61. .byte 0
  62. .endr
  63. stack_top3:
  64. .globl boot_indicate
  65. boot_indicate:
  66. .rept 16
  67. .byte 0
  68. .endr
  69. #else
  70. .globl stack_start
  71. .globl stack_top
  72. stack_start:
  73. .rept ISR_Stack_Size
  74. .byte 0
  75. .endr
  76. stack_top:
  77. #endif
  78. .text
  79. /* reset entry */
  80. .globl _reset
  81. _reset:
  82. /* Disable IRQ & FIQ */
  83. cpsid if
  84. /* Check for HYP mode */
  85. mrs r0, cpsr_all
  86. and r0, r0, #0x1F
  87. mov r8, #0x1A
  88. cmp r0, r8
  89. beq overHyped
  90. b continue
  91. overHyped: /* Get out of HYP mode */
  92. ldr r1, =continue
  93. msr ELR_hyp, r1
  94. mrs r1, cpsr_all
  95. and r1, r1, #0x1f ;@ CPSR_MODE_MASK
  96. orr r1, r1, #0x13 ;@ CPSR_MODE_SUPERVISOR
  97. msr SPSR_hyp, r1
  98. eret
  99. continue:
  100. /* disable mmu */
  101. bl rt_cpu_mmu_disable
  102. /* set the cpu to SVC32 mode and disable interrupt */
  103. mrs r0, cpsr
  104. bic r0, r0, #0x1f
  105. orr r0, r0, #0x13
  106. msr cpsr_c, r0
  107. #ifdef RT_USING_SMP
  108. mrc p15, 0, r0, c0, c0, 5
  109. ubfx r0, r0, #0, #2
  110. cmp r0, #0
  111. beq 1f
  112. /* write boot indicate */
  113. ldr r5, = boot_indicate
  114. str r0, [r5, r0, lsl #2]
  115. bl secondary_cpu_start
  116. b .
  117. 1:
  118. #endif
  119. /* setup stack */
  120. #ifdef RT_USING_SMP
  121. ldr r0, =stack_top0
  122. #else
  123. ldr r0, =stack_top
  124. #endif
  125. bl stack_setup
  126. /* clear .bss */
  127. mov r0,#0 /* get a zero */
  128. ldr r1,=__bss_start /* bss start */
  129. ldr r2,=__bss_end /* bss end */
  130. bss_loop:
  131. cmp r1,r2 /* check if data to clear */
  132. strlo r0,[r1],#4 /* clear 4 bytes */
  133. blo bss_loop /* loop until done */
  134. bl rt_hw_init_mmu_table
  135. bl init_mbox_mmu_map
  136. bl rt_hw_mmu_init
  137. /* start RT-Thread Kernel */
  138. ldr pc, _rtthread_startup
  139. _rtthread_startup:
  140. .word rtthread_startup
  141. stack_setup:
  142. @ Set the startup stack for svc
  143. mov sp, r0
  144. @ Enter Undefined Instruction Mode and set its Stack Pointer
  145. msr cpsr_c, #Mode_UND|I_Bit|F_Bit
  146. mov sp, r0
  147. sub r0, r0, #UND_Stack_Size
  148. @ Enter Abort Mode and set its Stack Pointer
  149. msr cpsr_c, #Mode_ABT|I_Bit|F_Bit
  150. mov sp, r0
  151. sub r0, r0, #ABT_Stack_Size
  152. @ Enter FIQ Mode and set its Stack Pointer
  153. msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit
  154. mov sp, r0
  155. sub r0, r0, #RT_FIQ_STACK_PGSZ
  156. @ Enter IRQ Mode and set its Stack Pointer
  157. msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit
  158. mov sp, r0
  159. sub r0, r0, #RT_IRQ_STACK_PGSZ
  160. /* come back to SVC mode */
  161. msr cpsr_c, #Mode_SVC|I_Bit|F_Bit
  162. bx lr
  163. .text
  164. /* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */
  165. .section .text.isr, "ax"
  166. .align 5
  167. .globl vector_fiq
  168. vector_fiq:
  169. stmfd sp!,{r0-r7,lr}
  170. bl rt_hw_trap_fiq
  171. ldmfd sp!,{r0-r7,lr}
  172. subs pc, lr, #4
  173. .globl rt_interrupt_enter
  174. .globl rt_interrupt_leave
  175. .globl rt_thread_switch_interrupt_flag
  176. .globl rt_interrupt_from_thread
  177. .globl rt_interrupt_to_thread
  178. .globl rt_current_thread
  179. .globl vmm_thread
  180. .globl vmm_virq_check
  181. .align 5
  182. .globl vector_irq
  183. vector_irq:
  184. #ifdef RT_USING_SMP
  185. clrex
  186. stmfd sp!, {r0, r1}
  187. cps #Mode_SVC
  188. mov r0, sp /* svc_sp */
  189. mov r1, lr /* svc_lr */
  190. cps #Mode_IRQ
  191. sub lr, lr, #4
  192. stmfd r0!, {r1, lr} /* svc_lr, svc_pc */
  193. stmfd r0!, {r2 - r12}
  194. ldmfd sp!, {r1, r2} /* original r0, r1 */
  195. stmfd r0!, {r1 - r2}
  196. mrs r1, spsr /* original mode */
  197. stmfd r0!, {r1}
  198. #ifdef RT_USING_LWP
  199. stmfd r0, {r13, r14}^ /* usr_sp, usr_lr */
  200. sub r0, #8
  201. #endif
  202. #ifdef RT_USING_FPU
  203. /* fpu context */
  204. vmrs r6, fpexc
  205. tst r6, #(1<<30)
  206. beq 1f
  207. vstmdb r0!, {d0-d15}
  208. vstmdb r0!, {d16-d31}
  209. vmrs r5, fpscr
  210. stmfd r0!, {r5}
  211. 1:
  212. stmfd r0!, {r6}
  213. #endif
  214. mov r8, r0
  215. bl rt_interrupt_enter
  216. bl rt_hw_trap_irq
  217. bl rt_interrupt_leave
  218. cps #Mode_SVC
  219. mov sp, r8
  220. mov r0, r8
  221. bl rt_scheduler_do_irq_switch
  222. b rt_hw_context_switch_exit
  223. #else
  224. stmfd sp!, {r0-r12,lr}
  225. bl rt_interrupt_enter
  226. bl rt_hw_trap_irq
  227. bl rt_interrupt_leave
  228. @ if rt_thread_switch_interrupt_flag set, jump to
  229. @ rt_hw_context_switch_interrupt_do and don't return
  230. ldr r0, =rt_thread_switch_interrupt_flag
  231. ldr r1, [r0]
  232. cmp r1, #1
  233. beq rt_hw_context_switch_interrupt_do
  234. ldmfd sp!, {r0-r12,lr}
  235. subs pc, lr, #4
  236. rt_hw_context_switch_interrupt_do:
  237. mov r1, #0 @ clear flag
  238. str r1, [r0]
  239. mov r1, sp @ r1 point to {r0-r3} in stack
  240. add sp, sp, #4*4
  241. ldmfd sp!, {r4-r12,lr}@ reload saved registers
  242. mrs r0, spsr @ get cpsr of interrupt thread
  243. sub r2, lr, #4 @ save old task's pc to r2
  244. @ Switch to SVC mode with no interrupt. If the usr mode guest is
  245. @ interrupted, this will just switch to the stack of kernel space.
  246. @ save the registers in kernel space won't trigger data abort.
  247. msr cpsr_c, #I_Bit|F_Bit|Mode_SVC
  248. stmfd sp!, {r2} @ push old task's pc
  249. stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4
  250. ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread
  251. stmfd sp!, {r1-r4} @ push old task's r0-r3
  252. stmfd sp!, {r0} @ push old task's cpsr
  253. #ifdef RT_USING_LWP
  254. stmfd sp, {r13, r14}^ @push usr_sp, usr_lr
  255. sub sp, #8
  256. #endif
  257. #ifdef RT_USING_FPU
  258. /* fpu context */
  259. vmrs r6, fpexc
  260. tst r6, #(1<<30)
  261. beq 1f
  262. vstmdb sp!, {d0-d15}
  263. vstmdb sp!, {d16-d31}
  264. vmrs r5, fpscr
  265. stmfd sp!, {r5}
  266. 1:
  267. stmfd sp!, {r6}
  268. #endif
  269. ldr r4, =rt_interrupt_from_thread
  270. ldr r5, [r4]
  271. str sp, [r5] @ store sp in preempted tasks's TCB
  272. ldr r6, =rt_interrupt_to_thread
  273. ldr r6, [r6]
  274. ldr sp, [r6] @ get new task's stack pointer
  275. #ifdef RT_USING_FPU
  276. /* fpu context */
  277. ldmfd sp!, {r6}
  278. vmsr fpexc, r6
  279. tst r6, #(1<<30)
  280. beq 1f
  281. ldmfd sp!, {r5}
  282. vmsr fpscr, r5
  283. vldmia sp!, {d16-d31}
  284. vldmia sp!, {d0-d15}
  285. 1:
  286. #endif
  287. #ifdef RT_USING_LWP
  288. ldmfd sp, {r13, r14}^ @pop usr_sp, usr_lr
  289. add sp, #8
  290. #endif
  291. ldmfd sp!, {r4} @ pop new task's cpsr to spsr
  292. msr spsr_cxsf, r4
  293. ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
  294. #endif
  295. .macro push_svc_reg
  296. sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */
  297. stmia sp, {r0 - r12} @/* Calling r0-r12 */
  298. mov r0, sp
  299. mrs r6, spsr @/* Save CPSR */
  300. str lr, [r0, #15*4] @/* Push PC */
  301. str r6, [r0, #16*4] @/* Push CPSR */
  302. cps #Mode_SVC
  303. str sp, [r0, #13*4] @/* Save calling SP */
  304. str lr, [r0, #14*4] @/* Save calling PC */
  305. .endm
  306. .align 5
  307. .globl vector_swi
  308. vector_swi:
  309. push_svc_reg
  310. bl rt_hw_trap_swi
  311. b .
  312. .align 5
  313. .globl vector_undef
  314. vector_undef:
  315. push_svc_reg
  316. cps #Mode_UND
  317. bl rt_hw_trap_undef
  318. #ifdef RT_USING_FPU
  319. ldr lr, [sp, #15*4]
  320. ldmia sp, {r0 - r12}
  321. add sp, sp, #17 * 4
  322. movs pc, lr
  323. #endif
  324. b .
  325. .align 5
  326. .globl vector_pabt
  327. vector_pabt:
  328. push_svc_reg
  329. bl rt_hw_trap_pabt
  330. b .
  331. .align 5
  332. .globl vector_dabt
  333. vector_dabt:
  334. push_svc_reg
  335. bl rt_hw_trap_dabt
  336. b .
  337. .align 5
  338. .globl vector_resv
  339. vector_resv:
  340. push_svc_reg
  341. bl rt_hw_trap_resv
  342. b .
  343. #ifdef RT_USING_SMP
  344. .global secondary_cpu_start
  345. secondary_cpu_start:
  346. /* set vector base */
  347. mrc p15, 0, r0, c1, c0, 0
  348. bic r0, #(1<<13)
  349. mcr p15, 0, r0, c1, c0, 0
  350. /* setup stack */
  351. mrc p15, 0, r0, c0, c0, 5
  352. ubfx r0, r0, #0, #2
  353. ldr r1, =stack_top0
  354. ldr r2, =ISR_Stack_Size
  355. mul r3, r2, r0
  356. add r0, r1, r3
  357. bl stack_setup
  358. /* initialize the mmu table and enable mmu */
  359. bl rt_hw_mmu_init
  360. b secondary_cpu_c_start
  361. #endif
  362. ;@ void arm_smp_enable(void);
  363. .globl arm_smp_enable
  364. arm_smp_enable:
  365. mrc p15, 0, r0, c1, c0, 1 ;@ set SMP bit in ACTLR
  366. orr r0, r0, #0x40
  367. mcr p15, 0, r0, c1, c0, 1
  368. bx lr
  369. /*
  370. mrrc p15, 1, r0, r1, c15
  371. orr r0, r0, #0x40
  372. mcrr p15, 1, r0, r1, c15
  373. dsb
  374. isb
  375. bx lr
  376. */
  377. .text
  378. ;@ void arm_smp_disable(void);
  379. .globl arm_smp_disable
  380. arm_smp_disable:
  381. mrc p15, 0, r0, c1, c0, 1 ;@ clear SMP bit in ACTLR
  382. bic r0, r0, #0x40
  383. mcr p15, 0, r0, c1, c0, 1
  384. bx lr
  385. /*
  386. mrrc p15, 1, r0, r1, c15
  387. bic r0, r0, #0x40
  388. mcrr p15, 1, r0, r1, c15
  389. bx lr
  390. */