drv_usart.c 32 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-10-30 SummerGift first version
  9. * 2020-03-16 SummerGift add device close feature
  10. * 2020-03-20 SummerGift fix bug caused by ORE
  11. * 2020-05-02 whj4674672 support stm32h7 uart dma
  12. * 2020-09-09 forest-rain support stm32wl uart
  13. * 2020-10-14 Dozingfiretruck Porting for stm32wbxx
  14. */
  15. #include "board.h"
  16. #include "drv_usart.h"
  17. #include "drv_config.h"
  18. #ifdef RT_USING_SERIAL
  19. //#define DRV_DEBUG
  20. #define LOG_TAG "drv.usart"
  21. #include <drv_log.h>
  22. #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
  23. !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
  24. !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
  25. #error "Please define at least one BSP_USING_UARTx"
  26. /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
  27. #endif
  28. #ifdef RT_SERIAL_USING_DMA
  29. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
  30. #endif
  31. enum
  32. {
  33. #ifdef BSP_USING_UART1
  34. UART1_INDEX,
  35. #endif
  36. #ifdef BSP_USING_UART2
  37. UART2_INDEX,
  38. #endif
  39. #ifdef BSP_USING_UART3
  40. UART3_INDEX,
  41. #endif
  42. #ifdef BSP_USING_UART4
  43. UART4_INDEX,
  44. #endif
  45. #ifdef BSP_USING_UART5
  46. UART5_INDEX,
  47. #endif
  48. #ifdef BSP_USING_UART6
  49. UART6_INDEX,
  50. #endif
  51. #ifdef BSP_USING_UART7
  52. UART7_INDEX,
  53. #endif
  54. #ifdef BSP_USING_UART8
  55. UART8_INDEX,
  56. #endif
  57. #ifdef BSP_USING_LPUART1
  58. LPUART1_INDEX,
  59. #endif
  60. };
  61. static struct stm32_uart_config uart_config[] =
  62. {
  63. #ifdef BSP_USING_UART1
  64. UART1_CONFIG,
  65. #endif
  66. #ifdef BSP_USING_UART2
  67. UART2_CONFIG,
  68. #endif
  69. #ifdef BSP_USING_UART3
  70. UART3_CONFIG,
  71. #endif
  72. #ifdef BSP_USING_UART4
  73. UART4_CONFIG,
  74. #endif
  75. #ifdef BSP_USING_UART5
  76. UART5_CONFIG,
  77. #endif
  78. #ifdef BSP_USING_UART6
  79. UART6_CONFIG,
  80. #endif
  81. #ifdef BSP_USING_UART7
  82. UART7_CONFIG,
  83. #endif
  84. #ifdef BSP_USING_UART8
  85. UART8_CONFIG,
  86. #endif
  87. #ifdef BSP_USING_LPUART1
  88. LPUART1_CONFIG,
  89. #endif
  90. };
  91. static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
  92. static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  93. {
  94. struct stm32_uart *uart;
  95. RT_ASSERT(serial != RT_NULL);
  96. RT_ASSERT(cfg != RT_NULL);
  97. uart = rt_container_of(serial, struct stm32_uart, serial);
  98. uart->handle.Instance = uart->config->Instance;
  99. uart->handle.Init.BaudRate = cfg->baud_rate;
  100. uart->handle.Init.Mode = UART_MODE_TX_RX;
  101. uart->handle.Init.OverSampling = UART_OVERSAMPLING_16;
  102. switch (cfg->flowcontrol)
  103. {
  104. case RT_SERIAL_FLOWCONTROL_NONE:
  105. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  106. break;
  107. case RT_SERIAL_FLOWCONTROL_CTSRTS:
  108. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS;
  109. break;
  110. default:
  111. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  112. break;
  113. }
  114. switch (cfg->data_bits)
  115. {
  116. case DATA_BITS_8:
  117. if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN)
  118. uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
  119. else
  120. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  121. break;
  122. case DATA_BITS_9:
  123. uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
  124. break;
  125. default:
  126. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  127. break;
  128. }
  129. switch (cfg->stop_bits)
  130. {
  131. case STOP_BITS_1:
  132. uart->handle.Init.StopBits = UART_STOPBITS_1;
  133. break;
  134. case STOP_BITS_2:
  135. uart->handle.Init.StopBits = UART_STOPBITS_2;
  136. break;
  137. default:
  138. uart->handle.Init.StopBits = UART_STOPBITS_1;
  139. break;
  140. }
  141. switch (cfg->parity)
  142. {
  143. case PARITY_NONE:
  144. uart->handle.Init.Parity = UART_PARITY_NONE;
  145. break;
  146. case PARITY_ODD:
  147. uart->handle.Init.Parity = UART_PARITY_ODD;
  148. break;
  149. case PARITY_EVEN:
  150. uart->handle.Init.Parity = UART_PARITY_EVEN;
  151. break;
  152. default:
  153. uart->handle.Init.Parity = UART_PARITY_NONE;
  154. break;
  155. }
  156. #ifdef RT_SERIAL_USING_DMA
  157. uart->dma_rx.last_index = 0;
  158. #endif
  159. if (HAL_UART_Init(&uart->handle) != HAL_OK)
  160. {
  161. return -RT_ERROR;
  162. }
  163. return RT_EOK;
  164. }
  165. static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
  166. {
  167. struct stm32_uart *uart;
  168. #ifdef RT_SERIAL_USING_DMA
  169. rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
  170. #endif
  171. RT_ASSERT(serial != RT_NULL);
  172. uart = rt_container_of(serial, struct stm32_uart, serial);
  173. switch (cmd)
  174. {
  175. /* disable interrupt */
  176. case RT_DEVICE_CTRL_CLR_INT:
  177. /* disable rx irq */
  178. NVIC_DisableIRQ(uart->config->irq_type);
  179. /* disable interrupt */
  180. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
  181. #ifdef RT_SERIAL_USING_DMA
  182. /* disable DMA */
  183. if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
  184. {
  185. HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq);
  186. if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK)
  187. {
  188. RT_ASSERT(0);
  189. }
  190. if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK)
  191. {
  192. RT_ASSERT(0);
  193. }
  194. }
  195. else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
  196. {
  197. HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq);
  198. if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK)
  199. {
  200. RT_ASSERT(0);
  201. }
  202. }
  203. #endif
  204. break;
  205. /* enable interrupt */
  206. case RT_DEVICE_CTRL_SET_INT:
  207. /* enable rx irq */
  208. HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
  209. HAL_NVIC_EnableIRQ(uart->config->irq_type);
  210. /* enable interrupt */
  211. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
  212. break;
  213. #ifdef RT_SERIAL_USING_DMA
  214. case RT_DEVICE_CTRL_CONFIG:
  215. stm32_dma_config(serial, ctrl_arg);
  216. break;
  217. #endif
  218. case RT_DEVICE_CTRL_CLOSE:
  219. if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK )
  220. {
  221. RT_ASSERT(0)
  222. }
  223. break;
  224. }
  225. return RT_EOK;
  226. }
  227. static int stm32_putc(struct rt_serial_device *serial, char c)
  228. {
  229. struct stm32_uart *uart;
  230. RT_ASSERT(serial != RT_NULL);
  231. uart = rt_container_of(serial, struct stm32_uart, serial);
  232. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  233. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
  234. || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
  235. || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3)
  236. uart->handle.Instance->TDR = c;
  237. #else
  238. uart->handle.Instance->DR = c;
  239. #endif
  240. while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET);
  241. return 1;
  242. }
  243. static int stm32_getc(struct rt_serial_device *serial)
  244. {
  245. int ch;
  246. struct stm32_uart *uart;
  247. RT_ASSERT(serial != RT_NULL);
  248. uart = rt_container_of(serial, struct stm32_uart, serial);
  249. ch = -1;
  250. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  251. {
  252. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
  253. || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
  254. || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
  255. ch = uart->handle.Instance->RDR & 0xff;
  256. #else
  257. ch = uart->handle.Instance->DR & 0xff;
  258. #endif
  259. }
  260. return ch;
  261. }
  262. static rt_size_t stm32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
  263. {
  264. struct stm32_uart *uart;
  265. RT_ASSERT(serial != RT_NULL);
  266. RT_ASSERT(buf != RT_NULL);
  267. uart = rt_container_of(serial, struct stm32_uart, serial);
  268. if (size == 0)
  269. {
  270. return 0;
  271. }
  272. if (RT_SERIAL_DMA_TX == direction)
  273. {
  274. if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
  275. {
  276. return size;
  277. }
  278. else
  279. {
  280. return 0;
  281. }
  282. }
  283. return 0;
  284. }
  285. /**
  286. * Uart common interrupt process. This need add to uart ISR.
  287. *
  288. * @param serial serial device
  289. */
  290. static void uart_isr(struct rt_serial_device *serial)
  291. {
  292. struct stm32_uart *uart;
  293. #ifdef RT_SERIAL_USING_DMA
  294. rt_size_t recv_total_index, recv_len;
  295. rt_base_t level;
  296. #endif
  297. RT_ASSERT(serial != RT_NULL);
  298. uart = rt_container_of(serial, struct stm32_uart, serial);
  299. /* UART in mode Receiver -------------------------------------------------*/
  300. if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) &&
  301. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET))
  302. {
  303. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  304. }
  305. #ifdef RT_SERIAL_USING_DMA
  306. else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET)
  307. && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
  308. {
  309. level = rt_hw_interrupt_disable();
  310. recv_total_index = serial->config.bufsz - __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
  311. recv_len = recv_total_index - uart->dma_rx.last_index;
  312. uart->dma_rx.last_index = recv_total_index;
  313. rt_hw_interrupt_enable(level);
  314. if (recv_len)
  315. {
  316. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  317. }
  318. __HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
  319. }
  320. else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) &&
  321. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET))
  322. {
  323. if ((serial->parent.open_flag & RT_DEVICE_FLAG_DMA_TX) != 0)
  324. {
  325. HAL_UART_IRQHandler(&(uart->handle));
  326. }
  327. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  328. }
  329. #endif
  330. else
  331. {
  332. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET)
  333. {
  334. __HAL_UART_CLEAR_OREFLAG(&uart->handle);
  335. }
  336. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET)
  337. {
  338. __HAL_UART_CLEAR_NEFLAG(&uart->handle);
  339. }
  340. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET)
  341. {
  342. __HAL_UART_CLEAR_FEFLAG(&uart->handle);
  343. }
  344. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET)
  345. {
  346. __HAL_UART_CLEAR_PEFLAG(&uart->handle);
  347. }
  348. #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
  349. && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
  350. && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB)
  351. #ifdef SOC_SERIES_STM32F3
  352. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET)
  353. {
  354. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBDF);
  355. }
  356. #else
  357. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
  358. {
  359. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
  360. }
  361. #endif
  362. #endif
  363. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
  364. {
  365. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS);
  366. }
  367. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET)
  368. {
  369. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE);
  370. }
  371. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) != RESET)
  372. {
  373. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  374. }
  375. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  376. {
  377. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
  378. }
  379. }
  380. }
  381. #ifdef RT_SERIAL_USING_DMA
  382. static void dma_isr(struct rt_serial_device *serial)
  383. {
  384. struct stm32_uart *uart;
  385. rt_size_t recv_total_index, recv_len;
  386. rt_base_t level;
  387. RT_ASSERT(serial != RT_NULL);
  388. uart = rt_container_of(serial, struct stm32_uart, serial);
  389. if ((__HAL_DMA_GET_IT_SOURCE(&(uart->dma_rx.handle), DMA_IT_TC) != RESET) ||
  390. (__HAL_DMA_GET_IT_SOURCE(&(uart->dma_rx.handle), DMA_IT_HT) != RESET))
  391. {
  392. level = rt_hw_interrupt_disable();
  393. recv_total_index = serial->config.bufsz - __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
  394. if (recv_total_index == 0)
  395. {
  396. recv_len = serial->config.bufsz - uart->dma_rx.last_index;
  397. }
  398. else
  399. {
  400. recv_len = recv_total_index - uart->dma_rx.last_index;
  401. }
  402. uart->dma_rx.last_index = recv_total_index;
  403. rt_hw_interrupt_enable(level);
  404. if (recv_len)
  405. {
  406. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  407. }
  408. }
  409. }
  410. #endif
  411. #if defined(BSP_USING_UART1)
  412. void USART1_IRQHandler(void)
  413. {
  414. /* enter interrupt */
  415. rt_interrupt_enter();
  416. uart_isr(&(uart_obj[UART1_INDEX].serial));
  417. /* leave interrupt */
  418. rt_interrupt_leave();
  419. }
  420. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
  421. void UART1_DMA_RX_IRQHandler(void)
  422. {
  423. /* enter interrupt */
  424. rt_interrupt_enter();
  425. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
  426. /* leave interrupt */
  427. rt_interrupt_leave();
  428. }
  429. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
  430. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
  431. void UART1_DMA_TX_IRQHandler(void)
  432. {
  433. /* enter interrupt */
  434. rt_interrupt_enter();
  435. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
  436. /* leave interrupt */
  437. rt_interrupt_leave();
  438. }
  439. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
  440. #endif /* BSP_USING_UART1 */
  441. #if defined(BSP_USING_UART2)
  442. void USART2_IRQHandler(void)
  443. {
  444. /* enter interrupt */
  445. rt_interrupt_enter();
  446. uart_isr(&(uart_obj[UART2_INDEX].serial));
  447. /* leave interrupt */
  448. rt_interrupt_leave();
  449. }
  450. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
  451. void UART2_DMA_RX_IRQHandler(void)
  452. {
  453. /* enter interrupt */
  454. rt_interrupt_enter();
  455. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle);
  456. /* leave interrupt */
  457. rt_interrupt_leave();
  458. }
  459. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
  460. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
  461. void UART2_DMA_TX_IRQHandler(void)
  462. {
  463. /* enter interrupt */
  464. rt_interrupt_enter();
  465. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle);
  466. /* leave interrupt */
  467. rt_interrupt_leave();
  468. }
  469. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
  470. #endif /* BSP_USING_UART2 */
  471. #if defined(BSP_USING_UART3)
  472. void USART3_IRQHandler(void)
  473. {
  474. /* enter interrupt */
  475. rt_interrupt_enter();
  476. uart_isr(&(uart_obj[UART3_INDEX].serial));
  477. /* leave interrupt */
  478. rt_interrupt_leave();
  479. }
  480. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
  481. void UART3_DMA_RX_IRQHandler(void)
  482. {
  483. /* enter interrupt */
  484. rt_interrupt_enter();
  485. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle);
  486. /* leave interrupt */
  487. rt_interrupt_leave();
  488. }
  489. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
  490. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
  491. void UART3_DMA_TX_IRQHandler(void)
  492. {
  493. /* enter interrupt */
  494. rt_interrupt_enter();
  495. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle);
  496. /* leave interrupt */
  497. rt_interrupt_leave();
  498. }
  499. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */
  500. #endif /* BSP_USING_UART3*/
  501. #if defined(BSP_USING_UART4)
  502. void UART4_IRQHandler(void)
  503. {
  504. /* enter interrupt */
  505. rt_interrupt_enter();
  506. uart_isr(&(uart_obj[UART4_INDEX].serial));
  507. /* leave interrupt */
  508. rt_interrupt_leave();
  509. }
  510. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
  511. void UART4_DMA_RX_IRQHandler(void)
  512. {
  513. /* enter interrupt */
  514. rt_interrupt_enter();
  515. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle);
  516. /* leave interrupt */
  517. rt_interrupt_leave();
  518. }
  519. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
  520. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
  521. void UART4_DMA_TX_IRQHandler(void)
  522. {
  523. /* enter interrupt */
  524. rt_interrupt_enter();
  525. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle);
  526. /* leave interrupt */
  527. rt_interrupt_leave();
  528. }
  529. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */
  530. #endif /* BSP_USING_UART4*/
  531. #if defined(BSP_USING_UART5)
  532. void UART5_IRQHandler(void)
  533. {
  534. /* enter interrupt */
  535. rt_interrupt_enter();
  536. uart_isr(&(uart_obj[UART5_INDEX].serial));
  537. /* leave interrupt */
  538. rt_interrupt_leave();
  539. }
  540. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
  541. void UART5_DMA_RX_IRQHandler(void)
  542. {
  543. /* enter interrupt */
  544. rt_interrupt_enter();
  545. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle);
  546. /* leave interrupt */
  547. rt_interrupt_leave();
  548. }
  549. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
  550. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
  551. void UART5_DMA_TX_IRQHandler(void)
  552. {
  553. /* enter interrupt */
  554. rt_interrupt_enter();
  555. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle);
  556. /* leave interrupt */
  557. rt_interrupt_leave();
  558. }
  559. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
  560. #endif /* BSP_USING_UART5*/
  561. #if defined(BSP_USING_UART6)
  562. void USART6_IRQHandler(void)
  563. {
  564. /* enter interrupt */
  565. rt_interrupt_enter();
  566. uart_isr(&(uart_obj[UART6_INDEX].serial));
  567. /* leave interrupt */
  568. rt_interrupt_leave();
  569. }
  570. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA)
  571. void UART6_DMA_RX_IRQHandler(void)
  572. {
  573. /* enter interrupt */
  574. rt_interrupt_enter();
  575. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle);
  576. /* leave interrupt */
  577. rt_interrupt_leave();
  578. }
  579. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
  580. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
  581. void UART6_DMA_TX_IRQHandler(void)
  582. {
  583. /* enter interrupt */
  584. rt_interrupt_enter();
  585. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle);
  586. /* leave interrupt */
  587. rt_interrupt_leave();
  588. }
  589. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
  590. #endif /* BSP_USING_UART6*/
  591. #if defined(BSP_USING_UART7)
  592. void UART7_IRQHandler(void)
  593. {
  594. /* enter interrupt */
  595. rt_interrupt_enter();
  596. uart_isr(&(uart_obj[UART7_INDEX].serial));
  597. /* leave interrupt */
  598. rt_interrupt_leave();
  599. }
  600. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA)
  601. void UART7_DMA_RX_IRQHandler(void)
  602. {
  603. /* enter interrupt */
  604. rt_interrupt_enter();
  605. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle);
  606. /* leave interrupt */
  607. rt_interrupt_leave();
  608. }
  609. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */
  610. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA)
  611. void UART7_DMA_TX_IRQHandler(void)
  612. {
  613. /* enter interrupt */
  614. rt_interrupt_enter();
  615. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle);
  616. /* leave interrupt */
  617. rt_interrupt_leave();
  618. }
  619. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */
  620. #endif /* BSP_USING_UART7*/
  621. #if defined(BSP_USING_UART8)
  622. void UART8_IRQHandler(void)
  623. {
  624. /* enter interrupt */
  625. rt_interrupt_enter();
  626. uart_isr(&(uart_obj[UART8_INDEX].serial));
  627. /* leave interrupt */
  628. rt_interrupt_leave();
  629. }
  630. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA)
  631. void UART8_DMA_RX_IRQHandler(void)
  632. {
  633. /* enter interrupt */
  634. rt_interrupt_enter();
  635. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle);
  636. /* leave interrupt */
  637. rt_interrupt_leave();
  638. }
  639. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */
  640. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA)
  641. void UART8_DMA_TX_IRQHandler(void)
  642. {
  643. /* enter interrupt */
  644. rt_interrupt_enter();
  645. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle);
  646. /* leave interrupt */
  647. rt_interrupt_leave();
  648. }
  649. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
  650. #endif /* BSP_USING_UART8*/
  651. #if defined(BSP_USING_LPUART1)
  652. void LPUART1_IRQHandler(void)
  653. {
  654. /* enter interrupt */
  655. rt_interrupt_enter();
  656. uart_isr(&(uart_obj[LPUART1_INDEX].serial));
  657. /* leave interrupt */
  658. rt_interrupt_leave();
  659. }
  660. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA)
  661. void LPUART1_DMA_RX_IRQHandler(void)
  662. {
  663. /* enter interrupt */
  664. rt_interrupt_enter();
  665. HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma_rx.handle);
  666. /* leave interrupt */
  667. rt_interrupt_leave();
  668. }
  669. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
  670. #endif /* BSP_USING_LPUART1*/
  671. static void stm32_uart_get_dma_config(void)
  672. {
  673. #ifdef BSP_USING_UART1
  674. uart_obj[UART1_INDEX].uart_dma_flag = 0;
  675. #ifdef BSP_UART1_RX_USING_DMA
  676. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  677. static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
  678. uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
  679. #endif
  680. #ifdef BSP_UART1_TX_USING_DMA
  681. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  682. static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG;
  683. uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
  684. #endif
  685. #endif
  686. #ifdef BSP_USING_UART2
  687. uart_obj[UART2_INDEX].uart_dma_flag = 0;
  688. #ifdef BSP_UART2_RX_USING_DMA
  689. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  690. static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
  691. uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
  692. #endif
  693. #ifdef BSP_UART2_TX_USING_DMA
  694. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  695. static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG;
  696. uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
  697. #endif
  698. #endif
  699. #ifdef BSP_USING_UART3
  700. uart_obj[UART3_INDEX].uart_dma_flag = 0;
  701. #ifdef BSP_UART3_RX_USING_DMA
  702. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  703. static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
  704. uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
  705. #endif
  706. #ifdef BSP_UART3_TX_USING_DMA
  707. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  708. static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG;
  709. uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
  710. #endif
  711. #endif
  712. #ifdef BSP_USING_UART4
  713. uart_obj[UART4_INDEX].uart_dma_flag = 0;
  714. #ifdef BSP_UART4_RX_USING_DMA
  715. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  716. static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
  717. uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
  718. #endif
  719. #ifdef BSP_UART4_TX_USING_DMA
  720. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  721. static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG;
  722. uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
  723. #endif
  724. #endif
  725. #ifdef BSP_USING_UART5
  726. uart_obj[UART5_INDEX].uart_dma_flag = 0;
  727. #ifdef BSP_UART5_RX_USING_DMA
  728. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  729. static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
  730. uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
  731. #endif
  732. #ifdef BSP_UART5_TX_USING_DMA
  733. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  734. static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG;
  735. uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx;
  736. #endif
  737. #endif
  738. #ifdef BSP_USING_UART6
  739. uart_obj[UART6_INDEX].uart_dma_flag = 0;
  740. #ifdef BSP_UART6_RX_USING_DMA
  741. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  742. static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
  743. uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx;
  744. #endif
  745. #ifdef BSP_UART6_TX_USING_DMA
  746. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  747. static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG;
  748. uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx;
  749. #endif
  750. #endif
  751. }
  752. #ifdef RT_SERIAL_USING_DMA
  753. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
  754. {
  755. struct rt_serial_rx_fifo *rx_fifo;
  756. DMA_HandleTypeDef *DMA_Handle;
  757. struct dma_config *dma_config;
  758. struct stm32_uart *uart;
  759. RT_ASSERT(serial != RT_NULL);
  760. uart = rt_container_of(serial, struct stm32_uart, serial);
  761. if (RT_DEVICE_FLAG_DMA_RX == flag)
  762. {
  763. DMA_Handle = &uart->dma_rx.handle;
  764. dma_config = uart->config->dma_rx;
  765. }
  766. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  767. {
  768. DMA_Handle = &uart->dma_tx.handle;
  769. dma_config = uart->config->dma_tx;
  770. }
  771. LOG_D("%s dma config start", uart->config->name);
  772. {
  773. rt_uint32_t tmpreg = 0x00U;
  774. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
  775. || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3)
  776. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  777. SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
  778. tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
  779. #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
  780. || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
  781. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  782. SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  783. tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  784. #elif defined(SOC_SERIES_STM32MP1)
  785. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  786. SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
  787. tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
  788. #endif
  789. #if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1)
  790. /* enable DMAMUX clock for L4+ and G4 */
  791. __HAL_RCC_DMAMUX1_CLK_ENABLE();
  792. #elif defined(SOC_SERIES_STM32MP1)
  793. __HAL_RCC_DMAMUX_CLK_ENABLE();
  794. #endif
  795. UNUSED(tmpreg); /* To avoid compiler warnings */
  796. }
  797. if (RT_DEVICE_FLAG_DMA_RX == flag)
  798. {
  799. __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
  800. }
  801. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  802. {
  803. __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
  804. }
  805. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3)
  806. DMA_Handle->Instance = dma_config->Instance;
  807. #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  808. DMA_Handle->Instance = dma_config->Instance;
  809. DMA_Handle->Init.Channel = dma_config->channel;
  810. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
  811. || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  812. DMA_Handle->Instance = dma_config->Instance;
  813. DMA_Handle->Init.Request = dma_config->request;
  814. #endif
  815. DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
  816. DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
  817. DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  818. DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  819. if (RT_DEVICE_FLAG_DMA_RX == flag)
  820. {
  821. DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
  822. DMA_Handle->Init.Mode = DMA_CIRCULAR;
  823. }
  824. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  825. {
  826. DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
  827. DMA_Handle->Init.Mode = DMA_NORMAL;
  828. }
  829. DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
  830. #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  831. DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
  832. #endif
  833. if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
  834. {
  835. RT_ASSERT(0);
  836. }
  837. if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
  838. {
  839. RT_ASSERT(0);
  840. }
  841. /* enable interrupt */
  842. if (flag == RT_DEVICE_FLAG_DMA_RX)
  843. {
  844. rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  845. /* Start DMA transfer */
  846. if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
  847. {
  848. /* Transfer error in reception process */
  849. RT_ASSERT(0);
  850. }
  851. CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
  852. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
  853. }
  854. /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */
  855. HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
  856. HAL_NVIC_EnableIRQ(dma_config->dma_irq);
  857. HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
  858. HAL_NVIC_EnableIRQ(uart->config->irq_type);
  859. LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance);
  860. LOG_D("%s dma config done", uart->config->name);
  861. }
  862. /**
  863. * @brief UART error callbacks
  864. * @param huart: UART handle
  865. * @note This example shows a simple way to report transfer error, and you can
  866. * add your own implementation.
  867. * @retval None
  868. */
  869. void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
  870. {
  871. RT_ASSERT(huart != NULL);
  872. struct stm32_uart *uart = (struct stm32_uart *)huart;
  873. LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode);
  874. UNUSED(uart);
  875. }
  876. /**
  877. * @brief Rx Transfer completed callback
  878. * @param huart: UART handle
  879. * @note This example shows a simple way to report end of DMA Rx transfer, and
  880. * you can add your own implementation.
  881. * @retval None
  882. */
  883. void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
  884. {
  885. struct stm32_uart *uart;
  886. RT_ASSERT(huart != NULL);
  887. uart = (struct stm32_uart *)huart;
  888. dma_isr(&uart->serial);
  889. }
  890. /**
  891. * @brief Rx Half transfer completed callback
  892. * @param huart: UART handle
  893. * @note This example shows a simple way to report end of DMA Rx Half transfer,
  894. * and you can add your own implementation.
  895. * @retval None
  896. */
  897. void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
  898. {
  899. struct stm32_uart *uart;
  900. RT_ASSERT(huart != NULL);
  901. uart = (struct stm32_uart *)huart;
  902. dma_isr(&uart->serial);
  903. }
  904. static void _dma_tx_complete(struct rt_serial_device *serial)
  905. {
  906. struct stm32_uart *uart;
  907. rt_size_t trans_total_index;
  908. rt_base_t level;
  909. RT_ASSERT(serial != RT_NULL);
  910. uart = rt_container_of(serial, struct stm32_uart, serial);
  911. level = rt_hw_interrupt_disable();
  912. trans_total_index = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle));
  913. rt_hw_interrupt_enable(level);
  914. if (trans_total_index == 0)
  915. {
  916. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
  917. }
  918. }
  919. /**
  920. * @brief HAL_UART_TxCpltCallback
  921. * @param huart: UART handle
  922. * @note This callback can be called by two functions, first in UART_EndTransmit_IT when
  923. * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode.
  924. * @retval None
  925. */
  926. void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
  927. {
  928. struct stm32_uart *uart;
  929. RT_ASSERT(huart != NULL);
  930. uart = (struct stm32_uart *)huart;
  931. _dma_tx_complete(&uart->serial);
  932. }
  933. #endif /* RT_SERIAL_USING_DMA */
  934. static const struct rt_uart_ops stm32_uart_ops =
  935. {
  936. .configure = stm32_configure,
  937. .control = stm32_control,
  938. .putc = stm32_putc,
  939. .getc = stm32_getc,
  940. .dma_transmit = stm32_dma_transmit
  941. };
  942. int rt_hw_usart_init(void)
  943. {
  944. rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart);
  945. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  946. rt_err_t result = 0;
  947. stm32_uart_get_dma_config();
  948. for (int i = 0; i < obj_num; i++)
  949. {
  950. /* init UART object */
  951. uart_obj[i].config = &uart_config[i];
  952. uart_obj[i].serial.ops = &stm32_uart_ops;
  953. uart_obj[i].serial.config = config;
  954. /* register UART device */
  955. result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
  956. RT_DEVICE_FLAG_RDWR
  957. | RT_DEVICE_FLAG_INT_RX
  958. | RT_DEVICE_FLAG_INT_TX
  959. | uart_obj[i].uart_dma_flag
  960. , NULL);
  961. RT_ASSERT(result == RT_EOK);
  962. }
  963. return result;
  964. }
  965. #endif /* RT_USING_SERIAL */