drv_uart.c 5.1 KB

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  1. /*
  2. * File : drv_uart.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://www.rt-thread.org/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. * 2013-05-18 Bernard The first version for LPC40xx
  13. * 2014-07-18 ArdaFu Port to TM4C129X
  14. */
  15. #include <rthw.h>
  16. #include <rtthread.h>
  17. #include <rtdevice.h>
  18. #include "board.h"
  19. //#include <components.h>
  20. #include "inc/hw_memmap.h"
  21. #include "driverlib/sysctl.h"
  22. #include "driverlib/gpio.h"
  23. #include "driverlib/uart.h"
  24. #include "driverlib/pin_map.h"
  25. #include "driverlib/interrupt.h"
  26. #include "driverlib/rom_map.h"
  27. typedef struct hw_uart_device
  28. {
  29. uint32_t hw_base; // base address
  30. }hw_uart_t;
  31. #define mUartGetHwPtr(serial) ((hw_uart_t*)(serial->parent.user_data))
  32. static rt_err_t hw_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  33. {
  34. uint32_t config = 0;
  35. hw_uart_t* uart;
  36. RT_ASSERT(serial != RT_NULL);
  37. uart = mUartGetHwPtr(serial);
  38. MAP_UARTDisable(uart->hw_base);
  39. // build UART Configuration parameter structure
  40. switch(cfg->data_bits)
  41. {
  42. case DATA_BITS_9:
  43. // enable 9bit address mode and set DATA_BIT_8
  44. MAP_UART9BitEnable(uart->hw_base);
  45. case DATA_BITS_8:
  46. config |= UART_CONFIG_WLEN_8;
  47. break;
  48. case DATA_BITS_7:
  49. config |= UART_CONFIG_WLEN_7;
  50. break;
  51. case DATA_BITS_6:
  52. config |= UART_CONFIG_WLEN_6;
  53. break;
  54. case DATA_BITS_5:
  55. config |= UART_CONFIG_WLEN_5;
  56. break;
  57. default:
  58. RT_ASSERT(0);
  59. break;
  60. }
  61. switch(cfg->parity)
  62. {
  63. case PARITY_ODD:
  64. config |= UART_CONFIG_PAR_ODD;
  65. break;
  66. case PARITY_EVEN:
  67. config |= UART_CONFIG_PAR_EVEN;
  68. break;
  69. case PARITY_NONE:
  70. config |= UART_CONFIG_PAR_NONE;
  71. break;
  72. default:
  73. RT_ASSERT(0);
  74. break;
  75. }
  76. switch(cfg->stop_bits)
  77. {
  78. case STOP_BITS_1:
  79. config |= UART_CONFIG_STOP_ONE;
  80. break;
  81. case STOP_BITS_2:
  82. config |= UART_CONFIG_STOP_TWO;
  83. break;
  84. default:
  85. RT_ASSERT(0);
  86. break;
  87. }
  88. // Initialize UART0 peripheral with given to corresponding parameter
  89. MAP_UARTConfigSetExpClk(uart->hw_base, SysClock, cfg->baud_rate, config);
  90. MAP_UARTFIFOEnable(uart->hw_base);
  91. // Enable the UART.
  92. MAP_UARTEnable(uart->hw_base);
  93. return RT_EOK;
  94. }
  95. static rt_err_t hw_control(struct rt_serial_device *serial, int cmd, void *arg)
  96. {
  97. hw_uart_t* uart;
  98. RT_ASSERT(serial != RT_NULL);
  99. uart = mUartGetHwPtr(serial);
  100. switch (cmd)
  101. {
  102. case RT_DEVICE_CTRL_CLR_INT:
  103. /* disable rx irq */
  104. MAP_UARTIntDisable(uart->hw_base, UART_INT_RX | UART_INT_RT);
  105. break;
  106. case RT_DEVICE_CTRL_SET_INT:
  107. /* enable rx irq */
  108. MAP_UARTIntEnable(uart->hw_base, UART_INT_RX | UART_INT_RT);
  109. break;
  110. }
  111. return RT_EOK;
  112. }
  113. static int hw_putc(struct rt_serial_device *serial, char c)
  114. {
  115. hw_uart_t* uart;
  116. RT_ASSERT(serial != RT_NULL);
  117. uart = mUartGetHwPtr(serial);
  118. MAP_UARTCharPut(uart->hw_base, *((uint8_t *)&c));
  119. return 1;
  120. }
  121. static int hw_getc(struct rt_serial_device *serial)
  122. {
  123. hw_uart_t* uart;
  124. RT_ASSERT(serial != RT_NULL);
  125. uart = mUartGetHwPtr(serial);
  126. return MAP_UARTCharGetNonBlocking(uart->hw_base);
  127. }
  128. static const struct rt_uart_ops hw_uart_ops =
  129. {
  130. hw_configure,
  131. hw_control,
  132. hw_putc,
  133. hw_getc,
  134. };
  135. #if defined(RT_USING_UART0)
  136. /* UART0 device driver structure */
  137. struct rt_serial_device serial0;
  138. hw_uart_t uart0 =
  139. {
  140. UART0_BASE,
  141. };
  142. void UART0_IRQHandler(void)
  143. {
  144. uint32_t intsrc;
  145. hw_uart_t *uart = &uart0;
  146. /* enter interrupt */
  147. rt_interrupt_enter();
  148. /* Determine the interrupt source */
  149. intsrc = MAP_UARTIntStatus(uart->hw_base, true);
  150. // Receive Data Available or Character time-out
  151. if (intsrc & (UART_INT_RX | UART_INT_RT))
  152. {
  153. MAP_UARTIntClear(uart->hw_base, intsrc);
  154. rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
  155. }
  156. /* leave interrupt */
  157. rt_interrupt_leave();
  158. }
  159. #endif
  160. int rt_hw_uart_init(void)
  161. {
  162. hw_uart_t* uart;
  163. struct serial_configure config;
  164. config.baud_rate = BAUD_RATE_115200;
  165. config.bit_order = BIT_ORDER_LSB;
  166. config.data_bits = DATA_BITS_8;
  167. config.parity = PARITY_NONE;
  168. config.stop_bits = STOP_BITS_1;
  169. config.invert = NRZ_NORMAL;
  170. config.bufsz = RT_SERIAL_RB_BUFSZ;
  171. #ifdef RT_USING_UART0
  172. uart = &uart0;
  173. serial0.ops = &hw_uart_ops;
  174. serial0.config = config;
  175. MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
  176. MAP_GPIOPinConfigure(GPIO_PA0_U0RX);
  177. MAP_GPIOPinConfigure(GPIO_PA1_U0TX);
  178. MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
  179. MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
  180. /* preemption = 1, sub-priority = 1 */
  181. //IntPrioritySet(INT_UART0, ((0x01 << 5) | 0x01));
  182. /* Enable Interrupt for UART channel */
  183. UARTIntRegister(uart->hw_base, UART0_IRQHandler);
  184. MAP_IntEnable(INT_UART0);
  185. MAP_UARTEnable(uart->hw_base);
  186. /* register UART0 device */
  187. rt_hw_serial_register(&serial0, "uart0",
  188. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  189. uart);
  190. #endif
  191. return 0;
  192. }
  193. //INIT_BOARD_EXPORT(rt_hw_uart_init);