mmcsd_core.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686
  1. /*
  2. * File : mmcsd_core.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2006, RT-Thread Development Team
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along
  17. * with this program; if not, write to the Free Software Foundation, Inc.,
  18. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19. *
  20. * Change Logs:
  21. * Date Author Notes
  22. * 2011-07-25 weety first version
  23. */
  24. #include <rtthread.h>
  25. #include <drivers/mmcsd_core.h>
  26. #include <drivers/sd.h>
  27. #ifndef RT_MMCSD_STACK_SIZE
  28. #define RT_MMCSD_STACK_SIZE 1024
  29. #endif
  30. #ifndef RT_MMCSD_THREAD_PREORITY
  31. #if (RT_THREAD_PRIORITY_MAX == 32)
  32. #define RT_MMCSD_THREAD_PREORITY 0x16
  33. #else
  34. #define RT_MMCSD_THREAD_PREORITY 0x40
  35. #endif
  36. #endif
  37. //static struct rt_semaphore mmcsd_sem;
  38. static struct rt_thread mmcsd_detect_thread;
  39. static rt_uint8_t mmcsd_stack[RT_MMCSD_STACK_SIZE];
  40. static struct rt_mailbox mmcsd_detect_mb;
  41. static rt_uint32_t mmcsd_detect_mb_pool[4];
  42. void mmcsd_host_lock(struct rt_mmcsd_host *host)
  43. {
  44. rt_sem_take(&host->bus_lock, RT_WAITING_FOREVER);
  45. }
  46. void mmcsd_host_unlock(struct rt_mmcsd_host *host)
  47. {
  48. rt_sem_release(&host->bus_lock);
  49. }
  50. void mmcsd_req_complete(struct rt_mmcsd_host *host)
  51. {
  52. rt_sem_release(&host->sem_ack);
  53. }
  54. void mmcsd_send_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
  55. {
  56. req->cmd->err = 0;
  57. req->cmd->mrq = req;
  58. if (req->data)
  59. {
  60. req->cmd->data = req->data;
  61. req->data->err = 0;
  62. req->data->mrq = req;
  63. if (req->stop)
  64. {
  65. req->data->stop = req->stop;
  66. req->stop->err = 0;
  67. req->stop->mrq = req;
  68. }
  69. }
  70. host->ops->request(host, req);
  71. rt_sem_take(&host->sem_ack, RT_WAITING_FOREVER);
  72. }
  73. rt_int32_t mmcsd_send_cmd(struct rt_mmcsd_host *host,
  74. struct rt_mmcsd_cmd *cmd,
  75. int retries)
  76. {
  77. struct rt_mmcsd_req req;
  78. rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
  79. rt_memset(cmd->resp, 0, sizeof(cmd->resp));
  80. req.cmd = cmd;
  81. cmd->data = RT_NULL;
  82. mmcsd_send_request(host, &req);
  83. return cmd->err;
  84. }
  85. rt_int32_t mmcsd_go_idle(struct rt_mmcsd_host *host)
  86. {
  87. rt_int32_t err;
  88. struct rt_mmcsd_cmd cmd;
  89. if (!controller_is_spi(host))
  90. {
  91. mmcsd_set_chip_select(host, MMCSD_CS_HIGH);
  92. mmcsd_delay_ms(1);
  93. }
  94. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  95. cmd.cmd_code = GO_IDLE_STATE;
  96. cmd.arg = 0;
  97. cmd.flags = RESP_SPI_R1 | RESP_NONE | CMD_BC;
  98. err = mmcsd_send_cmd(host, &cmd, 0);
  99. mmcsd_delay_ms(1);
  100. if (!controller_is_spi(host))
  101. {
  102. mmcsd_set_chip_select(host, MMCSD_CS_IGNORE);
  103. mmcsd_delay_ms(1);
  104. }
  105. return err;
  106. }
  107. rt_int32_t mmcsd_spi_read_ocr(struct rt_mmcsd_host *host,
  108. rt_int32_t high_capacity,
  109. rt_uint32_t *ocr)
  110. {
  111. struct rt_mmcsd_cmd cmd;
  112. rt_int32_t err;
  113. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  114. cmd.cmd_code = SPI_READ_OCR;
  115. cmd.arg = high_capacity ? (1 << 30) : 0;
  116. cmd.flags = RESP_SPI_R3;
  117. err = mmcsd_send_cmd(host, &cmd, 0);
  118. *ocr = cmd.resp[1];
  119. return err;
  120. }
  121. rt_int32_t mmcsd_all_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid)
  122. {
  123. rt_int32_t err;
  124. struct rt_mmcsd_cmd cmd;
  125. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  126. cmd.cmd_code = ALL_SEND_CID;
  127. cmd.arg = 0;
  128. cmd.flags = RESP_R2 | CMD_BCR;
  129. err = mmcsd_send_cmd(host, &cmd, 3);
  130. if (err)
  131. return err;
  132. rt_memcpy(cid, cmd.resp, sizeof(rt_uint32_t) * 4);
  133. return 0;
  134. }
  135. rt_int32_t mmcsd_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid)
  136. {
  137. rt_int32_t err, i;
  138. struct rt_mmcsd_req req;
  139. struct rt_mmcsd_cmd cmd;
  140. struct rt_mmcsd_data data;
  141. rt_uint32_t *buf = RT_NULL;
  142. if (!controller_is_spi(host))
  143. {
  144. if (!host->card)
  145. return -RT_ERROR;
  146. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  147. cmd.cmd_code = SEND_CID;
  148. cmd.arg = host->card->rca << 16;
  149. cmd.flags = RESP_R2 | CMD_AC;
  150. err = mmcsd_send_cmd(host, &cmd, 3);
  151. if (err)
  152. return err;
  153. rt_memcpy(cid, cmd.resp, sizeof(rt_uint32_t) * 4);
  154. return 0;
  155. }
  156. buf = (rt_uint32_t *)rt_malloc(16);
  157. if (!buf)
  158. {
  159. rt_kprintf("allocate memory failed\n");
  160. return -RT_ENOMEM;
  161. }
  162. rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
  163. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  164. rt_memset(&data, 0, sizeof(struct rt_mmcsd_data));
  165. req.cmd = &cmd;
  166. req.data = &data;
  167. cmd.cmd_code = SEND_CID;
  168. cmd.arg = 0;
  169. /* NOTE HACK: the RESP_SPI_R1 is always correct here, but we
  170. * rely on callers to never use this with "native" calls for reading
  171. * CSD or CID. Native versions of those commands use the R2 type,
  172. * not R1 plus a data block.
  173. */
  174. cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC;
  175. data.blksize = 16;
  176. data.blks = 1;
  177. data.flags = DATA_DIR_READ;
  178. data.buf = buf;
  179. /*
  180. * The spec states that CSR and CID accesses have a timeout
  181. * of 64 clock cycles.
  182. */
  183. data.timeout_ns = 0;
  184. data.timeout_clks = 64;
  185. mmcsd_send_request(host, &req);
  186. if (cmd.err || data.err)
  187. {
  188. rt_free(buf);
  189. return -RT_ERROR;
  190. }
  191. for (i = 0;i < 4;i++)
  192. cid[i] = buf[i];
  193. rt_free(buf);
  194. return 0;
  195. }
  196. rt_int32_t mmcsd_get_csd(struct rt_mmcsd_card *card, rt_uint32_t *csd)
  197. {
  198. rt_int32_t err, i;
  199. struct rt_mmcsd_req req;
  200. struct rt_mmcsd_cmd cmd;
  201. struct rt_mmcsd_data data;
  202. rt_uint32_t *buf = RT_NULL;
  203. if (!controller_is_spi(card->host))
  204. {
  205. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  206. cmd.cmd_code = SEND_CSD;
  207. cmd.arg = card->rca << 16;
  208. cmd.flags = RESP_R2 | CMD_AC;
  209. err = mmcsd_send_cmd(card->host, &cmd, 3);
  210. if (err)
  211. return err;
  212. rt_memcpy(csd, cmd.resp, sizeof(rt_uint32_t) * 4);
  213. return 0;
  214. }
  215. buf = (rt_uint32_t*)rt_malloc(16);
  216. if (!buf)
  217. {
  218. rt_kprintf("allocate memory failed\n");
  219. return -RT_ENOMEM;
  220. }
  221. rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
  222. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  223. rt_memset(&data, 0, sizeof(struct rt_mmcsd_data));
  224. req.cmd = &cmd;
  225. req.data = &data;
  226. cmd.cmd_code = SEND_CSD;
  227. cmd.arg = 0;
  228. /* NOTE HACK: the RESP_SPI_R1 is always correct here, but we
  229. * rely on callers to never use this with "native" calls for reading
  230. * CSD or CID. Native versions of those commands use the R2 type,
  231. * not R1 plus a data block.
  232. */
  233. cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC;
  234. data.blksize = 16;
  235. data.blks = 1;
  236. data.flags = DATA_DIR_READ;
  237. data.buf = buf;
  238. /*
  239. * The spec states that CSR and CID accesses have a timeout
  240. * of 64 clock cycles.
  241. */
  242. data.timeout_ns = 0;
  243. data.timeout_clks = 64;
  244. mmcsd_send_request(card->host, &req);
  245. if (cmd.err || data.err)
  246. {
  247. rt_free(buf);
  248. return -RT_ERROR;
  249. }
  250. for (i = 0;i < 4;i++)
  251. csd[i] = buf[i];
  252. rt_free(buf);
  253. return 0;
  254. }
  255. static rt_int32_t _mmcsd_select_card(struct rt_mmcsd_host *host,
  256. struct rt_mmcsd_card *card)
  257. {
  258. rt_int32_t err;
  259. struct rt_mmcsd_cmd cmd;
  260. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  261. cmd.cmd_code = SELECT_CARD;
  262. if (card)
  263. {
  264. cmd.arg = card->rca << 16;
  265. cmd.flags = RESP_R1 | CMD_AC;
  266. }
  267. else
  268. {
  269. cmd.arg = 0;
  270. cmd.flags = RESP_NONE | CMD_AC;
  271. }
  272. err = mmcsd_send_cmd(host, &cmd, 3);
  273. if (err)
  274. return err;
  275. return 0;
  276. }
  277. rt_int32_t mmcsd_select_card(struct rt_mmcsd_card *card)
  278. {
  279. return _mmcsd_select_card(card->host, card);
  280. }
  281. rt_int32_t mmcsd_deselect_cards(struct rt_mmcsd_card *card)
  282. {
  283. return _mmcsd_select_card(card->host, RT_NULL);
  284. }
  285. rt_int32_t mmcsd_spi_use_crc(struct rt_mmcsd_host *host, rt_int32_t use_crc)
  286. {
  287. struct rt_mmcsd_cmd cmd;
  288. rt_int32_t err;
  289. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  290. cmd.cmd_code = SPI_CRC_ON_OFF;
  291. cmd.flags = RESP_SPI_R1;
  292. cmd.arg = use_crc;
  293. err = mmcsd_send_cmd(host, &cmd, 0);
  294. if (!err)
  295. host->spi_use_crc = use_crc;
  296. return err;
  297. }
  298. rt_inline void mmcsd_set_iocfg(struct rt_mmcsd_host *host)
  299. {
  300. struct rt_mmcsd_io_cfg *io_cfg = &host->io_cfg;
  301. mmcsd_dbg("clock %uHz busmode %u powermode %u cs %u Vdd %u "
  302. "width %u \n",
  303. io_cfg->clock, io_cfg->bus_mode,
  304. io_cfg->power_mode, io_cfg->chip_select, io_cfg->vdd,
  305. io_cfg->bus_width);
  306. host->ops->set_iocfg(host, io_cfg);
  307. }
  308. /*
  309. * Control chip select pin on a host.
  310. */
  311. void mmcsd_set_chip_select(struct rt_mmcsd_host *host, rt_int32_t mode)
  312. {
  313. host->io_cfg.chip_select = mode;
  314. mmcsd_set_iocfg(host);
  315. }
  316. /*
  317. * Sets the host clock to the highest possible frequency that
  318. * is below "hz".
  319. */
  320. void mmcsd_set_clock(struct rt_mmcsd_host *host, rt_uint32_t clk)
  321. {
  322. if (clk < host->freq_min)
  323. {
  324. rt_kprintf("clock too low\n");
  325. }
  326. host->io_cfg.clock = clk;
  327. mmcsd_set_iocfg(host);
  328. }
  329. /*
  330. * Change the bus mode (open drain/push-pull) of a host.
  331. */
  332. void mmcsd_set_bus_mode(struct rt_mmcsd_host *host, rt_uint32_t mode)
  333. {
  334. host->io_cfg.bus_mode = mode;
  335. mmcsd_set_iocfg(host);
  336. }
  337. /*
  338. * Change data bus width of a host.
  339. */
  340. void mmcsd_set_bus_width(struct rt_mmcsd_host *host, rt_uint32_t width)
  341. {
  342. host->io_cfg.bus_width = width;
  343. mmcsd_set_iocfg(host);
  344. }
  345. void mmcsd_set_data_timeout(struct rt_mmcsd_data *data,
  346. const struct rt_mmcsd_card *card)
  347. {
  348. rt_uint32_t mult;
  349. if (card->card_type == CARD_TYPE_SDIO)
  350. {
  351. data->timeout_ns = 1000000000; /* SDIO card 1s */
  352. data->timeout_clks = 0;
  353. return;
  354. }
  355. /*
  356. * SD cards use a 100 multiplier rather than 10
  357. */
  358. mult = (card->card_type == CARD_TYPE_SD) ? 100 : 10;
  359. /*
  360. * Scale up the multiplier (and therefore the timeout) by
  361. * the r2w factor for writes.
  362. */
  363. if (data->flags & DATA_DIR_WRITE)
  364. mult <<= card->csd.r2w_factor;
  365. data->timeout_ns = card->tacc_ns * mult;
  366. data->timeout_clks = card->tacc_clks * mult;
  367. /*
  368. * SD cards also have an upper limit on the timeout.
  369. */
  370. if (card->card_type == CARD_TYPE_SD)
  371. {
  372. rt_uint32_t timeout_us, limit_us;
  373. timeout_us = data->timeout_ns / 1000;
  374. timeout_us += data->timeout_clks * 1000 /
  375. (card->host->io_cfg.clock / 1000);
  376. if (data->flags & DATA_DIR_WRITE)
  377. /*
  378. * The limit is really 250 ms, but that is
  379. * insufficient for some crappy cards.
  380. */
  381. limit_us = 300000;
  382. else
  383. limit_us = 100000;
  384. /*
  385. * SDHC cards always use these fixed values.
  386. */
  387. if (timeout_us > limit_us || card->flags & CARD_FLAG_SDHC)
  388. {
  389. data->timeout_ns = limit_us * 1000; /* SDHC card fixed 250ms */
  390. data->timeout_clks = 0;
  391. }
  392. }
  393. if (controller_is_spi(card->host))
  394. {
  395. if (data->flags & DATA_DIR_WRITE)
  396. {
  397. if (data->timeout_ns < 1000000000)
  398. data->timeout_ns = 1000000000; /* 1s */
  399. }
  400. else
  401. {
  402. if (data->timeout_ns < 100000000)
  403. data->timeout_ns = 100000000; /* 100ms */
  404. }
  405. }
  406. }
  407. /*
  408. * Mask off any voltages we don't support and select
  409. * the lowest voltage
  410. */
  411. rt_uint32_t mmcsd_select_voltage(struct rt_mmcsd_host *host, rt_uint32_t ocr)
  412. {
  413. int bit;
  414. ocr &= host->valid_ocr;
  415. bit = __rt_ffs(ocr);
  416. if (bit)
  417. {
  418. bit -= 1;
  419. ocr &= 3 << bit;
  420. host->io_cfg.vdd = bit;
  421. mmcsd_set_iocfg(host);
  422. }
  423. else
  424. {
  425. rt_kprintf("host doesn't support card's voltages\n");
  426. ocr = 0;
  427. }
  428. return ocr;
  429. }
  430. static void mmcsd_power_up(struct rt_mmcsd_host *host)
  431. {
  432. int bit = fls(host->valid_ocr) - 1;
  433. host->io_cfg.vdd = bit;
  434. if (controller_is_spi(host))
  435. {
  436. host->io_cfg.chip_select = MMCSD_CS_HIGH;
  437. host->io_cfg.bus_mode = MMCSD_BUSMODE_PUSHPULL;
  438. }
  439. else
  440. {
  441. host->io_cfg.chip_select = MMCSD_CS_IGNORE;
  442. host->io_cfg.bus_mode = MMCSD_BUSMODE_OPENDRAIN;
  443. }
  444. host->io_cfg.power_mode = MMCSD_POWER_UP;
  445. host->io_cfg.bus_width = MMCSD_BUS_WIDTH_1;
  446. mmcsd_set_iocfg(host);
  447. /*
  448. * This delay should be sufficient to allow the power supply
  449. * to reach the minimum voltage.
  450. */
  451. mmcsd_delay_ms(10);
  452. host->io_cfg.clock = host->freq_min;
  453. host->io_cfg.power_mode = MMCSD_POWER_ON;
  454. mmcsd_set_iocfg(host);
  455. /*
  456. * This delay must be at least 74 clock sizes, or 1 ms, or the
  457. * time required to reach a stable voltage.
  458. */
  459. mmcsd_delay_ms(10);
  460. }
  461. static void mmcsd_power_off(struct rt_mmcsd_host *host)
  462. {
  463. host->io_cfg.clock = 0;
  464. host->io_cfg.vdd = 0;
  465. if (!controller_is_spi(host))
  466. {
  467. host->io_cfg.bus_mode = MMCSD_BUSMODE_OPENDRAIN;
  468. host->io_cfg.chip_select = MMCSD_CS_IGNORE;
  469. }
  470. host->io_cfg.power_mode = MMCSD_POWER_OFF;
  471. host->io_cfg.bus_width = MMCSD_BUS_WIDTH_1;
  472. mmcsd_set_iocfg(host);
  473. }
  474. void mmcsd_change(struct rt_mmcsd_host *host)
  475. {
  476. rt_mb_send(&mmcsd_detect_mb, (rt_uint32_t)host);
  477. }
  478. void mmcsd_detect(void *param)
  479. {
  480. struct rt_mmcsd_host *host;
  481. rt_uint32_t ocr;
  482. rt_int32_t err;
  483. while (1)
  484. {
  485. if (rt_mb_recv(&mmcsd_detect_mb, (rt_uint32_t*)&host, RT_WAITING_FOREVER) == RT_EOK)
  486. {
  487. if (host->card == RT_NULL)
  488. {
  489. mmcsd_host_lock(host);
  490. mmcsd_power_up(host);
  491. mmcsd_go_idle(host);
  492. mmcsd_send_if_cond(host, host->valid_ocr);
  493. err = sdio_io_send_op_cond(host, 0, &ocr);
  494. if (!err)
  495. {
  496. if (init_sdio(host, ocr))
  497. mmcsd_power_off(host);
  498. mmcsd_host_unlock(host);
  499. continue;
  500. }
  501. /*
  502. * detect SD card
  503. */
  504. err = mmcsd_send_app_op_cond(host, 0, &ocr);
  505. if (!err)
  506. {
  507. if (init_sd(host, ocr))
  508. mmcsd_power_off(host);
  509. mmcsd_host_unlock(host);
  510. continue;
  511. }
  512. mmcsd_host_unlock(host);
  513. }
  514. }
  515. }
  516. }
  517. struct rt_mmcsd_host *mmcsd_alloc_host(void)
  518. {
  519. struct rt_mmcsd_host *host;
  520. host = rt_malloc(sizeof(struct rt_mmcsd_host));
  521. if (!host)
  522. {
  523. rt_kprintf("alloc host failed\n");
  524. return RT_NULL;
  525. }
  526. rt_memset(host, 0, sizeof(struct rt_mmcsd_host));
  527. host->max_seg_size = 65535;
  528. host->max_dma_segs = 1;
  529. host->max_blk_size = 512;
  530. host->max_blk_count = 4096;
  531. rt_sem_init(&host->bus_lock, "sd_bus_lock", 1, RT_IPC_FLAG_FIFO);
  532. rt_sem_init(&host->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO);
  533. return host;
  534. }
  535. void mmcsd_free_host(struct rt_mmcsd_host *host)
  536. {
  537. rt_sem_detach(&host->bus_lock);
  538. rt_sem_detach(&host->sem_ack);
  539. rt_free(host);
  540. }
  541. void rt_mmcsd_core_init(void)
  542. {
  543. rt_err_t ret;
  544. /* init detect sd cart thread */
  545. /* init mailbox and create detect sd card thread */
  546. ret = rt_mb_init(&mmcsd_detect_mb, "mmcsdmb",
  547. &mmcsd_detect_mb_pool[0], sizeof(mmcsd_detect_mb_pool),
  548. RT_IPC_FLAG_FIFO);
  549. RT_ASSERT(ret == RT_EOK);
  550. ret = rt_thread_init(&mmcsd_detect_thread, "mmcsd_detect", mmcsd_detect, RT_NULL,
  551. &mmcsd_stack[0], RT_MMCSD_STACK_SIZE, RT_MMCSD_THREAD_PREORITY, 20);
  552. if (ret == RT_EOK)
  553. {
  554. rt_thread_startup(&mmcsd_detect_thread);
  555. }
  556. rt_sdio_init();
  557. }