epi.c 37 KB

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  1. //*****************************************************************************
  2. //
  3. // epi.c - Driver for the EPI module.
  4. //
  5. // Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved.
  6. // Software License Agreement
  7. //
  8. // Texas Instruments (TI) is supplying this software for use solely and
  9. // exclusively on TI's microcontroller products. The software is owned by
  10. // TI and/or its suppliers, and is protected under applicable copyright
  11. // laws. You may not combine this software with "viral" open-source
  12. // software in order to form a larger program.
  13. //
  14. // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
  15. // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
  16. // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  17. // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
  18. // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
  19. // DAMAGES, FOR ANY REASON WHATSOEVER.
  20. //
  21. // This is part of revision 6459 of the Stellaris Peripheral Driver Library.
  22. //
  23. //*****************************************************************************
  24. #include "inc/hw_epi.h"
  25. #include "inc/hw_ints.h"
  26. #include "inc/hw_memmap.h"
  27. #include "inc/hw_types.h"
  28. #include "driverlib/debug.h"
  29. #include "driverlib/epi.h"
  30. #include "driverlib/interrupt.h"
  31. //*****************************************************************************
  32. //
  33. //! \addtogroup epi_api
  34. //! @{
  35. //
  36. //*****************************************************************************
  37. //*****************************************************************************
  38. //
  39. //! Sets the usage mode of the EPI module.
  40. //!
  41. //! \param ulBase is the EPI module base address.
  42. //! \param ulMode is the usage mode of the EPI module.
  43. //!
  44. //! This functions sets the operating mode of the EPI module. The parameter
  45. //! \e ulMode must be one of the following:
  46. //!
  47. //! - \b EPI_MODE_GENERAL - use for general-purpose mode operation
  48. //! - \b EPI_MODE_SDRAM - use with SDRAM device
  49. //! - \b EPI_MODE_HB8 - use with host-bus 8-bit interface
  50. //! - \b EPI_MODE_DISABLE - disable the EPI module
  51. //!
  52. //! Selection of any of the above modes will enable the EPI module, except
  53. //! for \b EPI_MODE_DISABLE which should be used to disable the module.
  54. //!
  55. //! \return None.
  56. //
  57. //*****************************************************************************
  58. void
  59. EPIModeSet(unsigned long ulBase, unsigned long ulMode)
  60. {
  61. //
  62. // Check the arguments.
  63. //
  64. ASSERT(ulBase == EPI0_BASE);
  65. ASSERT((ulMode == EPI_MODE_GENERAL) ||
  66. (ulMode == EPI_MODE_SDRAM) ||
  67. (ulMode == EPI_MODE_HB8) ||
  68. (ulMode == EPI_MODE_DISABLE));
  69. //
  70. // Write the mode word to the register.
  71. //
  72. HWREG(ulBase + EPI_O_CFG) = ulMode;
  73. }
  74. //*****************************************************************************
  75. //
  76. //! Sets the clock divider for the EPI module.
  77. //!
  78. //! \param ulBase is the EPI module base address.
  79. //! \param ulDivider is the value of the clock divider to be applied to
  80. //! the external interface (0-65535).
  81. //!
  82. //! This functions sets the clock divider(s) that will be used to determine the
  83. //! clock rate of the external interface. The \e ulDivider value is used to
  84. //! derive the EPI clock rate from the system clock based upon the following
  85. //! formula.
  86. //!
  87. //! EPIClock = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2))
  88. //!
  89. //! For example, a divider value of 1 results in an EPI clock rate of half
  90. //! the system clock, value of 2 or 3 yield one quarter of the system clock and
  91. //! a value of 4 results in one sixth of the system clock rate.
  92. //!
  93. //! In cases where a dual chip select mode is in use and different clock rates
  94. //! are required for each chip select, the \e ulDivider parameter must contain
  95. //! two dividers. The lower 16 bits define the divider to be used with CS0n
  96. //! and the upper 16 bits define the divider for CS1n.
  97. //!
  98. //! \return None.
  99. //
  100. //*****************************************************************************
  101. void
  102. EPIDividerSet(unsigned long ulBase, unsigned long ulDivider)
  103. {
  104. //
  105. // Check the arguments.
  106. //
  107. ASSERT(ulBase == EPI0_BASE);
  108. //
  109. // Write the divider value to the register.
  110. //
  111. HWREG(ulBase + EPI_O_BAUD) = ulDivider;
  112. }
  113. //*****************************************************************************
  114. //
  115. //! Configures the SDRAM mode of operation.
  116. //!
  117. //! \param ulBase is the EPI module base address.
  118. //! \param ulConfig is the SDRAM interface configuration.
  119. //! \param ulRefresh is the refresh count in core clocks (0-2047).
  120. //!
  121. //! This function is used to configure the SDRAM interface, when the SDRAM
  122. //! mode is chosen with the function EPIModeSet(). The parameter \e ulConfig
  123. //! is the logical OR of several sets of choices:
  124. //!
  125. //! The processor core frequency must be specified with one of the following:
  126. //!
  127. //! - \b EPI_SDRAM_CORE_FREQ_0_15 - core clock is 0 MHz < clk <= 15 MHz
  128. //! - \b EPI_SDRAM_CORE_FREQ_15_30 - core clock is 15 MHz < clk <= 30 MHz
  129. //! - \b EPI_SDRAM_CORE_FREQ_30_50 - core clock is 30 MHz < clk <= 50 MHz
  130. //! - \b EPI_SDRAM_CORE_FREQ_50_100 - core clock is 50 MHz < clk <= 100 MHz
  131. //!
  132. //! The low power mode is specified with one of the following:
  133. //!
  134. //! - \b EPI_SDRAM_LOW_POWER - enter low power, self-refresh state
  135. //! - \b EPI_SDRAM_FULL_POWER - normal operating state
  136. //!
  137. //! The SDRAM device size is specified with one of the following:
  138. //!
  139. //! - \b EPI_SDRAM_SIZE_64MBIT - 64 Mbit device (8 MB)
  140. //! - \b EPI_SDRAM_SIZE_128MBIT - 128 Mbit device (16 MB)
  141. //! - \b EPI_SDRAM_SIZE_256MBIT - 256 Mbit device (32 MB)
  142. //! - \b EPI_SDRAM_SIZE_512MBIT - 512 Mbit device (64 MB)
  143. //!
  144. //! The parameter \e ulRefresh sets the refresh counter in units of core
  145. //! clock ticks. It is an 11-bit value with a range of 0 - 2047 counts.
  146. //!
  147. //! \return None.
  148. //
  149. //*****************************************************************************
  150. void
  151. EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig,
  152. unsigned long ulRefresh)
  153. {
  154. //
  155. // Check the arguments.
  156. //
  157. ASSERT(ulBase == EPI0_BASE);
  158. ASSERT(ulRefresh < 2048);
  159. //
  160. // Fill in the refresh count field of the configuration word.
  161. //
  162. ulConfig &= ~EPI_SDRAMCFG_RFSH_M;
  163. ulConfig |= ulRefresh << EPI_SDRAMCFG_RFSH_S;
  164. //
  165. // Write the SDRAM configuration register.
  166. //
  167. HWREG(ulBase + EPI_O_SDRAMCFG) = ulConfig;
  168. }
  169. //*****************************************************************************
  170. //
  171. //! Configures the interface for Host-bus 8 operation.
  172. //!
  173. //! \param ulBase is the EPI module base address.
  174. //! \param ulConfig is the interface configuration.
  175. //! \param ulMaxWait is the maximum number of external clocks to wait
  176. //! if a FIFO ready signal is holding off the transaction.
  177. //!
  178. //! This function is used to configure the interface when used in Host-bus 8
  179. //! operation as chosen with the function EPIModeSet(). The parameter
  180. //! \e ulConfig is the logical OR of any of the following:
  181. //!
  182. //! - one of \b EPI_HB8_MODE_ADMUX, \b EPI_HB8_MODE_ADDEMUX,
  183. //! \b EPI_HB8_MODE_SRAM, or \b EPI_HB8_MODE_FIFO to select the HB8 mode
  184. //! - \b EPI_HB8_USE_TXEMPTY - enable TXEMPTY signal with FIFO
  185. //! - \b EPI_HB8_USE_RXFULL - enable RXFULL signal with FIFO
  186. //! - \b EPI_HB8_WRHIGH - use active high write strobe, otherwise it is
  187. //! active low
  188. //! - \b EPI_HB8_RDHIGH - use active high read strobe, otherwise it is
  189. //! active low
  190. //! - one of \b EPI_HB8_WRWAIT_0, \b EPI_HB8_WRWAIT_1, \b EPI_HB8_WRWAIT_2,
  191. //! or \b EPI_HB8_WRWAIT_3 to select the number of write wait states (default
  192. //! is 0 wait states)
  193. //! - one of \b EPI_HB8_RDWAIT_0, \b EPI_HB8_RDWAIT_1, \b EPI_HB8_RDWAIT_2,
  194. //! or \b EPI_HB8_RDWAIT_3 to select the number of read wait states (default
  195. //! is 0 wait states)
  196. //! - \b EPI_HB8_WORD_ACCESS - use Word Access mode to route bytes to the
  197. //! correct byte lanes allowing data to be stored in bits [31:8]. If absent,
  198. //! all data transfers use bits [7:0].
  199. //! - \b EPI_HB8_CSBAUD_DUAL - use different baud rates when accessing devices
  200. //! on each CSn. CS0n uses the baud rate specified by the lower 16 bits of the
  201. //! divider passed to EPIDividerSet() and CS1n uses the divider passed in the
  202. //! upper 16 bits. If this option is absent, both chip selects use the baud
  203. //! rate resulting from the divider in the lower 16 bits of the parameter passed
  204. //! to EPIDividerSet().
  205. //! - one of \b EPI_HB8_CSCFG_CS, \b EPI_HB8_CSCFG_ALE,
  206. //! \b EPI_HB8_CSCFG_DUAL_CS or \b EPI_HB8_CSCFG_ALE_DUAL. \b EPI_HB8_CSCFG_CS
  207. //! sets EPI30 to operate as a Chip Select (CSn) signal. When using this mode,
  208. //! \b EPI_HB8_MODE_ADMUX must not be specified. \b EPI_HB8_CSCFG_ALE sets
  209. //! EPI30 to operate as an address latch (ALE). \b EPI_HB8_CSCFG_DUAL_CS sets
  210. //! EPI30 to operate as CS0n and EPI27 as CS1n with the asserted chip select
  211. //! determined from the most significant address bit for the respective external
  212. //! address map. \b EPI_HB8_CSCFG_DUAL_ALE sets EPI30 as an address latch (ALE),
  213. //! EPI27 as CS0n and EPI26 as CS1n with the asserted chip select determined
  214. //! from the most significant address bit for the respective external address
  215. //! map.
  216. //!
  217. //! The parameter \e ulMaxWait is used if the FIFO mode is chosen. If a
  218. //! FIFO is used along with RXFULL or TXEMPTY ready signals, then this
  219. //! parameter determines the maximum number of clocks to wait when the
  220. //! transaction is being held off by by the FIFO using one of these ready
  221. //! signals. A value of 0 means to wait forever.
  222. //!
  223. //! \return None.
  224. //
  225. //*****************************************************************************
  226. void
  227. EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
  228. unsigned long ulMaxWait)
  229. {
  230. //
  231. // Check the arguments.
  232. //
  233. ASSERT(ulBase == EPI0_BASE);
  234. ASSERT(ulMaxWait < 256);
  235. //
  236. // Determine the CS and word access modes.
  237. //
  238. HWREG(ulBase + EPI_O_HB8CFG2) = (((ulConfig & EPI_HB8_WORD_ACCESS) ?
  239. EPI_HB8CFG2_WORD : 0) |
  240. ((ulConfig & EPI_HB8_CSBAUD_DUAL) ? EPI_HB8CFG2_CSBAUD : 0) | ((ulConfig & EPI_HB8_CSCFG_MASK) << 15));
  241. //
  242. // Fill in the max wait field of the configuration word.
  243. //
  244. ulConfig &= ~EPI_HB8CFG_MAXWAIT_M;
  245. ulConfig |= ulMaxWait << EPI_HB8CFG_MAXWAIT_S;
  246. //
  247. // Write the main HostBus8 configuration register.
  248. //
  249. HWREG(ulBase + EPI_O_HB8CFG) = ulConfig;
  250. }
  251. //*****************************************************************************
  252. //
  253. //! Configures the interface for general-purpose mode operation.
  254. //!
  255. //! \param ulBase is the EPI module base address.
  256. //! \param ulConfig is the interface configuration.
  257. //! \param ulFrameCount is the frame size in clocks, if the frame signal
  258. //! is used (0-15).
  259. //! \param ulMaxWait is the maximum number of external clocks to wait
  260. //! when the external clock enable is holding off the transaction (0-255).
  261. //!
  262. //! This function is used to configure the interface when used in
  263. //! general-purpose operation as chosen with the function EPIModeSet(). The
  264. //! parameter
  265. //! \e ulConfig is the logical OR of any of the following:
  266. //!
  267. //! - \b EPI_GPMODE_CLKPIN - interface clock is output on a pin
  268. //! - \b EPI_GPMODE_CLKGATE - clock is stopped when there is no transaction,
  269. //! otherwise it is free-running
  270. //! - \b EPI_GPMODE_RDYEN - the external peripheral drives an iRDY signal into
  271. //! pin EPI0S27. If absent, the peripheral is assumed to be ready at all times.
  272. //! This flag may only be used with a free-running clock (\b EPI_GPMODE_CLKGATE
  273. //! is absent).
  274. //! - \b EPI_GPMODE_FRAMEPIN - framing signal is emitted on a pin
  275. //! - \b EPI_GPMODE_FRAME50 - framing signal is 50/50 duty cycle, otherwise it
  276. //! is a pulse
  277. //! - \b EPI_GPMODE_READWRITE - read and write strobes are emitted on pins
  278. //! - \b EPI_GPMODE_WRITE2CYCLE - a two cycle write is used, otherwise a
  279. //! single-cycle write is used
  280. //! - \b EPI_GPMODE_READ2CYCLE - a two cycle read is used, otherwise a
  281. //! single-cycle read is used
  282. //! - \b EPI_GPMODE_ASIZE_NONE, \b EPI_GPMODE_ASIZE_4,
  283. //! \b EPI_GPMODE_ASIZE_12, or \b EPI_GPMODE_ASIZE_20 to choose no address
  284. //! bus, or and address bus size of 4, 12, or 20 bits
  285. //! - \b EPI_GPMODE_DSIZE_8, \b EPI_GPMODE_DSIZE_16,
  286. //! \b EPI_GPMODE_DSIZE_24, or \b EPI_GPMODE_DSIZE_32 to select a data bus
  287. //! size of 8, 16, 24, or 32 bits
  288. //! - \b EPI_GPMODE_WORD_ACCESS - use Word Access mode to route bytes to the
  289. //! correct byte lanes allowing data to be stored in the upper bits of the word
  290. //! when necessary.
  291. //!
  292. //! The parameter \e ulFrameCount is the number of clocks used to form the
  293. //! framing signal, if the framing signal is used. The behavior depends on
  294. //! whether the frame signal is a pulse or a 50/50 duty cycle. This value
  295. //! is not used if the framing signal is not enabled with the option
  296. //! \b EPI_GPMODE_FRAMEPIN.
  297. //!
  298. //! The parameter \e ulMaxWait is used if the external clock enable is turned
  299. //! on with the \b EPI_GPMODE_CLKENA option is used. In the case that
  300. //! external clock enable is used, this parameter determines the maximum
  301. //! number of clocks to wait when the external clock enable signal is holding
  302. //! off a transaction. A value of 0 means to wait forever. If a non-zero
  303. //! value is used and exceeded, an interrupt will occur and the transaction
  304. //! aborted.
  305. //!
  306. //! \return None.
  307. //
  308. //*****************************************************************************
  309. void
  310. EPIConfigGPModeSet(unsigned long ulBase, unsigned long ulConfig,
  311. unsigned long ulFrameCount, unsigned long ulMaxWait)
  312. {
  313. //
  314. // Check the arguments.
  315. //
  316. ASSERT(ulBase == EPI0_BASE);
  317. ASSERT(ulFrameCount < 16);
  318. ASSERT(ulMaxWait < 256);
  319. //
  320. // Set the word access mode.
  321. //
  322. HWREG(ulBase + EPI_O_GPCFG2) = ((ulConfig & EPI_GPMODE_WORD_ACCESS) ?
  323. EPI_GPCFG2_WORD : 0);
  324. //
  325. // Fill in the frame count field of the configuration word.
  326. //
  327. ulConfig &= ~EPI_GPCFG_FRMCNT_M;
  328. ulConfig |= ulFrameCount << EPI_GPCFG_FRMCNT_S;
  329. //
  330. // Fill in the max wait field of the configuration word.
  331. //
  332. ulConfig &= ~EPI_GPCFG_MAXWAIT_M;
  333. ulConfig |= ulMaxWait << EPI_GPCFG_MAXWAIT_S;
  334. //
  335. // Write the non-moded configuration register.
  336. //
  337. HWREG(ulBase + EPI_O_GPCFG) = ulConfig;
  338. }
  339. //*****************************************************************************
  340. //
  341. //! Configures the address map for the external interface.
  342. //!
  343. //! \param ulBase is the EPI module base address.
  344. //! \param ulMap is the address mapping configuration.
  345. //!
  346. //! This function is used to configure the address mapping for the external
  347. //! interface. This determines the base address of the external memory or
  348. //! device within the processor peripheral and/or memory space.
  349. //!
  350. //! The parameter \e ulMap is the logical OR of the following:
  351. //!
  352. //! - \b EPI_ADDR_PER_SIZE_256B, \b EPI_ADDR_PER_SIZE_64KB,
  353. //! \b EPI_ADDR_PER_SIZE_16MB, or \b EPI_ADDR_PER_SIZE_512MB to choose a
  354. //! peripheral address space of 256 bytes, 64 Kbytes, 16 Mbytes or 512 Mbytes
  355. //! - \b EPI_ADDR_PER_BASE_NONE, \b EPI_ADDR_PER_BASE_A, or
  356. //! \b EPI_ADDR_PER_BASE_C to choose the base address of the peripheral
  357. //! space as none, 0xA0000000, or 0xC0000000
  358. //! - \b EPI_ADDR_RAM_SIZE_256B, \b EPI_ADDR_RAM_SIZE_64KB,
  359. //! \b EPI_ADDR_RAM_SIZE_16MB, or \b EPI_ADDR_RAM_SIZE_512MB to choose a
  360. //! RAM address space of 256 bytes, 64 Kbytes, 16 Mbytes or 512 Mbytes
  361. //! - \b EPI_ADDR_RAM_BASE_NONE, \b EPI_ADDR_RAM_BASE_6, or
  362. //! \b EPI_ADDR_RAM_BASE_8 to choose the base address of the RAM space
  363. //! as none, 0x60000000, or 0x80000000
  364. //!
  365. //! \return None.
  366. //
  367. //*****************************************************************************
  368. void
  369. EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap)
  370. {
  371. //
  372. // Check the arguments.
  373. //
  374. ASSERT(ulBase == EPI0_BASE);
  375. ASSERT(ulMap < 0x100);
  376. //
  377. // Set the value of the address mapping register.
  378. //
  379. HWREG(ulBase + EPI_O_ADDRMAP) = ulMap;
  380. }
  381. //*****************************************************************************
  382. //
  383. //! Configures a non-blocking read transaction.
  384. //!
  385. //! \param ulBase is the EPI module base address.
  386. //! \param ulChannel is the read channel (0 or 1).
  387. //! \param ulDataSize is the size of the data items to read.
  388. //! \param ulAddress is the starting address to read.
  389. //!
  390. //! This function is used to configure a non-blocking read channel for a
  391. //! transaction. Two channels are available which can be used in a ping-pong
  392. //! method for continuous reading. It is not necessary to use both channels
  393. //! to perform a non-blocking read.
  394. //!
  395. //! The parameter \e ulDataSize is one of \b EPI_NBCONFIG_SIZE_8,
  396. //! \b EPI_NBCONFIG_SIZE_16, or \b EPI_NBCONFIG_SIZE_32 for 8-bit, 16-bit,
  397. //! or 32-bit sized data transfers.
  398. //!
  399. //! The parameter \e ulAddress is the starting address for the read, relative
  400. //! to the external device. The start of the device is address 0.
  401. //!
  402. //! Once configured, the non-blocking read is started by calling
  403. //! EPINonBlockingReadStart(). If the addresses to be read from the device
  404. //! are in a sequence, it is not necessary to call this function multiple
  405. //! times. Until it is changed, the EPI module will remember the last address
  406. //! that was used for a non-blocking read (per channel).
  407. //!
  408. //! \return None.
  409. //
  410. //*****************************************************************************
  411. void
  412. EPINonBlockingReadConfigure(unsigned long ulBase, unsigned long ulChannel,
  413. unsigned long ulDataSize, unsigned long ulAddress)
  414. {
  415. unsigned long ulOffset;
  416. //
  417. // Check the arguments.
  418. //
  419. ASSERT(ulBase == EPI0_BASE);
  420. ASSERT(ulChannel < 2);
  421. ASSERT(ulDataSize < 4);
  422. ASSERT(ulAddress < 0x20000000);
  423. //
  424. // Compute the offset needed to select the correct channel regs.
  425. //
  426. ulOffset = ulChannel * (EPI_O_RSIZE1 - EPI_O_RSIZE0);
  427. //
  428. // Write the data size register for the channel.
  429. //
  430. HWREG(ulBase + EPI_O_RSIZE0 + ulOffset) = ulDataSize;
  431. //
  432. // Write the starting address register for the channel.
  433. //
  434. HWREG(ulBase + EPI_O_RADDR0 + ulOffset) = ulAddress;
  435. }
  436. //*****************************************************************************
  437. //
  438. //! Starts a non-blocking read transaction.
  439. //!
  440. //! \param ulBase is the EPI module base address.
  441. //! \param ulChannel is the read channel (0 or 1).
  442. //! \param ulCount is the number of items to read (1-4095).
  443. //!
  444. //! This function starts a non-blocking read that was previously configured
  445. //! with the function EPINonBlockingReadConfigure(). Once this function is
  446. //! called, the EPI module will begin reading data from the external device
  447. //! into the read FIFO. The EPI will stop reading when the FIFO fills up
  448. //! and resume reading when the application drains the FIFO, until the
  449. //! total specified count of data items has been read.
  450. //!
  451. //! Once a read transaction is completed and the FIFO drained, another
  452. //! transaction can be started from the next address by calling this
  453. //! function again.
  454. //!
  455. //! \return None.
  456. //
  457. //*****************************************************************************
  458. void
  459. EPINonBlockingReadStart(unsigned long ulBase, unsigned long ulChannel,
  460. unsigned long ulCount)
  461. {
  462. unsigned long ulOffset;
  463. //
  464. // Check the arguments.
  465. //
  466. ASSERT(ulBase == EPI0_BASE);
  467. ASSERT(ulChannel < 2);
  468. ASSERT(ulCount < 4096);
  469. //
  470. // Compute the offset needed to select the correct channel regs.
  471. //
  472. ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);
  473. //
  474. // Write to the read count register.
  475. //
  476. HWREG(ulBase + EPI_O_RPSTD0 + ulOffset) = ulCount;
  477. }
  478. //*****************************************************************************
  479. //
  480. //! Stops a non-blocking read transaction.
  481. //!
  482. //! \param ulBase is the EPI module base address.
  483. //! \param ulChannel is the read channel (0 or 1).
  484. //!
  485. //! This function cancels a non-blocking read transaction that is already
  486. //! in progress.
  487. //!
  488. //! \return None.
  489. //
  490. //*****************************************************************************
  491. void
  492. EPINonBlockingReadStop(unsigned long ulBase, unsigned long ulChannel)
  493. {
  494. unsigned long ulOffset;
  495. //
  496. // Check the arguments.
  497. //
  498. ASSERT(ulBase == EPI0_BASE);
  499. ASSERT(ulChannel < 2);
  500. //
  501. // Compute the offset needed to select the correct channel regs.
  502. //
  503. ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);
  504. //
  505. // Write a 0 to the read count register, which will cancel the transaction.
  506. //
  507. HWREG(ulBase + EPI_O_RPSTD0 + ulOffset) = 0;
  508. }
  509. //*****************************************************************************
  510. //
  511. //! Get the count remaining for a non-blocking transaction.
  512. //!
  513. //! \param ulBase is the EPI module base address.
  514. //! \param ulChannel is the read channel (0 or 1).
  515. //!
  516. //! This function gets the remaining count of items for a non-blocking read
  517. //! transaction.
  518. //!
  519. //! \return The number of items remaining in the non-blocking read transaction.
  520. //
  521. //*****************************************************************************
  522. unsigned long
  523. EPINonBlockingReadCount(unsigned long ulBase, unsigned long ulChannel)
  524. {
  525. unsigned long ulOffset;
  526. //
  527. // Check the arguments.
  528. //
  529. ASSERT(ulBase == EPI0_BASE);
  530. ASSERT(ulChannel < 2);
  531. //
  532. // Compute the offset needed to select the correct channel regs.
  533. //
  534. ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);
  535. //
  536. // Read the count remaining and return the value to the caller.
  537. //
  538. return(HWREG(ulBase + EPI_O_RPSTD0 + ulOffset));
  539. }
  540. //*****************************************************************************
  541. //
  542. //! Get the count of items available in the read FIFO.
  543. //!
  544. //! \param ulBase is the EPI module base address.
  545. //!
  546. //! This function gets the number of items that are available to read in
  547. //! the read FIFO. The read FIFO is filled by a non-blocking read transaction
  548. //! which is configured by the functions EPINonBlockingReadConfigure() and
  549. //! EPINonBlockingReadStart().
  550. //!
  551. //! \return The number of items available to read in the read FIFO.
  552. //
  553. //*****************************************************************************
  554. unsigned long
  555. EPINonBlockingReadAvail(unsigned long ulBase)
  556. {
  557. //
  558. // Check the arguments.
  559. //
  560. ASSERT(ulBase == EPI0_BASE);
  561. //
  562. // Read the FIFO count and return it to the caller.
  563. //
  564. return(HWREG(ulBase + EPI_O_RFIFOCNT));
  565. }
  566. //*****************************************************************************
  567. //
  568. //! Read available data from the read FIFO, as 32-bit data items.
  569. //!
  570. //! \param ulBase is the EPI module base address.
  571. //! \param ulCount is the maximum count of items to read.
  572. //! \param pulBuf is the caller supplied buffer where the read data should
  573. //! be stored.
  574. //!
  575. //! This function reads 32-bit data items from the read FIFO and stores
  576. //! the values in a caller supplied buffer. The function will read and store
  577. //! data from the FIFO until there is no more data in the FIFO or the maximum
  578. //! count is reached as specified in the parameter \e ulCount. The actual
  579. //! count of items will be returned.
  580. //!
  581. //! \return The number of items read from the FIFO.
  582. //
  583. //*****************************************************************************
  584. unsigned long
  585. EPINonBlockingReadGet32(unsigned long ulBase, unsigned long ulCount,
  586. unsigned long *pulBuf)
  587. {
  588. unsigned long ulCountRead = 0;
  589. //
  590. // Check the arguments.
  591. //
  592. ASSERT(ulBase == EPI0_BASE);
  593. ASSERT(ulCount < 4096);
  594. ASSERT(pulBuf);
  595. //
  596. // Read from the FIFO while there are any items to read, and
  597. // the callers specified count is not exceeded.
  598. //
  599. while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
  600. {
  601. //
  602. // Read from the FIFO and store in the caller supplied buffer.
  603. //
  604. *pulBuf = HWREG(ulBase + EPI_O_READFIFO);
  605. //
  606. // Update the caller's buffer pointer and the count of items read.
  607. //
  608. pulBuf++;
  609. ulCountRead++;
  610. }
  611. //
  612. // Return the count of items read to the caller.
  613. //
  614. return(ulCountRead);
  615. }
  616. //*****************************************************************************
  617. //
  618. //! Read available data from the read FIFO, as 16-bit data items.
  619. //!
  620. //! \param ulBase is the EPI module base address.
  621. //! \param ulCount is the maximum count of items to read.
  622. //! \param pusBuf is the caller supplied buffer where the read data should
  623. //! be stored.
  624. //!
  625. //! This function reads 16-bit data items from the read FIFO and stores
  626. //! the values in a caller supplied buffer. The function will read and store
  627. //! data from the FIFO until there is no more data in the FIFO or the maximum
  628. //! count is reached as specified in the parameter \e ulCount. The actual
  629. //! count of items will be returned.
  630. //!
  631. //! \return The number of items read from the FIFO.
  632. //
  633. //*****************************************************************************
  634. unsigned long
  635. EPINonBlockingReadGet16(unsigned long ulBase, unsigned long ulCount,
  636. unsigned short *pusBuf)
  637. {
  638. unsigned long ulCountRead = 0;
  639. //
  640. // Check the arguments.
  641. //
  642. ASSERT(ulBase == EPI0_BASE);
  643. ASSERT(ulCount < 4096);
  644. ASSERT(pusBuf);
  645. //
  646. // Read from the FIFO while there are any items to read, and
  647. // the callers specified count is not exceeded.
  648. //
  649. while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
  650. {
  651. //
  652. // Read from the FIFO and store in the caller supplied buffer.
  653. //
  654. *pusBuf = (unsigned short)HWREG(ulBase + EPI_O_READFIFO);
  655. //
  656. // Update the caller's buffer pointer and the count of items read.
  657. //
  658. pusBuf++;
  659. ulCountRead++;
  660. }
  661. //
  662. // Return the count of items read to the caller.
  663. //
  664. return(ulCountRead);
  665. }
  666. //*****************************************************************************
  667. //
  668. //! Read available data from the read FIFO, as 8-bit data items.
  669. //!
  670. //! \param ulBase is the EPI module base address.
  671. //! \param ulCount is the maximum count of items to read.
  672. //! \param pucBuf is the caller supplied buffer where the read data should
  673. //! be stored.
  674. //!
  675. //! This function reads 8-bit data items from the read FIFO and stores
  676. //! the values in a caller supplied buffer. The function will read and store
  677. //! data from the FIFO until there is no more data in the FIFO or the maximum
  678. //! count is reached as specified in the parameter \e ulCount. The actual
  679. //! count of items will be returned.
  680. //!
  681. //! \return The number of items read from the FIFO.
  682. //
  683. //*****************************************************************************
  684. unsigned long
  685. EPINonBlockingReadGet8(unsigned long ulBase, unsigned long ulCount,
  686. unsigned char *pucBuf)
  687. {
  688. unsigned long ulCountRead = 0;
  689. //
  690. // Check the arguments.
  691. //
  692. ASSERT(ulBase == EPI0_BASE);
  693. ASSERT(ulCount < 4096);
  694. ASSERT(pucBuf);
  695. //
  696. // Read from the FIFO while there are any items to read, and
  697. // the callers specified count is not exceeded.
  698. //
  699. while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
  700. {
  701. //
  702. // Read from the FIFO and store in the caller supplied buffer.
  703. //
  704. *pucBuf = (unsigned char)HWREG(ulBase + EPI_O_READFIFO);
  705. //
  706. // Update the caller's buffer pointer and the count of items read.
  707. //
  708. pucBuf++;
  709. ulCountRead++;
  710. }
  711. //
  712. // Return the count of items read to the caller.
  713. //
  714. return(ulCountRead);
  715. }
  716. //*****************************************************************************
  717. //
  718. //! Configures the read FIFO.
  719. //!
  720. //! \param ulBase is the EPI module base address.
  721. //! \param ulConfig is the FIFO configuration.
  722. //!
  723. //! This function configures the FIFO trigger levels and error
  724. //! generation. The parameter \e ulConfig is the logical OR of the
  725. //! following:
  726. //!
  727. //! - \b EPI_FIFO_CONFIG_WTFULLERR - enables an error interrupt when a write is
  728. //! attempted and the write FIFO is full
  729. //! - \b EPI_FIFO_CONFIG_RSTALLERR - enables an error interrupt when a read is
  730. //! stalled due to an interleaved write or other reason
  731. //! - \b EPI_FIFO_CONFIG_TX_EMPTY, \b EPI_FIFO_CONFIG_TX_1_4,
  732. //! \b EPI_FIFO_CONFIG_TX_1_2, or \b EPI_FIFO_CONFIG_TX_3_4 to set the
  733. //! TX FIFO trigger level to empty, 1/4, 1/2, or 3/4 level
  734. //! - \b EPI_FIFO_CONFIG_RX_1_8, \b EPI_FIFO_CONFIG_RX_1_4,
  735. //! \b EPI_FIFO_CONFIG_RX_1_2, \b EPI_FIFO_CONFIG_RX_3_4,
  736. //! \b EPI_FIFO_CONFIG_RX_7_8, or \b EPI_FIFO_CONFIG_RX_FULL to set the
  737. //! RX FIFO trigger level to 1/8, 1/4, 1/2, 3/4, 7/8 or full level
  738. //!
  739. //! \return None.
  740. //
  741. //*****************************************************************************
  742. void
  743. EPIFIFOConfig(unsigned long ulBase, unsigned long ulConfig)
  744. {
  745. //
  746. // Check the arguments.
  747. //
  748. ASSERT(ulBase == EPI0_BASE);
  749. ASSERT(ulConfig == (ulConfig & 0x00030077));
  750. //
  751. // Load the configuration into the FIFO config reg.
  752. //
  753. HWREG(ulBase + EPI_O_FIFOLVL) = ulConfig;
  754. }
  755. //*****************************************************************************
  756. //
  757. //! Reads the number of empty slots in the write transaction FIFO.
  758. //!
  759. //! \param ulBase is the EPI module base address.
  760. //!
  761. //! This function returns the number of slots available in the transaction
  762. //! FIFO. It can be used in a polling method to avoid attempting a write
  763. //! that would stall.
  764. //!
  765. //! \return The number of empty slots in the transaction FIFO.
  766. //
  767. //*****************************************************************************
  768. unsigned long
  769. EPIWriteFIFOCountGet(unsigned long ulBase)
  770. {
  771. //
  772. // Check the arguments.
  773. //
  774. ASSERT(ulBase == EPI0_BASE);
  775. //
  776. // Read the FIFO count and return it to the caller.
  777. //
  778. return(HWREG(ulBase + EPI_O_WFIFOCNT));
  779. }
  780. //*****************************************************************************
  781. //
  782. //! Enables EPI interrupt sources.
  783. //!
  784. //! \param ulBase is the EPI module base address.
  785. //! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
  786. //!
  787. //! This function enables the specified EPI sources to generate interrupts.
  788. //! The \e ulIntFlags parameter can be the logical OR of any of the following
  789. //! values:
  790. //!
  791. //! - \b EPI_INT_TXREQ - transmit FIFO is below the trigger level
  792. //! - \b EPI_INT_RXREQ - read FIFO is above the trigger level
  793. //! - \b EPI_INT_ERR - an error condition occurred
  794. //!
  795. //! \return Returns None.
  796. //
  797. //*****************************************************************************
  798. void
  799. EPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
  800. {
  801. //
  802. // Check the arguments.
  803. //
  804. ASSERT(ulBase == EPI0_BASE);
  805. ASSERT(ulIntFlags < 16);
  806. //
  807. // Write the interrupt flags mask to the mask register.
  808. //
  809. HWREG(ulBase + EPI_O_IM) |= ulIntFlags;
  810. }
  811. //*****************************************************************************
  812. //
  813. //! Disables EPI interrupt sources.
  814. //!
  815. //! \param ulBase is the EPI module base address.
  816. //! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
  817. //!
  818. //! This function disables the specified EPI sources for interrupt
  819. //! generation. The \e ulIntFlags parameter can be the logical OR
  820. //! of any of the following values: \b EPI_INT_RXREQ, \b EPI_INT_TXREQ, or
  821. //! \b I2S_INT_ERR.
  822. //!
  823. //! \return Returns None.
  824. //
  825. //*****************************************************************************
  826. void
  827. EPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
  828. {
  829. //
  830. // Check the arguments.
  831. //
  832. ASSERT(ulBase == EPI0_BASE);
  833. ASSERT(ulIntFlags < 16);
  834. //
  835. // Write the interrupt flags mask to the mask register.
  836. //
  837. HWREG(ulBase + EPI_O_IM) &= ~ulIntFlags;
  838. }
  839. //*****************************************************************************
  840. //
  841. //! Gets the EPI interrupt status.
  842. //!
  843. //! \param ulBase is the EPI module base address.
  844. //! \param bMasked is set \b true to get the masked interrupt status, or
  845. //! \b false to get the raw interrupt status.
  846. //!
  847. //! This function returns the EPI interrupt status. It can return either
  848. //! the raw or masked interrupt status.
  849. //!
  850. //! \return Returns the masked or raw EPI interrupt status, as a bit field
  851. //! of any of the following values: \b EPI_INT_TXREQ, \b EPI_INT_RXREQ,
  852. //! or \b EPI_INT_ERR
  853. //
  854. //*****************************************************************************
  855. unsigned long
  856. EPIIntStatus(unsigned long ulBase, tBoolean bMasked)
  857. {
  858. //
  859. // Check the arguments.
  860. //
  861. ASSERT(ulBase == EPI0_BASE);
  862. //
  863. // Return either the interrupt status or the raw interrupt status as
  864. // requested.
  865. //
  866. if(bMasked)
  867. {
  868. return(HWREG(ulBase + EPI_O_MIS));
  869. }
  870. else
  871. {
  872. return(HWREG(ulBase + EPI_O_RIS));
  873. }
  874. }
  875. //*****************************************************************************
  876. //
  877. //! Gets the EPI error interrupt status.
  878. //!
  879. //! \param ulBase is the EPI module base address.
  880. //!
  881. //! This function returns the error status of the EPI. If the return value of
  882. //! the function EPIIntStatus() has the flag \b EPI_INT_ERR set, then this
  883. //! function can be used to determine the cause of the error.
  884. //!
  885. //! This function returns a bit mask of error flags, which can be the logical
  886. //! OR of any of the following:
  887. //!
  888. //! - \b EPI_INT_ERR_WTFULL - occurs when a write stalled when the transaction
  889. //! FIFO was full
  890. //! - \b EPI_INT_ERR_RSTALL - occurs when a read stalled
  891. //! - \b EPI_INT_ERR_TIMEOUT - occurs when the external clock enable held
  892. //! off a transaction longer than the configured maximum wait time
  893. //!
  894. //! \return Returns the interrupt error flags as the logical OR of any of
  895. //! the following: \b EPI_INT_ERR_WTFULL, \b EPI_INT_ERR_RSTALL, or
  896. //! \b EPI_INT_ERR_TIMEOUT.
  897. //
  898. //*****************************************************************************
  899. unsigned long
  900. EPIIntErrorStatus(unsigned long ulBase)
  901. {
  902. //
  903. // Check the arguments.
  904. //
  905. ASSERT(ulBase == EPI0_BASE);
  906. //
  907. // Read the error status and return to caller.
  908. //
  909. return(HWREG(ulBase + EPI_O_EISC));
  910. }
  911. //*****************************************************************************
  912. //
  913. //! Clears pending EPI error sources.
  914. //!
  915. //! \param ulBase is the EPI module base address.
  916. //! \param ulErrFlags is a bit mask of the error sources to be cleared.
  917. //!
  918. //! This function clears the specified pending EPI errors. The \e ulErrFlags
  919. //! parameter can be the logical OR of any of the following values:
  920. //! \b EPI_INT_ERR_WTFULL, \b EPI_INT_ERR_RSTALL, or \b EPI_INT_ERR_TIMEOUT.
  921. //!
  922. //! \return Returns None.
  923. //
  924. //*****************************************************************************
  925. void
  926. EPIIntErrorClear(unsigned long ulBase, unsigned long ulErrFlags)
  927. {
  928. //
  929. // Check the arguments.
  930. //
  931. ASSERT(ulBase == EPI0_BASE);
  932. ASSERT(ulErrFlags < 16);
  933. //
  934. // Write the error flags to the register to clear the pending errors.
  935. //
  936. HWREG(ulBase + EPI_O_EISC) = ulErrFlags;
  937. }
  938. //*****************************************************************************
  939. //
  940. //! Registers an interrupt handler for the EPI module.
  941. //!
  942. //! \param ulBase is the EPI module base address.
  943. //! \param pfnHandler is a pointer to the function to be called when the
  944. //! interrupt is activated.
  945. //!
  946. //! This sets and enables the handler to be called when the EPI module
  947. //! generates an interrupt. Specific EPI interrupts must still be enabled
  948. //! with the EPIIntEnable() function.
  949. //!
  950. //! \sa IntRegister() for important information about registering interrupt
  951. //! handlers.
  952. //!
  953. //! \return None.
  954. //
  955. //*****************************************************************************
  956. void
  957. EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
  958. {
  959. //
  960. // Check the arguments.
  961. //
  962. ASSERT(ulBase == EPI0_BASE);
  963. ASSERT(pfnHandler);
  964. //
  965. // Register the interrupt handler.
  966. //
  967. IntRegister(INT_EPI0, pfnHandler);
  968. //
  969. // Enable the EPI interface interrupt.
  970. //
  971. IntEnable(INT_EPI0);
  972. }
  973. //*****************************************************************************
  974. //
  975. //! Unregisters an interrupt handler for the EPI module.
  976. //!
  977. //! \param ulBase is the EPI module base address.
  978. //!
  979. //! This function will disable and clear the handler to be called when the
  980. //! EPI interrupt occurs.
  981. //!
  982. //! \sa IntRegister() for important information about registering interrupt
  983. //! handlers.
  984. //!
  985. //! \return None.
  986. //
  987. //*****************************************************************************
  988. void
  989. EPIIntUnregister(unsigned long ulBase)
  990. {
  991. //
  992. // Check the arguments.
  993. //
  994. ASSERT(ulBase == EPI0_BASE);
  995. //
  996. // Disable the EPI interface interrupt.
  997. //
  998. IntDisable(INT_EPI0);
  999. //
  1000. // Unregister the interrupt handler.
  1001. //
  1002. IntUnregister(INT_EPI0);
  1003. }
  1004. //*****************************************************************************
  1005. //
  1006. // Close the Doxygen group.
  1007. //! @}
  1008. //
  1009. //*****************************************************************************