mpu.c 15 KB

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  1. //*****************************************************************************
  2. //
  3. // mpu.c - Driver for the Cortex-M3 memory protection unit (MPU).
  4. //
  5. // Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved.
  6. // Software License Agreement
  7. //
  8. // Texas Instruments (TI) is supplying this software for use solely and
  9. // exclusively on TI's microcontroller products. The software is owned by
  10. // TI and/or its suppliers, and is protected under applicable copyright
  11. // laws. You may not combine this software with "viral" open-source
  12. // software in order to form a larger program.
  13. //
  14. // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
  15. // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
  16. // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  17. // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
  18. // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
  19. // DAMAGES, FOR ANY REASON WHATSOEVER.
  20. //
  21. // This is part of revision 6459 of the Stellaris Peripheral Driver Library.
  22. //
  23. //*****************************************************************************
  24. //*****************************************************************************
  25. //
  26. //! \addtogroup mpu_api
  27. //! @{
  28. //
  29. //*****************************************************************************
  30. #include "inc/hw_ints.h"
  31. #include "inc/hw_nvic.h"
  32. #include "inc/hw_types.h"
  33. #include "driverlib/debug.h"
  34. #include "driverlib/interrupt.h"
  35. #include "driverlib/mpu.h"
  36. //*****************************************************************************
  37. //
  38. //! Enables and configures the MPU for use.
  39. //!
  40. //! \param ulMPUConfig is the logical OR of the possible configurations.
  41. //!
  42. //! This function enables the Cortex-M3 memory protection unit. It also
  43. //! configures the default behavior when in privileged mode and while
  44. //! handling a hard fault or NMI. Prior to enabling the MPU, at least one
  45. //! region must be set by calling MPURegionSet() or else by enabling the
  46. //! default region for privileged mode by passing the
  47. //! \b MPU_CONFIG_PRIV_DEFAULT flag to MPUEnable().
  48. //! Once the MPU is enabled, a memory management fault will be generated
  49. //! for any memory access violations.
  50. //!
  51. //! The \e ulMPUConfig parameter should be the logical OR of any of the
  52. //! following:
  53. //!
  54. //! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in
  55. //! privileged mode and when no other regions are defined. If this option
  56. //! is not enabled, then there must be at least one valid region already
  57. //! defined when the MPU is enabled.
  58. //! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI
  59. //! exception handler. If this option is not enabled, then the MPU is
  60. //! disabled while in one of these exception handlers and the default
  61. //! memory map is applied.
  62. //! - \b MPU_CONFIG_NONE chooses none of the above options. In this case,
  63. //! no default memory map is provided in privileged mode, and the MPU will
  64. //! not be enabled in the fault handlers.
  65. //!
  66. //! \return None.
  67. //
  68. //*****************************************************************************
  69. void
  70. MPUEnable(unsigned long ulMPUConfig)
  71. {
  72. //
  73. // Check the arguments.
  74. //
  75. ASSERT(!(ulMPUConfig & ~(MPU_CONFIG_PRIV_DEFAULT |
  76. MPU_CONFIG_HARDFLT_NMI)));
  77. //
  78. // Set the MPU control bits according to the flags passed by the user,
  79. // and also set the enable bit.
  80. //
  81. HWREG(NVIC_MPU_CTRL) = ulMPUConfig | NVIC_MPU_CTRL_ENABLE;
  82. }
  83. //*****************************************************************************
  84. //
  85. //! Disables the MPU for use.
  86. //!
  87. //! This function disables the Cortex-M3 memory protection unit. When the
  88. //! MPU is disabled, the default memory map is used and memory management
  89. //! faults are not generated.
  90. //!
  91. //! \return None.
  92. //
  93. //*****************************************************************************
  94. void
  95. MPUDisable(void)
  96. {
  97. //
  98. // Turn off the MPU enable bit.
  99. //
  100. HWREG(NVIC_MPU_CTRL) &= ~NVIC_MPU_CTRL_ENABLE;
  101. }
  102. //*****************************************************************************
  103. //
  104. //! Gets the count of regions supported by the MPU.
  105. //!
  106. //! This function is used to get the number of regions that are supported by
  107. //! the MPU. This is the total number that are supported, including regions
  108. //! that are already programmed.
  109. //!
  110. //! \return The number of memory protection regions that are available
  111. //! for programming using MPURegionSet().
  112. //
  113. //*****************************************************************************
  114. unsigned long
  115. MPURegionCountGet(void)
  116. {
  117. //
  118. // Read the DREGION field of the MPU type register, and mask off
  119. // the bits of interest to get the count of regions.
  120. //
  121. return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M)
  122. >> NVIC_MPU_TYPE_DREGION_S);
  123. }
  124. //*****************************************************************************
  125. //
  126. //! Enables a specific region.
  127. //!
  128. //! \param ulRegion is the region number to enable.
  129. //!
  130. //! This function is used to enable a memory protection region. The region
  131. //! should already be set up with the MPURegionSet() function. Once enabled,
  132. //! the memory protection rules of the region will be applied and access
  133. //! violations will cause a memory management fault.
  134. //!
  135. //! \return None.
  136. //
  137. //*****************************************************************************
  138. void
  139. MPURegionEnable(unsigned long ulRegion)
  140. {
  141. //
  142. // Check the arguments.
  143. //
  144. ASSERT(ulRegion < 8);
  145. //
  146. // Select the region to modify.
  147. //
  148. HWREG(NVIC_MPU_NUMBER) = ulRegion;
  149. //
  150. // Modify the enable bit in the region attributes.
  151. //
  152. HWREG(NVIC_MPU_ATTR) |= NVIC_MPU_ATTR_ENABLE;
  153. }
  154. //*****************************************************************************
  155. //
  156. //! Disables a specific region.
  157. //!
  158. //! \param ulRegion is the region number to disable.
  159. //!
  160. //! This function is used to disable a previously enabled memory protection
  161. //! region. The region will remain configured if it is not overwritten with
  162. //! another call to MPURegionSet(), and can be enabled again by calling
  163. //! MPURegionEnable().
  164. //!
  165. //! \return None.
  166. //
  167. //*****************************************************************************
  168. void
  169. MPURegionDisable(unsigned long ulRegion)
  170. {
  171. //
  172. // Check the arguments.
  173. //
  174. ASSERT(ulRegion < 8);
  175. //
  176. // Select the region to modify.
  177. //
  178. HWREG(NVIC_MPU_NUMBER) = ulRegion;
  179. //
  180. // Modify the enable bit in the region attributes.
  181. //
  182. HWREG(NVIC_MPU_ATTR) &= ~NVIC_MPU_ATTR_ENABLE;
  183. }
  184. //*****************************************************************************
  185. //
  186. //! Sets up the access rules for a specific region.
  187. //!
  188. //! \param ulRegion is the region number to set up.
  189. //! \param ulAddr is the base address of the region. It must be aligned
  190. //! according to the size of the region specified in ulFlags.
  191. //! \param ulFlags is a set of flags to define the attributes of the region.
  192. //!
  193. //! This function sets up the protection rules for a region. The region has
  194. //! a base address and a set of attributes including the size, which must
  195. //! be a power of 2. The base address parameter, \e ulAddr, must be aligned
  196. //! according to the size.
  197. //!
  198. //! The \e ulFlags parameter is the logical OR of all of the attributes
  199. //! of the region. It is a combination of choices for region size,
  200. //! execute permission, read/write permissions, disabled sub-regions,
  201. //! and a flag to determine if the region is enabled.
  202. //!
  203. //! The size flag determines the size of a region, and must be one of the
  204. //! following:
  205. //!
  206. //! - \b MPU_RGN_SIZE_32B
  207. //! - \b MPU_RGN_SIZE_64B
  208. //! - \b MPU_RGN_SIZE_128B
  209. //! - \b MPU_RGN_SIZE_256B
  210. //! - \b MPU_RGN_SIZE_512B
  211. //! - \b MPU_RGN_SIZE_1K
  212. //! - \b MPU_RGN_SIZE_2K
  213. //! - \b MPU_RGN_SIZE_4K
  214. //! - \b MPU_RGN_SIZE_8K
  215. //! - \b MPU_RGN_SIZE_16K
  216. //! - \b MPU_RGN_SIZE_32K
  217. //! - \b MPU_RGN_SIZE_64K
  218. //! - \b MPU_RGN_SIZE_128K
  219. //! - \b MPU_RGN_SIZE_256K
  220. //! - \b MPU_RGN_SIZE_512K
  221. //! - \b MPU_RGN_SIZE_1M
  222. //! - \b MPU_RGN_SIZE_2M
  223. //! - \b MPU_RGN_SIZE_4M
  224. //! - \b MPU_RGN_SIZE_8M
  225. //! - \b MPU_RGN_SIZE_16M
  226. //! - \b MPU_RGN_SIZE_32M
  227. //! - \b MPU_RGN_SIZE_64M
  228. //! - \b MPU_RGN_SIZE_128M
  229. //! - \b MPU_RGN_SIZE_256M
  230. //! - \b MPU_RGN_SIZE_512M
  231. //! - \b MPU_RGN_SIZE_1G
  232. //! - \b MPU_RGN_SIZE_2G
  233. //! - \b MPU_RGN_SIZE_4G
  234. //!
  235. //! The execute permission flag must be one of the following:
  236. //!
  237. //! - \b MPU_RGN_PERM_EXEC enables the region for execution of code
  238. //! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code
  239. //!
  240. //! The read/write access permissions are applied separately for the
  241. //! privileged and user modes. The read/write access flags must be one
  242. //! of the following:
  243. //!
  244. //! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode
  245. //! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access
  246. //! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only
  247. //! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write
  248. //! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access
  249. //! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only
  250. //!
  251. //! The region is automatically divided into 8 equally-sized sub-regions by
  252. //! the MPU. Sub-regions can only be used in regions of size 256 bytes
  253. //! or larger. Any of these 8 sub-regions can be disabled. This allows
  254. //! for creation of ``holes'' in a region which can be left open, or overlaid
  255. //! by another region with different attributes. Any of the 8 sub-regions
  256. //! can be disabled with a logical OR of any of the following flags:
  257. //!
  258. //! - \b MPU_SUB_RGN_DISABLE_0
  259. //! - \b MPU_SUB_RGN_DISABLE_1
  260. //! - \b MPU_SUB_RGN_DISABLE_2
  261. //! - \b MPU_SUB_RGN_DISABLE_3
  262. //! - \b MPU_SUB_RGN_DISABLE_4
  263. //! - \b MPU_SUB_RGN_DISABLE_5
  264. //! - \b MPU_SUB_RGN_DISABLE_6
  265. //! - \b MPU_SUB_RGN_DISABLE_7
  266. //!
  267. //! Finally, the region can be initially enabled or disabled with one of
  268. //! the following flags:
  269. //!
  270. //! - \b MPU_RGN_ENABLE
  271. //! - \b MPU_RGN_DISABLE
  272. //!
  273. //! As an example, to set a region with the following attributes: size of
  274. //! 32 KB, execution enabled, read-only for both privileged and user, one
  275. //! sub-region disabled, and initially enabled; the \e ulFlags parameter would
  276. //! have the following value:
  277. //!
  278. //! <code>
  279. //! (MPU_RG_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO |
  280. //! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE)
  281. //! </code>
  282. //!
  283. //! \note This function will write to multiple registers and is not protected
  284. //! from interrupts. It is possible that an interrupt which accesses a
  285. //! region may occur while that region is in the process of being changed.
  286. //! The safest way to handle this is to disable a region before changing it.
  287. //! Refer to the discussion of this in the API Detailed Description section.
  288. //!
  289. //! \return None.
  290. //
  291. //*****************************************************************************
  292. void
  293. MPURegionSet(unsigned long ulRegion, unsigned long ulAddr,
  294. unsigned long ulFlags)
  295. {
  296. //
  297. // Check the arguments.
  298. //
  299. ASSERT(ulRegion < 8);
  300. ASSERT((ulAddr & ~0 << (((ulFlags & NVIC_MPU_ATTR_SIZE_M) >> 1) + 1))
  301. == ulAddr);
  302. //
  303. // Program the base address, use the region field to select the
  304. // region at the same time.
  305. //
  306. HWREG(NVIC_MPU_BASE) = ulAddr | ulRegion | NVIC_MPU_BASE_VALID;
  307. //
  308. // Program the region attributes. Set the TEX field and the S, C,
  309. // and B bits to fixed values that are suitable for all Stellaris
  310. // memory.
  311. //
  312. HWREG(NVIC_MPU_ATTR) = (ulFlags & ~(NVIC_MPU_ATTR_TEX_M |
  313. NVIC_MPU_ATTR_CACHEABLE)) |
  314. NVIC_MPU_ATTR_SHAREABLE |
  315. NVIC_MPU_ATTR_BUFFRABLE;
  316. }
  317. //*****************************************************************************
  318. //
  319. //! Gets the current settings for a specific region.
  320. //!
  321. //! \param ulRegion is the region number to get.
  322. //! \param pulAddr points to storage for the base address of the region.
  323. //! \param pulFlags points to the attribute flags for the region.
  324. //!
  325. //! This function retrieves the configuration of a specific region. The
  326. //! meanings and format of the parameters is the same as that of the
  327. //! MPURegionSet() function.
  328. //!
  329. //! This function can be used to save the configuration of a region for
  330. //! later use with the MPURegionSet() function. The region's enable state
  331. //! will be preserved in the attributes that are saved.
  332. //!
  333. //! \return None.
  334. //
  335. //*****************************************************************************
  336. void
  337. MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr,
  338. unsigned long *pulFlags)
  339. {
  340. //
  341. // Check the arguments.
  342. //
  343. ASSERT(ulRegion < 8);
  344. ASSERT(pulAddr);
  345. ASSERT(pulFlags);
  346. //
  347. // Select the region to get.
  348. //
  349. HWREG(NVIC_MPU_NUMBER) = ulRegion;
  350. //
  351. // Read and store the base address for the region.
  352. //
  353. *pulAddr = HWREG(NVIC_MPU_BASE);
  354. //
  355. // Read and store the region attributes.
  356. //
  357. *pulFlags = HWREG(NVIC_MPU_ATTR);
  358. }
  359. //*****************************************************************************
  360. //
  361. //! Registers an interrupt handler for the memory management fault.
  362. //!
  363. //! \param pfnHandler is a pointer to the function to be called when the
  364. //! memory management fault occurs.
  365. //!
  366. //! This sets and enables the handler to be called when the MPU generates
  367. //! a memory management fault due to a protection region access violation.
  368. //!
  369. //! \sa IntRegister() for important information about registering interrupt
  370. //! handlers.
  371. //!
  372. //! \return None.
  373. //
  374. //*****************************************************************************
  375. void
  376. MPUIntRegister(void (*pfnHandler)(void))
  377. {
  378. //
  379. // Check the arguments.
  380. //
  381. ASSERT(pfnHandler);
  382. //
  383. // Register the interrupt handler.
  384. //
  385. IntRegister(FAULT_MPU, pfnHandler);
  386. //
  387. // Enable the memory management fault.
  388. //
  389. IntEnable(FAULT_MPU);
  390. }
  391. //*****************************************************************************
  392. //
  393. //! Unregisters an interrupt handler for the memory management fault.
  394. //!
  395. //! This function will disable and clear the handler to be called when a
  396. //! memory management fault occurs.
  397. //!
  398. //! \sa IntRegister() for important information about registering interrupt
  399. //! handlers.
  400. //!
  401. //! \return None.
  402. //
  403. //*****************************************************************************
  404. void
  405. MPUIntUnregister(void)
  406. {
  407. //
  408. // Disable the interrupt.
  409. //
  410. IntDisable(FAULT_MPU);
  411. //
  412. // Unregister the interrupt handler.
  413. //
  414. IntUnregister(FAULT_MPU);
  415. }
  416. //*****************************************************************************
  417. //
  418. // Close the Doxygen group.
  419. //! @}
  420. //
  421. //*****************************************************************************