board.c 5.1 KB

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  1. /*
  2. * Copyright (C) 2020, Huada Semiconductor Co., Ltd.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-10-30 CDT first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include "board.h"
  13. /**
  14. * @addtogroup HC32
  15. */
  16. /*@{*/
  17. /*******************************************************************************
  18. * Function Name : Peripheral_WE
  19. * Description : MCU Peripheral registers write unprotected.
  20. * Input : None
  21. * Output : None
  22. * Return : None
  23. *******************************************************************************/
  24. void Peripheral_WE(void)
  25. {
  26. /* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
  27. GPIO_Unlock();
  28. /* Unlock PWC register: FCG0 */
  29. PWC_FCG0_Unlock();
  30. /* Unlock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */
  31. PWC_Unlock(PWC_UNLOCK_CODE_0 | PWC_UNLOCK_CODE_1);
  32. /* Unlock SRAM register: WTCR */
  33. SRAM_WTCR_Unlock();
  34. /* Unlock SRAM register: CKCR */
  35. // SRAM_CKCR_Unlock();
  36. /* Unlock all EFM registers */
  37. EFM_Unlock();
  38. /* Unlock EFM register: FWMC */
  39. // EFM_FWMC_Unlock();
  40. /* Unlock EFM OTP write protect registers */
  41. // EFM_OTP_WP_Unlock();
  42. }
  43. /*******************************************************************************
  44. * Function Name : Peripheral_WP
  45. * Description : MCU Peripheral registers write protected.
  46. * Input : None
  47. * Output : None
  48. * Return : None
  49. *******************************************************************************/
  50. void Peripheral_WP(void)
  51. {
  52. /* Lock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
  53. GPIO_Lock();
  54. /* Lock PWC register: FCG0 */
  55. // PWC_FCG0_Lock();
  56. /* Lock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */
  57. PWC_Lock(PWC_UNLOCK_CODE_0 | PWC_UNLOCK_CODE_1);
  58. /* Lock SRAM register: WTCR */
  59. // SRAM_WTCR_Lock();
  60. /* Lock SRAM register: CKCR */
  61. // SRAM_CKCR_Lock();
  62. /* Lock all EFM registers */
  63. // EFM_Lock();
  64. /* Lock EFM OTP write protect registers */
  65. // EFM_OTP_WP_Lock();
  66. /* Lock EFM register: FWMC */
  67. // EFM_FWMC_Lock();
  68. }
  69. /**
  70. * @brief BSP clock initialize.
  71. * Set board system clock to PLLH@240MHz
  72. * @param None
  73. * @retval None
  74. */
  75. void rt_hw_board_clock_init(void)
  76. {
  77. stc_clk_pllh_init_t stcPLLHInit;
  78. CLK_ClkDiv(CLK_CATE_ALL, \
  79. (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
  80. CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \
  81. CLK_HCLK_DIV1));
  82. (void)CLK_PLLHStrucInit(&stcPLLHInit);
  83. /* VCO = (8/1)*120 = 960MHz*/
  84. stcPLLHInit.u8PLLState = CLK_PLLH_ON;
  85. stcPLLHInit.PLLCFGR = 0UL;
  86. stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
  87. stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
  88. stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
  89. stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
  90. stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
  91. stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLLSRC_XTAL;
  92. (void)CLK_PLLHInit(&stcPLLHInit);
  93. /* Highspeed SRAM set to 1 Read/Write wait cycle */
  94. SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE_1, SRAM_WAIT_CYCLE_1);
  95. /* SRAM1_2_3_4_backup set to 2 Read/Write wait cycle */
  96. SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE_2, SRAM_WAIT_CYCLE_2);
  97. /* 0-wait @ 40MHz */
  98. EFM_SetWaitCycle(EFM_WAIT_CYCLE_5);
  99. /* 4 cycles for 200 ~ 250MHz */
  100. GPIO_SetReadWaitCycle(GPIO_READ_WAIT_4);
  101. CLK_SetSysClkSrc(CLK_SYSCLKSOURCE_PLLH);
  102. }
  103. /*******************************************************************************
  104. * Function Name : SysTick_Configuration
  105. * Description : Configures the SysTick for OS tick.
  106. * Input : None
  107. * Output : None
  108. * Return : None
  109. *******************************************************************************/
  110. void SysTick_Configuration(void)
  111. {
  112. stc_clk_freq_t stcClkFreq;
  113. rt_uint32_t cnts;
  114. CLK_GetClockFreq(&stcClkFreq);
  115. cnts = (rt_uint32_t)stcClkFreq.hclkFreq / RT_TICK_PER_SECOND;
  116. SysTick_Config(cnts);
  117. }
  118. /**
  119. * This is the timer interrupt service routine.
  120. *
  121. */
  122. void SysTick_Handler(void)
  123. {
  124. /* enter interrupt */
  125. rt_interrupt_enter();
  126. rt_tick_increase();
  127. /* leave interrupt */
  128. rt_interrupt_leave();
  129. }
  130. /**
  131. * This function will initialize HC32 board.
  132. */
  133. void rt_hw_board_init()
  134. {
  135. /* Unlock the protected registers. */
  136. Peripheral_WE();
  137. /* Configure the System clock */
  138. rt_hw_board_clock_init();
  139. /* Configure the SysTick */
  140. SysTick_Configuration();
  141. #ifdef RT_USING_HEAP
  142. rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
  143. #endif
  144. #ifdef RT_USING_COMPONENTS_INIT
  145. rt_components_board_init();
  146. #endif
  147. #ifdef RT_USING_CONSOLE
  148. rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
  149. #endif
  150. }
  151. void rt_hw_us_delay(rt_uint32_t us)
  152. {
  153. uint32_t start, now, delta, reload, us_tick;
  154. start = SysTick->VAL;
  155. reload = SysTick->LOAD;
  156. us_tick = SystemCoreClock / 1000000UL;
  157. do{
  158. now = SysTick->VAL;
  159. delta = start > now ? start - now : reload + start - now;
  160. }
  161. while(delta < us_tick * us);
  162. }
  163. /*@}*/