efm32_cmu.h 21 KB

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  1. /***************************************************************************//**
  2. * @file
  3. * @brief Clock management unit (CMU) API for EFM32.
  4. * @author Energy Micro AS
  5. * @version 1.3.0
  6. *******************************************************************************
  7. * @section License
  8. * <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
  9. *******************************************************************************
  10. *
  11. * This source code is the property of Energy Micro AS. The source and compiled
  12. * code may only be used on Energy Micro "EFM32" microcontrollers.
  13. *
  14. * This copyright notice may not be removed from the source code nor changed.
  15. *
  16. * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
  17. * obligation to support this Software. Energy Micro AS is providing the
  18. * Software "AS IS", with no express or implied warranties of any kind,
  19. * including, but not limited to, any implied warranties of merchantability
  20. * or fitness for any particular purpose or warranties against infringement
  21. * of any proprietary rights of a third party.
  22. *
  23. * Energy Micro AS will not be liable for any consequential, incidental, or
  24. * special damages, or any other relief, or for any claim by any third party,
  25. * arising from your use of this Software.
  26. *
  27. ******************************************************************************/
  28. #ifndef __EFM32_CMU_H
  29. #define __EFM32_CMU_H
  30. #include <stdbool.h>
  31. #include "efm32.h"
  32. #ifdef __cplusplus
  33. extern "C" {
  34. #endif
  35. /***************************************************************************//**
  36. * @addtogroup EFM32_Library
  37. * @{
  38. ******************************************************************************/
  39. /***************************************************************************//**
  40. * @addtogroup CMU
  41. * @{
  42. ******************************************************************************/
  43. /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
  44. /* Select register ids, for internal use */
  45. #define CMU_NOSEL_REG 0
  46. #define CMU_HFCLKSEL_REG 1
  47. #define CMU_LFACLKSEL_REG 2
  48. #define CMU_LFBCLKSEL_REG 3
  49. #define CMU_SEL_REG_POS 0
  50. #define CMU_SEL_REG_MASK 0xf
  51. /* Divisor register ids, for internal use */
  52. #define CMU_NODIV_REG 0
  53. #define CMU_HFPERCLKDIV_REG 1
  54. #define CMU_HFCORECLKDIV_REG 2
  55. #define CMU_LFAPRESC0_REG 3
  56. #define CMU_LFBPRESC0_REG 4
  57. #define CMU_DIV_REG_POS 4
  58. #define CMU_DIV_REG_MASK 0xf
  59. /* Enable register ids, for internal use */
  60. #define CMU_NO_EN_REG 0
  61. #define CMU_HFPERCLKDIV_EN_REG 1
  62. #define CMU_HFPERCLKEN0_EN_REG 2
  63. #define CMU_HFCORECLKEN0_EN_REG 3
  64. #define CMU_LFACLKEN0_EN_REG 4
  65. #define CMU_LFBCLKEN0_EN_REG 5
  66. #define CMU_PCNT_EN_REG 6
  67. #define CMU_EN_REG_POS 8
  68. #define CMU_EN_REG_MASK 0xf
  69. /* Enable register bit position, for internal use */
  70. #define CMU_EN_BIT_POS 12
  71. #define CMU_EN_BIT_MASK 0x1f
  72. /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
  73. /*******************************************************************************
  74. ******************************** ENUMS ************************************
  75. ******************************************************************************/
  76. /** Clock divisors. */
  77. typedef enum
  78. {
  79. cmuClkDiv_1 = 0, /**< Divide clock by 1. */
  80. cmuClkDiv_2 = 1, /**< Divide clock by 2. */
  81. cmuClkDiv_4 = 2, /**< Divide clock by 4. */
  82. cmuClkDiv_8 = 3, /**< Divide clock by 8. */
  83. cmuClkDiv_16 = 4, /**< Divide clock by 16. */
  84. cmuClkDiv_32 = 5, /**< Divide clock by 32. */
  85. cmuClkDiv_64 = 6, /**< Divide clock by 64. */
  86. cmuClkDiv_128 = 7, /**< Divide clock by 128. */
  87. cmuClkDiv_256 = 8, /**< Divide clock by 256. */
  88. cmuClkDiv_512 = 9, /**< Divide clock by 512. */
  89. cmuClkDiv_1024 = 10, /**< Divide clock by 1024. */
  90. cmuClkDiv_2048 = 11, /**< Divide clock by 2048. */
  91. cmuClkDiv_4096 = 12, /**< Divide clock by 4096. */
  92. cmuClkDiv_8192 = 13, /**< Divide clock by 8192. */
  93. cmuClkDiv_16384 = 14, /**< Divide clock by 16384. */
  94. cmuClkDiv_32768 = 15 /**< Divide clock by 32768. */
  95. } CMU_ClkDiv_TypeDef;
  96. /** High frequency RC bands. */
  97. typedef enum
  98. {
  99. /** 1MHz RC band. */
  100. cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ,
  101. /** 7MHz RC band. */
  102. cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ,
  103. /** 11MHz RC band. */
  104. cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ,
  105. /** 14MHz RC band. */
  106. cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ,
  107. /** 21MHz RC band. */
  108. cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ,
  109. /** 28MHz RC band. */
  110. cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ
  111. } CMU_HFRCOBand_TypeDef;
  112. /** Clock points in CMU. Please refer to CMU overview in reference manual. */
  113. typedef enum
  114. {
  115. /*******************/
  116. /* HF clock branch */
  117. /*******************/
  118. /** High frequency clock */
  119. cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  120. (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) |
  121. (CMU_NO_EN_REG << CMU_EN_REG_POS) |
  122. (0 << CMU_EN_BIT_POS),
  123. /**********************************/
  124. /* HF peripheral clock sub-branch */
  125. /**********************************/
  126. /** High frequency peripheral clock */
  127. cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS) |
  128. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  129. (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS) |
  130. (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS),
  131. /** Universal sync/async receiver/transmitter 0 clock. */
  132. #if defined(USART_COUNT) && (USART_COUNT > 0)
  133. cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  134. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  135. (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
  136. (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS),
  137. #endif
  138. /** Universal sync/async receiver/transmitter 1 clock. */
  139. #if defined(USART_COUNT) && (USART_COUNT > 1)
  140. cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  141. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  142. (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
  143. (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS),
  144. #endif
  145. /** Universal sync/async receiver/transmitter 2 clock. */
  146. #if defined(USART_COUNT) && (USART_COUNT > 2)
  147. cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  148. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  149. (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
  150. (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS),
  151. #endif
  152. /** Universal async receiver/transmitter 0 clock. */
  153. #if defined(UART_COUNT) && (UART_COUNT > 0)
  154. cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  155. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  156. (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
  157. (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS),
  158. #endif
  159. /** Timer 0 clock. */
  160. #if defined(TIMER_COUNT) && (TIMER_COUNT > 0)
  161. cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  162. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  163. (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
  164. (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS),
  165. #endif
  166. /** Timer 1 clock. */
  167. #if defined(TIMER_COUNT) && (TIMER_COUNT > 1)
  168. cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  169. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  170. (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
  171. (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS),
  172. #endif
  173. /** Timer 2 clock. */
  174. #if defined(TIMER_COUNT) && (TIMER_COUNT > 2)
  175. cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  176. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  177. (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
  178. (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS),
  179. #endif
  180. /** Analog comparator 0 clock. */
  181. #if defined(ACMP_COUNT) && (ACMP_COUNT > 0)
  182. cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  183. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  184. (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
  185. (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS),
  186. #endif
  187. /** Analog comparator 1 clock. */
  188. #if defined(ACMP_COUNT) && (ACMP_COUNT > 1)
  189. cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  190. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  191. (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
  192. (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS),
  193. #endif
  194. /** Peripheral reflex system clock. */
  195. #if defined(PRS_PRESENT)
  196. cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  197. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  198. (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
  199. (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS),
  200. #endif
  201. /** Digital to analog converter 0 clock. */
  202. #if defined(DAC_COUNT) && (DAC_COUNT > 0)
  203. cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  204. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  205. (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
  206. (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS),
  207. #endif
  208. /** General purpose input/output clock. */
  209. #if defined(GPIO_PRESENT)
  210. cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  211. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  212. (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
  213. (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS),
  214. #endif
  215. /** Voltage comparator clock. */
  216. #if defined(VCMP_PRESENT)
  217. cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  218. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  219. (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
  220. (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS),
  221. #endif
  222. /** Analog to digital converter 0 clock. */
  223. #if defined(ADC_COUNT) && (ADC_COUNT > 0)
  224. cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  225. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  226. (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
  227. (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS),
  228. #endif
  229. /** I2C 0 clock. */
  230. #if defined(I2C_COUNT) && (I2C_COUNT > 0)
  231. cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  232. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  233. (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
  234. (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS),
  235. #endif
  236. /**********************/
  237. /* HF core sub-branch */
  238. /**********************/
  239. /** Core clock */
  240. cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS) |
  241. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  242. (CMU_NO_EN_REG << CMU_EN_REG_POS) |
  243. (0 << CMU_EN_BIT_POS),
  244. /** Advanced encryption standard accelerator clock. */
  245. #if defined(AES_PRESENT)
  246. cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  247. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  248. (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
  249. (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS),
  250. #endif
  251. /** Direct memory access controller clock. */
  252. #if defined(DMA_PRESENT)
  253. cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  254. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  255. (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
  256. (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS),
  257. #endif
  258. /** Low energy clocking module clock. */
  259. cmuClock_CORELE = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  260. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  261. (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
  262. (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS),
  263. /** External bus interface clock. */
  264. #if defined(EBI_PRESENT)
  265. cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  266. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  267. (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
  268. (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS),
  269. #endif
  270. /***************/
  271. /* LF A branch */
  272. /***************/
  273. /** Low frequency A clock */
  274. cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  275. (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS) |
  276. (CMU_NO_EN_REG << CMU_EN_REG_POS) |
  277. (0 << CMU_EN_BIT_POS),
  278. /** Real time counter clock. */
  279. #if defined(RTC_PRESENT)
  280. cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
  281. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  282. (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
  283. (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS),
  284. #endif
  285. /** Low energy timer 0 clock. */
  286. #if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0)
  287. cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
  288. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  289. (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
  290. (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS),
  291. #endif
  292. /** Liquid crystal display, pre FDIV clock. */
  293. #if defined(LCD_PRESENT)
  294. cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
  295. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  296. (CMU_NO_EN_REG << CMU_EN_REG_POS) |
  297. (0 << CMU_EN_BIT_POS),
  298. /** Liquid crystal display clock. Please notice that FDIV prescaler
  299. * must be set by special API. */
  300. cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  301. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  302. (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
  303. (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS),
  304. #endif
  305. /** Pulse counter 0 clock. */
  306. #if defined(PCNT_COUNT) && (PCNT_COUNT > 0)
  307. cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  308. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  309. (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
  310. (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS),
  311. #endif
  312. /** Pulse counter 1 clock. */
  313. #if defined(PCNT_COUNT) && (PCNT_COUNT > 1)
  314. cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  315. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  316. (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
  317. (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS),
  318. #endif
  319. /** Pulse counter 2 clock. */
  320. #if defined(PCNT_COUNT) && (PCNT_COUNT > 2)
  321. cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  322. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  323. (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
  324. (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS),
  325. #endif
  326. /***************/
  327. /* LF B branch */
  328. /***************/
  329. /** Low frequency B clock */
  330. cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
  331. (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS) |
  332. (CMU_NO_EN_REG << CMU_EN_REG_POS) |
  333. (0 << CMU_EN_BIT_POS),
  334. /** Low energy universal asynchronous receiver/transmitter 0 clock. */
  335. #if defined(LEUART_COUNT) && (LEUART_COUNT > 0)
  336. cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |
  337. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  338. (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |
  339. (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS),
  340. #endif
  341. /** Low energy universal asynchronous receiver/transmitter 1 clock. */
  342. #if defined(LEUART_COUNT) && (LEUART_COUNT > 1)
  343. cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |
  344. (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
  345. (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |
  346. (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS),
  347. #endif
  348. } CMU_Clock_TypeDef;
  349. /** Oscillator types. */
  350. typedef enum
  351. {
  352. cmuOsc_LFXO, /**< Low frequency crystal oscillator. */
  353. cmuOsc_LFRCO, /**< Low frequency RC oscillator. */
  354. cmuOsc_HFXO, /**< High frequency crystal oscillator. */
  355. cmuOsc_HFRCO, /**< High frequency RC oscillator. */
  356. cmuOsc_AUXHFRCO /**< Auxiliary high frequency RC oscillator. */
  357. } CMU_Osc_TypeDef;
  358. /** Selectable clock sources. */
  359. typedef enum
  360. {
  361. cmuSelect_Error, /**< Usage error. */
  362. cmuSelect_Disabled, /**< Clock selector disabled. */
  363. cmuSelect_LFXO, /**< Low frequency crystal oscillator. */
  364. cmuSelect_LFRCO, /**< Low frequency RC oscillator. */
  365. cmuSelect_HFXO, /**< High frequency crystal oscillator. */
  366. cmuSelect_HFRCO, /**< High frequency RC oscillator. */
  367. cmuSelect_CORELEDIV2 /**< Core low energy clock divided by 2. */
  368. } CMU_Select_TypeDef;
  369. /*******************************************************************************
  370. ***************************** PROTOTYPES **********************************
  371. ******************************************************************************/
  372. uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
  373. CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
  374. void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
  375. void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
  376. uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
  377. CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
  378. void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
  379. void CMU_FreezeEnable(bool enable);
  380. CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);
  381. void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);
  382. uint32_t CMU_HFRCOStartupDelayGet(void);
  383. void CMU_HFRCOStartupDelaySet(uint32_t delay);
  384. /***************************************************************************//**
  385. * @brief
  386. * Clear one or more pending CMU interrupts.
  387. *
  388. * @param[in] flags
  389. * CMU interrupt sources to clear.
  390. ******************************************************************************/
  391. static __INLINE void CMU_IntClear(uint32_t flags)
  392. {
  393. CMU->IFC = flags;
  394. }
  395. /***************************************************************************//**
  396. * @brief
  397. * Disable one or more CMU interrupts.
  398. *
  399. * @param[in] flags
  400. * CMU interrupt sources to disable.
  401. ******************************************************************************/
  402. static __INLINE void CMU_IntDisable(uint32_t flags)
  403. {
  404. CMU->IEN &= ~flags;
  405. }
  406. /***************************************************************************//**
  407. * @brief
  408. * Enable one or more CMU interrupts.
  409. *
  410. * @note
  411. * Depending on the use, a pending interrupt may already be set prior to
  412. * enabling the interrupt. Consider using CMU_IntClear() prior to enabling
  413. * if such a pending interrupt should be ignored.
  414. *
  415. * @param[in] flags
  416. * CMU interrupt sources to enable.
  417. ******************************************************************************/
  418. static __INLINE void CMU_IntEnable(uint32_t flags)
  419. {
  420. CMU->IEN |= flags;
  421. }
  422. /***************************************************************************//**
  423. * @brief
  424. * Get pending CMU interrupts.
  425. *
  426. * @return
  427. * CMU interrupt sources pending.
  428. ******************************************************************************/
  429. static __INLINE uint32_t CMU_IntGet(void)
  430. {
  431. return(CMU->IF);
  432. }
  433. /**************************************************************************//**
  434. * @brief
  435. * Set one or more pending CMU interrupts from SW.
  436. *
  437. * @param[in] flags
  438. * CMU interrupt sources to set to pending.
  439. *****************************************************************************/
  440. static __INLINE void CMU_IntSet(uint32_t flags)
  441. {
  442. CMU->IFS = flags;
  443. }
  444. uint32_t CMU_LCDClkFDIVGet(void);
  445. void CMU_LCDClkFDIVSet(uint32_t div);
  446. /***************************************************************************//**
  447. * @brief
  448. * Lock the CMU in order to protect some of its registers against unintended
  449. * modification.
  450. *
  451. * @details
  452. * Please refer to the reference manual for CMU registers that will be
  453. * locked.
  454. *
  455. * @note
  456. * If locking the CMU registers, they must be unlocked prior to using any
  457. * CMU API functions modifying CMU registers protected by the lock.
  458. ******************************************************************************/
  459. static __INLINE void CMU_Lock(void)
  460. {
  461. CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
  462. }
  463. void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
  464. uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
  465. void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
  466. bool CMU_PCNTClockExternalGet(unsigned int inst);
  467. void CMU_PCNTClockExternalSet(unsigned int inst, bool external);
  468. /***************************************************************************//**
  469. * @brief
  470. * Unlock the CMU so that writing to locked registers again is possible.
  471. ******************************************************************************/
  472. static __INLINE void CMU_Unlock(void)
  473. {
  474. CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
  475. }
  476. /** @} (end addtogroup CMU) */
  477. /** @} (end addtogroup EFM32_Library) */
  478. #ifdef __cplusplus
  479. }
  480. #endif
  481. #endif /* __EFM32_CMU_H */