drv_can.c 22 KB

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  1. /*
  2. * Copyright (c) 2021 - 2022 hpmicro
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-05-08 hpmicro the first version
  9. */
  10. #include <rtthread.h>
  11. #include <rtdevice.h>
  12. #include <rthw.h>
  13. #include "board.h"
  14. #include "hpm_can_drv.h"
  15. #define CAN_SEND_WAIT_MS_MAX (1000U) /* CAN maximum wait time for transmission */
  16. #define CAN_SENDBOX_NUM (1U) /* CAN Hardware Transmission buffer number */
  17. #define CAN_FILTER_NUM_MAX (16U) /* CAN Hardware Filter number */
  18. #ifdef RT_USING_CAN
  19. typedef struct _hpm_can_struct
  20. {
  21. CAN_Type *can_base; /**< CAN Base address */
  22. const char *name; /**< CAN device name */
  23. int32_t irq_num; /**< CAN IRQ index */
  24. uint32_t fifo_index; /**< FIFO index, it is a fake value to satisfy the driver framework */
  25. can_config_t can_config; /**< CAN configuration for IP */
  26. struct rt_can_device can_dev; /**< CAN device configuration in rt-thread */
  27. uint32_t filter_num; /**< Filter number */
  28. can_filter_config_t filter_list[CAN_FILTER_NUM_MAX]; /**< Filter list */
  29. } hpm_can_t;
  30. /**
  31. * @brief Configure CAN controller
  32. * @param [in/out] can CAN device pointer
  33. * @param [in] cfg CAN configuration pointer
  34. * @retval RT_EOK for valid configuration
  35. * @retval -RT_ERROR for invalid configuration
  36. */
  37. static rt_err_t hpm_can_configure(struct rt_can_device *can, struct can_configure *cfg);
  38. /**
  39. * @brief Control/Get CAN state
  40. * including:interrupt, mode, priority, baudrate, filter, status
  41. * @param [in/out] can CAN device pointer
  42. * @param [in] cmd Control command
  43. * @param [in/out] arg Argument pointer
  44. * @retval RT_EOK for valid control command and arg
  45. * @retval -RT_ERROR for invalid control command or arg
  46. */
  47. static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg);
  48. /**
  49. * @brief Send out CAN message
  50. * @param [in] can CAN device pointer
  51. * @param [in] buf CAN message buffer
  52. * @param [in] boxno Mailbox number, it is not used in this porting
  53. * @retval RT_EOK No error
  54. * @retval -RT_ETIMEOUT timeout happened
  55. * @retval -RT_EFULL Transmission buffer is full
  56. */
  57. static int hpm_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno);
  58. /**
  59. * @brief Receive message from CAN
  60. * @param [in] can CAN device pointer
  61. * @param [out] buf CAN receive buffer
  62. * @param [in] boxno Mailbox Number, it is not used in this porting
  63. * @retval RT_EOK no error
  64. * @retval -RT_ERROR Error happened during reading receive FIFO
  65. * @retval -RT_EMPTY no data in receive FIFO
  66. */
  67. static int hpm_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno);
  68. /**
  69. * @brief Common Interrupt Service routine
  70. * @param [in] hpm_can HPM CAN pointer
  71. */
  72. static void hpm_can_isr(hpm_can_t *hpm_can);
  73. /**
  74. * @brief Decode data bytes from DLC
  75. * @param [in] dlc Data Length Code
  76. * @return decoded data bytes
  77. */
  78. static uint8_t can_get_data_bytes_from_dlc(uint32_t dlc);
  79. #if defined(HPM_CAN0_BASE) && defined(BSP_USING_CAN0)
  80. static hpm_can_t dev_can0 =
  81. {
  82. .can_base = HPM_CAN0,
  83. .name = "can0",
  84. .irq_num = IRQn_CAN0,
  85. .fifo_index = 0,
  86. };
  87. void can0_isr(void)
  88. {
  89. hpm_can_isr(&dev_can0);
  90. }
  91. SDK_DECLARE_EXT_ISR_M(IRQn_CAN0, can0_isr);
  92. #endif
  93. #if defined(HPM_CAN1_BASE) && defined(BSP_USING_CAN1)
  94. static hpm_can_t dev_can1 =
  95. {
  96. .can_base = HPM_CAN1,
  97. .name = "can1",
  98. .irq_num = IRQn_CAN1,
  99. .fifo_index = 1,
  100. };
  101. void can1_isr(void)
  102. {
  103. hpm_can_isr(&dev_can1);
  104. }
  105. SDK_DECLARE_EXT_ISR_M(IRQn_CAN1, can1_isr);
  106. #endif
  107. #if defined(HPM_CAN2_BASE) && defined(BSP_USING_CAN2)
  108. static hpm_can_t dev_can2 =
  109. {
  110. .can_base = HPM_CAN2,
  111. .name = "can2",
  112. .irq_num = IRQn_CAN2,
  113. .fifo_index = 2,
  114. };
  115. void can2_isr(void)
  116. {
  117. hpm_can_isr(&dev_can2);
  118. }
  119. SDK_DECLARE_EXT_ISR_M(IRQn_CAN2, can2_isr);
  120. #endif
  121. #if defined(HPM_CAN3_BASE) && defined(BSP_USING_CAN3)
  122. static hpm_can_t dev_can3 =
  123. {
  124. .can_base = HPM_CAN3,
  125. .name = "can3",
  126. .irq_num = IRQn_CAN3,
  127. .fifo_index = 3,
  128. };
  129. void can3_isr(void)
  130. {
  131. hpm_can_isr(&dev_can3);
  132. }
  133. SDK_DECLARE_EXT_ISR_M(IRQn_CAN3, can3_isr);
  134. #endif
  135. static hpm_can_t *hpm_cans[] = {
  136. #if defined(HPM_CAN0_BASE) && defined(BSP_USING_CAN0)
  137. &dev_can0,
  138. #endif
  139. #if defined(HPM_CAN1_BASE) && defined(BSP_USING_CAN1)
  140. &dev_can1,
  141. #endif
  142. #if defined(HPM_CAN2_BASE) && defined(BSP_USING_CAN2)
  143. &dev_can2,
  144. #endif
  145. #if defined(HPM_CAN3_BASE) && defined(BSP_USING_CAN3)
  146. &dev_can3,
  147. #endif
  148. };
  149. static const struct rt_can_ops hpm_can_ops = {
  150. .configure = hpm_can_configure,
  151. .control = hpm_can_control,
  152. .sendmsg = hpm_can_sendmsg,
  153. .recvmsg = hpm_can_recvmsg,
  154. };
  155. static void hpm_can_isr(hpm_can_t *hpm_can)
  156. {
  157. uint8_t tx_rx_flags = can_get_tx_rx_flags(hpm_can->can_base);
  158. uint8_t error_flags = can_get_error_interrupt_flags(hpm_can->can_base);
  159. /* High-priority message transmission done */
  160. if ((tx_rx_flags & CAN_EVENT_TX_PRIMARY_BUF) != 0U)
  161. {
  162. rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_TX_DONE | (0UL << 8));
  163. }
  164. /* Normal priority message transmission done */
  165. if ((tx_rx_flags & CAN_EVENT_TX_SECONDARY_BUF) != 0U)
  166. {
  167. rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_TX_DONE | (0UL << 8));
  168. }
  169. /* Data available in FIFO */
  170. if ((tx_rx_flags & CAN_EVENT_RECEIVE) == CAN_EVENT_RECEIVE)
  171. {
  172. rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RX_IND | (hpm_can->fifo_index << 8));
  173. }
  174. /* RX FIFO overflow */
  175. if ((tx_rx_flags & CAN_EVENT_RX_BUF_OVERRUN) != 0U)
  176. {
  177. rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RXOF_IND | (hpm_can->fifo_index << 8));
  178. }
  179. /* Error happened on CAN Bus */
  180. if (((tx_rx_flags & CAN_EVENT_ERROR) != 0U) || (error_flags != 0U))
  181. {
  182. uint8_t err_kind = can_get_last_error_kind(hpm_can->can_base);
  183. switch(err_kind)
  184. {
  185. case CAN_KIND_OF_ERROR_ACK_ERROR:
  186. hpm_can->can_dev.status.ackerrcnt++;
  187. break;
  188. case CAN_KIND_OF_ERROR_BIT_ERROR:
  189. hpm_can->can_dev.status.biterrcnt++;
  190. break;
  191. case CAN_KIND_OF_ERROR_CRC_ERROR:
  192. hpm_can->can_dev.status.crcerrcnt++;
  193. break;
  194. case CAN_KIND_OF_ERROR_FORM_ERROR:
  195. hpm_can->can_dev.status.formaterrcnt++;
  196. break;
  197. case CAN_KIND_OF_ERROR_STUFF_ERROR:
  198. hpm_can->can_dev.status.bitpaderrcnt++;
  199. break;
  200. }
  201. hpm_can->can_dev.status.rcverrcnt = can_get_receive_error_count(hpm_can->can_base);
  202. hpm_can->can_dev.status.snderrcnt = can_get_transmit_error_count(hpm_can->can_base);
  203. hpm_can->can_dev.status.lasterrtype = can_get_last_error_kind(hpm_can->can_base);
  204. hpm_can->can_dev.status.errcode = 0;
  205. if ((error_flags & CAN_ERROR_WARNING_LIMIT_FLAG) != 0U)
  206. {
  207. hpm_can->can_dev.status.errcode |= ERRWARNING;
  208. }
  209. if ((error_flags & CAN_ERROR_PASSIVE_INT_FLAG) != 0U)
  210. {
  211. hpm_can->can_dev.status.errcode |= ERRPASSIVE;
  212. }
  213. if (can_is_in_bus_off_mode(hpm_can->can_base))
  214. {
  215. hpm_can->can_dev.status.errcode |= BUSOFF;
  216. }
  217. }
  218. can_clear_tx_rx_flags(hpm_can->can_base, tx_rx_flags);
  219. can_clear_error_interrupt_flags(hpm_can->can_base, error_flags);
  220. }
  221. static rt_err_t hpm_can_configure(struct rt_can_device *can, struct can_configure *cfg)
  222. {
  223. RT_ASSERT(can);
  224. RT_ASSERT(cfg);
  225. hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data;
  226. RT_ASSERT(drv_can);
  227. #ifdef RT_CAN_USING_CANFD
  228. drv_can->can_config.enable_canfd = (cfg->enable_canfd != 0) ? true : false;
  229. if (cfg->use_bit_timing != 0U)
  230. {
  231. drv_can->can_config.use_lowlevel_timing_setting = true;
  232. drv_can->can_config.can_timing.prescaler = cfg->can_timing.prescaler;
  233. drv_can->can_config.can_timing.num_seg1 = cfg->can_timing.num_seg1;
  234. drv_can->can_config.can_timing.num_seg2 = cfg->can_timing.num_seg2;
  235. drv_can->can_config.can_timing.num_sjw = cfg->can_timing.num_sjw;
  236. drv_can->can_config.canfd_timing.prescaler = cfg->canfd_timing.prescaler;
  237. drv_can->can_config.canfd_timing.num_seg1 = cfg->canfd_timing.num_seg1;
  238. drv_can->can_config.canfd_timing.num_seg2 = cfg->canfd_timing.num_seg2;
  239. drv_can->can_config.canfd_timing.num_sjw = cfg->canfd_timing.num_sjw;
  240. }
  241. else
  242. #endif
  243. {
  244. drv_can->can_config.use_lowlevel_timing_setting = false;
  245. drv_can->can_config.baudrate = cfg->baud_rate;
  246. #ifdef RT_CAN_USING_CANFD
  247. drv_can->can_config.baudrate_fd = cfg->baud_rate_fd;
  248. #endif
  249. }
  250. switch (cfg->mode)
  251. {
  252. case RT_CAN_MODE_NORMAL:
  253. drv_can->can_config.mode = can_mode_normal;
  254. break;
  255. case RT_CAN_MODE_LISTEN:
  256. drv_can->can_config.mode = can_mode_listen_only;
  257. break;
  258. case RT_CAN_MODE_LOOPBACK:
  259. drv_can->can_config.mode = can_mode_loopback_internal;
  260. break;
  261. default:
  262. return -RT_ERROR;
  263. break;
  264. }
  265. drv_can->can_config.enable_tx_buffer_priority_mode = (cfg->privmode != 0U) ? true : false;
  266. init_can_pins(drv_can->can_base);
  267. uint32_t can_clk = board_init_can_clock(drv_can->can_base);
  268. drv_can->can_config.filter_list_num = drv_can->filter_num;
  269. drv_can->can_config.filter_list = &drv_can->filter_list[0];
  270. hpm_stat_t status = can_init(drv_can->can_base, &drv_can->can_config, can_clk);
  271. if (status != status_success)
  272. {
  273. return -RT_ERROR;
  274. }
  275. return RT_EOK;
  276. }
  277. static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg)
  278. {
  279. RT_ASSERT(can);
  280. hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data;
  281. RT_ASSERT(drv_can);
  282. uint32_t arg_val;
  283. rt_err_t err = RT_EOK;
  284. uint32_t temp;
  285. switch (cmd)
  286. {
  287. case RT_DEVICE_CTRL_CLR_INT:
  288. arg_val = (uint32_t) arg;
  289. intc_m_disable_irq(drv_can->irq_num);
  290. if (arg_val == RT_DEVICE_FLAG_INT_RX)
  291. {
  292. uint8_t irq_txrx_mask = CAN_EVENT_RECEIVE | CAN_EVENT_RX_BUF_ALMOST_FULL | CAN_EVENT_RX_BUF_FULL | CAN_EVENT_RX_BUF_OVERRUN;
  293. drv_can->can_config.irq_txrx_enable_mask &= (uint8_t)~irq_txrx_mask;
  294. can_disable_tx_rx_irq(drv_can->can_base, irq_txrx_mask);
  295. }
  296. else if (arg_val == RT_DEVICE_FLAG_INT_TX)
  297. {
  298. uint8_t irq_txrx_mask = CAN_EVENT_TX_PRIMARY_BUF | CAN_EVENT_TX_SECONDARY_BUF;
  299. drv_can->can_config.irq_txrx_enable_mask &= (uint8_t)~irq_txrx_mask;
  300. can_disable_tx_rx_irq(drv_can->can_base, irq_txrx_mask);
  301. }
  302. else if (arg_val == RT_DEVICE_CAN_INT_ERR)
  303. {
  304. uint8_t irq_txrx_mask = CAN_EVENT_ERROR;
  305. uint8_t irq_error_mask = CAN_ERROR_ARBITRAITION_LOST_INT_ENABLE | CAN_ERROR_PASSIVE_INT_ENABLE | CAN_ERROR_BUS_ERROR_INT_ENABLE;
  306. drv_can->can_config.irq_txrx_enable_mask &= (uint8_t)~irq_txrx_mask;
  307. drv_can->can_config.irq_error_enable_mask &= (uint8_t)~irq_error_mask;
  308. can_disable_tx_rx_irq(drv_can->can_base, irq_txrx_mask);
  309. can_disable_error_irq(drv_can->can_base, irq_error_mask);
  310. }
  311. else
  312. {
  313. err = -RT_ERROR;
  314. }
  315. break;
  316. case RT_DEVICE_CTRL_SET_INT:
  317. arg_val = (uint32_t) arg;
  318. if (arg_val == RT_DEVICE_FLAG_INT_RX)
  319. {
  320. uint8_t irq_txrx_mask = CAN_EVENT_RECEIVE | CAN_EVENT_RX_BUF_ALMOST_FULL | CAN_EVENT_RX_BUF_FULL | CAN_EVENT_RX_BUF_OVERRUN;
  321. drv_can->can_config.irq_txrx_enable_mask |= irq_txrx_mask;
  322. can_enable_tx_rx_irq(drv_can->can_base, irq_txrx_mask);
  323. intc_m_enable_irq_with_priority(drv_can->irq_num, 1);
  324. }
  325. else if (arg_val == RT_DEVICE_FLAG_INT_TX)
  326. {
  327. uint8_t irq_txrx_mask = CAN_EVENT_TX_PRIMARY_BUF | CAN_EVENT_TX_SECONDARY_BUF;
  328. drv_can->can_config.irq_txrx_enable_mask |= irq_txrx_mask;
  329. can_enable_tx_rx_irq(drv_can->can_base, irq_txrx_mask);
  330. intc_m_enable_irq_with_priority(drv_can->irq_num, 1);
  331. }
  332. else if (arg_val == RT_DEVICE_CAN_INT_ERR)
  333. {
  334. uint8_t irq_txrx_mask = CAN_EVENT_ERROR;
  335. uint8_t irq_error_mask = CAN_ERROR_ARBITRAITION_LOST_INT_ENABLE | CAN_ERROR_PASSIVE_INT_ENABLE | CAN_ERROR_BUS_ERROR_INT_ENABLE;
  336. drv_can->can_config.irq_txrx_enable_mask |= irq_txrx_mask;
  337. drv_can->can_config.irq_error_enable_mask |= irq_error_mask;
  338. can_enable_tx_rx_irq(drv_can->can_base, irq_txrx_mask);
  339. can_enable_error_irq(drv_can->can_base, irq_error_mask);
  340. intc_m_enable_irq_with_priority(drv_can->irq_num, 1);
  341. }
  342. else
  343. {
  344. err = -RT_ERROR;
  345. }
  346. break;
  347. case RT_CAN_CMD_SET_FILTER:
  348. {
  349. /* Convert the RT-Thread Filter format to the filter format supported by HPM CAN */
  350. struct rt_can_filter_config *filter = (struct rt_can_filter_config*)arg;
  351. if (filter != NULL)
  352. {
  353. drv_can->filter_num = filter->count;
  354. RT_ASSERT(filter->count <= CAN_FILTER_NUM_MAX);
  355. for (uint32_t i=0; i<filter->count; i++)
  356. {
  357. drv_can->filter_list[i].index = (filter->items[i].hdr == -1) ? i : filter->items[i].hdr;
  358. drv_can->filter_list[i].enable = (filter->actived != 0U) ? true : false;
  359. drv_can->filter_list[i].code = filter->items[i].id;
  360. drv_can->filter_list[i].id_mode = (filter->items[i].ide != 0U) ? can_filter_id_mode_extended_frames : can_filter_id_mode_standard_frames;
  361. drv_can->filter_list[i].mask = (~filter->items[i].mask) & ~(7UL <<29);
  362. }
  363. }
  364. else
  365. {
  366. drv_can->filter_num = 0;
  367. }
  368. err = hpm_can_configure(can, &drv_can->can_dev.config);
  369. }
  370. break;
  371. case RT_CAN_CMD_SET_MODE:
  372. arg_val = (uint32_t) arg;
  373. if ((arg_val != RT_CAN_MODE_NORMAL) && (arg_val != RT_CAN_MODE_LISTEN) && (arg_val != RT_CAN_MODE_LOOPBACK))
  374. {
  375. err = -RT_ERROR;
  376. break;
  377. }
  378. if (arg_val != drv_can->can_dev.config.mode)
  379. {
  380. drv_can->can_dev.config.mode = arg_val;
  381. err = hpm_can_configure(can, &drv_can->can_dev.config);
  382. }
  383. break;
  384. case RT_CAN_CMD_SET_BAUD:
  385. arg_val = (uint32_t) arg;
  386. if (arg_val != drv_can->can_dev.config.baud_rate)
  387. {
  388. drv_can->can_dev.config.baud_rate = arg_val;
  389. }
  390. err = hpm_can_configure(can, &drv_can->can_dev.config);
  391. break;
  392. #ifdef RT_CAN_USING_CANFD
  393. case RT_CAN_CMD_SET_CANFD:
  394. arg_val = (uint32_t) arg;
  395. if (arg_val != drv_can->can_dev.config.enable_canfd)
  396. {
  397. drv_can->can_dev.config.enable_canfd = arg_val;
  398. err = hpm_can_configure(can, &drv_can->can_dev.config);
  399. }
  400. break;
  401. case RT_CAN_CMD_SET_BAUD_FD:
  402. arg_val = (uint32_t) arg;
  403. if (arg_val != drv_can->can_dev.config.baud_rate_fd)
  404. {
  405. drv_can->can_dev.config.baud_rate_fd = arg_val;
  406. err = hpm_can_configure(can, &drv_can->can_dev.config);
  407. }
  408. break;
  409. case RT_CAN_CMD_SET_BITTIMING:
  410. {
  411. struct rt_can_bit_timing_config *timing_configs = (struct rt_can_bit_timing_config*)arg;
  412. if ((timing_configs == RT_NULL) || (timing_configs->count < 1) || (timing_configs->count > 2))
  413. {
  414. return -RT_ERROR;
  415. }
  416. if (timing_configs->count != 0U)
  417. {
  418. drv_can->can_dev.config.can_timing = timing_configs->items[0];
  419. }
  420. if (timing_configs->count == 2)
  421. {
  422. drv_can->can_dev.config.canfd_timing = timing_configs->items[1];
  423. }
  424. err = hpm_can_configure(can, &drv_can->can_dev.config);
  425. }
  426. break;
  427. #endif
  428. case RT_CAN_CMD_SET_PRIV:
  429. arg_val = (uint32_t)arg;
  430. if ((arg_val != RT_CAN_MODE_PRIV) && (arg_val != RT_CAN_MODE_NOPRIV))
  431. {
  432. return -RT_ERROR;
  433. }
  434. if (arg_val != drv_can->can_dev.config.privmode)
  435. {
  436. drv_can->can_dev.config.privmode = arg_val;
  437. err = hpm_can_configure(can, &drv_can->can_dev.config);
  438. }
  439. break;
  440. case RT_CAN_CMD_GET_STATUS:
  441. drv_can->can_dev.status.rcverrcnt = can_get_receive_error_count(drv_can->can_base);
  442. drv_can->can_dev.status.snderrcnt = can_get_transmit_error_count(drv_can->can_base);
  443. drv_can->can_dev.status.lasterrtype = can_get_last_error_kind(drv_can->can_base);
  444. temp = can_get_error_interrupt_flags(drv_can->can_base);
  445. drv_can->can_dev.status.errcode = 0;
  446. if ((temp & CAN_ERROR_WARNING_LIMIT_FLAG) != 0U)
  447. {
  448. drv_can->can_dev.status.errcode |= ERRWARNING;
  449. }
  450. if ((temp & CAN_ERROR_PASSIVE_INT_FLAG) != 0U)
  451. {
  452. drv_can->can_dev.status.errcode |= ERRPASSIVE;
  453. }
  454. if (can_is_in_bus_off_mode(drv_can->can_base))
  455. {
  456. drv_can->can_dev.status.errcode |= BUSOFF;
  457. }
  458. rt_memcpy(arg, &drv_can->can_dev.status, sizeof(drv_can->can_dev.status));
  459. break;
  460. }
  461. }
  462. static int hpm_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno)
  463. {
  464. RT_ASSERT(can);
  465. hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data;
  466. RT_ASSERT(drv_can);
  467. struct rt_can_msg *can_msg = (struct rt_can_msg *) buf;
  468. can_transmit_buf_t tx_buf = { 0 };
  469. tx_buf.id = can_msg->id;
  470. if (can_msg->ide == RT_CAN_STDID)
  471. {
  472. tx_buf.extend_id = false;
  473. }
  474. else
  475. {
  476. tx_buf.extend_id = true;
  477. }
  478. if (can_msg->rtr == RT_CAN_DTR)
  479. {
  480. tx_buf.remote_frame = false;
  481. }
  482. else
  483. {
  484. tx_buf.remote_frame = true;
  485. }
  486. #ifdef RT_CAN_USING_CANFD
  487. if (can_msg->fd_frame != 0)
  488. {
  489. tx_buf.canfd_frame = 1;
  490. tx_buf.bitrate_switch = 1;
  491. RT_ASSERT(can_msg->len <= 15);
  492. }
  493. else
  494. #endif
  495. {
  496. RT_ASSERT(can_msg->len <= 8);
  497. }
  498. uint32_t msg_len = can_get_data_bytes_from_dlc(can_msg->len);
  499. for (uint32_t i = 0; i < msg_len; i++)
  500. {
  501. tx_buf.data[i] = can_msg->data[i];
  502. }
  503. tx_buf.dlc = can_msg->len;
  504. uint32_t delay_cnt = 0;
  505. if (can_msg->priv != 0U)
  506. {
  507. while (can_is_primary_transmit_buffer_full(drv_can->can_base))
  508. {
  509. rt_thread_mdelay(1);
  510. delay_cnt++;
  511. if (delay_cnt >= CAN_SEND_WAIT_MS_MAX)
  512. {
  513. return -RT_ETIMEOUT;
  514. }
  515. }
  516. hpm_stat_t status = can_send_message_nonblocking(drv_can->can_base, &tx_buf);
  517. if (status != status_success)
  518. {
  519. return -RT_EFULL;
  520. }
  521. }
  522. else
  523. {
  524. while (can_is_secondary_transmit_buffer_full(drv_can->can_base))
  525. {
  526. rt_thread_mdelay(1);
  527. delay_cnt++;
  528. if (delay_cnt >= CAN_SEND_WAIT_MS_MAX)
  529. {
  530. return -RT_ETIMEOUT;
  531. }
  532. }
  533. hpm_stat_t status = can_send_message_nonblocking(drv_can->can_base, &tx_buf);
  534. if (status != status_success)
  535. {
  536. return -RT_EFULL;
  537. }
  538. }
  539. return RT_EOK;
  540. }
  541. static int hpm_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno)
  542. {
  543. RT_ASSERT(can);
  544. hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data;
  545. RT_ASSERT(drv_can);
  546. rt_can_msg_t can_msg = (rt_can_msg_t)buf;
  547. if (can_is_data_available_in_receive_buffer(drv_can->can_base)) {
  548. can_receive_buf_t rx_buf;
  549. hpm_stat_t status = can_read_received_message(drv_can->can_base, &rx_buf);
  550. if (status != status_success) {
  551. return -RT_ERROR;
  552. }
  553. if (rx_buf.extend_id != 0) {
  554. can_msg->ide = RT_CAN_EXTID;
  555. }
  556. else {
  557. can_msg->ide = RT_CAN_STDID;
  558. }
  559. can_msg->id = rx_buf.id;
  560. if (rx_buf.remote_frame != 0) {
  561. can_msg->rtr = RT_CAN_RTR;
  562. }
  563. else {
  564. can_msg->rtr = RT_CAN_DTR;
  565. }
  566. can_msg->len = rx_buf.dlc;
  567. uint32_t msg_len = can_get_data_bytes_from_dlc(can_msg->len);
  568. for(uint32_t i = 0; i < msg_len; i++) {
  569. can_msg->data[i] = rx_buf.data[i];
  570. }
  571. }
  572. else {
  573. return -RT_EEMPTY;
  574. }
  575. return RT_EOK;
  576. }
  577. static uint8_t can_get_data_bytes_from_dlc(uint32_t dlc)
  578. {
  579. uint32_t data_bytes = 0;
  580. dlc &= 0xFU;
  581. if (dlc <= 8U) {
  582. data_bytes = dlc;
  583. } else {
  584. switch (dlc) {
  585. case can_payload_size_12:
  586. data_bytes = 12U;
  587. break;
  588. case can_payload_size_16:
  589. data_bytes = 16U;
  590. break;
  591. case can_payload_size_20:
  592. data_bytes = 20U;
  593. break;
  594. case can_payload_size_24:
  595. data_bytes = 24U;
  596. break;
  597. case can_payload_size_32:
  598. data_bytes = 32U;
  599. break;
  600. case can_payload_size_48:
  601. data_bytes = 48U;
  602. break;
  603. case can_payload_size_64:
  604. data_bytes = 64U;
  605. break;
  606. default:
  607. /* Code should never touch here */
  608. break;
  609. }
  610. }
  611. return data_bytes;
  612. }
  613. int rt_hw_can_init(void)
  614. {
  615. struct can_configure config = CANDEFAULTCONFIG;
  616. config.privmode = RT_CAN_MODE_NOPRIV;
  617. config.sndboxnumber = CAN_SENDBOX_NUM;
  618. config.ticks = 50;
  619. for (uint32_t i = 0; i < ARRAY_SIZE(hpm_cans); i++)
  620. {
  621. hpm_cans[i]->can_dev.config = config;
  622. hpm_cans[i]->filter_num = 0;
  623. can_get_default_config(&hpm_cans[i]->can_config);
  624. rt_hw_can_register(&hpm_cans[i]->can_dev, hpm_cans[i]->name, &hpm_can_ops, hpm_cans[i]);
  625. }
  626. return RT_EOK;
  627. }
  628. INIT_BOARD_EXPORT(rt_hw_can_init);
  629. #endif